i915_drv.h revision 278146
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3/* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_drv.h 278146 2015-02-03 10:30:41Z kib $"); 32 33#ifndef _I915_DRV_H_ 34#define _I915_DRV_H_ 35 36#include <dev/agp/agp_i810.h> 37#include <dev/drm2/drm_mm.h> 38#include <dev/drm2/i915/i915_reg.h> 39#include <dev/drm2/i915/intel_ringbuffer.h> 40#include <dev/drm2/i915/intel_bios.h> 41 42/* General customization: 43 */ 44 45#define DRIVER_AUTHOR "Tungsten Graphics, Inc." 46 47#define DRIVER_NAME "i915" 48#define DRIVER_DESC "Intel Graphics" 49#define DRIVER_DATE "20080730" 50 51MALLOC_DECLARE(DRM_I915_GEM); 52 53enum pipe { 54 PIPE_A = 0, 55 PIPE_B, 56 PIPE_C, 57 I915_MAX_PIPES 58}; 59#define pipe_name(p) ((p) + 'A') 60#define I915_NUM_PIPE 2 61 62enum plane { 63 PLANE_A = 0, 64 PLANE_B, 65 PLANE_C, 66}; 67#define plane_name(p) ((p) + 'A') 68 69enum port { 70 PORT_A = 0, 71 PORT_B, 72 PORT_C, 73 PORT_D, 74 PORT_E, 75 I915_MAX_PORTS 76}; 77#define port_name(p) ((p) + 'A') 78 79#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 80 81 82#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 83 84struct intel_pch_pll { 85 int refcount; /* count of number of CRTCs sharing this PLL */ 86 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 87 bool on; /* is the PLL actually active? Disabled during modeset */ 88 int pll_reg; 89 int fp0_reg; 90 int fp1_reg; 91}; 92#define I915_NUM_PLLS 2 93 94/* Interface history: 95 * 96 * 1.1: Original. 97 * 1.2: Add Power Management 98 * 1.3: Add vblank support 99 * 1.4: Fix cmdbuffer path, add heap destroy 100 * 1.5: Add vblank pipe configuration 101 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 102 * - Support vertical blank on secondary display pipe 103 */ 104#define DRIVER_MAJOR 1 105#define DRIVER_MINOR 6 106#define DRIVER_PATCHLEVEL 0 107 108#define WATCH_COHERENCY 0 109#define WATCH_BUF 0 110#define WATCH_EXEC 0 111#define WATCH_LRU 0 112#define WATCH_RELOC 0 113#define WATCH_INACTIVE 0 114#define WATCH_PWRITE 0 115 116#define I915_GEM_PHYS_CURSOR_0 1 117#define I915_GEM_PHYS_CURSOR_1 2 118#define I915_GEM_PHYS_OVERLAY_REGS 3 119#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 120 121struct drm_i915_gem_phys_object { 122 int id; 123 drm_dma_handle_t *handle; 124 struct drm_i915_gem_object *cur_obj; 125}; 126 127struct drm_i915_private; 128 129struct drm_i915_display_funcs { 130 void (*dpms)(struct drm_crtc *crtc, int mode); 131 bool (*fbc_enabled)(struct drm_device *dev); 132 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 133 void (*disable_fbc)(struct drm_device *dev); 134 int (*get_display_clock_speed)(struct drm_device *dev); 135 int (*get_fifo_size)(struct drm_device *dev, int plane); 136 void (*update_wm)(struct drm_device *dev); 137 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 138 uint32_t sprite_width, int pixel_size); 139 void (*sanitize_pm)(struct drm_device *dev); 140 void (*update_linetime_wm)(struct drm_device *dev, int pipe, 141 struct drm_display_mode *mode); 142 int (*crtc_mode_set)(struct drm_crtc *crtc, 143 struct drm_display_mode *mode, 144 struct drm_display_mode *adjusted_mode, 145 int x, int y, 146 struct drm_framebuffer *old_fb); 147 void (*off)(struct drm_crtc *crtc); 148 void (*write_eld)(struct drm_connector *connector, 149 struct drm_crtc *crtc); 150 void (*fdi_link_train)(struct drm_crtc *crtc); 151 void (*init_clock_gating)(struct drm_device *dev); 152 void (*init_pch_clock_gating)(struct drm_device *dev); 153 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 154 struct drm_framebuffer *fb, 155 struct drm_i915_gem_object *obj); 156 void (*force_wake_get)(struct drm_i915_private *dev_priv); 157 void (*force_wake_put)(struct drm_i915_private *dev_priv); 158 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 159 int x, int y); 160 /* clock updates for mode set */ 161 /* cursor updates */ 162 /* render clock increase/decrease */ 163 /* display clock increase/decrease */ 164 /* pll clock increase/decrease */ 165}; 166 167struct intel_device_info { 168 u8 gen; 169 u8 not_supported:1; 170 u8 is_mobile:1; 171 u8 is_i85x:1; 172 u8 is_i915g:1; 173 u8 is_i945gm:1; 174 u8 is_g33:1; 175 u8 need_gfx_hws:1; 176 u8 is_g4x:1; 177 u8 is_pineview:1; 178 u8 is_broadwater:1; 179 u8 is_crestline:1; 180 u8 is_ivybridge:1; 181 u8 is_valleyview:1; 182 u8 has_pch_split:1; 183 u8 is_haswell:1; 184 u8 has_fbc:1; 185 u8 has_pipe_cxsr:1; 186 u8 has_hotplug:1; 187 u8 cursor_needs_physical:1; 188 u8 has_overlay:1; 189 u8 overlay_needs_physical:1; 190 u8 supports_tv:1; 191 u8 has_bsd_ring:1; 192 u8 has_blt_ring:1; 193 u8 has_llc:1; 194}; 195 196#define I915_PPGTT_PD_ENTRIES 512 197#define I915_PPGTT_PT_ENTRIES 1024 198struct i915_hw_ppgtt { 199 unsigned num_pd_entries; 200 vm_page_t *pt_pages; 201 uint32_t pd_offset; 202 vm_paddr_t *pt_dma_addr; 203 vm_paddr_t scratch_page_dma_addr; 204}; 205 206 207/* This must match up with the value previously used for execbuf2.rsvd1. */ 208#define DEFAULT_CONTEXT_ID 0 209struct i915_hw_context { 210 uint32_t id; 211 bool is_initialized; 212 struct drm_i915_file_private *file_priv; 213 struct intel_ring_buffer *ring; 214 struct drm_i915_gem_object *obj; 215}; 216 217enum no_fbc_reason { 218 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 219 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 220 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 221 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 222 FBC_BAD_PLANE, /* fbc not supported on plane */ 223 FBC_NOT_TILED, /* buffer not tiled */ 224 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 225 FBC_MODULE_PARAM, 226}; 227 228struct mem_block { 229 struct mem_block *next; 230 struct mem_block *prev; 231 int start; 232 int size; 233 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 234}; 235 236struct opregion_header; 237struct opregion_acpi; 238struct opregion_swsci; 239struct opregion_asle; 240 241struct intel_opregion { 242 struct opregion_header *header; 243 struct opregion_acpi *acpi; 244 struct opregion_swsci *swsci; 245 struct opregion_asle *asle; 246 void *vbt; 247 u32 *lid_state; 248}; 249#define OPREGION_SIZE (8*1024) 250 251#define I915_FENCE_REG_NONE -1 252#define I915_MAX_NUM_FENCES 16 253/* 16 fences + sign bit for FENCE_REG_NONE */ 254#define I915_MAX_NUM_FENCE_BITS 5 255 256struct drm_i915_fence_reg { 257 struct list_head lru_list; 258 struct drm_i915_gem_object *obj; 259 int pin_count; 260}; 261 262struct sdvo_device_mapping { 263 u8 initialized; 264 u8 dvo_port; 265 u8 slave_addr; 266 u8 dvo_wiring; 267 u8 i2c_pin; 268 u8 ddc_pin; 269}; 270 271enum intel_pch { 272 PCH_IBX, /* Ibexpeak PCH */ 273 PCH_CPT, /* Cougarpoint PCH */ 274 PCH_LPT, /* Lynxpoint PCH */ 275}; 276 277#define QUIRK_PIPEA_FORCE (1<<0) 278#define QUIRK_LVDS_SSC_DISABLE (1<<1) 279#define QUIRK_INVERT_BRIGHTNESS (1<<2) 280 281struct intel_fbdev; 282struct intel_fbc_work; 283 284typedef struct drm_i915_private { 285 struct drm_device *dev; 286 287 device_t gmbus_bridge[GMBUS_NUM_PORTS + 1]; 288 device_t bbbus_bridge[GMBUS_NUM_PORTS + 1]; 289 device_t gmbus[GMBUS_NUM_PORTS + 1]; 290 device_t bbbus[GMBUS_NUM_PORTS + 1]; 291 /** gmbus_sx protects against concurrent usage of the single hw gmbus 292 * controller on different i2c buses. */ 293 struct sx gmbus_sx; 294 uint32_t gpio_mmio_base; 295 296 int relative_constants_mode; 297 298 drm_local_map_t *sarea; 299 drm_local_map_t *mmio_map; 300 301 /** gt_fifo_count and the subsequent register write are synchronized 302 * with dev->struct_mutex. */ 303 unsigned gt_fifo_count; 304 /** forcewake_count is protected by gt_lock */ 305 unsigned forcewake_count; 306 /** gt_lock is also taken in irq contexts. */ 307 struct mtx gt_lock; 308 309 drm_i915_sarea_t *sarea_priv; 310 /* drm_i915_ring_buffer_t ring; */ 311 struct intel_ring_buffer rings[I915_NUM_RINGS]; 312 uint32_t next_seqno; 313 314 drm_dma_handle_t *status_page_dmah; 315 void *hw_status_page; 316 dma_addr_t dma_status_page; 317 uint32_t counter; 318 unsigned int status_gfx_addr; 319 struct drm_gem_object *hws_obj; 320 321 struct drm_i915_gem_object *pwrctx; 322 struct drm_i915_gem_object *renderctx; 323 324 unsigned int cpp; 325 int back_offset; 326 int front_offset; 327 int current_page; 328 int page_flipping; 329 330 atomic_t irq_received; 331 u32 trace_irq_seqno; 332 333 /** Cached value of IER to avoid reads in updating the bitfield */ 334 u32 pipestat[2]; 335 u32 irq_mask; 336 u32 gt_irq_mask; 337 u32 pch_irq_mask; 338 struct mtx irq_lock; 339 340 struct mtx dpio_lock; 341 342 u32 hotplug_supported_mask; 343 344 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 345 int num_pipe; 346 int num_pch_pll; 347 348 /* For hangcheck timer */ 349#define DRM_I915_HANGCHECK_PERIOD ((1500 /* in ms */ * hz) / 1000) 350 int hangcheck_count; 351 uint32_t last_acthd[I915_NUM_RINGS]; 352 uint32_t last_instdone; 353 uint32_t last_instdone1; 354 355 unsigned int stop_rings; 356 357 struct intel_opregion opregion; 358 359 360 /* overlay */ 361 struct intel_overlay *overlay; 362 bool sprite_scaling_enabled; 363 364 /* LVDS info */ 365 int backlight_level; /* restore backlight to this value */ 366 bool backlight_enabled; 367 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 368 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 369 370 /* Feature bits from the VBIOS */ 371 unsigned int int_tv_support:1; 372 unsigned int lvds_dither:1; 373 unsigned int lvds_vbt:1; 374 unsigned int int_crt_support:1; 375 unsigned int lvds_use_ssc:1; 376 unsigned int display_clock_mode:1; 377 int lvds_ssc_freq; 378 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 379 unsigned int lvds_val; /* used for checking LVDS channel mode */ 380 struct { 381 int rate; 382 int lanes; 383 int preemphasis; 384 int vswing; 385 386 bool initialized; 387 bool support; 388 int bpp; 389 struct edp_power_seq pps; 390 } edp; 391 bool no_aux_handshake; 392 393 int crt_ddc_pin; 394 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 395 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 396 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 397 398 /* PCH chipset type */ 399 enum intel_pch pch_type; 400 401 /* Display functions */ 402 struct drm_i915_display_funcs display; 403 404 unsigned long quirks; 405 406 /* Register state */ 407 bool modeset_on_lid; 408 u8 saveLBB; 409 u32 saveDSPACNTR; 410 u32 saveDSPBCNTR; 411 u32 saveDSPARB; 412 u32 saveHWS; 413 u32 savePIPEACONF; 414 u32 savePIPEBCONF; 415 u32 savePIPEASRC; 416 u32 savePIPEBSRC; 417 u32 saveFPA0; 418 u32 saveFPA1; 419 u32 saveDPLL_A; 420 u32 saveDPLL_A_MD; 421 u32 saveHTOTAL_A; 422 u32 saveHBLANK_A; 423 u32 saveHSYNC_A; 424 u32 saveVTOTAL_A; 425 u32 saveVBLANK_A; 426 u32 saveVSYNC_A; 427 u32 saveBCLRPAT_A; 428 u32 saveTRANSACONF; 429 u32 saveTRANS_HTOTAL_A; 430 u32 saveTRANS_HBLANK_A; 431 u32 saveTRANS_HSYNC_A; 432 u32 saveTRANS_VTOTAL_A; 433 u32 saveTRANS_VBLANK_A; 434 u32 saveTRANS_VSYNC_A; 435 u32 savePIPEASTAT; 436 u32 saveDSPASTRIDE; 437 u32 saveDSPASIZE; 438 u32 saveDSPAPOS; 439 u32 saveDSPAADDR; 440 u32 saveDSPASURF; 441 u32 saveDSPATILEOFF; 442 u32 savePFIT_PGM_RATIOS; 443 u32 saveBLC_HIST_CTL; 444 u32 saveBLC_PWM_CTL; 445 u32 saveBLC_PWM_CTL2; 446 u32 saveBLC_CPU_PWM_CTL; 447 u32 saveBLC_CPU_PWM_CTL2; 448 u32 saveFPB0; 449 u32 saveFPB1; 450 u32 saveDPLL_B; 451 u32 saveDPLL_B_MD; 452 u32 saveHTOTAL_B; 453 u32 saveHBLANK_B; 454 u32 saveHSYNC_B; 455 u32 saveVTOTAL_B; 456 u32 saveVBLANK_B; 457 u32 saveVSYNC_B; 458 u32 saveBCLRPAT_B; 459 u32 saveTRANSBCONF; 460 u32 saveTRANS_HTOTAL_B; 461 u32 saveTRANS_HBLANK_B; 462 u32 saveTRANS_HSYNC_B; 463 u32 saveTRANS_VTOTAL_B; 464 u32 saveTRANS_VBLANK_B; 465 u32 saveTRANS_VSYNC_B; 466 u32 savePIPEBSTAT; 467 u32 saveDSPBSTRIDE; 468 u32 saveDSPBSIZE; 469 u32 saveDSPBPOS; 470 u32 saveDSPBADDR; 471 u32 saveDSPBSURF; 472 u32 saveDSPBTILEOFF; 473 u32 saveVGA0; 474 u32 saveVGA1; 475 u32 saveVGA_PD; 476 u32 saveVGACNTRL; 477 u32 saveADPA; 478 u32 saveLVDS; 479 u32 savePP_ON_DELAYS; 480 u32 savePP_OFF_DELAYS; 481 u32 saveDVOA; 482 u32 saveDVOB; 483 u32 saveDVOC; 484 u32 savePP_ON; 485 u32 savePP_OFF; 486 u32 savePP_CONTROL; 487 u32 savePP_DIVISOR; 488 u32 savePFIT_CONTROL; 489 u32 save_palette_a[256]; 490 u32 save_palette_b[256]; 491 u32 saveDPFC_CB_BASE; 492 u32 saveFBC_CFB_BASE; 493 u32 saveFBC_LL_BASE; 494 u32 saveFBC_CONTROL; 495 u32 saveFBC_CONTROL2; 496 u32 saveIER; 497 u32 saveIIR; 498 u32 saveIMR; 499 u32 saveDEIER; 500 u32 saveDEIMR; 501 u32 saveGTIER; 502 u32 saveGTIMR; 503 u32 saveFDI_RXA_IMR; 504 u32 saveFDI_RXB_IMR; 505 u32 saveCACHE_MODE_0; 506 u32 saveMI_ARB_STATE; 507 u32 saveSWF0[16]; 508 u32 saveSWF1[16]; 509 u32 saveSWF2[3]; 510 u8 saveMSR; 511 u8 saveSR[8]; 512 u8 saveGR[25]; 513 u8 saveAR_INDEX; 514 u8 saveAR[21]; 515 u8 saveDACMASK; 516 u8 saveCR[37]; 517 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 518 u32 saveCURACNTR; 519 u32 saveCURAPOS; 520 u32 saveCURABASE; 521 u32 saveCURBCNTR; 522 u32 saveCURBPOS; 523 u32 saveCURBBASE; 524 u32 saveCURSIZE; 525 u32 saveDP_B; 526 u32 saveDP_C; 527 u32 saveDP_D; 528 u32 savePIPEA_GMCH_DATA_M; 529 u32 savePIPEB_GMCH_DATA_M; 530 u32 savePIPEA_GMCH_DATA_N; 531 u32 savePIPEB_GMCH_DATA_N; 532 u32 savePIPEA_DP_LINK_M; 533 u32 savePIPEB_DP_LINK_M; 534 u32 savePIPEA_DP_LINK_N; 535 u32 savePIPEB_DP_LINK_N; 536 u32 saveFDI_RXA_CTL; 537 u32 saveFDI_TXA_CTL; 538 u32 saveFDI_RXB_CTL; 539 u32 saveFDI_TXB_CTL; 540 u32 savePFA_CTL_1; 541 u32 savePFB_CTL_1; 542 u32 savePFA_WIN_SZ; 543 u32 savePFB_WIN_SZ; 544 u32 savePFA_WIN_POS; 545 u32 savePFB_WIN_POS; 546 u32 savePCH_DREF_CONTROL; 547 u32 saveDISP_ARB_CTL; 548 u32 savePIPEA_DATA_M1; 549 u32 savePIPEA_DATA_N1; 550 u32 savePIPEA_LINK_M1; 551 u32 savePIPEA_LINK_N1; 552 u32 savePIPEB_DATA_M1; 553 u32 savePIPEB_DATA_N1; 554 u32 savePIPEB_LINK_M1; 555 u32 savePIPEB_LINK_N1; 556 u32 saveMCHBAR_RENDER_STANDBY; 557 u32 savePCH_PORT_HOTPLUG; 558 559 struct { 560 /** Memory allocator for GTT stolen memory */ 561 struct drm_mm stolen; 562 /** Memory allocator for GTT */ 563 struct drm_mm gtt_space; 564 /** List of all objects in gtt_space. Used to restore gtt 565 * mappings on resume */ 566 struct list_head gtt_list; 567 568 /** Usable portion of the GTT for GEM */ 569 unsigned long gtt_start; 570 unsigned long gtt_mappable_end; 571 unsigned long gtt_end; 572 573 /** PPGTT used for aliasing the PPGTT with the GTT */ 574 struct i915_hw_ppgtt *aliasing_ppgtt; 575 576 /** 577 * List of objects currently involved in rendering from the 578 * ringbuffer. 579 * 580 * Includes buffers having the contents of their GPU caches 581 * flushed, not necessarily primitives. last_rendering_seqno 582 * represents when the rendering involved will be completed. 583 * 584 * A reference is held on the buffer while on this list. 585 */ 586 struct list_head active_list; 587 588 /** 589 * List of objects which are not in the ringbuffer but which 590 * still have a write_domain which needs to be flushed before 591 * unbinding. 592 * 593 * A reference is held on the buffer while on this list. 594 */ 595 struct list_head flushing_list; 596 597 /** 598 * LRU list of objects which are not in the ringbuffer and 599 * are ready to unbind, but are still in the GTT. 600 * 601 * last_rendering_seqno is 0 while an object is in this list. 602 * 603 * A reference is not held on the buffer while on this list, 604 * as merely being GTT-bound shouldn't prevent its being 605 * freed, and we'll pull it off the list in the free path. 606 */ 607 struct list_head inactive_list; 608 609 /** LRU list of objects with fence regs on them. */ 610 struct list_head fence_list; 611 612 /** 613 * We leave the user IRQ off as much as possible, 614 * but this means that requests will finish and never 615 * be retired once the system goes idle. Set a timer to 616 * fire periodically while the ring is running. When it 617 * fires, go retire requests. 618 */ 619 struct timeout_task retire_task; 620 621 /** 622 * Are we in a non-interruptible section of code like 623 * modesetting? 624 */ 625 bool interruptible; 626 627 uint32_t next_gem_seqno; 628 629 /** 630 * Waiting sequence number, if any 631 */ 632 uint32_t waiting_gem_seqno; 633 634 /** 635 * Last seq seen at irq time 636 */ 637 uint32_t irq_gem_seqno; 638 639 /** 640 * Flag if the X Server, and thus DRM, is not currently in 641 * control of the device. 642 * 643 * This is set between LeaveVT and EnterVT. It needs to be 644 * replaced with a semaphore. It also needs to be 645 * transitioned away from for kernel modesetting. 646 */ 647 int suspended; 648 649 /** 650 * Flag if the hardware appears to be wedged. 651 * 652 * This is set when attempts to idle the device timeout. 653 * It prevents command submission from occuring and makes 654 * every pending request fail 655 */ 656 int wedged; 657 658 /** Bit 6 swizzling required for X tiling */ 659 uint32_t bit_6_swizzle_x; 660 /** Bit 6 swizzling required for Y tiling */ 661 uint32_t bit_6_swizzle_y; 662 663 /* storage for physical objects */ 664 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 665 666 /* accounting, useful for userland debugging */ 667 size_t gtt_total; 668 size_t mappable_gtt_total; 669 size_t object_memory; 670 u32 object_count; 671 672 struct intel_gtt gtt; 673 eventhandler_tag i915_lowmem; 674 } mm; 675 676 const struct intel_device_info *info; 677 678 /* Old dri1 support infrastructure, beware the dragons ya fools entering 679 * here! */ 680 struct { 681 unsigned allow_batchbuffer : 1; 682 u32 *gfx_hws_cpu_addr; 683 } dri1; 684 685 /* Kernel Modesetting */ 686 687 struct sdvo_device_mapping sdvo_mappings[2]; 688 /* indicate whether the LVDS_BORDER should be enabled or not */ 689 unsigned int lvds_border_bits; 690 /* Panel fitter placement and size for Ironlake+ */ 691 u32 pch_pf_pos, pch_pf_size; 692 693 struct drm_crtc *plane_to_crtc_mapping[3]; 694 struct drm_crtc *pipe_to_crtc_mapping[3]; 695 /* wait_queue_head_t pending_flip_queue; XXXKIB */ 696 697 struct intel_pch_pll pch_plls[I915_NUM_PLLS]; 698 699 /* Reclocking support */ 700 bool render_reclock_avail; 701 bool lvds_downclock_avail; 702 /* indicates the reduced downclock for LVDS*/ 703 int lvds_downclock; 704 struct task idle_task; 705 struct callout idle_callout; 706 bool busy; 707 u16 orig_clock; 708 int child_dev_num; 709 struct child_device_config *child_dev; 710 struct drm_connector *int_lvds_connector; 711 struct drm_connector *int_edp_connector; 712 713 device_t bridge_dev; 714 bool mchbar_need_disable; 715 int mch_res_rid; 716 struct resource *mch_res; 717 718 struct mtx rps_lock; 719 u32 pm_iir; 720 struct task rps_task; 721 722 u8 cur_delay; 723 u8 min_delay; 724 u8 max_delay; 725 u8 fmax; 726 u8 fstart; 727 728 u64 last_count1; 729 unsigned long last_time1; 730 unsigned long chipset_power; 731 u64 last_count2; 732 struct timespec last_time2; 733 unsigned long gfx_power; 734 int c_m; 735 int r_t; 736 u8 corr; 737 struct mtx *mchdev_lock; 738 739 enum no_fbc_reason no_fbc_reason; 740 741 struct drm_mm_node *compressed_fb; 742 struct drm_mm_node *compressed_llb; 743 744 unsigned long cfb_size; 745 unsigned int cfb_fb; 746 int cfb_plane; 747 int cfb_y; 748 struct intel_fbc_work *fbc_work; 749 750 unsigned int fsb_freq, mem_freq, is_ddr3; 751 752 struct taskqueue *tq; 753 struct task error_task; 754 struct task hotplug_task; 755 int error_completion; 756 struct mtx error_completion_lock; 757 /* Protected by dev->error_lock. */ 758 struct drm_i915_error_state *first_error; 759 struct mtx error_lock; 760 struct callout hangcheck_timer; 761 762 unsigned long last_gpu_reset; 763 764 struct intel_fbdev *fbdev; 765 766 struct drm_property *broadcast_rgb_property; 767 struct drm_property *force_audio_property; 768 769 bool hw_contexts_disabled; 770 uint32_t hw_context_size; 771} drm_i915_private_t; 772 773/* Iterate over initialised rings */ 774#define for_each_ring(ring__, dev_priv__, i__) \ 775 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 776 if (((ring__) = &(dev_priv__)->rings[(i__)]), intel_ring_initialized((ring__))) 777 778enum hdmi_force_audio { 779 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 780 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 781 HDMI_AUDIO_AUTO, /* trust EDID */ 782 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 783}; 784 785enum i915_cache_level { 786 I915_CACHE_NONE, 787 I915_CACHE_LLC, 788 I915_CACHE_LLC_MLC, /* gen6+ */ 789}; 790 791enum intel_chip_family { 792 CHIP_I8XX = 0x01, 793 CHIP_I9XX = 0x02, 794 CHIP_I915 = 0x04, 795 CHIP_I965 = 0x08, 796}; 797 798/** driver private structure attached to each drm_gem_object */ 799struct drm_i915_gem_object { 800 struct drm_gem_object base; 801 802 /** Current space allocated to this object in the GTT, if any. */ 803 struct drm_mm_node *gtt_space; 804 struct list_head gtt_list; 805 /** This object's place on the active/flushing/inactive lists */ 806 struct list_head ring_list; 807 struct list_head mm_list; 808 /** This object's place on GPU write list */ 809 struct list_head gpu_write_list; 810 /** This object's place in the batchbuffer or on the eviction list */ 811 struct list_head exec_list; 812 813 /** 814 * This is set if the object is on the active or flushing lists 815 * (has pending rendering), and is not set if it's on inactive (ready 816 * to be unbound). 817 */ 818 unsigned int active:1; 819 820 /** 821 * This is set if the object has been written to since last bound 822 * to the GTT 823 */ 824 unsigned int dirty:1; 825 826 /** 827 * This is set if the object has been written to since the last 828 * GPU flush. 829 */ 830 unsigned int pending_gpu_write:1; 831 832 /** 833 * Fence register bits (if any) for this object. Will be set 834 * as needed when mapped into the GTT. 835 * Protected by dev->struct_mutex. 836 */ 837 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 838 839 /** 840 * Advice: are the backing pages purgeable? 841 */ 842 unsigned int madv:2; 843 844 /** 845 * Current tiling mode for the object. 846 */ 847 unsigned int tiling_mode:2; 848 /** 849 * Whether the tiling parameters for the currently associated fence 850 * register have changed. Note that for the purposes of tracking 851 * tiling changes we also treat the unfenced register, the register 852 * slot that the object occupies whilst it executes a fenced 853 * command (such as BLT on gen2/3), as a "fence". 854 */ 855 unsigned int fence_dirty:1; 856 857 /** How many users have pinned this object in GTT space. The following 858 * users can each hold at most one reference: pwrite/pread, pin_ioctl 859 * (via user_pin_count), execbuffer (objects are not allowed multiple 860 * times for the same batchbuffer), and the framebuffer code. When 861 * switching/pageflipping, the framebuffer code has at most two buffers 862 * pinned per crtc. 863 * 864 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 865 * bits with absolutely no headroom. So use 4 bits. */ 866 unsigned int pin_count:4; 867#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 868 869 /** 870 * Is the object at the current location in the gtt mappable and 871 * fenceable? Used to avoid costly recalculations. 872 */ 873 unsigned int map_and_fenceable:1; 874 875 /** 876 * Whether the current gtt mapping needs to be mappable (and isn't just 877 * mappable by accident). Track pin and fault separate for a more 878 * accurate mappable working set. 879 */ 880 unsigned int fault_mappable:1; 881 unsigned int pin_mappable:1; 882 unsigned int pin_display:1; 883 884 /* 885 * Is the GPU currently using a fence to access this buffer, 886 */ 887 unsigned int pending_fenced_gpu_access:1; 888 unsigned int fenced_gpu_access:1; 889 890 unsigned int cache_level:2; 891 892 unsigned int has_aliasing_ppgtt_mapping:1; 893 unsigned int has_global_gtt_mapping:1; 894 895 vm_page_t *pages; 896 int pages_pin_count; 897 898 /** 899 * DMAR support 900 */ 901 struct sglist *sg_list; 902 903 /** 904 * Used for performing relocations during execbuffer insertion. 905 */ 906 LIST_ENTRY(drm_i915_gem_object) exec_node; 907 unsigned long exec_handle; 908 struct drm_i915_gem_exec_object2 *exec_entry; 909 910 /** 911 * Current offset of the object in GTT space. 912 * 913 * This is the same as gtt_space->start 914 */ 915 uint32_t gtt_offset; 916 917 struct intel_ring_buffer *ring; 918 919 /** Breadcrumb of last rendering to the buffer. */ 920 uint32_t last_rendering_seqno; 921 /** Breadcrumb of last fenced GPU access to the buffer. */ 922 uint32_t last_fenced_seqno; 923 924 /** Current tiling stride for the object, if it's tiled. */ 925 uint32_t stride; 926 927 /** Record of address bit 17 of each page at last unbind. */ 928 unsigned long *bit_17; 929 930 /** User space pin count and filp owning the pin */ 931 uint32_t user_pin_count; 932 struct drm_file *pin_filp; 933 934 /** for phy allocated objects */ 935 struct drm_i915_gem_phys_object *phys_obj; 936 937 /** 938 * Number of crtcs where this object is currently the fb, but 939 * will be page flipped away on the next vblank. When it 940 * reaches 0, dev_priv->pending_flip_queue will be woken up. 941 */ 942 int pending_flip; 943}; 944 945#define to_intel_bo(x) __containerof(x, struct drm_i915_gem_object, base) 946 947/** 948 * Request queue structure. 949 * 950 * The request queue allows us to note sequence numbers that have been emitted 951 * and may be associated with active buffers to be retired. 952 * 953 * By keeping this list, we can avoid having to do questionable 954 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 955 * an emission time with seqnos for tracking how far ahead of the GPU we are. 956 */ 957struct drm_i915_gem_request { 958 /** On Which ring this request was generated */ 959 struct intel_ring_buffer *ring; 960 961 /** GEM sequence number associated with this request. */ 962 uint32_t seqno; 963 964 /** Postion in the ringbuffer of the end of the request */ 965 u32 tail; 966 967 /** Time at which this request was emitted, in jiffies. */ 968 unsigned long emitted_jiffies; 969 970 /** global list entry for this request */ 971 struct list_head list; 972 973 struct drm_i915_file_private *file_priv; 974 /** file_priv list entry for this request */ 975 struct list_head client_list; 976}; 977 978struct drm_i915_file_private { 979 struct { 980 struct list_head request_list; 981 struct mtx lck; 982 } mm; 983 struct drm_gem_names context_idr; 984}; 985 986struct drm_i915_error_state { 987 u_int ref; 988 u32 eir; 989 u32 pgtbl_er; 990 u32 ier; 991 bool waiting[I915_NUM_RINGS]; 992 u32 pipestat[I915_MAX_PIPES]; 993 u32 tail[I915_NUM_RINGS]; 994 u32 head[I915_NUM_RINGS]; 995 u32 ipeir[I915_NUM_RINGS]; 996 u32 ipehr[I915_NUM_RINGS]; 997 u32 instdone[I915_NUM_RINGS]; 998 u32 acthd[I915_NUM_RINGS]; 999 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 1000 /* our own tracking of ring head and tail */ 1001 u32 cpu_ring_head[I915_NUM_RINGS]; 1002 u32 cpu_ring_tail[I915_NUM_RINGS]; 1003 u32 error; /* gen6+ */ 1004 u32 instpm[I915_NUM_RINGS]; 1005 u32 instps[I915_NUM_RINGS]; 1006 u32 instdone1; 1007 u32 seqno[I915_NUM_RINGS]; 1008 u64 bbaddr; 1009 u32 fault_reg[I915_NUM_RINGS]; 1010 u32 done_reg; 1011 u32 faddr[I915_NUM_RINGS]; 1012 u64 fence[I915_MAX_NUM_FENCES]; 1013 struct timeval time; 1014 struct drm_i915_error_ring { 1015 struct drm_i915_error_object { 1016 int page_count; 1017 u32 gtt_offset; 1018 u32 *pages[0]; 1019 } *ringbuffer, *batchbuffer; 1020 struct drm_i915_error_request { 1021 long jiffies; 1022 u32 seqno; 1023 u32 tail; 1024 } *requests; 1025 int num_requests; 1026 } ring[I915_NUM_RINGS]; 1027 struct drm_i915_error_buffer { 1028 u32 size; 1029 u32 name; 1030 u32 seqno; 1031 u32 gtt_offset; 1032 u32 read_domains; 1033 u32 write_domain; 1034 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 1035 s32 pinned:2; 1036 u32 tiling:2; 1037 u32 dirty:1; 1038 u32 purgeable:1; 1039 s32 ring:4; 1040 u32 cache_level:2; 1041 } *active_bo, *pinned_bo; 1042 u32 active_bo_count, pinned_bo_count; 1043 struct intel_overlay_error_state *overlay; 1044 struct intel_display_error_state *display; 1045}; 1046 1047/** 1048 * RC6 is a special power stage which allows the GPU to enter an very 1049 * low-voltage mode when idle, using down to 0V while at this stage. This 1050 * stage is entered automatically when the GPU is idle when RC6 support is 1051 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1052 * 1053 * There are different RC6 modes available in Intel GPU, which differentiate 1054 * among each other with the latency required to enter and leave RC6 and 1055 * voltage consumed by the GPU in different states. 1056 * 1057 * The combination of the following flags define which states GPU is allowed 1058 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1059 * RC6pp is deepest RC6. Their support by hardware varies according to the 1060 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1061 * which brings the most power savings; deeper states save more power, but 1062 * require higher latency to switch to and wake up. 1063 */ 1064#define INTEL_RC6_ENABLE (1<<0) 1065#define INTEL_RC6p_ENABLE (1<<1) 1066#define INTEL_RC6pp_ENABLE (1<<2) 1067 1068extern int intel_iommu_enabled; 1069extern struct drm_ioctl_desc i915_ioctls[]; 1070extern struct drm_driver_info i915_driver_info; 1071extern struct cdev_pager_ops i915_gem_pager_ops; 1072extern unsigned int i915_fbpercrtc; 1073extern int i915_panel_ignore_lid; 1074extern int i915_panel_invert_brightness; 1075extern unsigned int i915_powersave; 1076extern int i915_prefault_disable; 1077extern int i915_semaphores; 1078extern unsigned int i915_lvds_downclock; 1079extern int i915_lvds_channel_mode; 1080extern int i915_panel_use_ssc; 1081extern int i915_vbt_sdvo_panel_type; 1082extern int i915_enable_rc6; 1083extern int i915_enable_fbc; 1084extern int i915_enable_ppgtt; 1085extern int i915_enable_hangcheck; 1086 1087const struct intel_device_info *i915_get_device_id(int device); 1088 1089int i915_reset(struct drm_device *dev); 1090extern int intel_gpu_reset(struct drm_device *dev); 1091 1092/* i915_debug.c */ 1093int i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 1094 struct sysctl_oid *top); 1095void i915_sysctl_cleanup(struct drm_device *dev); 1096 1097 /* i915_dma.c */ 1098int i915_batchbuffer(struct drm_device *dev, void *data, 1099 struct drm_file *file_priv); 1100int i915_cmdbuffer(struct drm_device *dev, void *data, 1101 struct drm_file *file_priv); 1102int i915_getparam(struct drm_device *dev, void *data, 1103 struct drm_file *file_priv); 1104void i915_update_dri1_breadcrumb(struct drm_device *dev); 1105extern void i915_kernel_lost_context(struct drm_device * dev); 1106extern int i915_driver_load(struct drm_device *, unsigned long flags); 1107extern int i915_driver_unload(struct drm_device *); 1108extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1109extern void i915_driver_lastclose(struct drm_device * dev); 1110extern void i915_driver_preclose(struct drm_device *dev, 1111 struct drm_file *file_priv); 1112extern void i915_driver_postclose(struct drm_device *dev, 1113 struct drm_file *file_priv); 1114extern int i915_driver_device_is_agp(struct drm_device * dev); 1115extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1116 unsigned long arg); 1117extern int i915_emit_box(struct drm_device *dev, 1118 struct drm_clip_rect __user *boxes, 1119 int i, int DR1, int DR4); 1120int i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box, 1121 int DR1, int DR4); 1122 1123unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1124unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1125void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1126unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1127unsigned long i915_read_mch_val(void); 1128bool i915_gpu_raise(void); 1129bool i915_gpu_lower(void); 1130bool i915_gpu_busy(void); 1131bool i915_gpu_turbo_disable(void); 1132 1133/* i915_irq.c */ 1134extern int i915_irq_emit(struct drm_device *dev, void *data, 1135 struct drm_file *file_priv); 1136extern void intel_irq_init(struct drm_device *dev); 1137 1138void intel_enable_asle(struct drm_device *dev); 1139void i915_hangcheck_elapsed(void *context); 1140void i915_handle_error(struct drm_device *dev, bool wedged); 1141void i915_error_state_free(struct drm_i915_error_state *error); 1142 1143void i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1144void i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1145 1146void i915_destroy_error_state(struct drm_device *dev); 1147 1148/* i915_gem.c */ 1149int i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size, 1150 uint32_t *handle_p); 1151int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1152 struct drm_file *file_priv); 1153int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1154 struct drm_file *file_priv); 1155int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1156 struct drm_file *file_priv); 1157int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1158 struct drm_file *file_priv); 1159int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1160 struct drm_file *file_priv); 1161int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1162 struct drm_file *file_priv); 1163int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1164 struct drm_file *file_priv); 1165int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1166 struct drm_file *file_priv); 1167int i915_gem_execbuffer(struct drm_device *dev, void *data, 1168 struct drm_file *file_priv); 1169int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1170 struct drm_file *file_priv); 1171int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1172 struct drm_file *file_priv); 1173int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1174 struct drm_file *file_priv); 1175int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1176 struct drm_file *file_priv); 1177int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1178 struct drm_file *file_priv); 1179int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1180 struct drm_file *file_priv); 1181int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1182 struct drm_file *file_priv); 1183int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1184 struct drm_file *file_priv); 1185int i915_gem_set_tiling(struct drm_device *dev, void *data, 1186 struct drm_file *file_priv); 1187int i915_gem_get_tiling(struct drm_device *dev, void *data, 1188 struct drm_file *file_priv); 1189int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1190 struct drm_file *file_priv); 1191void i915_gem_load(struct drm_device *dev); 1192void i915_gem_unload(struct drm_device *dev); 1193int i915_gem_init_object(struct drm_gem_object *obj); 1194void i915_gem_free_object(struct drm_gem_object *obj); 1195int i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment, 1196 bool map_and_fenceable); 1197void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1198int i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1199void i915_gem_lastclose(struct drm_device *dev); 1200uint32_t i915_get_gem_seqno(struct drm_device *dev); 1201 1202static inline bool 1203i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1204{ 1205 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1206 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1207 dev_priv->fence_regs[obj->fence_reg].pin_count++; 1208 return true; 1209 } else 1210 return false; 1211} 1212 1213static inline void 1214i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1215{ 1216 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1217 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1218 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1219 } 1220} 1221 1222void i915_gem_retire_requests(struct drm_device *dev); 1223void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1224void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1225struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1226 size_t size); 1227uint32_t i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1228 uint32_t size, int tiling_mode); 1229int i915_mutex_lock_interruptible(struct drm_device *dev); 1230int i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1231 bool write); 1232int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, 1233 bool write); 1234int i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1235 u32 alignment, struct intel_ring_buffer *pipelined); 1236void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); 1237int i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1238int i915_gem_flush_ring(struct intel_ring_buffer *ring, 1239 uint32_t invalidate_domains, uint32_t flush_domains); 1240void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1241int i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); 1242int i915_gem_object_sync(struct drm_i915_gem_object *obj, 1243 struct intel_ring_buffer *to); 1244int i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1245int i915_gem_idle(struct drm_device *dev); 1246int i915_gem_init(struct drm_device *dev); 1247int i915_gem_init_hw(struct drm_device *dev); 1248void i915_gem_init_swizzling(struct drm_device *dev); 1249void i915_gem_init_ppgtt(struct drm_device *dev); 1250void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1251int i915_gpu_idle(struct drm_device *dev); 1252void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1253 struct intel_ring_buffer *ring, uint32_t seqno); 1254int i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file, 1255 struct drm_i915_gem_request *request); 1256int i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 1257void i915_gem_reset(struct drm_device *dev); 1258int i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno); 1259int i915_gem_mmap(struct drm_device *dev, uint64_t offset, int prot); 1260int i915_gem_fault(struct drm_device *dev, uint64_t offset, int prot, 1261 uint64_t *phys); 1262void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1263int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1264 enum i915_cache_level cache_level); 1265 1266/* i915_gem_context.c */ 1267void i915_gem_context_init(struct drm_device *dev); 1268void i915_gem_context_fini(struct drm_device *dev); 1269void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 1270int i915_switch_context(struct intel_ring_buffer *ring, 1271 struct drm_file *file, int to_id); 1272int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 1273 struct drm_file *file); 1274int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 1275 struct drm_file *file); 1276 1277void i915_gem_free_all_phys_object(struct drm_device *dev); 1278void i915_gem_detach_phys_object(struct drm_device *dev, 1279 struct drm_i915_gem_object *obj); 1280int i915_gem_attach_phys_object(struct drm_device *dev, 1281 struct drm_i915_gem_object *obj, int id, int align); 1282 1283int i915_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, 1284 struct drm_mode_create_dumb *args); 1285int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1286 uint32_t handle, uint64_t *offset); 1287int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1288 uint32_t handle); 1289 1290/* i915_gem_tiling.c */ 1291void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1292void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1293void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1294void i915_gem_object_do_bit_17_swizzle_page(struct drm_i915_gem_object *obj, 1295 struct vm_page *m); 1296 1297/* i915_gem_evict.c */ 1298int i915_gem_evict_something(struct drm_device *dev, int min_size, 1299 unsigned alignment, bool mappable); 1300int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only); 1301 1302/* i915_gem_stolen.c */ 1303int i915_gem_init_stolen(struct drm_device *dev); 1304void i915_gem_cleanup_stolen(struct drm_device *dev); 1305 1306/* i915_suspend.c */ 1307extern int i915_save_state(struct drm_device *dev); 1308extern int i915_restore_state(struct drm_device *dev); 1309 1310/* intel_iic.c */ 1311extern int intel_setup_gmbus(struct drm_device *dev); 1312extern void intel_teardown_gmbus(struct drm_device *dev); 1313extern void intel_gmbus_set_speed(device_t idev, int speed); 1314extern void intel_gmbus_force_bit(device_t idev, bool force_bit); 1315extern void intel_iic_reset(struct drm_device *dev); 1316static inline bool intel_gmbus_is_port_valid(unsigned port) 1317{ 1318 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 1319} 1320extern device_t intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 1321 unsigned port); 1322 1323/* intel_opregion.c */ 1324int intel_opregion_setup(struct drm_device *dev); 1325extern void intel_opregion_init(struct drm_device *dev); 1326extern void intel_opregion_fini(struct drm_device *dev); 1327extern void intel_opregion_asle_intr(struct drm_device *dev); 1328extern void intel_opregion_gse_intr(struct drm_device *dev); 1329extern void intel_opregion_enable_asle(struct drm_device *dev); 1330 1331/* i915_gem_gtt.c */ 1332int i915_gem_init_aliasing_ppgtt(struct drm_device *dev); 1333void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1334void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1335 struct drm_i915_gem_object *obj, enum i915_cache_level cache_level); 1336void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1337 struct drm_i915_gem_object *obj); 1338 1339void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1340int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 1341void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, 1342 enum i915_cache_level cache_level); 1343void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1344void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 1345int i915_gem_init_global_gtt(struct drm_device *dev, unsigned long start, 1346 unsigned long mappable_end, unsigned long end); 1347 1348/* modesetting */ 1349extern void intel_modeset_init_hw(struct drm_device *dev); 1350extern void intel_modeset_init(struct drm_device *dev); 1351extern void intel_modeset_gem_init(struct drm_device *dev); 1352extern void intel_modeset_cleanup(struct drm_device *dev); 1353extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1354extern bool intel_fbc_enabled(struct drm_device *dev); 1355extern void intel_disable_fbc(struct drm_device *dev); 1356extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1357extern void ironlake_init_pch_refclk(struct drm_device *dev); 1358extern void ironlake_enable_rc6(struct drm_device *dev); 1359extern void gen6_set_rps(struct drm_device *dev, u8 val); 1360extern void intel_detect_pch(struct drm_device *dev); 1361extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1362/* IPS */ 1363extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); 1364extern void intel_gpu_ips_teardown(void); 1365 1366extern bool i915_semaphore_is_enabled(struct drm_device *dev); 1367extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1368extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); 1369extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1370extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); 1371 1372extern void vlv_force_wake_get(struct drm_i915_private *dev_priv); 1373extern void vlv_force_wake_put(struct drm_i915_private *dev_priv); 1374 1375extern struct intel_overlay_error_state *intel_overlay_capture_error_state( 1376 struct drm_device *dev); 1377extern void intel_overlay_print_error_state(struct sbuf *m, 1378 struct intel_overlay_error_state *error); 1379extern struct intel_display_error_state *intel_display_capture_error_state( 1380 struct drm_device *dev); 1381extern void intel_display_print_error_state(struct sbuf *m, 1382 struct drm_device *dev, struct intel_display_error_state *error); 1383 1384static inline void 1385trace_i915_reg_rw(boolean_t rw, int reg, uint64_t val, int sz) 1386{ 1387 1388 CTR4(KTR_DRM_REG, "[%x/%d] %c %x", reg, sz, rw ? "w" : "r", val); 1389} 1390 1391/* On SNB platform, before reading ring registers forcewake bit 1392 * must be set to prevent GT core from power down and stale values being 1393 * returned. 1394 */ 1395void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1396void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1397int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1398 1399#define __i915_read(x, y) \ 1400 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1401 1402__i915_read(8, 8) 1403__i915_read(16, 16) 1404__i915_read(32, 32) 1405__i915_read(64, 64) 1406#undef __i915_read 1407 1408#define __i915_write(x, y) \ 1409 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1410 1411__i915_write(8, 8) 1412__i915_write(16, 16) 1413__i915_write(32, 32) 1414__i915_write(64, 64) 1415#undef __i915_write 1416 1417#define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1418#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1419 1420#define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1421#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1422#define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 1423#define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 1424 1425#define I915_READ(reg) i915_read32(dev_priv, (reg)) 1426#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1427#define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 1428#define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 1429 1430#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1431#define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1432 1433#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1434#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1435 1436#define I915_VERBOSE 0 1437 1438/** 1439 * Reads a dword out of the status page, which is written to from the command 1440 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 1441 * MI_STORE_DATA_IMM. 1442 * 1443 * The following dwords have a reserved meaning: 1444 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 1445 * 0x04: ring 0 head pointer 1446 * 0x05: ring 1 head pointer (915-class) 1447 * 0x06: ring 2 head pointer (915-class) 1448 * 0x10-0x1b: Context status DWords (GM45) 1449 * 0x1f: Last written status offset. (GM45) 1450 * 1451 * The area from dword 0x20 to 0x3ff is available for driver usage. 1452 */ 1453#define I915_GEM_HWS_INDEX 0x20 1454 1455#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1456 1457#define IS_I830(dev) ((dev)->pci_device == 0x3577) 1458#define IS_845G(dev) ((dev)->pci_device == 0x2562) 1459#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1460#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1461#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1462#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1463#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1464#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1465#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1466#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1467#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1468#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1469#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1470#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1471#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1472#define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1473#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1474#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1475#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1476#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1477#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1478#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1479 1480/* XXXKIB LEGACY */ 1481#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 1482 (dev)->pci_device == 0x2982 || \ 1483 (dev)->pci_device == 0x2992 || \ 1484 (dev)->pci_device == 0x29A2 || \ 1485 (dev)->pci_device == 0x2A02 || \ 1486 (dev)->pci_device == 0x2A12 || \ 1487 (dev)->pci_device == 0x2A42 || \ 1488 (dev)->pci_device == 0x2E02 || \ 1489 (dev)->pci_device == 0x2E12 || \ 1490 (dev)->pci_device == 0x2E22 || \ 1491 (dev)->pci_device == 0x2E32) 1492 1493#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 1494 1495#define IS_IGDG(dev) ((dev)->pci_device == 0xa001) 1496#define IS_IGDGM(dev) ((dev)->pci_device == 0xa011) 1497#define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) 1498 1499#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 1500 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 1501/* XXXKIB LEGACY END */ 1502 1503#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1504#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1505#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1506#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1507#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1508#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1509 1510#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1511#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1512#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1513#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1514 1515#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 1516#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) 1517 1518#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1519#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1520 1521/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1522 * rows, which changed the alignment requirements and fence programming. 1523 */ 1524#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1525 IS_I915GM(dev))) 1526#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1527#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1528#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1529#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1530#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1531#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1532/* dsparb controlled by hw only */ 1533#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1534 1535#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1536#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1537#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1538 1539#define HAS_PCH_SPLIT(dev) (INTEL_INFO(dev)->has_pch_split) 1540#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1541 1542#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1543#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 1544#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1545#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1546 1547#define PRIMARY_RINGBUFFER_SIZE (128*1024) 1548 1549static inline bool 1550i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1551{ 1552 1553 return ((int32_t)(seq1 - seq2) >= 0); 1554} 1555 1556static inline void i915_gem_chipset_flush(struct drm_device *dev) 1557{ 1558 if (INTEL_INFO(dev)->gen < 6) 1559 intel_gtt_chipset_flush(); 1560} 1561 1562static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 1563{ 1564 /* KASSERT(obj->pages != NULL, ("pin and NULL pages")); */ 1565 obj->pages_pin_count++; 1566} 1567static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 1568{ 1569 KASSERT(obj->pages_pin_count != 0, ("zero pages_pin_count")); 1570 obj->pages_pin_count--; 1571} 1572 1573u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); 1574 1575#endif 1576