i915_drm.h revision 302408
1/* 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27#ifndef _UAPI_I915_DRM_H_ 28#define _UAPI_I915_DRM_H_ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/11/sys/dev/drm2/i915/i915_drm.h 298955 2016-05-03 03:41:25Z pfg $"); 32 33#include <dev/drm2/drm.h> 34 35/* Please note that modifications to all structs defined here are 36 * subject to backwards-compatibility constraints. 37 */ 38 39 40/* Each region is a minimum of 16k, and there are at most 255 of them. 41 */ 42#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 43 * of chars for next/prev indices */ 44#define I915_LOG_MIN_TEX_REGION_SIZE 14 45 46typedef struct _drm_i915_init { 47 enum { 48 I915_INIT_DMA = 0x01, 49 I915_CLEANUP_DMA = 0x02, 50 I915_RESUME_DMA = 0x03 51 } func; 52 unsigned int mmio_offset; 53 int sarea_priv_offset; 54 unsigned int ring_start; 55 unsigned int ring_end; 56 unsigned int ring_size; 57 unsigned int front_offset; 58 unsigned int back_offset; 59 unsigned int depth_offset; 60 unsigned int w; 61 unsigned int h; 62 unsigned int pitch; 63 unsigned int pitch_bits; 64 unsigned int back_pitch; 65 unsigned int depth_pitch; 66 unsigned int cpp; 67 unsigned int chipset; 68} drm_i915_init_t; 69 70typedef struct _drm_i915_sarea { 71 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 72 int last_upload; /* last time texture was uploaded */ 73 int last_enqueue; /* last time a buffer was enqueued */ 74 int last_dispatch; /* age of the most recently dispatched buffer */ 75 int ctxOwner; /* last context to upload state */ 76 int texAge; 77 int pf_enabled; /* is pageflipping allowed? */ 78 int pf_active; 79 int pf_current_page; /* which buffer is being displayed? */ 80 int perf_boxes; /* performance boxes to be displayed */ 81 int width, height; /* screen size in pixels */ 82 83 drm_handle_t front_handle; 84 int front_offset; 85 int front_size; 86 87 drm_handle_t back_handle; 88 int back_offset; 89 int back_size; 90 91 drm_handle_t depth_handle; 92 int depth_offset; 93 int depth_size; 94 95 drm_handle_t tex_handle; 96 int tex_offset; 97 int tex_size; 98 int log_tex_granularity; 99 int pitch; 100 int rotation; /* 0, 90, 180 or 270 */ 101 int rotated_offset; 102 int rotated_size; 103 int rotated_pitch; 104 int virtualX, virtualY; 105 106 unsigned int front_tiled; 107 unsigned int back_tiled; 108 unsigned int depth_tiled; 109 unsigned int rotated_tiled; 110 unsigned int rotated2_tiled; 111 112 int pipeA_x; 113 int pipeA_y; 114 int pipeA_w; 115 int pipeA_h; 116 int pipeB_x; 117 int pipeB_y; 118 int pipeB_w; 119 int pipeB_h; 120 121 /* fill out some space for old userspace triple buffer */ 122 drm_handle_t unused_handle; 123 __u32 unused1, unused2, unused3; 124 125 /* buffer object handles for static buffers. May change 126 * over the lifetime of the client. 127 */ 128 __u32 front_bo_handle; 129 __u32 back_bo_handle; 130 __u32 unused_bo_handle; 131 __u32 depth_bo_handle; 132 133} drm_i915_sarea_t; 134 135/* due to userspace building against these headers we need some compat here */ 136#define planeA_x pipeA_x 137#define planeA_y pipeA_y 138#define planeA_w pipeA_w 139#define planeA_h pipeA_h 140#define planeB_x pipeB_x 141#define planeB_y pipeB_y 142#define planeB_w pipeB_w 143#define planeB_h pipeB_h 144 145/* Flags for perf_boxes 146 */ 147#define I915_BOX_RING_EMPTY 0x1 148#define I915_BOX_FLIP 0x2 149#define I915_BOX_WAIT 0x4 150#define I915_BOX_TEXTURE_LOAD 0x8 151#define I915_BOX_LOST_CONTEXT 0x10 152 153/* I915 specific ioctls 154 * The device specific ioctl range is 0x40 to 0x79. 155 */ 156#define DRM_I915_INIT 0x00 157#define DRM_I915_FLUSH 0x01 158#define DRM_I915_FLIP 0x02 159#define DRM_I915_BATCHBUFFER 0x03 160#define DRM_I915_IRQ_EMIT 0x04 161#define DRM_I915_IRQ_WAIT 0x05 162#define DRM_I915_GETPARAM 0x06 163#define DRM_I915_SETPARAM 0x07 164#define DRM_I915_ALLOC 0x08 165#define DRM_I915_FREE 0x09 166#define DRM_I915_INIT_HEAP 0x0a 167#define DRM_I915_CMDBUFFER 0x0b 168#define DRM_I915_DESTROY_HEAP 0x0c 169#define DRM_I915_SET_VBLANK_PIPE 0x0d 170#define DRM_I915_GET_VBLANK_PIPE 0x0e 171#define DRM_I915_VBLANK_SWAP 0x0f 172#define DRM_I915_HWS_ADDR 0x11 173#define DRM_I915_GEM_INIT 0x13 174#define DRM_I915_GEM_EXECBUFFER 0x14 175#define DRM_I915_GEM_PIN 0x15 176#define DRM_I915_GEM_UNPIN 0x16 177#define DRM_I915_GEM_BUSY 0x17 178#define DRM_I915_GEM_THROTTLE 0x18 179#define DRM_I915_GEM_ENTERVT 0x19 180#define DRM_I915_GEM_LEAVEVT 0x1a 181#define DRM_I915_GEM_CREATE 0x1b 182#define DRM_I915_GEM_PREAD 0x1c 183#define DRM_I915_GEM_PWRITE 0x1d 184#define DRM_I915_GEM_MMAP 0x1e 185#define DRM_I915_GEM_SET_DOMAIN 0x1f 186#define DRM_I915_GEM_SW_FINISH 0x20 187#define DRM_I915_GEM_SET_TILING 0x21 188#define DRM_I915_GEM_GET_TILING 0x22 189#define DRM_I915_GEM_GET_APERTURE 0x23 190#define DRM_I915_GEM_MMAP_GTT 0x24 191#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 192#define DRM_I915_GEM_MADVISE 0x26 193#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 194#define DRM_I915_OVERLAY_ATTRS 0x28 195#define DRM_I915_GEM_EXECBUFFER2 0x29 196#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 197#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 198#define DRM_I915_GEM_WAIT 0x2c 199#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 200#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 201#define DRM_I915_GEM_SET_CACHING 0x2f 202#define DRM_I915_GEM_GET_CACHING 0x30 203#define DRM_I915_REG_READ 0x31 204 205#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 206#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 207#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) 208#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 209#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 210#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 211#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 212#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 213#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 214#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 215#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 216#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 217#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 218#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 219#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 220#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 221#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 222#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 223#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 224#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 225#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 226#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 227#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 228#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 229#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 230#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 231#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 232#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 233#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 234#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 235#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 236#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 237#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 238#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 239#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 240#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 241#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 242#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 243#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 244#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 245#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 246#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 247#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 248#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 249#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 250#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 251#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 252#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 253 254/* Allow drivers to submit batchbuffers directly to hardware, relying 255 * on the security mechanisms provided by hardware. 256 */ 257typedef struct drm_i915_batchbuffer { 258 int start; /* agp offset */ 259 int used; /* nr bytes in use */ 260 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 261 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 262 int num_cliprects; /* mulitpass with multiple cliprects? */ 263 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 264} drm_i915_batchbuffer_t; 265 266/* As above, but pass a pointer to userspace buffer which can be 267 * validated by the kernel prior to sending to hardware. 268 */ 269typedef struct _drm_i915_cmdbuffer { 270 char __user *buf; /* pointer to userspace command buffer */ 271 int sz; /* nr bytes in buf */ 272 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 273 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 274 int num_cliprects; /* mulitpass with multiple cliprects? */ 275 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 276} drm_i915_cmdbuffer_t; 277 278/* Userspace can request & wait on irq's: 279 */ 280typedef struct drm_i915_irq_emit { 281 int __user *irq_seq; 282} drm_i915_irq_emit_t; 283 284typedef struct drm_i915_irq_wait { 285 int irq_seq; 286} drm_i915_irq_wait_t; 287 288/* Ioctl to query kernel params: 289 */ 290#define I915_PARAM_IRQ_ACTIVE 1 291#define I915_PARAM_ALLOW_BATCHBUFFER 2 292#define I915_PARAM_LAST_DISPATCH 3 293#define I915_PARAM_CHIPSET_ID 4 294#define I915_PARAM_HAS_GEM 5 295#define I915_PARAM_NUM_FENCES_AVAIL 6 296#define I915_PARAM_HAS_OVERLAY 7 297#define I915_PARAM_HAS_PAGEFLIPPING 8 298#define I915_PARAM_HAS_EXECBUF2 9 299#define I915_PARAM_HAS_BSD 10 300#define I915_PARAM_HAS_BLT 11 301#define I915_PARAM_HAS_RELAXED_FENCING 12 302#define I915_PARAM_HAS_COHERENT_RINGS 13 303#define I915_PARAM_HAS_EXEC_CONSTANTS 14 304#define I915_PARAM_HAS_RELAXED_DELTA 15 305#define I915_PARAM_HAS_GEN7_SOL_RESET 16 306#define I915_PARAM_HAS_LLC 17 307#define I915_PARAM_HAS_ALIASING_PPGTT 18 308#define I915_PARAM_HAS_WAIT_TIMEOUT 19 309#define I915_PARAM_HAS_SEMAPHORES 20 310#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 311#define I915_PARAM_RSVD_FOR_FUTURE_USE 22 312#define I915_PARAM_HAS_SECURE_BATCHES 23 313#define I915_PARAM_HAS_PINNED_BATCHES 24 314 315typedef struct drm_i915_getparam { 316 int param; 317 int __user *value; 318} drm_i915_getparam_t; 319 320/* Ioctl to set kernel params: 321 */ 322#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 323#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 324#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 325#define I915_SETPARAM_NUM_USED_FENCES 4 326 327typedef struct drm_i915_setparam { 328 int param; 329 int value; 330} drm_i915_setparam_t; 331 332/* A memory manager for regions of shared memory: 333 */ 334#define I915_MEM_REGION_AGP 1 335 336typedef struct drm_i915_mem_alloc { 337 int region; 338 int alignment; 339 int size; 340 int __user *region_offset; /* offset from start of fb or agp */ 341} drm_i915_mem_alloc_t; 342 343typedef struct drm_i915_mem_free { 344 int region; 345 int region_offset; 346} drm_i915_mem_free_t; 347 348typedef struct drm_i915_mem_init_heap { 349 int region; 350 int size; 351 int start; 352} drm_i915_mem_init_heap_t; 353 354/* Allow memory manager to be torn down and re-initialized (eg on 355 * rotate): 356 */ 357typedef struct drm_i915_mem_destroy_heap { 358 int region; 359} drm_i915_mem_destroy_heap_t; 360 361/* Allow X server to configure which pipes to monitor for vblank signals 362 */ 363#define DRM_I915_VBLANK_PIPE_A 1 364#define DRM_I915_VBLANK_PIPE_B 2 365 366typedef struct drm_i915_vblank_pipe { 367 int pipe; 368} drm_i915_vblank_pipe_t; 369 370/* Schedule buffer swap at given vertical blank: 371 */ 372typedef struct drm_i915_vblank_swap { 373 drm_drawable_t drawable; 374 enum drm_vblank_seq_type seqtype; 375 unsigned int sequence; 376} drm_i915_vblank_swap_t; 377 378typedef struct drm_i915_hws_addr { 379 __u64 addr; 380} drm_i915_hws_addr_t; 381 382struct drm_i915_gem_init { 383 /** 384 * Beginning offset in the GTT to be managed by the DRM memory 385 * manager. 386 */ 387 __u64 gtt_start; 388 /** 389 * Ending offset in the GTT to be managed by the DRM memory 390 * manager. 391 */ 392 __u64 gtt_end; 393}; 394 395struct drm_i915_gem_create { 396 /** 397 * Requested size for the object. 398 * 399 * The (page-aligned) allocated size for the object will be returned. 400 */ 401 __u64 size; 402 /** 403 * Returned handle for the object. 404 * 405 * Object handles are nonzero. 406 */ 407 __u32 handle; 408 __u32 pad; 409}; 410 411struct drm_i915_gem_pread { 412 /** Handle for the object being read. */ 413 __u32 handle; 414 __u32 pad; 415 /** Offset into the object to read from */ 416 __u64 offset; 417 /** Length of data to read */ 418 __u64 size; 419 /** 420 * Pointer to write the data into. 421 * 422 * This is a fixed-size type for 32/64 compatibility. 423 */ 424 __u64 data_ptr; 425}; 426 427struct drm_i915_gem_pwrite { 428 /** Handle for the object being written to. */ 429 __u32 handle; 430 __u32 pad; 431 /** Offset into the object to write to */ 432 __u64 offset; 433 /** Length of data to write */ 434 __u64 size; 435 /** 436 * Pointer to read the data from. 437 * 438 * This is a fixed-size type for 32/64 compatibility. 439 */ 440 __u64 data_ptr; 441}; 442 443struct drm_i915_gem_mmap { 444 /** Handle for the object being mapped. */ 445 __u32 handle; 446 __u32 pad; 447 /** Offset in the object to map. */ 448 __u64 offset; 449 /** 450 * Length of data to map. 451 * 452 * The value will be page-aligned. 453 */ 454 __u64 size; 455 /** 456 * Returned pointer the data was mapped at. 457 * 458 * This is a fixed-size type for 32/64 compatibility. 459 */ 460 __u64 addr_ptr; 461}; 462 463struct drm_i915_gem_mmap_gtt { 464 /** Handle for the object being mapped. */ 465 __u32 handle; 466 __u32 pad; 467 /** 468 * Fake offset to use for subsequent mmap call 469 * 470 * This is a fixed-size type for 32/64 compatibility. 471 */ 472 __u64 offset; 473}; 474 475struct drm_i915_gem_set_domain { 476 /** Handle for the object */ 477 __u32 handle; 478 479 /** New read domains */ 480 __u32 read_domains; 481 482 /** New write domain */ 483 __u32 write_domain; 484}; 485 486struct drm_i915_gem_sw_finish { 487 /** Handle for the object */ 488 __u32 handle; 489}; 490 491struct drm_i915_gem_relocation_entry { 492 /** 493 * Handle of the buffer being pointed to by this relocation entry. 494 * 495 * It's appealing to make this be an index into the mm_validate_entry 496 * list to refer to the buffer, but this allows the driver to create 497 * a relocation list for state buffers and not re-write it per 498 * exec using the buffer. 499 */ 500 __u32 target_handle; 501 502 /** 503 * Value to be added to the offset of the target buffer to make up 504 * the relocation entry. 505 */ 506 __u32 delta; 507 508 /** Offset in the buffer the relocation entry will be written into */ 509 __u64 offset; 510 511 /** 512 * Offset value of the target buffer that the relocation entry was last 513 * written as. 514 * 515 * If the buffer has the same offset as last time, we can skip syncing 516 * and writing the relocation. This value is written back out by 517 * the execbuffer ioctl when the relocation is written. 518 */ 519 __u64 presumed_offset; 520 521 /** 522 * Target memory domains read by this operation. 523 */ 524 __u32 read_domains; 525 526 /** 527 * Target memory domains written by this operation. 528 * 529 * Note that only one domain may be written by the whole 530 * execbuffer operation, so that where there are conflicts, 531 * the application will get -EINVAL back. 532 */ 533 __u32 write_domain; 534}; 535 536/** @{ 537 * Intel memory domains 538 * 539 * Most of these just align with the various caches in 540 * the system and are used to flush and invalidate as 541 * objects end up cached in different domains. 542 */ 543/** CPU cache */ 544#define I915_GEM_DOMAIN_CPU 0x00000001 545/** Render cache, used by 2D and 3D drawing */ 546#define I915_GEM_DOMAIN_RENDER 0x00000002 547/** Sampler cache, used by texture engine */ 548#define I915_GEM_DOMAIN_SAMPLER 0x00000004 549/** Command queue, used to load batch buffers */ 550#define I915_GEM_DOMAIN_COMMAND 0x00000008 551/** Instruction cache, used by shader programs */ 552#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 553/** Vertex address cache */ 554#define I915_GEM_DOMAIN_VERTEX 0x00000020 555/** GTT domain - aperture and scanout */ 556#define I915_GEM_DOMAIN_GTT 0x00000040 557/** @} */ 558 559struct drm_i915_gem_exec_object { 560 /** 561 * User's handle for a buffer to be bound into the GTT for this 562 * operation. 563 */ 564 __u32 handle; 565 566 /** Number of relocations to be performed on this buffer */ 567 __u32 relocation_count; 568 /** 569 * Pointer to array of struct drm_i915_gem_relocation_entry containing 570 * the relocations to be performed in this buffer. 571 */ 572 __u64 relocs_ptr; 573 574 /** Required alignment in graphics aperture */ 575 __u64 alignment; 576 577 /** 578 * Returned value of the updated offset of the object, for future 579 * presumed_offset writes. 580 */ 581 __u64 offset; 582}; 583 584struct drm_i915_gem_execbuffer { 585 /** 586 * List of buffers to be validated with their relocations to be 587 * performend on them. 588 * 589 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 590 * 591 * These buffers must be listed in an order such that all relocations 592 * a buffer is performing refer to buffers that have already appeared 593 * in the validate list. 594 */ 595 __u64 buffers_ptr; 596 __u32 buffer_count; 597 598 /** Offset in the batchbuffer to start execution from. */ 599 __u32 batch_start_offset; 600 /** Bytes used in batchbuffer from batch_start_offset */ 601 __u32 batch_len; 602 __u32 DR1; 603 __u32 DR4; 604 __u32 num_cliprects; 605 /** This is a struct drm_clip_rect *cliprects */ 606 __u64 cliprects_ptr; 607}; 608 609struct drm_i915_gem_exec_object2 { 610 /** 611 * User's handle for a buffer to be bound into the GTT for this 612 * operation. 613 */ 614 __u32 handle; 615 616 /** Number of relocations to be performed on this buffer */ 617 __u32 relocation_count; 618 /** 619 * Pointer to array of struct drm_i915_gem_relocation_entry containing 620 * the relocations to be performed in this buffer. 621 */ 622 __u64 relocs_ptr; 623 624 /** Required alignment in graphics aperture */ 625 __u64 alignment; 626 627 /** 628 * Returned value of the updated offset of the object, for future 629 * presumed_offset writes. 630 */ 631 __u64 offset; 632 633#define EXEC_OBJECT_NEEDS_FENCE (1<<0) 634 __u64 flags; 635 __u64 rsvd1; 636 __u64 rsvd2; 637}; 638 639struct drm_i915_gem_execbuffer2 { 640 /** 641 * List of gem_exec_object2 structs 642 */ 643 __u64 buffers_ptr; 644 __u32 buffer_count; 645 646 /** Offset in the batchbuffer to start execution from. */ 647 __u32 batch_start_offset; 648 /** Bytes used in batchbuffer from batch_start_offset */ 649 __u32 batch_len; 650 __u32 DR1; 651 __u32 DR4; 652 __u32 num_cliprects; 653 /** This is a struct drm_clip_rect *cliprects */ 654 __u64 cliprects_ptr; 655#define I915_EXEC_RING_MASK (7<<0) 656#define I915_EXEC_DEFAULT (0<<0) 657#define I915_EXEC_RENDER (1<<0) 658#define I915_EXEC_BSD (2<<0) 659#define I915_EXEC_BLT (3<<0) 660 661/* Used for switching the constants addressing mode on gen4+ RENDER ring. 662 * Gen6+ only supports relative addressing to dynamic state (default) and 663 * absolute addressing. 664 * 665 * These flags are ignored for the BSD and BLT rings. 666 */ 667#define I915_EXEC_CONSTANTS_MASK (3<<6) 668#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 669#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 670#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 671 __u64 flags; 672 __u64 rsvd1; /* now used for context info */ 673 __u64 rsvd2; 674}; 675 676/** Resets the SO write offset registers for transform feedback on gen7. */ 677#define I915_EXEC_GEN7_SOL_RESET (1<<8) 678 679/** Request a privileged ("secure") batch buffer. Note only available for 680 * DRM_ROOT_ONLY | DRM_MASTER processes. 681 */ 682#define I915_EXEC_SECURE (1<<9) 683 684/** Inform the kernel that the batch is and will always be pinned. This 685 * negates the requirement for a workaround to be performed to avoid 686 * an incoherent CS (such as can be found on 830/845). If this flag is 687 * not passed, the kernel will endeavour to make sure the batch is 688 * coherent with the CS before execution. If this flag is passed, 689 * userspace assumes the responsibility for ensuring the same. 690 */ 691#define I915_EXEC_IS_PINNED (1<<10) 692 693#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 694#define i915_execbuffer2_set_context_id(eb2, context) \ 695 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 696#define i915_execbuffer2_get_context_id(eb2) \ 697 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 698 699struct drm_i915_gem_pin { 700 /** Handle of the buffer to be pinned. */ 701 __u32 handle; 702 __u32 pad; 703 704 /** alignment required within the aperture */ 705 __u64 alignment; 706 707 /** Returned GTT offset of the buffer. */ 708 __u64 offset; 709}; 710 711struct drm_i915_gem_unpin { 712 /** Handle of the buffer to be unpinned. */ 713 __u32 handle; 714 __u32 pad; 715}; 716 717struct drm_i915_gem_busy { 718 /** Handle of the buffer to check for busy */ 719 __u32 handle; 720 721 /** Return busy status (1 if busy, 0 if idle). 722 * The high word is used to indicate on which rings the object 723 * currently resides: 724 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) 725 */ 726 __u32 busy; 727}; 728 729#define I915_CACHING_NONE 0 730#define I915_CACHING_CACHED 1 731 732struct drm_i915_gem_caching { 733 /** 734 * Handle of the buffer to set/get the caching level of. */ 735 __u32 handle; 736 737 /** 738 * Caching level to apply or return value 739 * 740 * bits0-15 are for generic caching control (i.e. the above defined 741 * values). bits16-31 are reserved for platform-specific variations 742 * (e.g. l3$ caching on gen7). */ 743 __u32 caching; 744}; 745 746#define I915_TILING_NONE 0 747#define I915_TILING_X 1 748#define I915_TILING_Y 2 749 750#define I915_BIT_6_SWIZZLE_NONE 0 751#define I915_BIT_6_SWIZZLE_9 1 752#define I915_BIT_6_SWIZZLE_9_10 2 753#define I915_BIT_6_SWIZZLE_9_11 3 754#define I915_BIT_6_SWIZZLE_9_10_11 4 755/* Not seen by userland */ 756#define I915_BIT_6_SWIZZLE_UNKNOWN 5 757/* Seen by userland. */ 758#define I915_BIT_6_SWIZZLE_9_17 6 759#define I915_BIT_6_SWIZZLE_9_10_17 7 760 761struct drm_i915_gem_set_tiling { 762 /** Handle of the buffer to have its tiling state updated */ 763 __u32 handle; 764 765 /** 766 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 767 * I915_TILING_Y). 768 * 769 * This value is to be set on request, and will be updated by the 770 * kernel on successful return with the actual chosen tiling layout. 771 * 772 * The tiling mode may be demoted to I915_TILING_NONE when the system 773 * has bit 6 swizzling that can't be managed correctly by GEM. 774 * 775 * Buffer contents become undefined when changing tiling_mode. 776 */ 777 __u32 tiling_mode; 778 779 /** 780 * Stride in bytes for the object when in I915_TILING_X or 781 * I915_TILING_Y. 782 */ 783 __u32 stride; 784 785 /** 786 * Returned address bit 6 swizzling required for CPU access through 787 * mmap mapping. 788 */ 789 __u32 swizzle_mode; 790}; 791 792struct drm_i915_gem_get_tiling { 793 /** Handle of the buffer to get tiling state for. */ 794 __u32 handle; 795 796 /** 797 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 798 * I915_TILING_Y). 799 */ 800 __u32 tiling_mode; 801 802 /** 803 * Returned address bit 6 swizzling required for CPU access through 804 * mmap mapping. 805 */ 806 __u32 swizzle_mode; 807}; 808 809struct drm_i915_gem_get_aperture { 810 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 811 __u64 aper_size; 812 813 /** 814 * Available space in the aperture used by i915_gem_execbuffer, in 815 * bytes 816 */ 817 __u64 aper_available_size; 818}; 819 820struct drm_i915_get_pipe_from_crtc_id { 821 /** ID of CRTC being requested **/ 822 __u32 crtc_id; 823 824 /** pipe of requested CRTC **/ 825 __u32 pipe; 826}; 827 828#define I915_MADV_WILLNEED 0 829#define I915_MADV_DONTNEED 1 830#define __I915_MADV_PURGED 2 /* internal state */ 831 832struct drm_i915_gem_madvise { 833 /** Handle of the buffer to change the backing store advice */ 834 __u32 handle; 835 836 /* Advice: either the buffer will be needed again in the near future, 837 * or wont be and could be discarded under memory pressure. 838 */ 839 __u32 madv; 840 841 /** Whether the backing store still exists. */ 842 __u32 retained; 843}; 844 845/* flags */ 846#define I915_OVERLAY_TYPE_MASK 0xff 847#define I915_OVERLAY_YUV_PLANAR 0x01 848#define I915_OVERLAY_YUV_PACKED 0x02 849#define I915_OVERLAY_RGB 0x03 850 851#define I915_OVERLAY_DEPTH_MASK 0xff00 852#define I915_OVERLAY_RGB24 0x1000 853#define I915_OVERLAY_RGB16 0x2000 854#define I915_OVERLAY_RGB15 0x3000 855#define I915_OVERLAY_YUV422 0x0100 856#define I915_OVERLAY_YUV411 0x0200 857#define I915_OVERLAY_YUV420 0x0300 858#define I915_OVERLAY_YUV410 0x0400 859 860#define I915_OVERLAY_SWAP_MASK 0xff0000 861#define I915_OVERLAY_NO_SWAP 0x000000 862#define I915_OVERLAY_UV_SWAP 0x010000 863#define I915_OVERLAY_Y_SWAP 0x020000 864#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 865 866#define I915_OVERLAY_FLAGS_MASK 0xff000000 867#define I915_OVERLAY_ENABLE 0x01000000 868 869struct drm_intel_overlay_put_image { 870 /* various flags and src format description */ 871 __u32 flags; 872 /* source picture description */ 873 __u32 bo_handle; 874 /* stride values and offsets are in bytes, buffer relative */ 875 __u16 stride_Y; /* stride for packed formats */ 876 __u16 stride_UV; 877 __u32 offset_Y; /* offset for packet formats */ 878 __u32 offset_U; 879 __u32 offset_V; 880 /* in pixels */ 881 __u16 src_width; 882 __u16 src_height; 883 /* to compensate the scaling factors for partially covered surfaces */ 884 __u16 src_scan_width; 885 __u16 src_scan_height; 886 /* output crtc description */ 887 __u32 crtc_id; 888 __u16 dst_x; 889 __u16 dst_y; 890 __u16 dst_width; 891 __u16 dst_height; 892}; 893 894/* flags */ 895#define I915_OVERLAY_UPDATE_ATTRS (1<<0) 896#define I915_OVERLAY_UPDATE_GAMMA (1<<1) 897struct drm_intel_overlay_attrs { 898 __u32 flags; 899 __u32 color_key; 900 __s32 brightness; 901 __u32 contrast; 902 __u32 saturation; 903 __u32 gamma0; 904 __u32 gamma1; 905 __u32 gamma2; 906 __u32 gamma3; 907 __u32 gamma4; 908 __u32 gamma5; 909}; 910 911/* 912 * Intel sprite handling 913 * 914 * Color keying works with a min/mask/max tuple. Both source and destination 915 * color keying is allowed. 916 * 917 * Source keying: 918 * Sprite pixels within the min & max values, masked against the color channels 919 * specified in the mask field, will be transparent. All other pixels will 920 * be displayed on top of the primary plane. For RGB surfaces, only the min 921 * and mask fields will be used; ranged compares are not allowed. 922 * 923 * Destination keying: 924 * Primary plane pixels that match the min value, masked against the color 925 * channels specified in the mask field, will be replaced by corresponding 926 * pixels from the sprite plane. 927 * 928 * Note that source & destination keying are exclusive; only one can be 929 * active on a given plane. 930 */ 931 932#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 933#define I915_SET_COLORKEY_DESTINATION (1<<1) 934#define I915_SET_COLORKEY_SOURCE (1<<2) 935struct drm_intel_sprite_colorkey { 936 __u32 plane_id; 937 __u32 min_value; 938 __u32 channel_mask; 939 __u32 max_value; 940 __u32 flags; 941}; 942 943struct drm_i915_gem_wait { 944 /** Handle of BO we shall wait on */ 945 __u32 bo_handle; 946 __u32 flags; 947 /** Number of nanoseconds to wait, Returns time remaining. */ 948 __s64 timeout_ns; 949}; 950 951struct drm_i915_gem_context_create { 952 /* output: id of new context*/ 953 __u32 ctx_id; 954 __u32 pad; 955}; 956 957struct drm_i915_gem_context_destroy { 958 __u32 ctx_id; 959 __u32 pad; 960}; 961 962struct drm_i915_reg_read { 963 __u64 offset; 964 __u64 val; /* Return value */ 965}; 966 967/* For use by IPS driver */ 968extern unsigned long i915_read_mch_val(void); 969extern bool i915_gpu_raise(void); 970extern bool i915_gpu_lower(void); 971extern bool i915_gpu_busy(void); 972extern bool i915_gpu_turbo_disable(void); 973#endif /* _UAPI_I915_DRM_H_ */ 974