i915_drm.h revision 271705
1/*- 2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_drm.h 271705 2014-09-17 08:28:50Z dumbbell $"); 29 30#ifndef _I915_DRM_H_ 31#define _I915_DRM_H_ 32 33/* Please note that modifications to all structs defined here are 34 * subject to backwards-compatibility constraints. 35 */ 36 37#include <dev/drm2/drm.h> 38 39/* Each region is a minimum of 16k, and there are at most 255 of them. 40 */ 41#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 42 * of chars for next/prev indices */ 43#define I915_LOG_MIN_TEX_REGION_SIZE 14 44 45typedef struct _drm_i915_init { 46 enum { 47 I915_INIT_DMA = 0x01, 48 I915_CLEANUP_DMA = 0x02, 49 I915_RESUME_DMA = 0x03, 50 51 /* Since this struct isn't versioned, just used a new 52 * 'func' code to indicate the presence of dri2 sarea 53 * info. */ 54 I915_INIT_DMA2 = 0x04 55 } func; 56 unsigned int mmio_offset; 57 int sarea_priv_offset; 58 unsigned int ring_start; 59 unsigned int ring_end; 60 unsigned int ring_size; 61 unsigned int front_offset; 62 unsigned int back_offset; 63 unsigned int depth_offset; 64 unsigned int w; 65 unsigned int h; 66 unsigned int pitch; 67 unsigned int pitch_bits; 68 unsigned int back_pitch; 69 unsigned int depth_pitch; 70 unsigned int cpp; 71 unsigned int chipset; 72 unsigned int sarea_handle; 73} drm_i915_init_t; 74 75typedef struct drm_i915_sarea { 76 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 77 int last_upload; /* last time texture was uploaded */ 78 int last_enqueue; /* last time a buffer was enqueued */ 79 int last_dispatch; /* age of the most recently dispatched buffer */ 80 int ctxOwner; /* last context to upload state */ 81 int texAge; 82 int pf_enabled; /* is pageflipping allowed? */ 83 int pf_active; 84 int pf_current_page; /* which buffer is being displayed? */ 85 int perf_boxes; /* performance boxes to be displayed */ 86 int width, height; /* screen size in pixels */ 87 88 drm_handle_t front_handle; 89 int front_offset; 90 int front_size; 91 92 drm_handle_t back_handle; 93 int back_offset; 94 int back_size; 95 96 drm_handle_t depth_handle; 97 int depth_offset; 98 int depth_size; 99 100 drm_handle_t tex_handle; 101 int tex_offset; 102 int tex_size; 103 int log_tex_granularity; 104 int pitch; 105 int rotation; /* 0, 90, 180 or 270 */ 106 int rotated_offset; 107 int rotated_size; 108 int rotated_pitch; 109 int virtualX, virtualY; 110 111 unsigned int front_tiled; 112 unsigned int back_tiled; 113 unsigned int depth_tiled; 114 unsigned int rotated_tiled; 115 unsigned int rotated2_tiled; 116 117 int planeA_x; 118 int planeA_y; 119 int planeA_w; 120 int planeA_h; 121 int planeB_x; 122 int planeB_y; 123 int planeB_w; 124 int planeB_h; 125 126 /* Triple buffering */ 127 drm_handle_t third_handle; 128 int third_offset; 129 int third_size; 130 unsigned int third_tiled; 131 132 /* buffer object handles for the static buffers. May change 133 * over the lifetime of the client, though it doesn't in our current 134 * implementation. 135 */ 136 unsigned int front_bo_handle; 137 unsigned int back_bo_handle; 138 unsigned int third_bo_handle; 139 unsigned int depth_bo_handle; 140} drm_i915_sarea_t; 141 142/* Driver specific fence types and classes. 143 */ 144 145/* The only fence class we support */ 146#define DRM_I915_FENCE_CLASS_ACCEL 0 147/* Fence type that guarantees read-write flush */ 148#define DRM_I915_FENCE_TYPE_RW 2 149/* MI_FLUSH programmed just before the fence */ 150#define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000 151 152/* Flags for perf_boxes 153 */ 154#define I915_BOX_RING_EMPTY 0x1 155#define I915_BOX_FLIP 0x2 156#define I915_BOX_WAIT 0x4 157#define I915_BOX_TEXTURE_LOAD 0x8 158#define I915_BOX_LOST_CONTEXT 0x10 159 160/* I915 specific ioctls 161 * The device specific ioctl range is 0x40 to 0x79. 162 */ 163#define DRM_I915_INIT 0x00 164#define DRM_I915_FLUSH 0x01 165#define DRM_I915_FLIP 0x02 166#define DRM_I915_BATCHBUFFER 0x03 167#define DRM_I915_IRQ_EMIT 0x04 168#define DRM_I915_IRQ_WAIT 0x05 169#define DRM_I915_GETPARAM 0x06 170#define DRM_I915_SETPARAM 0x07 171#define DRM_I915_ALLOC 0x08 172#define DRM_I915_FREE 0x09 173#define DRM_I915_INIT_HEAP 0x0a 174#define DRM_I915_CMDBUFFER 0x0b 175#define DRM_I915_DESTROY_HEAP 0x0c 176#define DRM_I915_SET_VBLANK_PIPE 0x0d 177#define DRM_I915_GET_VBLANK_PIPE 0x0e 178#define DRM_I915_VBLANK_SWAP 0x0f 179#define DRM_I915_MMIO 0x10 180#define DRM_I915_HWS_ADDR 0x11 181#define DRM_I915_EXECBUFFER 0x12 182#define DRM_I915_GEM_INIT 0x13 183#define DRM_I915_GEM_EXECBUFFER 0x14 184#define DRM_I915_GEM_PIN 0x15 185#define DRM_I915_GEM_UNPIN 0x16 186#define DRM_I915_GEM_BUSY 0x17 187#define DRM_I915_GEM_THROTTLE 0x18 188#define DRM_I915_GEM_ENTERVT 0x19 189#define DRM_I915_GEM_LEAVEVT 0x1a 190#define DRM_I915_GEM_CREATE 0x1b 191#define DRM_I915_GEM_PREAD 0x1c 192#define DRM_I915_GEM_PWRITE 0x1d 193#define DRM_I915_GEM_MMAP 0x1e 194#define DRM_I915_GEM_SET_DOMAIN 0x1f 195#define DRM_I915_GEM_SW_FINISH 0x20 196#define DRM_I915_GEM_SET_TILING 0x21 197#define DRM_I915_GEM_GET_TILING 0x22 198#define DRM_I915_GEM_GET_APERTURE 0x23 199#define DRM_I915_GEM_MMAP_GTT 0x24 200#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 201#define DRM_I915_GEM_MADVISE 0x26 202#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 203#define DRM_I915_OVERLAY_ATTRS 0x28 204#define DRM_I915_GEM_EXECBUFFER2 0x29 205#define DRM_I915_GET_SPRITE_COLORKEY 0x2a 206#define DRM_I915_SET_SPRITE_COLORKEY 0x2b 207#define DRM_I915_GEM_CONTEXT_CREATE 0x2d 208#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 209 210#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 211#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 212#define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t) 213#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 214#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 215#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 216#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 217#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 218#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 219#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 220#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 221#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 222#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 223#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 224#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 225#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 226#define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio) 227#define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer) 228#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 229#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 230#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 231#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 232#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 233#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 234#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 235#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 236#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 237#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 238#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 239#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 240#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 241#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 242#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 243#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 244#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 245#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 246#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 247#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 248#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 249#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 250#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 251#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 252#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 253#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 254#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 255 256/* Asynchronous page flipping: 257 */ 258typedef struct drm_i915_flip { 259 /* 260 * This is really talking about planes, and we could rename it 261 * except for the fact that some of the duplicated i915_drm.h files 262 * out there check for HAVE_I915_FLIP and so might pick up this 263 * version. 264 */ 265 int pipes; 266} drm_i915_flip_t; 267 268/* Allow drivers to submit batchbuffers directly to hardware, relying 269 * on the security mechanisms provided by hardware. 270 */ 271typedef struct drm_i915_batchbuffer { 272 int start; /* agp offset */ 273 int used; /* nr bytes in use */ 274 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 275 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 276 int num_cliprects; /* mulitpass with multiple cliprects? */ 277 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 278} drm_i915_batchbuffer_t; 279 280/* As above, but pass a pointer to userspace buffer which can be 281 * validated by the kernel prior to sending to hardware. 282 */ 283typedef struct _drm_i915_cmdbuffer { 284 char __user *buf; /* pointer to userspace command buffer */ 285 int sz; /* nr bytes in buf */ 286 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 287 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 288 int num_cliprects; /* mulitpass with multiple cliprects? */ 289 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 290} drm_i915_cmdbuffer_t; 291 292/* Userspace can request & wait on irq's: 293 */ 294typedef struct drm_i915_irq_emit { 295 int __user *irq_seq; 296} drm_i915_irq_emit_t; 297 298typedef struct drm_i915_irq_wait { 299 int irq_seq; 300} drm_i915_irq_wait_t; 301 302/* Ioctl to query kernel params: 303 */ 304#define I915_PARAM_IRQ_ACTIVE 1 305#define I915_PARAM_ALLOW_BATCHBUFFER 2 306#define I915_PARAM_LAST_DISPATCH 3 307#define I915_PARAM_CHIPSET_ID 4 308#define I915_PARAM_HAS_GEM 5 309#define I915_PARAM_NUM_FENCES_AVAIL 6 310#define I915_PARAM_HAS_OVERLAY 7 311#define I915_PARAM_HAS_PAGEFLIPPING 8 312#define I915_PARAM_HAS_EXECBUF2 9 313#define I915_PARAM_HAS_BSD 10 314#define I915_PARAM_HAS_BLT 11 315#define I915_PARAM_HAS_RELAXED_FENCING 12 316#define I915_PARAM_HAS_COHERENT_RINGS 13 317#define I915_PARAM_HAS_EXEC_CONSTANTS 14 318#define I915_PARAM_HAS_RELAXED_DELTA 15 319#define I915_PARAM_HAS_GEN7_SOL_RESET 16 320#define I915_PARAM_HAS_LLC 17 321 322typedef struct drm_i915_getparam { 323 int param; 324 int __user *value; 325} drm_i915_getparam_t; 326 327/* Ioctl to set kernel params: 328 */ 329#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 330#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 331#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 332#define I915_SETPARAM_NUM_USED_FENCES 4 333 334typedef struct drm_i915_setparam { 335 int param; 336 int value; 337} drm_i915_setparam_t; 338 339/* A memory manager for regions of shared memory: 340 */ 341#define I915_MEM_REGION_AGP 1 342 343typedef struct drm_i915_mem_alloc { 344 int region; 345 int alignment; 346 int size; 347 int __user *region_offset; /* offset from start of fb or agp */ 348} drm_i915_mem_alloc_t; 349 350typedef struct drm_i915_mem_free { 351 int region; 352 int region_offset; 353} drm_i915_mem_free_t; 354 355typedef struct drm_i915_mem_init_heap { 356 int region; 357 int size; 358 int start; 359} drm_i915_mem_init_heap_t; 360 361/* Allow memory manager to be torn down and re-initialized (eg on 362 * rotate): 363 */ 364typedef struct drm_i915_mem_destroy_heap { 365 int region; 366} drm_i915_mem_destroy_heap_t; 367 368/* Allow X server to configure which pipes to monitor for vblank signals 369 */ 370#define DRM_I915_VBLANK_PIPE_A 1 371#define DRM_I915_VBLANK_PIPE_B 2 372 373typedef struct drm_i915_vblank_pipe { 374 int pipe; 375} drm_i915_vblank_pipe_t; 376 377/* Schedule buffer swap at given vertical blank: 378 */ 379typedef struct drm_i915_vblank_swap { 380 drm_drawable_t drawable; 381 enum drm_vblank_seq_type seqtype; 382 unsigned int sequence; 383} drm_i915_vblank_swap_t; 384 385#define I915_MMIO_READ 0 386#define I915_MMIO_WRITE 1 387 388#define I915_MMIO_MAY_READ 0x1 389#define I915_MMIO_MAY_WRITE 0x2 390 391#define MMIO_REGS_IA_PRIMATIVES_COUNT 0 392#define MMIO_REGS_IA_VERTICES_COUNT 1 393#define MMIO_REGS_VS_INVOCATION_COUNT 2 394#define MMIO_REGS_GS_PRIMITIVES_COUNT 3 395#define MMIO_REGS_GS_INVOCATION_COUNT 4 396#define MMIO_REGS_CL_PRIMITIVES_COUNT 5 397#define MMIO_REGS_CL_INVOCATION_COUNT 6 398#define MMIO_REGS_PS_INVOCATION_COUNT 7 399#define MMIO_REGS_PS_DEPTH_COUNT 8 400 401typedef struct drm_i915_mmio_entry { 402 unsigned int flag; 403 unsigned int offset; 404 unsigned int size; 405} drm_i915_mmio_entry_t; 406 407typedef struct drm_i915_mmio { 408 unsigned int read_write:1; 409 unsigned int reg:31; 410 void __user *data; 411} drm_i915_mmio_t; 412 413typedef struct drm_i915_hws_addr { 414 uint64_t addr; 415} drm_i915_hws_addr_t; 416 417/* 418 * Relocation header is 4 uint32_ts 419 * 0 - 32 bit reloc count 420 * 1 - 32-bit relocation type 421 * 2-3 - 64-bit user buffer handle ptr for another list of relocs. 422 */ 423#define I915_RELOC_HEADER 4 424 425/* 426 * type 0 relocation has 4-uint32_t stride 427 * 0 - offset into buffer 428 * 1 - delta to add in 429 * 2 - buffer handle 430 * 3 - reserved (for optimisations later). 431 */ 432/* 433 * type 1 relocation has 4-uint32_t stride. 434 * Hangs off the first item in the op list. 435 * Performed after all valiations are done. 436 * Try to group relocs into the same relocatee together for 437 * performance reasons. 438 * 0 - offset into buffer 439 * 1 - delta to add in 440 * 2 - buffer index in op list. 441 * 3 - relocatee index in op list. 442 */ 443#define I915_RELOC_TYPE_0 0 444#define I915_RELOC0_STRIDE 4 445#define I915_RELOC_TYPE_1 1 446#define I915_RELOC1_STRIDE 4 447 448 449struct drm_i915_op_arg { 450 uint64_t next; 451 uint64_t reloc_ptr; 452 int handled; 453 unsigned int pad64; 454 union { 455 struct drm_bo_op_req req; 456 struct drm_bo_arg_rep rep; 457 } d; 458 459}; 460 461struct drm_i915_execbuffer { 462 uint64_t ops_list; 463 uint32_t num_buffers; 464 struct drm_i915_batchbuffer batch; 465 drm_context_t context; /* for lockless use in the future */ 466 struct drm_fence_arg fence_arg; 467}; 468 469struct drm_i915_gem_init { 470 /** 471 * Beginning offset in the GTT to be managed by the DRM memory 472 * manager. 473 */ 474 uint64_t gtt_start; 475 /** 476 * Ending offset in the GTT to be managed by the DRM memory 477 * manager. 478 */ 479 uint64_t gtt_end; 480}; 481 482struct drm_i915_gem_create { 483 /** 484 * Requested size for the object. 485 * 486 * The (page-aligned) allocated size for the object will be returned. 487 */ 488 uint64_t size; 489 /** 490 * Returned handle for the object. 491 * 492 * Object handles are nonzero. 493 */ 494 uint32_t handle; 495 uint32_t pad; 496}; 497 498struct drm_i915_gem_pread { 499 /** Handle for the object being read. */ 500 uint32_t handle; 501 uint32_t pad; 502 /** Offset into the object to read from */ 503 uint64_t offset; 504 /** Length of data to read */ 505 uint64_t size; 506 /** Pointer to write the data into. */ 507 uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */ 508}; 509 510struct drm_i915_gem_pwrite { 511 /** Handle for the object being written to. */ 512 uint32_t handle; 513 uint32_t pad; 514 /** Offset into the object to write to */ 515 uint64_t offset; 516 /** Length of data to write */ 517 uint64_t size; 518 /** Pointer to read the data from. */ 519 uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */ 520}; 521 522struct drm_i915_gem_mmap { 523 /** Handle for the object being mapped. */ 524 uint32_t handle; 525 uint32_t pad; 526 /** Offset in the object to map. */ 527 uint64_t offset; 528 /** 529 * Length of data to map. 530 * 531 * The value will be page-aligned. 532 */ 533 uint64_t size; 534 /** Returned pointer the data was mapped at */ 535 uint64_t addr_ptr; /* void *, but pointers are not 32/64 compatible */ 536}; 537 538struct drm_i915_gem_mmap_gtt { 539 /** Handle for the object being mapped. */ 540 uint32_t handle; 541 uint32_t pad; 542 /** 543 * Fake offset to use for subsequent mmap call 544 * 545 * This is a fixed-size type for 32/64 compatibility. 546 */ 547 uint64_t offset; 548}; 549 550struct drm_i915_gem_set_domain { 551 /** Handle for the object */ 552 uint32_t handle; 553 554 /** New read domains */ 555 uint32_t read_domains; 556 557 /** New write domain */ 558 uint32_t write_domain; 559}; 560 561struct drm_i915_gem_sw_finish { 562 /** Handle for the object */ 563 uint32_t handle; 564}; 565 566struct drm_i915_gem_relocation_entry { 567 /** 568 * Handle of the buffer being pointed to by this relocation entry. 569 * 570 * It's appealing to make this be an index into the mm_validate_entry 571 * list to refer to the buffer, but this allows the driver to create 572 * a relocation list for state buffers and not re-write it per 573 * exec using the buffer. 574 */ 575 uint32_t target_handle; 576 577 /** 578 * Value to be added to the offset of the target buffer to make up 579 * the relocation entry. 580 */ 581 uint32_t delta; 582 583 /** Offset in the buffer the relocation entry will be written into */ 584 uint64_t offset; 585 586 /** 587 * Offset value of the target buffer that the relocation entry was last 588 * written as. 589 * 590 * If the buffer has the same offset as last time, we can skip syncing 591 * and writing the relocation. This value is written back out by 592 * the execbuffer ioctl when the relocation is written. 593 */ 594 uint64_t presumed_offset; 595 596 /** 597 * Target memory domains read by this operation. 598 */ 599 uint32_t read_domains; 600 601 /** 602 * Target memory domains written by this operation. 603 * 604 * Note that only one domain may be written by the whole 605 * execbuffer operation, so that where there are conflicts, 606 * the application will get -EINVAL back. 607 */ 608 uint32_t write_domain; 609}; 610 611/** @{ 612 * Intel memory domains 613 * 614 * Most of these just align with the various caches in 615 * the system and are used to flush and invalidate as 616 * objects end up cached in different domains. 617 */ 618/** CPU cache */ 619#define I915_GEM_DOMAIN_CPU 0x00000001 620/** Render cache, used by 2D and 3D drawing */ 621#define I915_GEM_DOMAIN_RENDER 0x00000002 622/** Sampler cache, used by texture engine */ 623#define I915_GEM_DOMAIN_SAMPLER 0x00000004 624/** Command queue, used to load batch buffers */ 625#define I915_GEM_DOMAIN_COMMAND 0x00000008 626/** Instruction cache, used by shader programs */ 627#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 628/** Vertex address cache */ 629#define I915_GEM_DOMAIN_VERTEX 0x00000020 630/** GTT domain - aperture and scanout */ 631#define I915_GEM_DOMAIN_GTT 0x00000040 632/** @} */ 633 634struct drm_i915_gem_exec_object { 635 /** 636 * User's handle for a buffer to be bound into the GTT for this 637 * operation. 638 */ 639 uint32_t handle; 640 641 /** Number of relocations to be performed on this buffer */ 642 uint32_t relocation_count; 643 /** 644 * Pointer to array of struct drm_i915_gem_relocation_entry containing 645 * the relocations to be performed in this buffer. 646 */ 647 uint64_t relocs_ptr; 648 649 /** Required alignment in graphics aperture */ 650 uint64_t alignment; 651 652 /** 653 * Returned value of the updated offset of the object, for future 654 * presumed_offset writes. 655 */ 656 uint64_t offset; 657}; 658 659struct drm_i915_gem_execbuffer { 660 /** 661 * List of buffers to be validated with their relocations to be 662 * performend on them. 663 * 664 * This is a pointer to an array of struct drm_i915_gem_validate_entry. 665 * 666 * These buffers must be listed in an order such that all relocations 667 * a buffer is performing refer to buffers that have already appeared 668 * in the validate list. 669 */ 670 uint64_t buffers_ptr; 671 uint32_t buffer_count; 672 673 /** Offset in the batchbuffer to start execution from. */ 674 uint32_t batch_start_offset; 675 /** Bytes used in batchbuffer from batch_start_offset */ 676 uint32_t batch_len; 677 uint32_t DR1; 678 uint32_t DR4; 679 uint32_t num_cliprects; 680 uint64_t cliprects_ptr; /* struct drm_clip_rect *cliprects */ 681}; 682 683struct drm_i915_gem_exec_object2 { 684 /** 685 * User's handle for a buffer to be bound into the GTT for this 686 * operation. 687 */ 688 uint32_t handle; 689 690 /** Number of relocations to be performed on this buffer */ 691 uint32_t relocation_count; 692 /** 693 * Pointer to array of struct drm_i915_gem_relocation_entry containing 694 * the relocations to be performed in this buffer. 695 */ 696 uint64_t relocs_ptr; 697 698 /** Required alignment in graphics aperture */ 699 uint64_t alignment; 700 701 /** 702 * Returned value of the updated offset of the object, for future 703 * presumed_offset writes. 704 */ 705 uint64_t offset; 706 707#define EXEC_OBJECT_NEEDS_FENCE (1<<0) 708 uint64_t flags; 709 uint64_t rsvd1; /* now used for context info */ 710 uint64_t rsvd2; 711}; 712 713struct drm_i915_gem_execbuffer2 { 714 /** 715 * List of gem_exec_object2 structs 716 */ 717 uint64_t buffers_ptr; 718 uint32_t buffer_count; 719 720 /** Offset in the batchbuffer to start execution from. */ 721 uint32_t batch_start_offset; 722 /** Bytes used in batchbuffer from batch_start_offset */ 723 uint32_t batch_len; 724 uint32_t DR1; 725 uint32_t DR4; 726 uint32_t num_cliprects; 727 /** This is a struct drm_clip_rect *cliprects */ 728 uint64_t cliprects_ptr; 729#define I915_EXEC_RING_MASK (7<<0) 730#define I915_EXEC_DEFAULT (0<<0) 731#define I915_EXEC_RENDER (1<<0) 732#define I915_EXEC_BSD (2<<0) 733#define I915_EXEC_BLT (3<<0) 734 735/* Used for switching the constants addressing mode on gen4+ RENDER ring. 736 * Gen6+ only supports relative addressing to dynamic state (default) and 737 * absolute addressing. 738 * 739 * These flags are ignored for the BSD and BLT rings. 740 */ 741#define I915_EXEC_CONSTANTS_MASK (3<<6) 742#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ 743#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) 744#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ 745 uint64_t flags; 746 uint64_t rsvd1; 747 uint64_t rsvd2; 748}; 749 750/** Resets the SO write offset registers for transform feedback on gen7. */ 751#define I915_EXEC_GEN7_SOL_RESET (1<<8) 752 753#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 754#define i915_execbuffer2_set_context_id(eb2, context) \ 755 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 756#define i915_execbuffer2_get_context_id(eb2) \ 757 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 758 759struct drm_i915_gem_pin { 760 /** Handle of the buffer to be pinned. */ 761 uint32_t handle; 762 uint32_t pad; 763 764 /** alignment required within the aperture */ 765 uint64_t alignment; 766 767 /** Returned GTT offset of the buffer. */ 768 uint64_t offset; 769}; 770 771struct drm_i915_gem_unpin { 772 /** Handle of the buffer to be unpinned. */ 773 uint32_t handle; 774 uint32_t pad; 775}; 776 777struct drm_i915_gem_busy { 778 /** Handle of the buffer to check for busy */ 779 uint32_t handle; 780 781 /** Return busy status (1 if busy, 0 if idle) */ 782 uint32_t busy; 783}; 784 785#define I915_TILING_NONE 0 786#define I915_TILING_X 1 787#define I915_TILING_Y 2 788 789#define I915_BIT_6_SWIZZLE_NONE 0 790#define I915_BIT_6_SWIZZLE_9 1 791#define I915_BIT_6_SWIZZLE_9_10 2 792#define I915_BIT_6_SWIZZLE_9_11 3 793#define I915_BIT_6_SWIZZLE_9_10_11 4 794/* Not seen by userland */ 795#define I915_BIT_6_SWIZZLE_UNKNOWN 5 796/* Seen by userland. */ 797#define I915_BIT_6_SWIZZLE_9_17 6 798#define I915_BIT_6_SWIZZLE_9_10_17 7 799 800struct drm_i915_gem_set_tiling { 801 /** Handle of the buffer to have its tiling state updated */ 802 uint32_t handle; 803 804 /** 805 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 806 * I915_TILING_Y). 807 * 808 * This value is to be set on request, and will be updated by the 809 * kernel on successful return with the actual chosen tiling layout. 810 * 811 * The tiling mode may be demoted to I915_TILING_NONE when the system 812 * has bit 6 swizzling that can't be managed correctly by GEM. 813 * 814 * Buffer contents become undefined when changing tiling_mode. 815 */ 816 uint32_t tiling_mode; 817 818 /** 819 * Stride in bytes for the object when in I915_TILING_X or 820 * I915_TILING_Y. 821 */ 822 uint32_t stride; 823 824 /** 825 * Returned address bit 6 swizzling required for CPU access through 826 * mmap mapping. 827 */ 828 uint32_t swizzle_mode; 829}; 830 831struct drm_i915_gem_get_tiling { 832 /** Handle of the buffer to get tiling state for. */ 833 uint32_t handle; 834 835 /** 836 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 837 * I915_TILING_Y). 838 */ 839 uint32_t tiling_mode; 840 841 /** 842 * Returned address bit 6 swizzling required for CPU access through 843 * mmap mapping. 844 */ 845 uint32_t swizzle_mode; 846}; 847 848struct drm_i915_gem_get_aperture { 849 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 850 uint64_t aper_size; 851 852 /** 853 * Available space in the aperture used by i915_gem_execbuffer, in 854 * bytes 855 */ 856 uint64_t aper_available_size; 857}; 858 859struct drm_i915_get_pipe_from_crtc_id { 860 /** ID of CRTC being requested **/ 861 uint32_t crtc_id; 862 863 /** pipe of requested CRTC **/ 864 uint32_t pipe; 865}; 866 867#define I915_MADV_WILLNEED 0 868#define I915_MADV_DONTNEED 1 869#define I915_MADV_PURGED_INTERNAL 2 /* internal state */ 870 871struct drm_i915_gem_madvise { 872 /** Handle of the buffer to change the backing store advice */ 873 uint32_t handle; 874 875 /* Advice: either the buffer will be needed again in the near future, 876 * or wont be and could be discarded under memory pressure. 877 */ 878 uint32_t madv; 879 880 /** Whether the backing store still exists. */ 881 uint32_t retained; 882}; 883 884#define I915_OVERLAY_TYPE_MASK 0xff 885#define I915_OVERLAY_YUV_PLANAR 0x01 886#define I915_OVERLAY_YUV_PACKED 0x02 887#define I915_OVERLAY_RGB 0x03 888 889#define I915_OVERLAY_DEPTH_MASK 0xff00 890#define I915_OVERLAY_RGB24 0x1000 891#define I915_OVERLAY_RGB16 0x2000 892#define I915_OVERLAY_RGB15 0x3000 893#define I915_OVERLAY_YUV422 0x0100 894#define I915_OVERLAY_YUV411 0x0200 895#define I915_OVERLAY_YUV420 0x0300 896#define I915_OVERLAY_YUV410 0x0400 897 898#define I915_OVERLAY_SWAP_MASK 0xff0000 899#define I915_OVERLAY_NO_SWAP 0x000000 900#define I915_OVERLAY_UV_SWAP 0x010000 901#define I915_OVERLAY_Y_SWAP 0x020000 902#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 903 904#define I915_OVERLAY_FLAGS_MASK 0xff000000 905#define I915_OVERLAY_ENABLE 0x01000000 906 907struct drm_intel_overlay_put_image { 908 /* various flags and src format description */ 909 uint32_t flags; 910 /* source picture description */ 911 uint32_t bo_handle; 912 /* stride values and offsets are in bytes, buffer relative */ 913 uint16_t stride_Y; /* stride for packed formats */ 914 uint16_t stride_UV; 915 uint32_t offset_Y; /* offset for packet formats */ 916 uint32_t offset_U; 917 uint32_t offset_V; 918 /* in pixels */ 919 uint16_t src_width; 920 uint16_t src_height; 921 /* to compensate the scaling factors for partially covered surfaces */ 922 uint16_t src_scan_width; 923 uint16_t src_scan_height; 924 /* output crtc description */ 925 uint32_t crtc_id; 926 uint16_t dst_x; 927 uint16_t dst_y; 928 uint16_t dst_width; 929 uint16_t dst_height; 930}; 931 932/* flags */ 933#define I915_OVERLAY_UPDATE_ATTRS (1<<0) 934#define I915_OVERLAY_UPDATE_GAMMA (1<<1) 935struct drm_intel_overlay_attrs { 936 uint32_t flags; 937 uint32_t color_key; 938 int32_t brightness; 939 uint32_t contrast; 940 uint32_t saturation; 941 uint32_t gamma0; 942 uint32_t gamma1; 943 uint32_t gamma2; 944 uint32_t gamma3; 945 uint32_t gamma4; 946 uint32_t gamma5; 947}; 948 949/* 950 * Intel sprite handling 951 * 952 * Color keying works with a min/mask/max tuple. Both source and destination 953 * color keying is allowed. 954 * 955 * Source keying: 956 * Sprite pixels within the min & max values, masked against the color channels 957 * specified in the mask field, will be transparent. All other pixels will 958 * be displayed on top of the primary plane. For RGB surfaces, only the min 959 * and mask fields will be used; ranged compares are not allowed. 960 * 961 * Destination keying: 962 * Primary plane pixels that match the min value, masked against the color 963 * channels specified in the mask field, will be replaced by corresponding 964 * pixels from the sprite plane. 965 * 966 * Note that source & destination keying are exclusive; only one can be 967 * active on a given plane. 968 */ 969 970#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ 971#define I915_SET_COLORKEY_DESTINATION (1<<1) 972#define I915_SET_COLORKEY_SOURCE (1<<2) 973struct drm_intel_sprite_colorkey { 974 uint32_t plane_id; 975 uint32_t min_value; 976 uint32_t channel_mask; 977 uint32_t max_value; 978 uint32_t flags; 979}; 980 981struct drm_i915_gem_context_create { 982 /* output: id of new context*/ 983 uint32_t ctx_id; 984 uint32_t pad; 985}; 986 987struct drm_i915_gem_context_destroy { 988 uint32_t ctx_id; 989 uint32_t pad; 990}; 991 992#endif /* _I915_DRM_H_ */ 993