i915_dma.c revision 271705
1235783Skib/* i915_dma.c -- DMA support for the I915 -*- linux-c -*- 2235783Skib */ 3235783Skib/*- 4235783Skib * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5235783Skib * All Rights Reserved. 6235783Skib * 7235783Skib * Permission is hereby granted, free of charge, to any person obtaining a 8235783Skib * copy of this software and associated documentation files (the 9235783Skib * "Software"), to deal in the Software without restriction, including 10235783Skib * without limitation the rights to use, copy, modify, merge, publish, 11235783Skib * distribute, sub license, and/or sell copies of the Software, and to 12235783Skib * permit persons to whom the Software is furnished to do so, subject to 13235783Skib * the following conditions: 14235783Skib * 15235783Skib * The above copyright notice and this permission notice (including the 16235783Skib * next paragraph) shall be included in all copies or substantial portions 17235783Skib * of the Software. 18235783Skib * 19235783Skib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20235783Skib * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21235783Skib * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22235783Skib * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23235783Skib * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24235783Skib * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25235783Skib * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26235783Skib * 27235783Skib */ 28235783Skib 29235783Skib#include <sys/cdefs.h> 30235783Skib__FBSDID("$FreeBSD: head/sys/dev/drm2/i915/i915_dma.c 271705 2014-09-17 08:28:50Z dumbbell $"); 31235783Skib 32235783Skib#include <dev/drm2/drmP.h> 33235783Skib#include <dev/drm2/drm.h> 34235783Skib#include <dev/drm2/i915/i915_drm.h> 35235783Skib#include <dev/drm2/i915/i915_drv.h> 36235783Skib#include <dev/drm2/i915/intel_drv.h> 37235783Skib#include <dev/drm2/i915/intel_ringbuffer.h> 38235783Skib 39235783Skibstatic struct drm_i915_private *i915_mch_dev; 40235783Skib/* 41235783Skib * Lock protecting IPS related data structures 42235783Skib * - i915_mch_dev 43235783Skib * - dev_priv->max_delay 44235783Skib * - dev_priv->min_delay 45235783Skib * - dev_priv->fmax 46235783Skib * - dev_priv->gpu_busy 47235783Skib */ 48235783Skibstatic struct mtx mchdev_lock; 49235783SkibMTX_SYSINIT(mchdev, &mchdev_lock, "mchdev", MTX_DEF); 50235783Skib 51235783Skibstatic void i915_pineview_get_mem_freq(struct drm_device *dev); 52235783Skibstatic void i915_ironlake_get_mem_freq(struct drm_device *dev); 53235783Skibstatic int i915_driver_unload_int(struct drm_device *dev, bool locked); 54235783Skib 55235783Skibstatic void i915_write_hws_pga(struct drm_device *dev) 56235783Skib{ 57235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 58235783Skib u32 addr; 59235783Skib 60235783Skib addr = dev_priv->status_page_dmah->busaddr; 61235783Skib if (INTEL_INFO(dev)->gen >= 4) 62235783Skib addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; 63235783Skib I915_WRITE(HWS_PGA, addr); 64235783Skib} 65235783Skib 66235783Skib/** 67235783Skib * Sets up the hardware status page for devices that need a physical address 68235783Skib * in the register. 69235783Skib */ 70235783Skibstatic int i915_init_phys_hws(struct drm_device *dev) 71235783Skib{ 72235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 73235783Skib struct intel_ring_buffer *ring = LP_RING(dev_priv); 74235783Skib 75235783Skib /* 76235783Skib * Program Hardware Status Page 77235783Skib * XXXKIB Keep 4GB limit for allocation for now. This method 78235783Skib * of allocation is used on <= 965 hardware, that has several 79235783Skib * erratas regarding the use of physical memory > 4 GB. 80235783Skib */ 81235783Skib DRM_UNLOCK(dev); 82235783Skib dev_priv->status_page_dmah = 83235783Skib drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); 84235783Skib DRM_LOCK(dev); 85235783Skib if (!dev_priv->status_page_dmah) { 86235783Skib DRM_ERROR("Can not allocate hardware status page\n"); 87235783Skib return -ENOMEM; 88235783Skib } 89235783Skib ring->status_page.page_addr = dev_priv->hw_status_page = 90235783Skib dev_priv->status_page_dmah->vaddr; 91235783Skib dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; 92235783Skib 93235783Skib memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 94235783Skib 95235783Skib i915_write_hws_pga(dev); 96235783Skib DRM_DEBUG("Enabled hardware status page, phys %jx\n", 97235783Skib (uintmax_t)dev_priv->dma_status_page); 98235783Skib return 0; 99235783Skib} 100235783Skib 101235783Skib/** 102235783Skib * Frees the hardware status page, whether it's a physical address or a virtual 103235783Skib * address set up by the X Server. 104235783Skib */ 105235783Skibstatic void i915_free_hws(struct drm_device *dev) 106235783Skib{ 107235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 108235783Skib struct intel_ring_buffer *ring = LP_RING(dev_priv); 109235783Skib 110235783Skib if (dev_priv->status_page_dmah) { 111235783Skib drm_pci_free(dev, dev_priv->status_page_dmah); 112235783Skib dev_priv->status_page_dmah = NULL; 113235783Skib } 114235783Skib 115235783Skib if (dev_priv->status_gfx_addr) { 116235783Skib dev_priv->status_gfx_addr = 0; 117235783Skib ring->status_page.gfx_addr = 0; 118235783Skib drm_core_ioremapfree(&dev_priv->hws_map, dev); 119235783Skib } 120235783Skib 121235783Skib /* Need to rewrite hardware status page */ 122235783Skib I915_WRITE(HWS_PGA, 0x1ffff000); 123235783Skib} 124235783Skib 125235783Skibvoid i915_kernel_lost_context(struct drm_device * dev) 126235783Skib{ 127235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 128235783Skib struct intel_ring_buffer *ring = LP_RING(dev_priv); 129235783Skib 130235783Skib /* 131235783Skib * We should never lose context on the ring with modesetting 132235783Skib * as we don't expose it to userspace 133235783Skib */ 134235783Skib if (drm_core_check_feature(dev, DRIVER_MODESET)) 135235783Skib return; 136235783Skib 137235783Skib ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; 138235783Skib ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; 139235783Skib ring->space = ring->head - (ring->tail + 8); 140235783Skib if (ring->space < 0) 141235783Skib ring->space += ring->size; 142235783Skib 143235783Skib#if 1 144235783Skib KIB_NOTYET(); 145235783Skib#else 146235783Skib if (!dev->primary->master) 147235783Skib return; 148235783Skib#endif 149235783Skib 150235783Skib if (ring->head == ring->tail && dev_priv->sarea_priv) 151235783Skib dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; 152235783Skib} 153235783Skib 154235783Skibstatic int i915_dma_cleanup(struct drm_device * dev) 155235783Skib{ 156235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 157235783Skib int i; 158235783Skib 159235783Skib 160235783Skib /* Make sure interrupts are disabled here because the uninstall ioctl 161235783Skib * may not have been called from userspace and after dev_private 162235783Skib * is freed, it's too late. 163235783Skib */ 164235783Skib if (dev->irq_enabled) 165235783Skib drm_irq_uninstall(dev); 166235783Skib 167235783Skib for (i = 0; i < I915_NUM_RINGS; i++) 168235783Skib intel_cleanup_ring_buffer(&dev_priv->rings[i]); 169235783Skib 170235783Skib /* Clear the HWS virtual address at teardown */ 171235783Skib if (I915_NEED_GFX_HWS(dev)) 172235783Skib i915_free_hws(dev); 173235783Skib 174235783Skib return 0; 175235783Skib} 176235783Skib 177235783Skibstatic int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) 178235783Skib{ 179235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 180235783Skib int ret; 181235783Skib 182235783Skib dev_priv->sarea = drm_getsarea(dev); 183235783Skib if (!dev_priv->sarea) { 184235783Skib DRM_ERROR("can not find sarea!\n"); 185235783Skib i915_dma_cleanup(dev); 186235783Skib return -EINVAL; 187235783Skib } 188235783Skib 189235783Skib dev_priv->sarea_priv = (drm_i915_sarea_t *) 190235783Skib ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset); 191235783Skib 192235783Skib if (init->ring_size != 0) { 193235783Skib if (LP_RING(dev_priv)->obj != NULL) { 194235783Skib i915_dma_cleanup(dev); 195235783Skib DRM_ERROR("Client tried to initialize ringbuffer in " 196235783Skib "GEM mode\n"); 197235783Skib return -EINVAL; 198235783Skib } 199235783Skib 200235783Skib ret = intel_render_ring_init_dri(dev, 201235783Skib init->ring_start, 202235783Skib init->ring_size); 203235783Skib if (ret) { 204235783Skib i915_dma_cleanup(dev); 205235783Skib return ret; 206235783Skib } 207235783Skib } 208235783Skib 209235783Skib dev_priv->cpp = init->cpp; 210235783Skib dev_priv->back_offset = init->back_offset; 211235783Skib dev_priv->front_offset = init->front_offset; 212235783Skib dev_priv->current_page = 0; 213235783Skib dev_priv->sarea_priv->pf_current_page = 0; 214235783Skib 215235783Skib /* Allow hardware batchbuffers unless told otherwise. 216235783Skib */ 217235783Skib dev_priv->allow_batchbuffer = 1; 218235783Skib 219235783Skib return 0; 220235783Skib} 221235783Skib 222235783Skibstatic int i915_dma_resume(struct drm_device * dev) 223235783Skib{ 224235783Skib drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 225235783Skib struct intel_ring_buffer *ring = LP_RING(dev_priv); 226235783Skib 227235783Skib DRM_DEBUG("\n"); 228235783Skib 229235783Skib if (ring->map.handle == NULL) { 230235783Skib DRM_ERROR("can not ioremap virtual address for" 231235783Skib " ring buffer\n"); 232235783Skib return -ENOMEM; 233235783Skib } 234235783Skib 235235783Skib /* Program Hardware Status Page */ 236235783Skib if (!ring->status_page.page_addr) { 237235783Skib DRM_ERROR("Can not find hardware status page\n"); 238235783Skib return -EINVAL; 239235783Skib } 240235783Skib DRM_DEBUG("hw status page @ %p\n", ring->status_page.page_addr); 241235783Skib if (ring->status_page.gfx_addr != 0) 242235783Skib intel_ring_setup_status_page(ring); 243235783Skib else 244235783Skib i915_write_hws_pga(dev); 245235783Skib 246235783Skib DRM_DEBUG("Enabled hardware status page\n"); 247235783Skib 248235783Skib return 0; 249235783Skib} 250235783Skib 251235783Skibstatic int i915_dma_init(struct drm_device *dev, void *data, 252235783Skib struct drm_file *file_priv) 253235783Skib{ 254235783Skib drm_i915_init_t *init = data; 255235783Skib int retcode = 0; 256235783Skib 257235783Skib switch (init->func) { 258235783Skib case I915_INIT_DMA: 259235783Skib retcode = i915_initialize(dev, init); 260235783Skib break; 261235783Skib case I915_CLEANUP_DMA: 262235783Skib retcode = i915_dma_cleanup(dev); 263235783Skib break; 264235783Skib case I915_RESUME_DMA: 265235783Skib retcode = i915_dma_resume(dev); 266235783Skib break; 267235783Skib default: 268235783Skib retcode = -EINVAL; 269235783Skib break; 270235783Skib } 271235783Skib 272235783Skib return retcode; 273235783Skib} 274235783Skib 275235783Skib/* Implement basically the same security restrictions as hardware does 276235783Skib * for MI_BATCH_NON_SECURE. These can be made stricter at any time. 277235783Skib * 278235783Skib * Most of the calculations below involve calculating the size of a 279235783Skib * particular instruction. It's important to get the size right as 280235783Skib * that tells us where the next instruction to check is. Any illegal 281235783Skib * instruction detected will be given a size of zero, which is a 282235783Skib * signal to abort the rest of the buffer. 283235783Skib */ 284235783Skibstatic int do_validate_cmd(int cmd) 285235783Skib{ 286235783Skib switch (((cmd >> 29) & 0x7)) { 287235783Skib case 0x0: 288235783Skib switch ((cmd >> 23) & 0x3f) { 289235783Skib case 0x0: 290235783Skib return 1; /* MI_NOOP */ 291235783Skib case 0x4: 292235783Skib return 1; /* MI_FLUSH */ 293235783Skib default: 294235783Skib return 0; /* disallow everything else */ 295235783Skib } 296235783Skib break; 297235783Skib case 0x1: 298235783Skib return 0; /* reserved */ 299235783Skib case 0x2: 300235783Skib return (cmd & 0xff) + 2; /* 2d commands */ 301235783Skib case 0x3: 302235783Skib if (((cmd >> 24) & 0x1f) <= 0x18) 303235783Skib return 1; 304235783Skib 305235783Skib switch ((cmd >> 24) & 0x1f) { 306235783Skib case 0x1c: 307235783Skib return 1; 308235783Skib case 0x1d: 309235783Skib switch ((cmd >> 16) & 0xff) { 310235783Skib case 0x3: 311235783Skib return (cmd & 0x1f) + 2; 312235783Skib case 0x4: 313235783Skib return (cmd & 0xf) + 2; 314235783Skib default: 315235783Skib return (cmd & 0xffff) + 2; 316235783Skib } 317235783Skib case 0x1e: 318235783Skib if (cmd & (1 << 23)) 319235783Skib return (cmd & 0xffff) + 1; 320235783Skib else 321235783Skib return 1; 322235783Skib case 0x1f: 323235783Skib if ((cmd & (1 << 23)) == 0) /* inline vertices */ 324235783Skib return (cmd & 0x1ffff) + 2; 325235783Skib else if (cmd & (1 << 17)) /* indirect random */ 326235783Skib if ((cmd & 0xffff) == 0) 327235783Skib return 0; /* unknown length, too hard */ 328235783Skib else 329235783Skib return (((cmd & 0xffff) + 1) / 2) + 1; 330235783Skib else 331235783Skib return 2; /* indirect sequential */ 332235783Skib default: 333235783Skib return 0; 334235783Skib } 335235783Skib default: 336235783Skib return 0; 337235783Skib } 338235783Skib 339235783Skib return 0; 340235783Skib} 341235783Skib 342235783Skibstatic int validate_cmd(int cmd) 343235783Skib{ 344235783Skib int ret = do_validate_cmd(cmd); 345235783Skib 346235783Skib/* printk("validate_cmd( %x ): %d\n", cmd, ret); */ 347235783Skib 348235783Skib return ret; 349235783Skib} 350235783Skib 351235783Skibstatic int i915_emit_cmds(struct drm_device *dev, int __user *buffer, 352235783Skib int dwords) 353235783Skib{ 354235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 355235783Skib int i; 356235783Skib 357235783Skib if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8) 358235783Skib return -EINVAL; 359235783Skib 360235783Skib BEGIN_LP_RING((dwords+1)&~1); 361235783Skib 362235783Skib for (i = 0; i < dwords;) { 363235783Skib int cmd, sz; 364235783Skib 365235783Skib if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) 366235783Skib return -EINVAL; 367235783Skib 368235783Skib if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) 369235783Skib return -EINVAL; 370235783Skib 371235783Skib OUT_RING(cmd); 372235783Skib 373235783Skib while (++i, --sz) { 374235783Skib if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], 375235783Skib sizeof(cmd))) { 376235783Skib return -EINVAL; 377235783Skib } 378235783Skib OUT_RING(cmd); 379235783Skib } 380235783Skib } 381235783Skib 382235783Skib if (dwords & 1) 383235783Skib OUT_RING(0); 384235783Skib 385235783Skib ADVANCE_LP_RING(); 386235783Skib 387235783Skib return 0; 388235783Skib} 389235783Skib 390235783Skibint i915_emit_box(struct drm_device * dev, 391235783Skib struct drm_clip_rect *boxes, 392235783Skib int i, int DR1, int DR4) 393235783Skib{ 394235783Skib struct drm_clip_rect box; 395235783Skib 396235783Skib if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) { 397235783Skib return -EFAULT; 398235783Skib } 399235783Skib 400235783Skib return (i915_emit_box_p(dev, &box, DR1, DR4)); 401235783Skib} 402235783Skib 403235783Skibint 404235783Skibi915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box, 405235783Skib int DR1, int DR4) 406235783Skib{ 407235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 408235783Skib int ret; 409235783Skib 410235783Skib if (box->y2 <= box->y1 || box->x2 <= box->x1 || box->y2 <= 0 || 411235783Skib box->x2 <= 0) { 412235783Skib DRM_ERROR("Bad box %d,%d..%d,%d\n", 413235783Skib box->x1, box->y1, box->x2, box->y2); 414235783Skib return -EINVAL; 415235783Skib } 416235783Skib 417235783Skib if (INTEL_INFO(dev)->gen >= 4) { 418235783Skib ret = BEGIN_LP_RING(4); 419235783Skib if (ret != 0) 420235783Skib return (ret); 421235783Skib 422235783Skib OUT_RING(GFX_OP_DRAWRECT_INFO_I965); 423235783Skib OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); 424235783Skib OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); 425235783Skib OUT_RING(DR4); 426235783Skib } else { 427235783Skib ret = BEGIN_LP_RING(6); 428235783Skib if (ret != 0) 429235783Skib return (ret); 430235783Skib 431235783Skib OUT_RING(GFX_OP_DRAWRECT_INFO); 432235783Skib OUT_RING(DR1); 433235783Skib OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); 434235783Skib OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); 435235783Skib OUT_RING(DR4); 436235783Skib OUT_RING(0); 437235783Skib } 438235783Skib ADVANCE_LP_RING(); 439235783Skib 440235783Skib return 0; 441235783Skib} 442235783Skib 443235783Skib/* XXX: Emitting the counter should really be moved to part of the IRQ 444235783Skib * emit. For now, do it in both places: 445235783Skib */ 446235783Skib 447235783Skibstatic void i915_emit_breadcrumb(struct drm_device *dev) 448235783Skib{ 449235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 450235783Skib 451235783Skib if (++dev_priv->counter > 0x7FFFFFFFUL) 452235783Skib dev_priv->counter = 0; 453235783Skib if (dev_priv->sarea_priv) 454235783Skib dev_priv->sarea_priv->last_enqueue = dev_priv->counter; 455235783Skib 456235783Skib if (BEGIN_LP_RING(4) == 0) { 457235783Skib OUT_RING(MI_STORE_DWORD_INDEX); 458235783Skib OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 459235783Skib OUT_RING(dev_priv->counter); 460235783Skib OUT_RING(0); 461235783Skib ADVANCE_LP_RING(); 462235783Skib } 463235783Skib} 464235783Skib 465235783Skibstatic int i915_dispatch_cmdbuffer(struct drm_device * dev, 466235783Skib drm_i915_cmdbuffer_t * cmd, struct drm_clip_rect *cliprects, void *cmdbuf) 467235783Skib{ 468235783Skib int nbox = cmd->num_cliprects; 469235783Skib int i = 0, count, ret; 470235783Skib 471235783Skib if (cmd->sz & 0x3) { 472235783Skib DRM_ERROR("alignment\n"); 473235783Skib return -EINVAL; 474235783Skib } 475235783Skib 476235783Skib i915_kernel_lost_context(dev); 477235783Skib 478235783Skib count = nbox ? nbox : 1; 479235783Skib 480235783Skib for (i = 0; i < count; i++) { 481235783Skib if (i < nbox) { 482235783Skib ret = i915_emit_box_p(dev, &cmd->cliprects[i], 483235783Skib cmd->DR1, cmd->DR4); 484235783Skib if (ret) 485235783Skib return ret; 486235783Skib } 487235783Skib 488235783Skib ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4); 489235783Skib if (ret) 490235783Skib return ret; 491235783Skib } 492235783Skib 493235783Skib i915_emit_breadcrumb(dev); 494235783Skib return 0; 495235783Skib} 496235783Skib 497235783Skibstatic int 498235783Skibi915_dispatch_batchbuffer(struct drm_device * dev, 499235783Skib drm_i915_batchbuffer_t * batch, struct drm_clip_rect *cliprects) 500235783Skib{ 501235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 502235783Skib int nbox = batch->num_cliprects; 503235783Skib int i, count, ret; 504235783Skib 505235783Skib if ((batch->start | batch->used) & 0x7) { 506235783Skib DRM_ERROR("alignment\n"); 507235783Skib return -EINVAL; 508235783Skib } 509235783Skib 510235783Skib i915_kernel_lost_context(dev); 511235783Skib 512235783Skib count = nbox ? nbox : 1; 513235783Skib 514235783Skib for (i = 0; i < count; i++) { 515235783Skib if (i < nbox) { 516235783Skib int ret = i915_emit_box_p(dev, &cliprects[i], 517235783Skib batch->DR1, batch->DR4); 518235783Skib if (ret) 519235783Skib return ret; 520235783Skib } 521235783Skib 522235783Skib if (!IS_I830(dev) && !IS_845G(dev)) { 523235783Skib ret = BEGIN_LP_RING(2); 524235783Skib if (ret != 0) 525235783Skib return (ret); 526235783Skib 527235783Skib if (INTEL_INFO(dev)->gen >= 4) { 528235783Skib OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | 529235783Skib MI_BATCH_NON_SECURE_I965); 530235783Skib OUT_RING(batch->start); 531235783Skib } else { 532235783Skib OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); 533235783Skib OUT_RING(batch->start | MI_BATCH_NON_SECURE); 534235783Skib } 535235783Skib } else { 536235783Skib ret = BEGIN_LP_RING(4); 537235783Skib if (ret != 0) 538235783Skib return (ret); 539235783Skib 540235783Skib OUT_RING(MI_BATCH_BUFFER); 541235783Skib OUT_RING(batch->start | MI_BATCH_NON_SECURE); 542235783Skib OUT_RING(batch->start + batch->used - 4); 543235783Skib OUT_RING(0); 544235783Skib } 545235783Skib ADVANCE_LP_RING(); 546235783Skib } 547235783Skib 548235783Skib i915_emit_breadcrumb(dev); 549235783Skib 550235783Skib return 0; 551235783Skib} 552235783Skib 553235783Skibstatic int i915_dispatch_flip(struct drm_device * dev) 554235783Skib{ 555235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 556235783Skib int ret; 557235783Skib 558235783Skib if (!dev_priv->sarea_priv) 559235783Skib return -EINVAL; 560235783Skib 561235783Skib DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", 562235783Skib __func__, 563235783Skib dev_priv->current_page, 564235783Skib dev_priv->sarea_priv->pf_current_page); 565235783Skib 566235783Skib i915_kernel_lost_context(dev); 567235783Skib 568235783Skib ret = BEGIN_LP_RING(10); 569235783Skib if (ret) 570235783Skib return ret; 571235783Skib OUT_RING(MI_FLUSH | MI_READ_FLUSH); 572235783Skib OUT_RING(0); 573235783Skib 574235783Skib OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); 575235783Skib OUT_RING(0); 576235783Skib if (dev_priv->current_page == 0) { 577235783Skib OUT_RING(dev_priv->back_offset); 578235783Skib dev_priv->current_page = 1; 579235783Skib } else { 580235783Skib OUT_RING(dev_priv->front_offset); 581235783Skib dev_priv->current_page = 0; 582235783Skib } 583235783Skib OUT_RING(0); 584235783Skib 585235783Skib OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); 586235783Skib OUT_RING(0); 587235783Skib 588235783Skib ADVANCE_LP_RING(); 589235783Skib 590235783Skib if (++dev_priv->counter > 0x7FFFFFFFUL) 591235783Skib dev_priv->counter = 0; 592235783Skib if (dev_priv->sarea_priv) 593235783Skib dev_priv->sarea_priv->last_enqueue = dev_priv->counter; 594235783Skib 595235783Skib if (BEGIN_LP_RING(4) == 0) { 596235783Skib OUT_RING(MI_STORE_DWORD_INDEX); 597235783Skib OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 598235783Skib OUT_RING(dev_priv->counter); 599235783Skib OUT_RING(0); 600235783Skib ADVANCE_LP_RING(); 601235783Skib } 602235783Skib 603235783Skib dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; 604235783Skib return 0; 605235783Skib} 606235783Skib 607235783Skibstatic int 608235783Skibi915_quiescent(struct drm_device *dev) 609235783Skib{ 610235783Skib struct intel_ring_buffer *ring = LP_RING(dev->dev_private); 611235783Skib 612235783Skib i915_kernel_lost_context(dev); 613235783Skib return (intel_wait_ring_idle(ring)); 614235783Skib} 615235783Skib 616235783Skibstatic int 617235783Skibi915_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) 618235783Skib{ 619235783Skib int ret; 620235783Skib 621235783Skib RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 622235783Skib 623235783Skib DRM_LOCK(dev); 624235783Skib ret = i915_quiescent(dev); 625235783Skib DRM_UNLOCK(dev); 626235783Skib 627235783Skib return (ret); 628235783Skib} 629235783Skib 630239375Skibint i915_batchbuffer(struct drm_device *dev, void *data, 631235783Skib struct drm_file *file_priv) 632235783Skib{ 633235783Skib drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 634235783Skib drm_i915_sarea_t *sarea_priv; 635235783Skib drm_i915_batchbuffer_t *batch = data; 636235783Skib struct drm_clip_rect *cliprects; 637235783Skib size_t cliplen; 638235783Skib int ret; 639235783Skib 640235783Skib if (!dev_priv->allow_batchbuffer) { 641235783Skib DRM_ERROR("Batchbuffer ioctl disabled\n"); 642235783Skib return -EINVAL; 643235783Skib } 644235783Skib DRM_UNLOCK(dev); 645235783Skib 646235783Skib DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n", 647235783Skib batch->start, batch->used, batch->num_cliprects); 648235783Skib 649235783Skib cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect); 650235783Skib if (batch->num_cliprects < 0) 651235783Skib return -EFAULT; 652235783Skib if (batch->num_cliprects != 0) { 653235783Skib cliprects = malloc(batch->num_cliprects * 654235783Skib sizeof(struct drm_clip_rect), DRM_MEM_DMA, 655235783Skib M_WAITOK | M_ZERO); 656235783Skib 657235783Skib ret = -copyin(batch->cliprects, cliprects, 658235783Skib batch->num_cliprects * sizeof(struct drm_clip_rect)); 659235783Skib if (ret != 0) { 660235783Skib DRM_LOCK(dev); 661235783Skib goto fail_free; 662235783Skib } 663235783Skib } else 664235783Skib cliprects = NULL; 665235783Skib 666235783Skib DRM_LOCK(dev); 667235783Skib RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 668235783Skib ret = i915_dispatch_batchbuffer(dev, batch, cliprects); 669235783Skib 670235783Skib sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv; 671235783Skib if (sarea_priv) 672235783Skib sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 673235783Skib 674235783Skibfail_free: 675235783Skib free(cliprects, DRM_MEM_DMA); 676235783Skib return ret; 677235783Skib} 678235783Skib 679239375Skibint i915_cmdbuffer(struct drm_device *dev, void *data, 680235783Skib struct drm_file *file_priv) 681235783Skib{ 682235783Skib drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 683235783Skib drm_i915_sarea_t *sarea_priv; 684235783Skib drm_i915_cmdbuffer_t *cmdbuf = data; 685235783Skib struct drm_clip_rect *cliprects = NULL; 686235783Skib void *batch_data; 687235783Skib int ret; 688235783Skib 689235783Skib DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n", 690235783Skib cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); 691235783Skib 692235783Skib if (cmdbuf->num_cliprects < 0) 693235783Skib return -EINVAL; 694235783Skib 695235783Skib DRM_UNLOCK(dev); 696235783Skib 697235783Skib batch_data = malloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK); 698235783Skib 699235783Skib ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz); 700235783Skib if (ret != 0) { 701235783Skib DRM_LOCK(dev); 702235783Skib goto fail_batch_free; 703235783Skib } 704235783Skib 705235783Skib if (cmdbuf->num_cliprects) { 706235783Skib cliprects = malloc(cmdbuf->num_cliprects * 707235783Skib sizeof(struct drm_clip_rect), DRM_MEM_DMA, 708235783Skib M_WAITOK | M_ZERO); 709235783Skib ret = -copyin(cmdbuf->cliprects, cliprects, 710235783Skib cmdbuf->num_cliprects * sizeof(struct drm_clip_rect)); 711235783Skib if (ret != 0) { 712235783Skib DRM_LOCK(dev); 713235783Skib goto fail_clip_free; 714235783Skib } 715235783Skib } 716235783Skib 717235783Skib DRM_LOCK(dev); 718235783Skib RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 719235783Skib ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data); 720235783Skib if (ret) { 721235783Skib DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); 722235783Skib goto fail_clip_free; 723235783Skib } 724235783Skib 725235783Skib sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv; 726235783Skib if (sarea_priv) 727235783Skib sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 728235783Skib 729235783Skibfail_clip_free: 730235783Skib free(cliprects, DRM_MEM_DMA); 731235783Skibfail_batch_free: 732235783Skib free(batch_data, DRM_MEM_DMA); 733235783Skib return ret; 734235783Skib} 735235783Skib 736235783Skibstatic int i915_flip_bufs(struct drm_device *dev, void *data, 737235783Skib struct drm_file *file_priv) 738235783Skib{ 739235783Skib int ret; 740235783Skib 741235783Skib DRM_DEBUG("%s\n", __func__); 742235783Skib 743235783Skib RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 744235783Skib 745235783Skib ret = i915_dispatch_flip(dev); 746235783Skib 747235783Skib return ret; 748235783Skib} 749235783Skib 750239375Skibint i915_getparam(struct drm_device *dev, void *data, 751235783Skib struct drm_file *file_priv) 752235783Skib{ 753235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 754235783Skib drm_i915_getparam_t *param = data; 755235783Skib int value; 756235783Skib 757235783Skib if (!dev_priv) { 758235783Skib DRM_ERROR("called with no initialization\n"); 759235783Skib return -EINVAL; 760235783Skib } 761235783Skib 762235783Skib switch (param->param) { 763235783Skib case I915_PARAM_IRQ_ACTIVE: 764235783Skib value = dev->irq_enabled ? 1 : 0; 765235783Skib break; 766235783Skib case I915_PARAM_ALLOW_BATCHBUFFER: 767235783Skib value = dev_priv->allow_batchbuffer ? 1 : 0; 768235783Skib break; 769235783Skib case I915_PARAM_LAST_DISPATCH: 770235783Skib value = READ_BREADCRUMB(dev_priv); 771235783Skib break; 772235783Skib case I915_PARAM_CHIPSET_ID: 773235783Skib value = dev->pci_device; 774235783Skib break; 775235783Skib case I915_PARAM_HAS_GEM: 776235783Skib value = 1; 777235783Skib break; 778235783Skib case I915_PARAM_NUM_FENCES_AVAIL: 779235783Skib value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; 780235783Skib break; 781235783Skib case I915_PARAM_HAS_OVERLAY: 782235783Skib value = dev_priv->overlay ? 1 : 0; 783235783Skib break; 784235783Skib case I915_PARAM_HAS_PAGEFLIPPING: 785235783Skib value = 1; 786235783Skib break; 787235783Skib case I915_PARAM_HAS_EXECBUF2: 788235783Skib value = 1; 789235783Skib break; 790235783Skib case I915_PARAM_HAS_BSD: 791235783Skib value = HAS_BSD(dev); 792235783Skib break; 793235783Skib case I915_PARAM_HAS_BLT: 794235783Skib value = HAS_BLT(dev); 795235783Skib break; 796235783Skib case I915_PARAM_HAS_RELAXED_FENCING: 797235783Skib value = 1; 798235783Skib break; 799235783Skib case I915_PARAM_HAS_COHERENT_RINGS: 800235783Skib value = 1; 801235783Skib break; 802235783Skib case I915_PARAM_HAS_EXEC_CONSTANTS: 803235783Skib value = INTEL_INFO(dev)->gen >= 4; 804235783Skib break; 805235783Skib case I915_PARAM_HAS_RELAXED_DELTA: 806235783Skib value = 1; 807235783Skib break; 808235783Skib case I915_PARAM_HAS_GEN7_SOL_RESET: 809235783Skib value = 1; 810235783Skib break; 811235783Skib case I915_PARAM_HAS_LLC: 812235783Skib value = HAS_LLC(dev); 813235783Skib break; 814235783Skib default: 815235783Skib DRM_DEBUG_DRIVER("Unknown parameter %d\n", 816235783Skib param->param); 817235783Skib return -EINVAL; 818235783Skib } 819235783Skib 820235783Skib if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { 821235783Skib DRM_ERROR("DRM_COPY_TO_USER failed\n"); 822235783Skib return -EFAULT; 823235783Skib } 824235783Skib 825235783Skib return 0; 826235783Skib} 827235783Skib 828235783Skibstatic int i915_setparam(struct drm_device *dev, void *data, 829235783Skib struct drm_file *file_priv) 830235783Skib{ 831235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 832235783Skib drm_i915_setparam_t *param = data; 833235783Skib 834235783Skib if (!dev_priv) { 835235783Skib DRM_ERROR("called with no initialization\n"); 836235783Skib return -EINVAL; 837235783Skib } 838235783Skib 839235783Skib switch (param->param) { 840235783Skib case I915_SETPARAM_USE_MI_BATCHBUFFER_START: 841235783Skib break; 842235783Skib case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: 843235783Skib dev_priv->tex_lru_log_granularity = param->value; 844235783Skib break; 845235783Skib case I915_SETPARAM_ALLOW_BATCHBUFFER: 846235783Skib dev_priv->allow_batchbuffer = param->value; 847235783Skib break; 848235783Skib case I915_SETPARAM_NUM_USED_FENCES: 849235783Skib if (param->value > dev_priv->num_fence_regs || 850235783Skib param->value < 0) 851235783Skib return -EINVAL; 852235783Skib /* Userspace can use first N regs */ 853235783Skib dev_priv->fence_reg_start = param->value; 854235783Skib break; 855235783Skib default: 856235783Skib DRM_DEBUG("unknown parameter %d\n", param->param); 857235783Skib return -EINVAL; 858235783Skib } 859235783Skib 860235783Skib return 0; 861235783Skib} 862235783Skib 863235783Skibstatic int i915_set_status_page(struct drm_device *dev, void *data, 864235783Skib struct drm_file *file_priv) 865235783Skib{ 866235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 867235783Skib drm_i915_hws_addr_t *hws = data; 868235783Skib struct intel_ring_buffer *ring = LP_RING(dev_priv); 869235783Skib 870235783Skib if (!I915_NEED_GFX_HWS(dev)) 871235783Skib return -EINVAL; 872235783Skib 873235783Skib if (!dev_priv) { 874235783Skib DRM_ERROR("called with no initialization\n"); 875235783Skib return -EINVAL; 876235783Skib } 877235783Skib 878235783Skib DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr); 879235783Skib if (drm_core_check_feature(dev, DRIVER_MODESET)) { 880235783Skib DRM_ERROR("tried to set status page when mode setting active\n"); 881235783Skib return 0; 882235783Skib } 883235783Skib 884235783Skib ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 885235783Skib hws->addr & (0x1ffff<<12); 886235783Skib 887235783Skib dev_priv->hws_map.offset = dev->agp->base + hws->addr; 888235783Skib dev_priv->hws_map.size = 4*1024; 889235783Skib dev_priv->hws_map.type = 0; 890235783Skib dev_priv->hws_map.flags = 0; 891235783Skib dev_priv->hws_map.mtrr = 0; 892235783Skib 893235783Skib drm_core_ioremap_wc(&dev_priv->hws_map, dev); 894235783Skib if (dev_priv->hws_map.virtual == NULL) { 895235783Skib i915_dma_cleanup(dev); 896235783Skib ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0; 897235783Skib DRM_ERROR("can not ioremap virtual address for" 898235783Skib " G33 hw status page\n"); 899235783Skib return -ENOMEM; 900235783Skib } 901235783Skib ring->status_page.page_addr = dev_priv->hw_status_page = 902235783Skib dev_priv->hws_map.virtual; 903235783Skib 904235783Skib memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 905235783Skib I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); 906235783Skib DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n", 907235783Skib dev_priv->status_gfx_addr); 908235783Skib DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page); 909235783Skib return 0; 910235783Skib} 911235783Skib 912235783Skibstatic bool 913235783Skibintel_enable_ppgtt(struct drm_device *dev) 914235783Skib{ 915235783Skib if (i915_enable_ppgtt >= 0) 916235783Skib return i915_enable_ppgtt; 917235783Skib 918235783Skib /* Disable ppgtt on SNB if VT-d is on. */ 919235783Skib if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled) 920235783Skib return false; 921235783Skib 922235783Skib return true; 923235783Skib} 924235783Skib 925235783Skibstatic int 926235783Skibi915_load_gem_init(struct drm_device *dev) 927235783Skib{ 928235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 929235783Skib unsigned long prealloc_size, gtt_size, mappable_size; 930235783Skib int ret; 931235783Skib 932235783Skib prealloc_size = dev_priv->mm.gtt.stolen_size; 933235783Skib gtt_size = dev_priv->mm.gtt.gtt_total_entries << PAGE_SHIFT; 934235783Skib mappable_size = dev_priv->mm.gtt.gtt_mappable_entries << PAGE_SHIFT; 935235783Skib 936235783Skib /* Basic memrange allocator for stolen space */ 937235783Skib drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size); 938235783Skib 939235783Skib DRM_LOCK(dev); 940235783Skib if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { 941235783Skib /* PPGTT pdes are stolen from global gtt ptes, so shrink the 942235783Skib * aperture accordingly when using aliasing ppgtt. */ 943235783Skib gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; 944235783Skib /* For paranoia keep the guard page in between. */ 945235783Skib gtt_size -= PAGE_SIZE; 946235783Skib 947235783Skib i915_gem_do_init(dev, 0, mappable_size, gtt_size); 948235783Skib 949235783Skib ret = i915_gem_init_aliasing_ppgtt(dev); 950235783Skib if (ret) { 951235783Skib DRM_UNLOCK(dev); 952235783Skib return ret; 953235783Skib } 954235783Skib } else { 955235783Skib /* Let GEM Manage all of the aperture. 956235783Skib * 957235783Skib * However, leave one page at the end still bound to the scratch 958235783Skib * page. There are a number of places where the hardware 959235783Skib * apparently prefetches past the end of the object, and we've 960235783Skib * seen multiple hangs with the GPU head pointer stuck in a 961235783Skib * batchbuffer bound at the last page of the aperture. One page 962235783Skib * should be enough to keep any prefetching inside of the 963235783Skib * aperture. 964235783Skib */ 965235783Skib i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE); 966235783Skib } 967235783Skib 968235783Skib ret = i915_gem_init_hw(dev); 969235783Skib DRM_UNLOCK(dev); 970235783Skib if (ret != 0) { 971235783Skib i915_gem_cleanup_aliasing_ppgtt(dev); 972235783Skib return (ret); 973235783Skib } 974235783Skib 975235783Skib#if 0 976235783Skib /* Try to set up FBC with a reasonable compressed buffer size */ 977235783Skib if (I915_HAS_FBC(dev) && i915_powersave) { 978235783Skib int cfb_size; 979235783Skib 980235783Skib /* Leave 1M for line length buffer & misc. */ 981235783Skib 982235783Skib /* Try to get a 32M buffer... */ 983235783Skib if (prealloc_size > (36*1024*1024)) 984235783Skib cfb_size = 32*1024*1024; 985235783Skib else /* fall back to 7/8 of the stolen space */ 986235783Skib cfb_size = prealloc_size * 7 / 8; 987235783Skib i915_setup_compression(dev, cfb_size); 988235783Skib } 989235783Skib#endif 990235783Skib 991235783Skib /* Allow hardware batchbuffers unless told otherwise. */ 992235783Skib dev_priv->allow_batchbuffer = 1; 993235783Skib return 0; 994235783Skib} 995235783Skib 996235783Skibstatic int 997235783Skibi915_load_modeset_init(struct drm_device *dev) 998235783Skib{ 999235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 1000235783Skib int ret; 1001235783Skib 1002235783Skib ret = intel_parse_bios(dev); 1003235783Skib if (ret) 1004235783Skib DRM_INFO("failed to find VBIOS tables\n"); 1005235783Skib 1006235783Skib#if 0 1007235783Skib intel_register_dsm_handler(); 1008235783Skib#endif 1009235783Skib 1010235783Skib /* IIR "flip pending" bit means done if this bit is set */ 1011235783Skib if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE)) 1012235783Skib dev_priv->flip_pending_is_done = true; 1013235783Skib 1014235783Skib intel_modeset_init(dev); 1015235783Skib 1016235783Skib ret = i915_load_gem_init(dev); 1017235783Skib if (ret != 0) 1018235783Skib goto cleanup_gem; 1019235783Skib 1020235783Skib intel_modeset_gem_init(dev); 1021235783Skib 1022235783Skib ret = drm_irq_install(dev); 1023235783Skib if (ret) 1024235783Skib goto cleanup_gem; 1025235783Skib 1026235783Skib dev->vblank_disable_allowed = 1; 1027235783Skib 1028235783Skib ret = intel_fbdev_init(dev); 1029235783Skib if (ret) 1030235783Skib goto cleanup_gem; 1031235783Skib 1032235783Skib drm_kms_helper_poll_init(dev); 1033235783Skib 1034235783Skib /* We're off and running w/KMS */ 1035235783Skib dev_priv->mm.suspended = 0; 1036235783Skib 1037235783Skib return (0); 1038235783Skib 1039235783Skibcleanup_gem: 1040235783Skib DRM_LOCK(dev); 1041235783Skib i915_gem_cleanup_ringbuffer(dev); 1042235783Skib DRM_UNLOCK(dev); 1043235783Skib i915_gem_cleanup_aliasing_ppgtt(dev); 1044235783Skib return (ret); 1045235783Skib} 1046235783Skib 1047235783Skibstatic int 1048235783Skibi915_get_bridge_dev(struct drm_device *dev) 1049235783Skib{ 1050235783Skib struct drm_i915_private *dev_priv; 1051235783Skib 1052235783Skib dev_priv = dev->dev_private; 1053235783Skib 1054235783Skib dev_priv->bridge_dev = intel_gtt_get_bridge_device(); 1055235783Skib if (dev_priv->bridge_dev == NULL) { 1056235783Skib DRM_ERROR("bridge device not found\n"); 1057235783Skib return (-1); 1058235783Skib } 1059235783Skib return (0); 1060235783Skib} 1061235783Skib 1062235783Skib#define MCHBAR_I915 0x44 1063235783Skib#define MCHBAR_I965 0x48 1064235783Skib#define MCHBAR_SIZE (4*4096) 1065235783Skib 1066235783Skib#define DEVEN_REG 0x54 1067235783Skib#define DEVEN_MCHBAR_EN (1 << 28) 1068235783Skib 1069235783Skib/* Allocate space for the MCH regs if needed, return nonzero on error */ 1070235783Skibstatic int 1071235783Skibintel_alloc_mchbar_resource(struct drm_device *dev) 1072235783Skib{ 1073235783Skib drm_i915_private_t *dev_priv; 1074235783Skib device_t vga; 1075235783Skib int reg; 1076235783Skib u32 temp_lo, temp_hi; 1077235783Skib u64 mchbar_addr, temp; 1078235783Skib 1079235783Skib dev_priv = dev->dev_private; 1080235783Skib reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; 1081235783Skib 1082235783Skib if (INTEL_INFO(dev)->gen >= 4) 1083235783Skib temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4); 1084235783Skib else 1085235783Skib temp_hi = 0; 1086235783Skib temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4); 1087235783Skib mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 1088235783Skib 1089235783Skib /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 1090235783Skib#ifdef XXX_CONFIG_PNP 1091235783Skib if (mchbar_addr && 1092235783Skib pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) 1093235783Skib return 0; 1094235783Skib#endif 1095235783Skib 1096235783Skib /* Get some space for it */ 1097235783Skib vga = device_get_parent(dev->device); 1098235783Skib dev_priv->mch_res_rid = 0x100; 1099235783Skib dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga), 1100235783Skib dev->device, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL, 1101235783Skib MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE); 1102235783Skib if (dev_priv->mch_res == NULL) { 1103235783Skib DRM_ERROR("failed mchbar resource alloc\n"); 1104235783Skib return (-ENOMEM); 1105235783Skib } 1106235783Skib 1107235783Skib if (INTEL_INFO(dev)->gen >= 4) { 1108235783Skib temp = rman_get_start(dev_priv->mch_res); 1109235783Skib temp >>= 32; 1110235783Skib pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4); 1111235783Skib } 1112235783Skib pci_write_config(dev_priv->bridge_dev, reg, 1113235783Skib rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4); 1114235783Skib return (0); 1115235783Skib} 1116235783Skib 1117235783Skibstatic void 1118235783Skibintel_setup_mchbar(struct drm_device *dev) 1119235783Skib{ 1120235783Skib drm_i915_private_t *dev_priv; 1121235783Skib int mchbar_reg; 1122235783Skib u32 temp; 1123235783Skib bool enabled; 1124235783Skib 1125235783Skib dev_priv = dev->dev_private; 1126235783Skib mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; 1127235783Skib 1128235783Skib dev_priv->mchbar_need_disable = false; 1129235783Skib 1130235783Skib if (IS_I915G(dev) || IS_I915GM(dev)) { 1131235783Skib temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4); 1132235783Skib enabled = (temp & DEVEN_MCHBAR_EN) != 0; 1133235783Skib } else { 1134235783Skib temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4); 1135235783Skib enabled = temp & 1; 1136235783Skib } 1137235783Skib 1138235783Skib /* If it's already enabled, don't have to do anything */ 1139235783Skib if (enabled) { 1140235783Skib DRM_DEBUG("mchbar already enabled\n"); 1141235783Skib return; 1142235783Skib } 1143235783Skib 1144235783Skib if (intel_alloc_mchbar_resource(dev)) 1145235783Skib return; 1146235783Skib 1147235783Skib dev_priv->mchbar_need_disable = true; 1148235783Skib 1149235783Skib /* Space is allocated or reserved, so enable it. */ 1150235783Skib if (IS_I915G(dev) || IS_I915GM(dev)) { 1151235783Skib pci_write_config(dev_priv->bridge_dev, DEVEN_REG, 1152235783Skib temp | DEVEN_MCHBAR_EN, 4); 1153235783Skib } else { 1154235783Skib temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4); 1155235783Skib pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4); 1156235783Skib } 1157235783Skib} 1158235783Skib 1159235783Skibstatic void 1160235783Skibintel_teardown_mchbar(struct drm_device *dev) 1161235783Skib{ 1162235783Skib drm_i915_private_t *dev_priv; 1163235783Skib device_t vga; 1164235783Skib int mchbar_reg; 1165235783Skib u32 temp; 1166235783Skib 1167235783Skib dev_priv = dev->dev_private; 1168235783Skib mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; 1169235783Skib 1170235783Skib if (dev_priv->mchbar_need_disable) { 1171235783Skib if (IS_I915G(dev) || IS_I915GM(dev)) { 1172235783Skib temp = pci_read_config(dev_priv->bridge_dev, 1173235783Skib DEVEN_REG, 4); 1174235783Skib temp &= ~DEVEN_MCHBAR_EN; 1175235783Skib pci_write_config(dev_priv->bridge_dev, DEVEN_REG, 1176235783Skib temp, 4); 1177235783Skib } else { 1178235783Skib temp = pci_read_config(dev_priv->bridge_dev, 1179235783Skib mchbar_reg, 4); 1180235783Skib temp &= ~1; 1181235783Skib pci_write_config(dev_priv->bridge_dev, mchbar_reg, 1182235783Skib temp, 4); 1183235783Skib } 1184235783Skib } 1185235783Skib 1186235783Skib if (dev_priv->mch_res != NULL) { 1187235783Skib vga = device_get_parent(dev->device); 1188235783Skib BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->device, 1189235783Skib SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res); 1190235783Skib BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->device, 1191235783Skib SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res); 1192235783Skib dev_priv->mch_res = NULL; 1193235783Skib } 1194235783Skib} 1195235783Skib 1196235783Skibint 1197235783Skibi915_driver_load(struct drm_device *dev, unsigned long flags) 1198235783Skib{ 1199235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 1200235783Skib unsigned long base, size; 1201235783Skib int mmio_bar, ret; 1202235783Skib 1203235783Skib ret = 0; 1204235783Skib 1205235783Skib /* i915 has 4 more counters */ 1206235783Skib dev->counters += 4; 1207235783Skib dev->types[6] = _DRM_STAT_IRQ; 1208235783Skib dev->types[7] = _DRM_STAT_PRIMARY; 1209235783Skib dev->types[8] = _DRM_STAT_SECONDARY; 1210235783Skib dev->types[9] = _DRM_STAT_DMA; 1211235783Skib 1212235783Skib dev_priv = malloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER, 1213235783Skib M_ZERO | M_WAITOK); 1214235783Skib if (dev_priv == NULL) 1215235783Skib return -ENOMEM; 1216235783Skib 1217235783Skib dev->dev_private = (void *)dev_priv; 1218235783Skib dev_priv->dev = dev; 1219235783Skib dev_priv->info = i915_get_device_id(dev->pci_device); 1220235783Skib 1221235783Skib if (i915_get_bridge_dev(dev)) { 1222235783Skib free(dev_priv, DRM_MEM_DRIVER); 1223235783Skib return (-EIO); 1224235783Skib } 1225235783Skib dev_priv->mm.gtt = intel_gtt_get(); 1226235783Skib 1227235783Skib /* Add register map (needed for suspend/resume) */ 1228235783Skib mmio_bar = IS_GEN2(dev) ? 1 : 0; 1229235783Skib base = drm_get_resource_start(dev, mmio_bar); 1230235783Skib size = drm_get_resource_len(dev, mmio_bar); 1231235783Skib 1232235783Skib ret = drm_addmap(dev, base, size, _DRM_REGISTERS, 1233235783Skib _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map); 1234235783Skib 1235235783Skib dev_priv->tq = taskqueue_create("915", M_WAITOK, 1236235783Skib taskqueue_thread_enqueue, &dev_priv->tq); 1237235783Skib taskqueue_start_threads(&dev_priv->tq, 1, PWAIT, "i915 taskq"); 1238235783Skib mtx_init(&dev_priv->gt_lock, "915gt", NULL, MTX_DEF); 1239235783Skib mtx_init(&dev_priv->error_lock, "915err", NULL, MTX_DEF); 1240235783Skib mtx_init(&dev_priv->error_completion_lock, "915cmp", NULL, MTX_DEF); 1241235783Skib mtx_init(&dev_priv->rps_lock, "915rps", NULL, MTX_DEF); 1242235783Skib 1243235783Skib dev_priv->has_gem = 1; 1244235783Skib intel_irq_init(dev); 1245235783Skib 1246235783Skib intel_setup_mchbar(dev); 1247235783Skib intel_setup_gmbus(dev); 1248235783Skib intel_opregion_setup(dev); 1249235783Skib 1250235783Skib intel_setup_bios(dev); 1251235783Skib 1252235783Skib i915_gem_load(dev); 1253235783Skib 1254235783Skib /* Init HWS */ 1255235783Skib if (!I915_NEED_GFX_HWS(dev)) { 1256235783Skib ret = i915_init_phys_hws(dev); 1257235783Skib if (ret != 0) { 1258235783Skib drm_rmmap(dev, dev_priv->mmio_map); 1259235783Skib drm_free(dev_priv, sizeof(struct drm_i915_private), 1260235783Skib DRM_MEM_DRIVER); 1261235783Skib return ret; 1262235783Skib } 1263235783Skib } 1264235783Skib 1265235783Skib if (IS_PINEVIEW(dev)) 1266235783Skib i915_pineview_get_mem_freq(dev); 1267235783Skib else if (IS_GEN5(dev)) 1268235783Skib i915_ironlake_get_mem_freq(dev); 1269235783Skib 1270235783Skib mtx_init(&dev_priv->irq_lock, "userirq", NULL, MTX_DEF); 1271235783Skib 1272235783Skib if (IS_IVYBRIDGE(dev)) 1273235783Skib dev_priv->num_pipe = 3; 1274235783Skib else if (IS_MOBILE(dev) || !IS_GEN2(dev)) 1275235783Skib dev_priv->num_pipe = 2; 1276235783Skib else 1277235783Skib dev_priv->num_pipe = 1; 1278235783Skib 1279235783Skib ret = drm_vblank_init(dev, dev_priv->num_pipe); 1280235783Skib if (ret) 1281235783Skib goto out_gem_unload; 1282235783Skib 1283235783Skib /* Start out suspended */ 1284235783Skib dev_priv->mm.suspended = 1; 1285235783Skib 1286235783Skib intel_detect_pch(dev); 1287235783Skib 1288235783Skib if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1289235783Skib DRM_UNLOCK(dev); 1290235783Skib ret = i915_load_modeset_init(dev); 1291235783Skib DRM_LOCK(dev); 1292235783Skib if (ret < 0) { 1293235783Skib DRM_ERROR("failed to init modeset\n"); 1294235783Skib goto out_gem_unload; 1295235783Skib } 1296235783Skib } 1297235783Skib 1298235783Skib intel_opregion_init(dev); 1299235783Skib 1300235783Skib callout_init(&dev_priv->hangcheck_timer, 1); 1301235783Skib callout_reset(&dev_priv->hangcheck_timer, DRM_I915_HANGCHECK_PERIOD, 1302235783Skib i915_hangcheck_elapsed, dev); 1303235783Skib 1304235783Skib if (IS_GEN5(dev)) { 1305235783Skib mtx_lock(&mchdev_lock); 1306235783Skib i915_mch_dev = dev_priv; 1307235783Skib dev_priv->mchdev_lock = &mchdev_lock; 1308235783Skib mtx_unlock(&mchdev_lock); 1309235783Skib } 1310235783Skib 1311235783Skib return (0); 1312235783Skib 1313235783Skibout_gem_unload: 1314235783Skib /* XXXKIB */ 1315235783Skib (void) i915_driver_unload_int(dev, true); 1316235783Skib return (ret); 1317235783Skib} 1318235783Skib 1319235783Skibstatic int 1320235783Skibi915_driver_unload_int(struct drm_device *dev, bool locked) 1321235783Skib{ 1322235783Skib struct drm_i915_private *dev_priv = dev->dev_private; 1323235783Skib int ret; 1324235783Skib 1325235783Skib if (!locked) 1326235783Skib DRM_LOCK(dev); 1327235783Skib ret = i915_gpu_idle(dev, true); 1328235783Skib if (ret) 1329235783Skib DRM_ERROR("failed to idle hardware: %d\n", ret); 1330235783Skib if (!locked) 1331235783Skib DRM_UNLOCK(dev); 1332235783Skib 1333235783Skib i915_free_hws(dev); 1334235783Skib 1335235783Skib intel_teardown_mchbar(dev); 1336235783Skib 1337235783Skib if (locked) 1338235783Skib DRM_UNLOCK(dev); 1339235783Skib if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1340235783Skib intel_fbdev_fini(dev); 1341235783Skib intel_modeset_cleanup(dev); 1342235783Skib } 1343235783Skib 1344235783Skib /* Free error state after interrupts are fully disabled. */ 1345235783Skib callout_stop(&dev_priv->hangcheck_timer); 1346235783Skib callout_drain(&dev_priv->hangcheck_timer); 1347235783Skib 1348235783Skib i915_destroy_error_state(dev); 1349235783Skib 1350235783Skib intel_opregion_fini(dev); 1351235783Skib 1352235783Skib if (locked) 1353235783Skib DRM_LOCK(dev); 1354235783Skib 1355235783Skib if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1356235783Skib if (!locked) 1357235783Skib DRM_LOCK(dev); 1358235783Skib i915_gem_free_all_phys_object(dev); 1359235783Skib i915_gem_cleanup_ringbuffer(dev); 1360271705Sdumbbell i915_gem_context_fini(dev); 1361235783Skib if (!locked) 1362235783Skib DRM_UNLOCK(dev); 1363235783Skib i915_gem_cleanup_aliasing_ppgtt(dev); 1364235783Skib#if 1 1365235783Skib KIB_NOTYET(); 1366235783Skib#else 1367235783Skib if (I915_HAS_FBC(dev) && i915_powersave) 1368235783Skib i915_cleanup_compression(dev); 1369235783Skib#endif 1370235783Skib drm_mm_takedown(&dev_priv->mm.stolen); 1371235783Skib 1372235783Skib intel_cleanup_overlay(dev); 1373235783Skib 1374235783Skib if (!I915_NEED_GFX_HWS(dev)) 1375235783Skib i915_free_hws(dev); 1376235783Skib } 1377235783Skib 1378235783Skib i915_gem_unload(dev); 1379235783Skib 1380235783Skib mtx_destroy(&dev_priv->irq_lock); 1381235783Skib 1382235783Skib if (dev_priv->tq != NULL) 1383235783Skib taskqueue_free(dev_priv->tq); 1384235783Skib 1385235783Skib bus_generic_detach(dev->device); 1386235783Skib drm_rmmap(dev, dev_priv->mmio_map); 1387235783Skib intel_teardown_gmbus(dev); 1388235783Skib 1389235783Skib mtx_destroy(&dev_priv->error_lock); 1390235783Skib mtx_destroy(&dev_priv->error_completion_lock); 1391235783Skib mtx_destroy(&dev_priv->rps_lock); 1392235783Skib drm_free(dev->dev_private, sizeof(drm_i915_private_t), 1393235783Skib DRM_MEM_DRIVER); 1394235783Skib 1395235783Skib return (0); 1396235783Skib} 1397235783Skib 1398235783Skibint 1399235783Skibi915_driver_unload(struct drm_device *dev) 1400235783Skib{ 1401235783Skib 1402235783Skib return (i915_driver_unload_int(dev, true)); 1403235783Skib} 1404235783Skib 1405235783Skibint 1406235783Skibi915_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1407235783Skib{ 1408235783Skib struct drm_i915_file_private *i915_file_priv; 1409235783Skib 1410235783Skib i915_file_priv = malloc(sizeof(*i915_file_priv), DRM_MEM_FILES, 1411235783Skib M_WAITOK | M_ZERO); 1412235783Skib 1413235783Skib mtx_init(&i915_file_priv->mm.lck, "915fp", NULL, MTX_DEF); 1414235783Skib INIT_LIST_HEAD(&i915_file_priv->mm.request_list); 1415235783Skib file_priv->driver_priv = i915_file_priv; 1416235783Skib 1417271705Sdumbbell drm_gem_names_init(&i915_file_priv->context_idr); 1418271705Sdumbbell 1419235783Skib return (0); 1420235783Skib} 1421235783Skib 1422235783Skibvoid 1423235783Skibi915_driver_lastclose(struct drm_device * dev) 1424235783Skib{ 1425235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 1426235783Skib 1427235783Skib if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) { 1428235783Skib#if 1 1429235783Skib KIB_NOTYET(); 1430235783Skib#else 1431235783Skib drm_fb_helper_restore(); 1432235783Skib vga_switcheroo_process_delayed_switch(); 1433235783Skib#endif 1434235783Skib return; 1435235783Skib } 1436235783Skib i915_gem_lastclose(dev); 1437235783Skib i915_dma_cleanup(dev); 1438235783Skib} 1439235783Skib 1440235783Skibvoid i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) 1441235783Skib{ 1442235783Skib 1443271705Sdumbbell i915_gem_context_close(dev, file_priv); 1444235783Skib i915_gem_release(dev, file_priv); 1445235783Skib} 1446235783Skib 1447235783Skibvoid i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) 1448235783Skib{ 1449235783Skib struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; 1450235783Skib 1451235783Skib mtx_destroy(&i915_file_priv->mm.lck); 1452235783Skib drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES); 1453235783Skib} 1454235783Skib 1455235783Skibstruct drm_ioctl_desc i915_ioctls[] = { 1456235783Skib DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1457235783Skib DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), 1458235783Skib DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), 1459235783Skib DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), 1460235783Skib DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), 1461235783Skib DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), 1462235783Skib DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), 1463235783Skib DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1464235783Skib DRM_IOCTL_DEF(DRM_I915_ALLOC, drm_noop, DRM_AUTH), 1465235783Skib DRM_IOCTL_DEF(DRM_I915_FREE, drm_noop, DRM_AUTH), 1466235783Skib DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1467235783Skib DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), 1468235783Skib DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), 1469235783Skib DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), 1470235783Skib DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), 1471235783Skib DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), 1472235783Skib DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1473235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1474235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH | DRM_UNLOCKED), 1475235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH | DRM_UNLOCKED), 1476235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), 1477235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), 1478235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), 1479235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH), 1480235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1481235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1482235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0), 1483235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED), 1484235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED), 1485235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0), 1486235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED), 1487235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED), 1488235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED), 1489235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0), 1490235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0), 1491235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED), 1492235783Skib DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), 1493235783Skib DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED), 1494235783Skib DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), 1495235783Skib DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), 1496235783Skib DRM_IOCTL_DEF(DRM_I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), 1497235783Skib DRM_IOCTL_DEF(DRM_I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), 1498271705Sdumbbell DRM_IOCTL_DEF(DRM_I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED), 1499271705Sdumbbell DRM_IOCTL_DEF(DRM_I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED), 1500235783Skib}; 1501235783Skib 1502239375Skib#ifdef COMPAT_FREEBSD32 1503239375Skibextern drm_ioctl_desc_t i915_compat_ioctls[]; 1504239375Skibextern int i915_compat_ioctls_nr; 1505239375Skib#endif 1506239375Skib 1507235783Skibstruct drm_driver_info i915_driver_info = { 1508235783Skib .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | 1509235783Skib DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ | 1510235783Skib DRIVER_GEM /*| DRIVER_MODESET*/, 1511235783Skib 1512235783Skib .buf_priv_size = sizeof(drm_i915_private_t), 1513235783Skib .load = i915_driver_load, 1514235783Skib .open = i915_driver_open, 1515235783Skib .unload = i915_driver_unload, 1516235783Skib .preclose = i915_driver_preclose, 1517235783Skib .lastclose = i915_driver_lastclose, 1518235783Skib .postclose = i915_driver_postclose, 1519235783Skib .device_is_agp = i915_driver_device_is_agp, 1520235783Skib .gem_init_object = i915_gem_init_object, 1521235783Skib .gem_free_object = i915_gem_free_object, 1522235783Skib .gem_pager_ops = &i915_gem_pager_ops, 1523235783Skib .dumb_create = i915_gem_dumb_create, 1524235783Skib .dumb_map_offset = i915_gem_mmap_gtt, 1525235783Skib .dumb_destroy = i915_gem_dumb_destroy, 1526235783Skib .sysctl_init = i915_sysctl_init, 1527235783Skib .sysctl_cleanup = i915_sysctl_cleanup, 1528235783Skib 1529235783Skib .ioctls = i915_ioctls, 1530239375Skib#ifdef COMPAT_FREEBSD32 1531239375Skib .compat_ioctls = i915_compat_ioctls, 1532239375Skib .compat_ioctls_nr = &i915_compat_ioctls_nr, 1533239375Skib#endif 1534235783Skib .max_ioctl = DRM_ARRAY_SIZE(i915_ioctls), 1535235783Skib 1536235783Skib .name = DRIVER_NAME, 1537235783Skib .desc = DRIVER_DESC, 1538235783Skib .date = DRIVER_DATE, 1539235783Skib .major = DRIVER_MAJOR, 1540235783Skib .minor = DRIVER_MINOR, 1541235783Skib .patchlevel = DRIVER_PATCHLEVEL, 1542235783Skib}; 1543235783Skib 1544235783Skib/** 1545235783Skib * Determine if the device really is AGP or not. 1546235783Skib * 1547235783Skib * All Intel graphics chipsets are treated as AGP, even if they are really 1548235783Skib * built-in. 1549235783Skib * 1550235783Skib * \param dev The device to be tested. 1551235783Skib * 1552235783Skib * \returns 1553235783Skib * A value of 1 is always retured to indictate every i9x5 is AGP. 1554235783Skib */ 1555235783Skibint i915_driver_device_is_agp(struct drm_device * dev) 1556235783Skib{ 1557235783Skib return 1; 1558235783Skib} 1559235783Skib 1560235783Skibstatic void i915_pineview_get_mem_freq(struct drm_device *dev) 1561235783Skib{ 1562235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 1563235783Skib u32 tmp; 1564235783Skib 1565235783Skib tmp = I915_READ(CLKCFG); 1566235783Skib 1567235783Skib switch (tmp & CLKCFG_FSB_MASK) { 1568235783Skib case CLKCFG_FSB_533: 1569235783Skib dev_priv->fsb_freq = 533; /* 133*4 */ 1570235783Skib break; 1571235783Skib case CLKCFG_FSB_800: 1572235783Skib dev_priv->fsb_freq = 800; /* 200*4 */ 1573235783Skib break; 1574235783Skib case CLKCFG_FSB_667: 1575235783Skib dev_priv->fsb_freq = 667; /* 167*4 */ 1576235783Skib break; 1577235783Skib case CLKCFG_FSB_400: 1578235783Skib dev_priv->fsb_freq = 400; /* 100*4 */ 1579235783Skib break; 1580235783Skib } 1581235783Skib 1582235783Skib switch (tmp & CLKCFG_MEM_MASK) { 1583235783Skib case CLKCFG_MEM_533: 1584235783Skib dev_priv->mem_freq = 533; 1585235783Skib break; 1586235783Skib case CLKCFG_MEM_667: 1587235783Skib dev_priv->mem_freq = 667; 1588235783Skib break; 1589235783Skib case CLKCFG_MEM_800: 1590235783Skib dev_priv->mem_freq = 800; 1591235783Skib break; 1592235783Skib } 1593235783Skib 1594235783Skib /* detect pineview DDR3 setting */ 1595235783Skib tmp = I915_READ(CSHRDDR3CTL); 1596235783Skib dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; 1597235783Skib} 1598235783Skib 1599235783Skibstatic void i915_ironlake_get_mem_freq(struct drm_device *dev) 1600235783Skib{ 1601235783Skib drm_i915_private_t *dev_priv = dev->dev_private; 1602235783Skib u16 ddrpll, csipll; 1603235783Skib 1604235783Skib ddrpll = I915_READ16(DDRMPLL1); 1605235783Skib csipll = I915_READ16(CSIPLL0); 1606235783Skib 1607235783Skib switch (ddrpll & 0xff) { 1608235783Skib case 0xc: 1609235783Skib dev_priv->mem_freq = 800; 1610235783Skib break; 1611235783Skib case 0x10: 1612235783Skib dev_priv->mem_freq = 1066; 1613235783Skib break; 1614235783Skib case 0x14: 1615235783Skib dev_priv->mem_freq = 1333; 1616235783Skib break; 1617235783Skib case 0x18: 1618235783Skib dev_priv->mem_freq = 1600; 1619235783Skib break; 1620235783Skib default: 1621235783Skib DRM_DEBUG("unknown memory frequency 0x%02x\n", 1622235783Skib ddrpll & 0xff); 1623235783Skib dev_priv->mem_freq = 0; 1624235783Skib break; 1625235783Skib } 1626235783Skib 1627235783Skib dev_priv->r_t = dev_priv->mem_freq; 1628235783Skib 1629235783Skib switch (csipll & 0x3ff) { 1630235783Skib case 0x00c: 1631235783Skib dev_priv->fsb_freq = 3200; 1632235783Skib break; 1633235783Skib case 0x00e: 1634235783Skib dev_priv->fsb_freq = 3733; 1635235783Skib break; 1636235783Skib case 0x010: 1637235783Skib dev_priv->fsb_freq = 4266; 1638235783Skib break; 1639235783Skib case 0x012: 1640235783Skib dev_priv->fsb_freq = 4800; 1641235783Skib break; 1642235783Skib case 0x014: 1643235783Skib dev_priv->fsb_freq = 5333; 1644235783Skib break; 1645235783Skib case 0x016: 1646235783Skib dev_priv->fsb_freq = 5866; 1647235783Skib break; 1648235783Skib case 0x018: 1649235783Skib dev_priv->fsb_freq = 6400; 1650235783Skib break; 1651235783Skib default: 1652235783Skib DRM_DEBUG("unknown fsb frequency 0x%04x\n", 1653235783Skib csipll & 0x3ff); 1654235783Skib dev_priv->fsb_freq = 0; 1655235783Skib break; 1656235783Skib } 1657235783Skib 1658235783Skib if (dev_priv->fsb_freq == 3200) { 1659235783Skib dev_priv->c_m = 0; 1660235783Skib } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { 1661235783Skib dev_priv->c_m = 1; 1662235783Skib } else { 1663235783Skib dev_priv->c_m = 2; 1664235783Skib } 1665235783Skib} 1666235783Skib 1667235783Skibstatic const struct cparams { 1668235783Skib u16 i; 1669235783Skib u16 t; 1670235783Skib u16 m; 1671235783Skib u16 c; 1672235783Skib} cparams[] = { 1673235783Skib { 1, 1333, 301, 28664 }, 1674235783Skib { 1, 1066, 294, 24460 }, 1675235783Skib { 1, 800, 294, 25192 }, 1676235783Skib { 0, 1333, 276, 27605 }, 1677235783Skib { 0, 1066, 276, 27605 }, 1678235783Skib { 0, 800, 231, 23784 }, 1679235783Skib}; 1680235783Skib 1681235783Skibunsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 1682235783Skib{ 1683235783Skib u64 total_count, diff, ret; 1684235783Skib u32 count1, count2, count3, m = 0, c = 0; 1685235783Skib unsigned long now = jiffies_to_msecs(jiffies), diff1; 1686235783Skib int i; 1687235783Skib 1688235783Skib diff1 = now - dev_priv->last_time1; 1689235783Skib /* 1690235783Skib * sysctl(8) reads the value of sysctl twice in rapid 1691235783Skib * succession. There is high chance that it happens in the 1692235783Skib * same timer tick. Use the cached value to not divide by 1693235783Skib * zero and give the hw a chance to gather more samples. 1694235783Skib */ 1695235783Skib if (diff1 <= 10) 1696235783Skib return (dev_priv->chipset_power); 1697235783Skib 1698235783Skib count1 = I915_READ(DMIEC); 1699235783Skib count2 = I915_READ(DDREC); 1700235783Skib count3 = I915_READ(CSIEC); 1701235783Skib 1702235783Skib total_count = count1 + count2 + count3; 1703235783Skib 1704235783Skib /* FIXME: handle per-counter overflow */ 1705235783Skib if (total_count < dev_priv->last_count1) { 1706235783Skib diff = ~0UL - dev_priv->last_count1; 1707235783Skib diff += total_count; 1708235783Skib } else { 1709235783Skib diff = total_count - dev_priv->last_count1; 1710235783Skib } 1711235783Skib 1712235783Skib for (i = 0; i < DRM_ARRAY_SIZE(cparams); i++) { 1713235783Skib if (cparams[i].i == dev_priv->c_m && 1714235783Skib cparams[i].t == dev_priv->r_t) { 1715235783Skib m = cparams[i].m; 1716235783Skib c = cparams[i].c; 1717235783Skib break; 1718235783Skib } 1719235783Skib } 1720235783Skib 1721235783Skib diff = diff / diff1; 1722235783Skib ret = ((m * diff) + c); 1723235783Skib ret = ret / 10; 1724235783Skib 1725235783Skib dev_priv->last_count1 = total_count; 1726235783Skib dev_priv->last_time1 = now; 1727235783Skib 1728235783Skib dev_priv->chipset_power = ret; 1729235783Skib return (ret); 1730235783Skib} 1731235783Skib 1732235783Skibunsigned long i915_mch_val(struct drm_i915_private *dev_priv) 1733235783Skib{ 1734235783Skib unsigned long m, x, b; 1735235783Skib u32 tsfs; 1736235783Skib 1737235783Skib tsfs = I915_READ(TSFS); 1738235783Skib 1739235783Skib m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); 1740235783Skib x = I915_READ8(I915_TR1); 1741235783Skib 1742235783Skib b = tsfs & TSFS_INTR_MASK; 1743235783Skib 1744235783Skib return ((m * x) / 127) - b; 1745235783Skib} 1746235783Skib 1747235783Skibstatic u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 1748235783Skib{ 1749235783Skib static const struct v_table { 1750235783Skib u16 vd; /* in .1 mil */ 1751235783Skib u16 vm; /* in .1 mil */ 1752235783Skib } v_table[] = { 1753235783Skib { 0, 0, }, 1754235783Skib { 375, 0, }, 1755235783Skib { 500, 0, }, 1756235783Skib { 625, 0, }, 1757235783Skib { 750, 0, }, 1758235783Skib { 875, 0, }, 1759235783Skib { 1000, 0, }, 1760235783Skib { 1125, 0, }, 1761235783Skib { 4125, 3000, }, 1762235783Skib { 4125, 3000, }, 1763235783Skib { 4125, 3000, }, 1764235783Skib { 4125, 3000, }, 1765235783Skib { 4125, 3000, }, 1766235783Skib { 4125, 3000, }, 1767235783Skib { 4125, 3000, }, 1768235783Skib { 4125, 3000, }, 1769235783Skib { 4125, 3000, }, 1770235783Skib { 4125, 3000, }, 1771235783Skib { 4125, 3000, }, 1772235783Skib { 4125, 3000, }, 1773235783Skib { 4125, 3000, }, 1774235783Skib { 4125, 3000, }, 1775235783Skib { 4125, 3000, }, 1776235783Skib { 4125, 3000, }, 1777235783Skib { 4125, 3000, }, 1778235783Skib { 4125, 3000, }, 1779235783Skib { 4125, 3000, }, 1780235783Skib { 4125, 3000, }, 1781235783Skib { 4125, 3000, }, 1782235783Skib { 4125, 3000, }, 1783235783Skib { 4125, 3000, }, 1784235783Skib { 4125, 3000, }, 1785235783Skib { 4250, 3125, }, 1786235783Skib { 4375, 3250, }, 1787235783Skib { 4500, 3375, }, 1788235783Skib { 4625, 3500, }, 1789235783Skib { 4750, 3625, }, 1790235783Skib { 4875, 3750, }, 1791235783Skib { 5000, 3875, }, 1792235783Skib { 5125, 4000, }, 1793235783Skib { 5250, 4125, }, 1794235783Skib { 5375, 4250, }, 1795235783Skib { 5500, 4375, }, 1796235783Skib { 5625, 4500, }, 1797235783Skib { 5750, 4625, }, 1798235783Skib { 5875, 4750, }, 1799235783Skib { 6000, 4875, }, 1800235783Skib { 6125, 5000, }, 1801235783Skib { 6250, 5125, }, 1802235783Skib { 6375, 5250, }, 1803235783Skib { 6500, 5375, }, 1804235783Skib { 6625, 5500, }, 1805235783Skib { 6750, 5625, }, 1806235783Skib { 6875, 5750, }, 1807235783Skib { 7000, 5875, }, 1808235783Skib { 7125, 6000, }, 1809235783Skib { 7250, 6125, }, 1810235783Skib { 7375, 6250, }, 1811235783Skib { 7500, 6375, }, 1812235783Skib { 7625, 6500, }, 1813235783Skib { 7750, 6625, }, 1814235783Skib { 7875, 6750, }, 1815235783Skib { 8000, 6875, }, 1816235783Skib { 8125, 7000, }, 1817235783Skib { 8250, 7125, }, 1818235783Skib { 8375, 7250, }, 1819235783Skib { 8500, 7375, }, 1820235783Skib { 8625, 7500, }, 1821235783Skib { 8750, 7625, }, 1822235783Skib { 8875, 7750, }, 1823235783Skib { 9000, 7875, }, 1824235783Skib { 9125, 8000, }, 1825235783Skib { 9250, 8125, }, 1826235783Skib { 9375, 8250, }, 1827235783Skib { 9500, 8375, }, 1828235783Skib { 9625, 8500, }, 1829235783Skib { 9750, 8625, }, 1830235783Skib { 9875, 8750, }, 1831235783Skib { 10000, 8875, }, 1832235783Skib { 10125, 9000, }, 1833235783Skib { 10250, 9125, }, 1834235783Skib { 10375, 9250, }, 1835235783Skib { 10500, 9375, }, 1836235783Skib { 10625, 9500, }, 1837235783Skib { 10750, 9625, }, 1838235783Skib { 10875, 9750, }, 1839235783Skib { 11000, 9875, }, 1840235783Skib { 11125, 10000, }, 1841235783Skib { 11250, 10125, }, 1842235783Skib { 11375, 10250, }, 1843235783Skib { 11500, 10375, }, 1844235783Skib { 11625, 10500, }, 1845235783Skib { 11750, 10625, }, 1846235783Skib { 11875, 10750, }, 1847235783Skib { 12000, 10875, }, 1848235783Skib { 12125, 11000, }, 1849235783Skib { 12250, 11125, }, 1850235783Skib { 12375, 11250, }, 1851235783Skib { 12500, 11375, }, 1852235783Skib { 12625, 11500, }, 1853235783Skib { 12750, 11625, }, 1854235783Skib { 12875, 11750, }, 1855235783Skib { 13000, 11875, }, 1856235783Skib { 13125, 12000, }, 1857235783Skib { 13250, 12125, }, 1858235783Skib { 13375, 12250, }, 1859235783Skib { 13500, 12375, }, 1860235783Skib { 13625, 12500, }, 1861235783Skib { 13750, 12625, }, 1862235783Skib { 13875, 12750, }, 1863235783Skib { 14000, 12875, }, 1864235783Skib { 14125, 13000, }, 1865235783Skib { 14250, 13125, }, 1866235783Skib { 14375, 13250, }, 1867235783Skib { 14500, 13375, }, 1868235783Skib { 14625, 13500, }, 1869235783Skib { 14750, 13625, }, 1870235783Skib { 14875, 13750, }, 1871235783Skib { 15000, 13875, }, 1872235783Skib { 15125, 14000, }, 1873235783Skib { 15250, 14125, }, 1874235783Skib { 15375, 14250, }, 1875235783Skib { 15500, 14375, }, 1876235783Skib { 15625, 14500, }, 1877235783Skib { 15750, 14625, }, 1878235783Skib { 15875, 14750, }, 1879235783Skib { 16000, 14875, }, 1880235783Skib { 16125, 15000, }, 1881235783Skib }; 1882235783Skib if (dev_priv->info->is_mobile) 1883235783Skib return v_table[pxvid].vm; 1884235783Skib else 1885235783Skib return v_table[pxvid].vd; 1886235783Skib} 1887235783Skib 1888235783Skibvoid i915_update_gfx_val(struct drm_i915_private *dev_priv) 1889235783Skib{ 1890235783Skib struct timespec now, diff1; 1891235783Skib u64 diff; 1892235783Skib unsigned long diffms; 1893235783Skib u32 count; 1894235783Skib 1895235783Skib if (dev_priv->info->gen != 5) 1896235783Skib return; 1897235783Skib 1898235783Skib nanotime(&now); 1899235783Skib diff1 = now; 1900235783Skib timespecsub(&diff1, &dev_priv->last_time2); 1901235783Skib 1902235783Skib /* Don't divide by 0 */ 1903235783Skib diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; 1904235783Skib if (!diffms) 1905235783Skib return; 1906235783Skib 1907235783Skib count = I915_READ(GFXEC); 1908235783Skib 1909235783Skib if (count < dev_priv->last_count2) { 1910235783Skib diff = ~0UL - dev_priv->last_count2; 1911235783Skib diff += count; 1912235783Skib } else { 1913235783Skib diff = count - dev_priv->last_count2; 1914235783Skib } 1915235783Skib 1916235783Skib dev_priv->last_count2 = count; 1917235783Skib dev_priv->last_time2 = now; 1918235783Skib 1919235783Skib /* More magic constants... */ 1920235783Skib diff = diff * 1181; 1921235783Skib diff = diff / (diffms * 10); 1922235783Skib dev_priv->gfx_power = diff; 1923235783Skib} 1924235783Skib 1925235783Skibunsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 1926235783Skib{ 1927235783Skib unsigned long t, corr, state1, corr2, state2; 1928235783Skib u32 pxvid, ext_v; 1929235783Skib 1930235783Skib pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4)); 1931235783Skib pxvid = (pxvid >> 24) & 0x7f; 1932235783Skib ext_v = pvid_to_extvid(dev_priv, pxvid); 1933235783Skib 1934235783Skib state1 = ext_v; 1935235783Skib 1936235783Skib t = i915_mch_val(dev_priv); 1937235783Skib 1938235783Skib /* Revel in the empirically derived constants */ 1939235783Skib 1940235783Skib /* Correction factor in 1/100000 units */ 1941235783Skib if (t > 80) 1942235783Skib corr = ((t * 2349) + 135940); 1943235783Skib else if (t >= 50) 1944235783Skib corr = ((t * 964) + 29317); 1945235783Skib else /* < 50 */ 1946235783Skib corr = ((t * 301) + 1004); 1947235783Skib 1948235783Skib corr = corr * ((150142 * state1) / 10000 - 78642); 1949235783Skib corr /= 100000; 1950235783Skib corr2 = (corr * dev_priv->corr); 1951235783Skib 1952235783Skib state2 = (corr2 * state1) / 10000; 1953235783Skib state2 /= 100; /* convert to mW */ 1954235783Skib 1955235783Skib i915_update_gfx_val(dev_priv); 1956235783Skib 1957235783Skib return dev_priv->gfx_power + state2; 1958235783Skib} 1959235783Skib 1960235783Skib/** 1961235783Skib * i915_read_mch_val - return value for IPS use 1962235783Skib * 1963235783Skib * Calculate and return a value for the IPS driver to use when deciding whether 1964235783Skib * we have thermal and power headroom to increase CPU or GPU power budget. 1965235783Skib */ 1966235783Skibunsigned long i915_read_mch_val(void) 1967235783Skib{ 1968235783Skib struct drm_i915_private *dev_priv; 1969235783Skib unsigned long chipset_val, graphics_val, ret = 0; 1970235783Skib 1971235783Skib mtx_lock(&mchdev_lock); 1972235783Skib if (!i915_mch_dev) 1973235783Skib goto out_unlock; 1974235783Skib dev_priv = i915_mch_dev; 1975235783Skib 1976235783Skib chipset_val = i915_chipset_val(dev_priv); 1977235783Skib graphics_val = i915_gfx_val(dev_priv); 1978235783Skib 1979235783Skib ret = chipset_val + graphics_val; 1980235783Skib 1981235783Skibout_unlock: 1982235783Skib mtx_unlock(&mchdev_lock); 1983235783Skib 1984235783Skib return ret; 1985235783Skib} 1986235783Skib 1987235783Skib/** 1988235783Skib * i915_gpu_raise - raise GPU frequency limit 1989235783Skib * 1990235783Skib * Raise the limit; IPS indicates we have thermal headroom. 1991235783Skib */ 1992235783Skibbool i915_gpu_raise(void) 1993235783Skib{ 1994235783Skib struct drm_i915_private *dev_priv; 1995235783Skib bool ret = true; 1996235783Skib 1997235783Skib mtx_lock(&mchdev_lock); 1998235783Skib if (!i915_mch_dev) { 1999235783Skib ret = false; 2000235783Skib goto out_unlock; 2001235783Skib } 2002235783Skib dev_priv = i915_mch_dev; 2003235783Skib 2004235783Skib if (dev_priv->max_delay > dev_priv->fmax) 2005235783Skib dev_priv->max_delay--; 2006235783Skib 2007235783Skibout_unlock: 2008235783Skib mtx_unlock(&mchdev_lock); 2009235783Skib 2010235783Skib return ret; 2011235783Skib} 2012235783Skib 2013235783Skib/** 2014235783Skib * i915_gpu_lower - lower GPU frequency limit 2015235783Skib * 2016235783Skib * IPS indicates we're close to a thermal limit, so throttle back the GPU 2017235783Skib * frequency maximum. 2018235783Skib */ 2019235783Skibbool i915_gpu_lower(void) 2020235783Skib{ 2021235783Skib struct drm_i915_private *dev_priv; 2022235783Skib bool ret = true; 2023235783Skib 2024235783Skib mtx_lock(&mchdev_lock); 2025235783Skib if (!i915_mch_dev) { 2026235783Skib ret = false; 2027235783Skib goto out_unlock; 2028235783Skib } 2029235783Skib dev_priv = i915_mch_dev; 2030235783Skib 2031235783Skib if (dev_priv->max_delay < dev_priv->min_delay) 2032235783Skib dev_priv->max_delay++; 2033235783Skib 2034235783Skibout_unlock: 2035235783Skib mtx_unlock(&mchdev_lock); 2036235783Skib 2037235783Skib return ret; 2038235783Skib} 2039235783Skib 2040235783Skib/** 2041235783Skib * i915_gpu_busy - indicate GPU business to IPS 2042235783Skib * 2043235783Skib * Tell the IPS driver whether or not the GPU is busy. 2044235783Skib */ 2045235783Skibbool i915_gpu_busy(void) 2046235783Skib{ 2047235783Skib struct drm_i915_private *dev_priv; 2048235783Skib bool ret = false; 2049235783Skib 2050235783Skib mtx_lock(&mchdev_lock); 2051235783Skib if (!i915_mch_dev) 2052235783Skib goto out_unlock; 2053235783Skib dev_priv = i915_mch_dev; 2054235783Skib 2055235783Skib ret = dev_priv->busy; 2056235783Skib 2057235783Skibout_unlock: 2058235783Skib mtx_unlock(&mchdev_lock); 2059235783Skib 2060235783Skib return ret; 2061235783Skib} 2062235783Skib 2063235783Skib/** 2064235783Skib * i915_gpu_turbo_disable - disable graphics turbo 2065235783Skib * 2066235783Skib * Disable graphics turbo by resetting the max frequency and setting the 2067235783Skib * current frequency to the default. 2068235783Skib */ 2069235783Skibbool i915_gpu_turbo_disable(void) 2070235783Skib{ 2071235783Skib struct drm_i915_private *dev_priv; 2072235783Skib bool ret = true; 2073235783Skib 2074235783Skib mtx_lock(&mchdev_lock); 2075235783Skib if (!i915_mch_dev) { 2076235783Skib ret = false; 2077235783Skib goto out_unlock; 2078235783Skib } 2079235783Skib dev_priv = i915_mch_dev; 2080235783Skib 2081235783Skib dev_priv->max_delay = dev_priv->fstart; 2082235783Skib 2083235783Skib if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart)) 2084235783Skib ret = false; 2085235783Skib 2086235783Skibout_unlock: 2087235783Skib mtx_unlock(&mchdev_lock); 2088235783Skib 2089235783Skib return ret; 2090235783Skib} 2091