drm_mode.h revision 235783
1235783Skib/* 2235783Skib * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> 3235783Skib * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com> 4235783Skib * Copyright (c) 2008 Red Hat Inc. 5235783Skib * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA 6235783Skib * Copyright (c) 2007-2008 Intel Corporation 7235783Skib * 8235783Skib * Permission is hereby granted, free of charge, to any person obtaining a 9235783Skib * copy of this software and associated documentation files (the "Software"), 10235783Skib * to deal in the Software without restriction, including without limitation 11235783Skib * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12235783Skib * and/or sell copies of the Software, and to permit persons to whom the 13235783Skib * Software is furnished to do so, subject to the following conditions: 14235783Skib * 15235783Skib * The above copyright notice and this permission notice shall be included in 16235783Skib * all copies or substantial portions of the Software. 17235783Skib * 18235783Skib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19235783Skib * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20235783Skib * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 21235783Skib * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22235783Skib * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 23235783Skib * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 24235783Skib * IN THE SOFTWARE. 25235783Skib * 26235783Skib * $FreeBSD: head/sys/dev/drm2/drm_mode.h 235783 2012-05-22 11:07:44Z kib $ 27235783Skib */ 28235783Skib 29235783Skib#ifndef _DRM_MODE_H 30235783Skib#define _DRM_MODE_H 31235783Skib 32235783Skib#define DRM_DISPLAY_INFO_LEN 32 33235783Skib#define DRM_CONNECTOR_NAME_LEN 32 34235783Skib#define DRM_DISPLAY_MODE_LEN 32 35235783Skib#define DRM_PROP_NAME_LEN 32 36235783Skib 37235783Skib#define DRM_MODE_TYPE_BUILTIN (1<<0) 38235783Skib#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) 39235783Skib#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) 40235783Skib#define DRM_MODE_TYPE_PREFERRED (1<<3) 41235783Skib#define DRM_MODE_TYPE_DEFAULT (1<<4) 42235783Skib#define DRM_MODE_TYPE_USERDEF (1<<5) 43235783Skib#define DRM_MODE_TYPE_DRIVER (1<<6) 44235783Skib 45235783Skib/* Video mode flags */ 46235783Skib/* bit compatible with the xorg definitions. */ 47235783Skib#define DRM_MODE_FLAG_PHSYNC (1<<0) 48235783Skib#define DRM_MODE_FLAG_NHSYNC (1<<1) 49235783Skib#define DRM_MODE_FLAG_PVSYNC (1<<2) 50235783Skib#define DRM_MODE_FLAG_NVSYNC (1<<3) 51235783Skib#define DRM_MODE_FLAG_INTERLACE (1<<4) 52235783Skib#define DRM_MODE_FLAG_DBLSCAN (1<<5) 53235783Skib#define DRM_MODE_FLAG_CSYNC (1<<6) 54235783Skib#define DRM_MODE_FLAG_PCSYNC (1<<7) 55235783Skib#define DRM_MODE_FLAG_NCSYNC (1<<8) 56235783Skib#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ 57235783Skib#define DRM_MODE_FLAG_BCAST (1<<10) 58235783Skib#define DRM_MODE_FLAG_PIXMUX (1<<11) 59235783Skib#define DRM_MODE_FLAG_DBLCLK (1<<12) 60235783Skib#define DRM_MODE_FLAG_CLKDIV2 (1<<13) 61235783Skib 62235783Skib/* DPMS flags */ 63235783Skib/* bit compatible with the xorg definitions. */ 64235783Skib#define DRM_MODE_DPMS_ON 0 65235783Skib#define DRM_MODE_DPMS_STANDBY 1 66235783Skib#define DRM_MODE_DPMS_SUSPEND 2 67235783Skib#define DRM_MODE_DPMS_OFF 3 68235783Skib 69235783Skib/* Scaling mode options */ 70235783Skib#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or 71235783Skib software can still scale) */ 72235783Skib#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */ 73235783Skib#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ 74235783Skib#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ 75235783Skib 76235783Skib/* Dithering mode options */ 77235783Skib#define DRM_MODE_DITHERING_OFF 0 78235783Skib#define DRM_MODE_DITHERING_ON 1 79235783Skib#define DRM_MODE_DITHERING_AUTO 2 80235783Skib 81235783Skib/* Dirty info options */ 82235783Skib#define DRM_MODE_DIRTY_OFF 0 83235783Skib#define DRM_MODE_DIRTY_ON 1 84235783Skib#define DRM_MODE_DIRTY_ANNOTATE 2 85235783Skib 86235783Skibstruct drm_mode_modeinfo { 87235783Skib uint32_t clock; 88235783Skib uint16_t hdisplay, hsync_start, hsync_end, htotal, hskew; 89235783Skib uint16_t vdisplay, vsync_start, vsync_end, vtotal, vscan; 90235783Skib 91235783Skib uint32_t vrefresh; 92235783Skib 93235783Skib uint32_t flags; 94235783Skib uint32_t type; 95235783Skib char name[DRM_DISPLAY_MODE_LEN]; 96235783Skib}; 97235783Skib 98235783Skibstruct drm_mode_card_res { 99235783Skib uint64_t fb_id_ptr; 100235783Skib uint64_t crtc_id_ptr; 101235783Skib uint64_t connector_id_ptr; 102235783Skib uint64_t encoder_id_ptr; 103235783Skib uint32_t count_fbs; 104235783Skib uint32_t count_crtcs; 105235783Skib uint32_t count_connectors; 106235783Skib uint32_t count_encoders; 107235783Skib uint32_t min_width, max_width; 108235783Skib uint32_t min_height, max_height; 109235783Skib}; 110235783Skib 111235783Skibstruct drm_mode_crtc { 112235783Skib uint64_t set_connectors_ptr; 113235783Skib uint32_t count_connectors; 114235783Skib 115235783Skib uint32_t crtc_id; /**< Id */ 116235783Skib uint32_t fb_id; /**< Id of framebuffer */ 117235783Skib 118235783Skib uint32_t x, y; /**< Position on the frameuffer */ 119235783Skib 120235783Skib uint32_t gamma_size; 121235783Skib uint32_t mode_valid; 122235783Skib struct drm_mode_modeinfo mode; 123235783Skib}; 124235783Skib 125235783Skib#define DRM_MODE_PRESENT_TOP_FIELD (1<<0) 126235783Skib#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1) 127235783Skib 128235783Skib/* Planes blend with or override other bits on the CRTC */ 129235783Skibstruct drm_mode_set_plane { 130235783Skib uint32_t plane_id; 131235783Skib uint32_t crtc_id; 132235783Skib uint32_t fb_id; /* fb object contains surface format type */ 133235783Skib uint32_t flags; /* see above flags */ 134235783Skib 135235783Skib /* Signed dest location allows it to be partially off screen */ 136235783Skib int32_t crtc_x, crtc_y; 137235783Skib uint32_t crtc_w, crtc_h; 138235783Skib 139235783Skib /* Source values are 16.16 fixed point */ 140235783Skib uint32_t src_x, src_y; 141235783Skib uint32_t src_h, src_w; 142235783Skib}; 143235783Skib 144235783Skibstruct drm_mode_get_plane { 145235783Skib uint32_t plane_id; 146235783Skib 147235783Skib uint32_t crtc_id; 148235783Skib uint32_t fb_id; 149235783Skib 150235783Skib uint32_t possible_crtcs; 151235783Skib uint32_t gamma_size; 152235783Skib 153235783Skib uint32_t count_format_types; 154235783Skib uint64_t format_type_ptr; 155235783Skib}; 156235783Skib 157235783Skibstruct drm_mode_get_plane_res { 158235783Skib uint64_t plane_id_ptr; 159235783Skib uint32_t count_planes; 160235783Skib}; 161235783Skib 162235783Skib#define DRM_MODE_ENCODER_NONE 0 163235783Skib#define DRM_MODE_ENCODER_DAC 1 164235783Skib#define DRM_MODE_ENCODER_TMDS 2 165235783Skib#define DRM_MODE_ENCODER_LVDS 3 166235783Skib#define DRM_MODE_ENCODER_TVDAC 4 167235783Skib 168235783Skibstruct drm_mode_get_encoder { 169235783Skib uint32_t encoder_id; 170235783Skib uint32_t encoder_type; 171235783Skib 172235783Skib uint32_t crtc_id; /**< Id of crtc */ 173235783Skib 174235783Skib uint32_t possible_crtcs; 175235783Skib uint32_t possible_clones; 176235783Skib}; 177235783Skib 178235783Skib/* This is for connectors with multiple signal types. */ 179235783Skib/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ 180235783Skib#define DRM_MODE_SUBCONNECTOR_Automatic 0 181235783Skib#define DRM_MODE_SUBCONNECTOR_Unknown 0 182235783Skib#define DRM_MODE_SUBCONNECTOR_DVID 3 183235783Skib#define DRM_MODE_SUBCONNECTOR_DVIA 4 184235783Skib#define DRM_MODE_SUBCONNECTOR_Composite 5 185235783Skib#define DRM_MODE_SUBCONNECTOR_SVIDEO 6 186235783Skib#define DRM_MODE_SUBCONNECTOR_Component 8 187235783Skib#define DRM_MODE_SUBCONNECTOR_SCART 9 188235783Skib 189235783Skib#define DRM_MODE_CONNECTOR_Unknown 0 190235783Skib#define DRM_MODE_CONNECTOR_VGA 1 191235783Skib#define DRM_MODE_CONNECTOR_DVII 2 192235783Skib#define DRM_MODE_CONNECTOR_DVID 3 193235783Skib#define DRM_MODE_CONNECTOR_DVIA 4 194235783Skib#define DRM_MODE_CONNECTOR_Composite 5 195235783Skib#define DRM_MODE_CONNECTOR_SVIDEO 6 196235783Skib#define DRM_MODE_CONNECTOR_LVDS 7 197235783Skib#define DRM_MODE_CONNECTOR_Component 8 198235783Skib#define DRM_MODE_CONNECTOR_9PinDIN 9 199235783Skib#define DRM_MODE_CONNECTOR_DisplayPort 10 200235783Skib#define DRM_MODE_CONNECTOR_HDMIA 11 201235783Skib#define DRM_MODE_CONNECTOR_HDMIB 12 202235783Skib#define DRM_MODE_CONNECTOR_TV 13 203235783Skib#define DRM_MODE_CONNECTOR_eDP 14 204235783Skib 205235783Skibstruct drm_mode_get_connector { 206235783Skib 207235783Skib uint64_t encoders_ptr; 208235783Skib uint64_t modes_ptr; 209235783Skib uint64_t props_ptr; 210235783Skib uint64_t prop_values_ptr; 211235783Skib 212235783Skib uint32_t count_modes; 213235783Skib uint32_t count_props; 214235783Skib uint32_t count_encoders; 215235783Skib 216235783Skib uint32_t encoder_id; /**< Current Encoder */ 217235783Skib uint32_t connector_id; /**< Id */ 218235783Skib uint32_t connector_type; 219235783Skib uint32_t connector_type_id; 220235783Skib 221235783Skib uint32_t connection; 222235783Skib uint32_t mm_width, mm_height; /**< HxW in millimeters */ 223235783Skib uint32_t subpixel; 224235783Skib}; 225235783Skib 226235783Skib#define DRM_MODE_PROP_PENDING (1<<0) 227235783Skib#define DRM_MODE_PROP_RANGE (1<<1) 228235783Skib#define DRM_MODE_PROP_IMMUTABLE (1<<2) 229235783Skib#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ 230235783Skib#define DRM_MODE_PROP_BLOB (1<<4) 231235783Skib 232235783Skibstruct drm_mode_property_enum { 233235783Skib uint64_t value; 234235783Skib char name[DRM_PROP_NAME_LEN]; 235235783Skib}; 236235783Skib 237235783Skibstruct drm_mode_get_property { 238235783Skib uint64_t values_ptr; /* values and blob lengths */ 239235783Skib uint64_t enum_blob_ptr; /* enum and blob id ptrs */ 240235783Skib 241235783Skib uint32_t prop_id; 242235783Skib uint32_t flags; 243235783Skib char name[DRM_PROP_NAME_LEN]; 244235783Skib 245235783Skib uint32_t count_values; 246235783Skib uint32_t count_enum_blobs; 247235783Skib}; 248235783Skib 249235783Skibstruct drm_mode_connector_set_property { 250235783Skib uint64_t value; 251235783Skib uint32_t prop_id; 252235783Skib uint32_t connector_id; 253235783Skib}; 254235783Skib 255235783Skibstruct drm_mode_get_blob { 256235783Skib uint32_t blob_id; 257235783Skib uint32_t length; 258235783Skib uint64_t data; 259235783Skib}; 260235783Skib 261235783Skibstruct drm_mode_fb_cmd { 262235783Skib uint32_t fb_id; 263235783Skib uint32_t width, height; 264235783Skib uint32_t pitch; 265235783Skib uint32_t bpp; 266235783Skib uint32_t depth; 267235783Skib /* driver specific handle */ 268235783Skib uint32_t handle; 269235783Skib}; 270235783Skib 271235783Skib#define DRM_MODE_FB_INTERLACED (1<<0 /* for interlaced framebuffers */ 272235783Skib 273235783Skibstruct drm_mode_fb_cmd2 { 274235783Skib uint32_t fb_id; 275235783Skib uint32_t width, height; 276235783Skib uint32_t pixel_format; /* fourcc code from drm_fourcc.h */ 277235783Skib uint32_t flags; /* see above flags */ 278235783Skib 279235783Skib /* 280235783Skib * In case of planar formats, this ioctl allows up to 4 281235783Skib * buffer objects with offets and pitches per plane. 282235783Skib * The pitch and offset order is dictated by the fourcc, 283235783Skib * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as: 284235783Skib * 285235783Skib * YUV 4:2:0 image with a plane of 8 bit Y samples 286235783Skib * followed by an interleaved U/V plane containing 287235783Skib * 8 bit 2x2 subsampled colour difference samples. 288235783Skib * 289235783Skib * So it would consist of Y as offset[0] and UV as 290235783Skib * offeset[1]. Note that offset[0] will generally 291235783Skib * be 0. 292235783Skib */ 293235783Skib uint32_t handles[4]; 294235783Skib uint32_t pitches[4]; /* pitch for each plane */ 295235783Skib uint32_t offsets[4]; /* offset of each plane */ 296235783Skib}; 297235783Skib 298235783Skib#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 299235783Skib#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02 300235783Skib#define DRM_MODE_FB_DIRTY_FLAGS 0x03 301235783Skib 302235783Skib#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256 303235783Skib 304235783Skib/* 305235783Skib * Mark a region of a framebuffer as dirty. 306235783Skib * 307235783Skib * Some hardware does not automatically update display contents 308235783Skib * as a hardware or software draw to a framebuffer. This ioctl 309235783Skib * allows userspace to tell the kernel and the hardware what 310235783Skib * regions of the framebuffer have changed. 311235783Skib * 312235783Skib * The kernel or hardware is free to update more then just the 313235783Skib * region specified by the clip rects. The kernel or hardware 314235783Skib * may also delay and/or coalesce several calls to dirty into a 315235783Skib * single update. 316235783Skib * 317235783Skib * Userspace may annotate the updates, the annotates are a 318235783Skib * promise made by the caller that the change is either a copy 319235783Skib * of pixels or a fill of a single color in the region specified. 320235783Skib * 321235783Skib * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then 322235783Skib * the number of updated regions are half of num_clips given, 323235783Skib * where the clip rects are paired in src and dst. The width and 324235783Skib * height of each one of the pairs must match. 325235783Skib * 326235783Skib * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller 327235783Skib * promises that the region specified of the clip rects is filled 328235783Skib * completely with a single color as given in the color argument. 329235783Skib */ 330235783Skib 331235783Skibstruct drm_mode_fb_dirty_cmd { 332235783Skib uint32_t fb_id; 333235783Skib uint32_t flags; 334235783Skib uint32_t color; 335235783Skib uint32_t num_clips; 336235783Skib uint64_t clips_ptr; 337235783Skib}; 338235783Skib 339235783Skibstruct drm_mode_mode_cmd { 340235783Skib uint32_t connector_id; 341235783Skib struct drm_mode_modeinfo mode; 342235783Skib}; 343235783Skib 344235783Skib#define DRM_MODE_CURSOR_BO (1<<0) 345235783Skib#define DRM_MODE_CURSOR_MOVE (1<<1) 346235783Skib 347235783Skib/* 348235783Skib * depending on the value in flags diffrent members are used. 349235783Skib * 350235783Skib * CURSOR_BO uses 351235783Skib * crtc 352235783Skib * width 353235783Skib * height 354235783Skib * handle - if 0 turns the cursor of 355235783Skib * 356235783Skib * CURSOR_MOVE uses 357235783Skib * crtc 358235783Skib * x 359235783Skib * y 360235783Skib */ 361235783Skibstruct drm_mode_cursor { 362235783Skib uint32_t flags; 363235783Skib uint32_t crtc_id; 364235783Skib int32_t x; 365235783Skib int32_t y; 366235783Skib uint32_t width; 367235783Skib uint32_t height; 368235783Skib /* driver specific handle */ 369235783Skib uint32_t handle; 370235783Skib}; 371235783Skib 372235783Skibstruct drm_mode_crtc_lut { 373235783Skib uint32_t crtc_id; 374235783Skib uint32_t gamma_size; 375235783Skib 376235783Skib /* pointers to arrays */ 377235783Skib uint64_t red; 378235783Skib uint64_t green; 379235783Skib uint64_t blue; 380235783Skib}; 381235783Skib 382235783Skib#define DRM_MODE_PAGE_FLIP_EVENT 0x01 383235783Skib#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT 384235783Skib 385235783Skib/* 386235783Skib * Request a page flip on the specified crtc. 387235783Skib * 388235783Skib * This ioctl will ask KMS to schedule a page flip for the specified 389235783Skib * crtc. Once any pending rendering targeting the specified fb (as of 390235783Skib * ioctl time) has completed, the crtc will be reprogrammed to display 391235783Skib * that fb after the next vertical refresh. The ioctl returns 392235783Skib * immediately, but subsequent rendering to the current fb will block 393235783Skib * in the execbuffer ioctl until the page flip happens. If a page 394235783Skib * flip is already pending as the ioctl is called, EBUSY will be 395235783Skib * returned. 396235783Skib * 397235783Skib * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will 398235783Skib * request that drm sends back a vblank event (see drm.h: struct 399235783Skib * drm_event_vblank) when the page flip is done. The user_data field 400235783Skib * passed in with this ioctl will be returned as the user_data field 401235783Skib * in the vblank event struct. 402235783Skib * 403235783Skib * The reserved field must be zero until we figure out something 404235783Skib * clever to use it for. 405235783Skib */ 406235783Skib 407235783Skibstruct drm_mode_crtc_page_flip { 408235783Skib uint32_t crtc_id; 409235783Skib uint32_t fb_id; 410235783Skib uint32_t flags; 411235783Skib uint32_t reserved; 412235783Skib uint64_t user_data; 413235783Skib}; 414235783Skib 415235783Skib/* create a dumb scanout buffer */ 416235783Skibstruct drm_mode_create_dumb { 417235783Skib uint32_t height; 418235783Skib uint32_t width; 419235783Skib uint32_t bpp; 420235783Skib uint32_t flags; 421235783Skib /* handle, pitch, size will be returned */ 422235783Skib uint32_t handle; 423235783Skib uint32_t pitch; 424235783Skib uint64_t size; 425235783Skib}; 426235783Skib 427235783Skib/* set up for mmap of a dumb scanout buffer */ 428235783Skibstruct drm_mode_map_dumb { 429235783Skib /** Handle for the object being mapped. */ 430235783Skib uint32_t handle; 431235783Skib uint32_t pad; 432235783Skib /** 433235783Skib * Fake offset to use for subsequent mmap call 434235783Skib * 435235783Skib * This is a fixed-size type for 32/64 compatibility. 436235783Skib */ 437235783Skib uint64_t offset; 438235783Skib}; 439235783Skib 440235783Skibstruct drm_mode_destroy_dumb { 441235783Skib uint32_t handle; 442235783Skib}; 443235783Skib 444235783Skib#endif 445