1235783Skib/* 2235783Skib * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> 3235783Skib * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com> 4235783Skib * Copyright (c) 2008 Red Hat Inc. 5235783Skib * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA 6235783Skib * Copyright (c) 2007-2008 Intel Corporation 7235783Skib * 8235783Skib * Permission is hereby granted, free of charge, to any person obtaining a 9235783Skib * copy of this software and associated documentation files (the "Software"), 10235783Skib * to deal in the Software without restriction, including without limitation 11235783Skib * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12235783Skib * and/or sell copies of the Software, and to permit persons to whom the 13235783Skib * Software is furnished to do so, subject to the following conditions: 14235783Skib * 15235783Skib * The above copyright notice and this permission notice shall be included in 16235783Skib * all copies or substantial portions of the Software. 17235783Skib * 18235783Skib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19235783Skib * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20235783Skib * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 21235783Skib * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22235783Skib * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 23235783Skib * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 24235783Skib * IN THE SOFTWARE. 25235783Skib * 26235783Skib * $FreeBSD$ 27235783Skib */ 28235783Skib 29235783Skib#ifndef _DRM_MODE_H 30235783Skib#define _DRM_MODE_H 31235783Skib 32280183Sdumbbell#include <dev/drm2/drm_os_freebsd.h> 33280183Sdumbbell 34235783Skib#define DRM_DISPLAY_INFO_LEN 32 35235783Skib#define DRM_CONNECTOR_NAME_LEN 32 36235783Skib#define DRM_DISPLAY_MODE_LEN 32 37235783Skib#define DRM_PROP_NAME_LEN 32 38235783Skib 39235783Skib#define DRM_MODE_TYPE_BUILTIN (1<<0) 40235783Skib#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) 41235783Skib#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) 42235783Skib#define DRM_MODE_TYPE_PREFERRED (1<<3) 43235783Skib#define DRM_MODE_TYPE_DEFAULT (1<<4) 44235783Skib#define DRM_MODE_TYPE_USERDEF (1<<5) 45235783Skib#define DRM_MODE_TYPE_DRIVER (1<<6) 46235783Skib 47235783Skib/* Video mode flags */ 48235783Skib/* bit compatible with the xorg definitions. */ 49235783Skib#define DRM_MODE_FLAG_PHSYNC (1<<0) 50235783Skib#define DRM_MODE_FLAG_NHSYNC (1<<1) 51235783Skib#define DRM_MODE_FLAG_PVSYNC (1<<2) 52235783Skib#define DRM_MODE_FLAG_NVSYNC (1<<3) 53235783Skib#define DRM_MODE_FLAG_INTERLACE (1<<4) 54235783Skib#define DRM_MODE_FLAG_DBLSCAN (1<<5) 55235783Skib#define DRM_MODE_FLAG_CSYNC (1<<6) 56235783Skib#define DRM_MODE_FLAG_PCSYNC (1<<7) 57235783Skib#define DRM_MODE_FLAG_NCSYNC (1<<8) 58235783Skib#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ 59235783Skib#define DRM_MODE_FLAG_BCAST (1<<10) 60235783Skib#define DRM_MODE_FLAG_PIXMUX (1<<11) 61235783Skib#define DRM_MODE_FLAG_DBLCLK (1<<12) 62235783Skib#define DRM_MODE_FLAG_CLKDIV2 (1<<13) 63235783Skib 64235783Skib/* DPMS flags */ 65235783Skib/* bit compatible with the xorg definitions. */ 66235783Skib#define DRM_MODE_DPMS_ON 0 67235783Skib#define DRM_MODE_DPMS_STANDBY 1 68235783Skib#define DRM_MODE_DPMS_SUSPEND 2 69235783Skib#define DRM_MODE_DPMS_OFF 3 70235783Skib 71235783Skib/* Scaling mode options */ 72235783Skib#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or 73235783Skib software can still scale) */ 74235783Skib#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */ 75235783Skib#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ 76235783Skib#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ 77235783Skib 78235783Skib/* Dithering mode options */ 79235783Skib#define DRM_MODE_DITHERING_OFF 0 80235783Skib#define DRM_MODE_DITHERING_ON 1 81235783Skib#define DRM_MODE_DITHERING_AUTO 2 82235783Skib 83235783Skib/* Dirty info options */ 84235783Skib#define DRM_MODE_DIRTY_OFF 0 85235783Skib#define DRM_MODE_DIRTY_ON 1 86235783Skib#define DRM_MODE_DIRTY_ANNOTATE 2 87235783Skib 88235783Skibstruct drm_mode_modeinfo { 89280183Sdumbbell __u32 clock; 90280183Sdumbbell __u16 hdisplay, hsync_start, hsync_end, htotal, hskew; 91280183Sdumbbell __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan; 92235783Skib 93280183Sdumbbell __u32 vrefresh; 94235783Skib 95280183Sdumbbell __u32 flags; 96280183Sdumbbell __u32 type; 97235783Skib char name[DRM_DISPLAY_MODE_LEN]; 98235783Skib}; 99235783Skib 100235783Skibstruct drm_mode_card_res { 101280183Sdumbbell __u64 fb_id_ptr; 102280183Sdumbbell __u64 crtc_id_ptr; 103280183Sdumbbell __u64 connector_id_ptr; 104280183Sdumbbell __u64 encoder_id_ptr; 105280183Sdumbbell __u32 count_fbs; 106280183Sdumbbell __u32 count_crtcs; 107280183Sdumbbell __u32 count_connectors; 108280183Sdumbbell __u32 count_encoders; 109280183Sdumbbell __u32 min_width, max_width; 110280183Sdumbbell __u32 min_height, max_height; 111235783Skib}; 112235783Skib 113235783Skibstruct drm_mode_crtc { 114280183Sdumbbell __u64 set_connectors_ptr; 115280183Sdumbbell __u32 count_connectors; 116235783Skib 117280183Sdumbbell __u32 crtc_id; /**< Id */ 118280183Sdumbbell __u32 fb_id; /**< Id of framebuffer */ 119235783Skib 120280183Sdumbbell __u32 x, y; /**< Position on the frameuffer */ 121235783Skib 122280183Sdumbbell __u32 gamma_size; 123280183Sdumbbell __u32 mode_valid; 124235783Skib struct drm_mode_modeinfo mode; 125235783Skib}; 126235783Skib 127235783Skib#define DRM_MODE_PRESENT_TOP_FIELD (1<<0) 128235783Skib#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1) 129235783Skib 130235783Skib/* Planes blend with or override other bits on the CRTC */ 131235783Skibstruct drm_mode_set_plane { 132280183Sdumbbell __u32 plane_id; 133280183Sdumbbell __u32 crtc_id; 134280183Sdumbbell __u32 fb_id; /* fb object contains surface format type */ 135280183Sdumbbell __u32 flags; /* see above flags */ 136235783Skib 137235783Skib /* Signed dest location allows it to be partially off screen */ 138280183Sdumbbell __s32 crtc_x, crtc_y; 139280183Sdumbbell __u32 crtc_w, crtc_h; 140235783Skib 141235783Skib /* Source values are 16.16 fixed point */ 142280183Sdumbbell __u32 src_x, src_y; 143280183Sdumbbell __u32 src_h, src_w; 144235783Skib}; 145235783Skib 146235783Skibstruct drm_mode_get_plane { 147280183Sdumbbell __u32 plane_id; 148235783Skib 149280183Sdumbbell __u32 crtc_id; 150280183Sdumbbell __u32 fb_id; 151235783Skib 152280183Sdumbbell __u32 possible_crtcs; 153280183Sdumbbell __u32 gamma_size; 154235783Skib 155280183Sdumbbell __u32 count_format_types; 156280183Sdumbbell __u64 format_type_ptr; 157235783Skib}; 158235783Skib 159235783Skibstruct drm_mode_get_plane_res { 160280183Sdumbbell __u64 plane_id_ptr; 161280183Sdumbbell __u32 count_planes; 162235783Skib}; 163235783Skib 164235783Skib#define DRM_MODE_ENCODER_NONE 0 165235783Skib#define DRM_MODE_ENCODER_DAC 1 166235783Skib#define DRM_MODE_ENCODER_TMDS 2 167235783Skib#define DRM_MODE_ENCODER_LVDS 3 168235783Skib#define DRM_MODE_ENCODER_TVDAC 4 169280183Sdumbbell#define DRM_MODE_ENCODER_VIRTUAL 5 170235783Skib 171235783Skibstruct drm_mode_get_encoder { 172280183Sdumbbell __u32 encoder_id; 173280183Sdumbbell __u32 encoder_type; 174235783Skib 175280183Sdumbbell __u32 crtc_id; /**< Id of crtc */ 176235783Skib 177280183Sdumbbell __u32 possible_crtcs; 178280183Sdumbbell __u32 possible_clones; 179235783Skib}; 180235783Skib 181235783Skib/* This is for connectors with multiple signal types. */ 182235783Skib/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ 183235783Skib#define DRM_MODE_SUBCONNECTOR_Automatic 0 184235783Skib#define DRM_MODE_SUBCONNECTOR_Unknown 0 185235783Skib#define DRM_MODE_SUBCONNECTOR_DVID 3 186235783Skib#define DRM_MODE_SUBCONNECTOR_DVIA 4 187235783Skib#define DRM_MODE_SUBCONNECTOR_Composite 5 188235783Skib#define DRM_MODE_SUBCONNECTOR_SVIDEO 6 189235783Skib#define DRM_MODE_SUBCONNECTOR_Component 8 190235783Skib#define DRM_MODE_SUBCONNECTOR_SCART 9 191235783Skib 192235783Skib#define DRM_MODE_CONNECTOR_Unknown 0 193235783Skib#define DRM_MODE_CONNECTOR_VGA 1 194235783Skib#define DRM_MODE_CONNECTOR_DVII 2 195235783Skib#define DRM_MODE_CONNECTOR_DVID 3 196235783Skib#define DRM_MODE_CONNECTOR_DVIA 4 197235783Skib#define DRM_MODE_CONNECTOR_Composite 5 198235783Skib#define DRM_MODE_CONNECTOR_SVIDEO 6 199235783Skib#define DRM_MODE_CONNECTOR_LVDS 7 200235783Skib#define DRM_MODE_CONNECTOR_Component 8 201235783Skib#define DRM_MODE_CONNECTOR_9PinDIN 9 202235783Skib#define DRM_MODE_CONNECTOR_DisplayPort 10 203235783Skib#define DRM_MODE_CONNECTOR_HDMIA 11 204235783Skib#define DRM_MODE_CONNECTOR_HDMIB 12 205235783Skib#define DRM_MODE_CONNECTOR_TV 13 206235783Skib#define DRM_MODE_CONNECTOR_eDP 14 207280183Sdumbbell#define DRM_MODE_CONNECTOR_VIRTUAL 15 208235783Skib 209235783Skibstruct drm_mode_get_connector { 210235783Skib 211280183Sdumbbell __u64 encoders_ptr; 212280183Sdumbbell __u64 modes_ptr; 213280183Sdumbbell __u64 props_ptr; 214280183Sdumbbell __u64 prop_values_ptr; 215235783Skib 216280183Sdumbbell __u32 count_modes; 217280183Sdumbbell __u32 count_props; 218280183Sdumbbell __u32 count_encoders; 219235783Skib 220280183Sdumbbell __u32 encoder_id; /**< Current Encoder */ 221280183Sdumbbell __u32 connector_id; /**< Id */ 222280183Sdumbbell __u32 connector_type; 223280183Sdumbbell __u32 connector_type_id; 224235783Skib 225280183Sdumbbell __u32 connection; 226280183Sdumbbell __u32 mm_width, mm_height; /**< HxW in millimeters */ 227280183Sdumbbell __u32 subpixel; 228235783Skib}; 229235783Skib 230235783Skib#define DRM_MODE_PROP_PENDING (1<<0) 231235783Skib#define DRM_MODE_PROP_RANGE (1<<1) 232235783Skib#define DRM_MODE_PROP_IMMUTABLE (1<<2) 233235783Skib#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ 234235783Skib#define DRM_MODE_PROP_BLOB (1<<4) 235277487Skib#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */ 236235783Skib 237235783Skibstruct drm_mode_property_enum { 238280183Sdumbbell __u64 value; 239235783Skib char name[DRM_PROP_NAME_LEN]; 240235783Skib}; 241235783Skib 242235783Skibstruct drm_mode_get_property { 243280183Sdumbbell __u64 values_ptr; /* values and blob lengths */ 244280183Sdumbbell __u64 enum_blob_ptr; /* enum and blob id ptrs */ 245235783Skib 246280183Sdumbbell __u32 prop_id; 247280183Sdumbbell __u32 flags; 248235783Skib char name[DRM_PROP_NAME_LEN]; 249235783Skib 250280183Sdumbbell __u32 count_values; 251280183Sdumbbell __u32 count_enum_blobs; 252235783Skib}; 253235783Skib 254235783Skibstruct drm_mode_connector_set_property { 255280183Sdumbbell __u64 value; 256280183Sdumbbell __u32 prop_id; 257280183Sdumbbell __u32 connector_id; 258235783Skib}; 259235783Skib 260277487Skibstruct drm_mode_obj_get_properties { 261280183Sdumbbell __u64 props_ptr; 262280183Sdumbbell __u64 prop_values_ptr; 263280183Sdumbbell __u32 count_props; 264280183Sdumbbell __u32 obj_id; 265280183Sdumbbell __u32 obj_type; 266277487Skib}; 267277487Skib 268277487Skibstruct drm_mode_obj_set_property { 269280183Sdumbbell __u64 value; 270280183Sdumbbell __u32 prop_id; 271280183Sdumbbell __u32 obj_id; 272280183Sdumbbell __u32 obj_type; 273277487Skib}; 274277487Skib 275235783Skibstruct drm_mode_get_blob { 276280183Sdumbbell __u32 blob_id; 277280183Sdumbbell __u32 length; 278280183Sdumbbell __u64 data; 279235783Skib}; 280235783Skib 281235783Skibstruct drm_mode_fb_cmd { 282280183Sdumbbell __u32 fb_id; 283280183Sdumbbell __u32 width, height; 284280183Sdumbbell __u32 pitch; 285280183Sdumbbell __u32 bpp; 286280183Sdumbbell __u32 depth; 287235783Skib /* driver specific handle */ 288280183Sdumbbell __u32 handle; 289235783Skib}; 290235783Skib 291280183Sdumbbell#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ 292235783Skib 293235783Skibstruct drm_mode_fb_cmd2 { 294280183Sdumbbell __u32 fb_id; 295280183Sdumbbell __u32 width, height; 296280183Sdumbbell __u32 pixel_format; /* fourcc code from drm_fourcc.h */ 297280183Sdumbbell __u32 flags; /* see above flags */ 298235783Skib 299235783Skib /* 300235783Skib * In case of planar formats, this ioctl allows up to 4 301235783Skib * buffer objects with offets and pitches per plane. 302235783Skib * The pitch and offset order is dictated by the fourcc, 303235783Skib * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as: 304235783Skib * 305235783Skib * YUV 4:2:0 image with a plane of 8 bit Y samples 306235783Skib * followed by an interleaved U/V plane containing 307235783Skib * 8 bit 2x2 subsampled colour difference samples. 308235783Skib * 309235783Skib * So it would consist of Y as offset[0] and UV as 310235783Skib * offeset[1]. Note that offset[0] will generally 311235783Skib * be 0. 312235783Skib */ 313280183Sdumbbell __u32 handles[4]; 314280183Sdumbbell __u32 pitches[4]; /* pitch for each plane */ 315280183Sdumbbell __u32 offsets[4]; /* offset of each plane */ 316235783Skib}; 317235783Skib 318235783Skib#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 319235783Skib#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02 320235783Skib#define DRM_MODE_FB_DIRTY_FLAGS 0x03 321235783Skib 322235783Skib#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256 323235783Skib 324235783Skib/* 325235783Skib * Mark a region of a framebuffer as dirty. 326235783Skib * 327235783Skib * Some hardware does not automatically update display contents 328235783Skib * as a hardware or software draw to a framebuffer. This ioctl 329235783Skib * allows userspace to tell the kernel and the hardware what 330235783Skib * regions of the framebuffer have changed. 331235783Skib * 332235783Skib * The kernel or hardware is free to update more then just the 333235783Skib * region specified by the clip rects. The kernel or hardware 334235783Skib * may also delay and/or coalesce several calls to dirty into a 335235783Skib * single update. 336235783Skib * 337235783Skib * Userspace may annotate the updates, the annotates are a 338235783Skib * promise made by the caller that the change is either a copy 339235783Skib * of pixels or a fill of a single color in the region specified. 340235783Skib * 341235783Skib * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then 342235783Skib * the number of updated regions are half of num_clips given, 343235783Skib * where the clip rects are paired in src and dst. The width and 344235783Skib * height of each one of the pairs must match. 345235783Skib * 346235783Skib * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller 347235783Skib * promises that the region specified of the clip rects is filled 348235783Skib * completely with a single color as given in the color argument. 349235783Skib */ 350235783Skib 351235783Skibstruct drm_mode_fb_dirty_cmd { 352280183Sdumbbell __u32 fb_id; 353280183Sdumbbell __u32 flags; 354280183Sdumbbell __u32 color; 355280183Sdumbbell __u32 num_clips; 356280183Sdumbbell __u64 clips_ptr; 357235783Skib}; 358235783Skib 359235783Skibstruct drm_mode_mode_cmd { 360280183Sdumbbell __u32 connector_id; 361235783Skib struct drm_mode_modeinfo mode; 362235783Skib}; 363235783Skib 364280183Sdumbbell#define DRM_MODE_CURSOR_BO 0x01 365280183Sdumbbell#define DRM_MODE_CURSOR_MOVE 0x02 366280183Sdumbbell#define DRM_MODE_CURSOR_FLAGS 0x03 367235783Skib 368235783Skib/* 369280183Sdumbbell * depending on the value in flags different members are used. 370235783Skib * 371235783Skib * CURSOR_BO uses 372235783Skib * crtc 373235783Skib * width 374235783Skib * height 375235783Skib * handle - if 0 turns the cursor of 376235783Skib * 377235783Skib * CURSOR_MOVE uses 378235783Skib * crtc 379235783Skib * x 380235783Skib * y 381235783Skib */ 382235783Skibstruct drm_mode_cursor { 383280183Sdumbbell __u32 flags; 384280183Sdumbbell __u32 crtc_id; 385280183Sdumbbell __s32 x; 386280183Sdumbbell __s32 y; 387280183Sdumbbell __u32 width; 388280183Sdumbbell __u32 height; 389235783Skib /* driver specific handle */ 390280183Sdumbbell __u32 handle; 391235783Skib}; 392235783Skib 393235783Skibstruct drm_mode_crtc_lut { 394280183Sdumbbell __u32 crtc_id; 395280183Sdumbbell __u32 gamma_size; 396235783Skib 397235783Skib /* pointers to arrays */ 398280183Sdumbbell __u64 red; 399280183Sdumbbell __u64 green; 400280183Sdumbbell __u64 blue; 401235783Skib}; 402235783Skib 403235783Skib#define DRM_MODE_PAGE_FLIP_EVENT 0x01 404235783Skib#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT 405235783Skib 406235783Skib/* 407235783Skib * Request a page flip on the specified crtc. 408235783Skib * 409235783Skib * This ioctl will ask KMS to schedule a page flip for the specified 410235783Skib * crtc. Once any pending rendering targeting the specified fb (as of 411235783Skib * ioctl time) has completed, the crtc will be reprogrammed to display 412235783Skib * that fb after the next vertical refresh. The ioctl returns 413235783Skib * immediately, but subsequent rendering to the current fb will block 414235783Skib * in the execbuffer ioctl until the page flip happens. If a page 415235783Skib * flip is already pending as the ioctl is called, EBUSY will be 416235783Skib * returned. 417235783Skib * 418235783Skib * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will 419235783Skib * request that drm sends back a vblank event (see drm.h: struct 420235783Skib * drm_event_vblank) when the page flip is done. The user_data field 421235783Skib * passed in with this ioctl will be returned as the user_data field 422235783Skib * in the vblank event struct. 423235783Skib * 424235783Skib * The reserved field must be zero until we figure out something 425235783Skib * clever to use it for. 426235783Skib */ 427235783Skib 428235783Skibstruct drm_mode_crtc_page_flip { 429280183Sdumbbell __u32 crtc_id; 430280183Sdumbbell __u32 fb_id; 431280183Sdumbbell __u32 flags; 432280183Sdumbbell __u32 reserved; 433280183Sdumbbell __u64 user_data; 434235783Skib}; 435235783Skib 436235783Skib/* create a dumb scanout buffer */ 437235783Skibstruct drm_mode_create_dumb { 438235783Skib uint32_t height; 439235783Skib uint32_t width; 440235783Skib uint32_t bpp; 441235783Skib uint32_t flags; 442235783Skib /* handle, pitch, size will be returned */ 443235783Skib uint32_t handle; 444235783Skib uint32_t pitch; 445235783Skib uint64_t size; 446235783Skib}; 447235783Skib 448235783Skib/* set up for mmap of a dumb scanout buffer */ 449235783Skibstruct drm_mode_map_dumb { 450235783Skib /** Handle for the object being mapped. */ 451280183Sdumbbell __u32 handle; 452280183Sdumbbell __u32 pad; 453235783Skib /** 454235783Skib * Fake offset to use for subsequent mmap call 455235783Skib * 456235783Skib * This is a fixed-size type for 32/64 compatibility. 457235783Skib */ 458280183Sdumbbell __u64 offset; 459235783Skib}; 460235783Skib 461235783Skibstruct drm_mode_destroy_dumb { 462235783Skib uint32_t handle; 463235783Skib}; 464235783Skib 465235783Skib#endif 466