drm.h revision 277487
1/** 2 * \file drm.h 3 * Header for the Direct Rendering Manager 4 * 5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 6 * 7 * \par Acknowledgments: 8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. 9 */ 10 11/*- 12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 14 * All rights reserved. 15 * 16 * Permission is hereby granted, free of charge, to any person obtaining a 17 * copy of this software and associated documentation files (the "Software"), 18 * to deal in the Software without restriction, including without limitation 19 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 20 * and/or sell copies of the Software, and to permit persons to whom the 21 * Software is furnished to do so, subject to the following conditions: 22 * 23 * The above copyright notice and this permission notice (including the next 24 * paragraph) shall be included in all copies or substantial portions of the 25 * Software. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 33 * OTHER DEALINGS IN THE SOFTWARE. 34 */ 35 36#include <sys/cdefs.h> 37__FBSDID("$FreeBSD: head/sys/dev/drm2/drm.h 277487 2015-01-21 16:10:37Z kib $"); 38 39/** 40 * \mainpage 41 * 42 * The Direct Rendering Manager (DRM) is a device-independent kernel-level 43 * device driver that provides support for the XFree86 Direct Rendering 44 * Infrastructure (DRI). 45 * 46 * The DRM supports the Direct Rendering Infrastructure (DRI) in four major 47 * ways: 48 * -# The DRM provides synchronized access to the graphics hardware via 49 * the use of an optimized two-tiered lock. 50 * -# The DRM enforces the DRI security policy for access to the graphics 51 * hardware by only allowing authenticated X11 clients access to 52 * restricted regions of memory. 53 * -# The DRM provides a generic DMA engine, complete with multiple 54 * queues and the ability to detect the need for an OpenGL context 55 * switch. 56 * -# The DRM is extensible via the use of small device-specific modules 57 * that rely extensively on the API exported by the DRM module. 58 * 59 */ 60 61#ifndef _DRM_H_ 62#define _DRM_H_ 63 64#ifndef __user 65#define __user 66#endif 67#ifndef __iomem 68#define __iomem 69#endif 70 71#ifdef __GNUC__ 72# define DEPRECATED __attribute__ ((deprecated)) 73#else 74# define DEPRECATED 75#endif 76 77#if defined(__linux__) 78#include <asm/ioctl.h> /* For _IO* macros */ 79#define DRM_IOCTL_NR(n) _IOC_NR(n) 80#define DRM_IOC_VOID _IOC_NONE 81#define DRM_IOC_READ _IOC_READ 82#define DRM_IOC_WRITE _IOC_WRITE 83#define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE 84#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) 85#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) 86#include <sys/ioccom.h> 87#define DRM_IOCTL_NR(n) ((n) & 0xff) 88#define DRM_IOC_VOID IOC_VOID 89#define DRM_IOC_READ IOC_OUT 90#define DRM_IOC_WRITE IOC_IN 91#define DRM_IOC_READWRITE IOC_INOUT 92#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) 93#endif 94 95#ifdef __OpenBSD__ 96#define DRM_MAJOR 81 97#endif 98#if defined(__linux__) || defined(__NetBSD__) 99#define DRM_MAJOR 226 100#endif 101#define DRM_MAX_MINOR 15 102 103#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ 104#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ 105#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ 106#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ 107 108#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ 109#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ 110#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) 111#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 112#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 113 114#if defined(__linux__) 115typedef unsigned int drm_handle_t; 116#else 117#include <sys/types.h> 118typedef unsigned long drm_handle_t; /**< To mapped regions */ 119#endif 120typedef unsigned int drm_context_t; /**< GLXContext handle */ 121typedef unsigned int drm_drawable_t; 122typedef unsigned int drm_magic_t; /**< Magic for authentication */ 123 124/** 125 * Cliprect. 126 * 127 * \warning If you change this structure, make sure you change 128 * XF86DRIClipRectRec in the server as well 129 * 130 * \note KW: Actually it's illegal to change either for 131 * backwards-compatibility reasons. 132 */ 133struct drm_clip_rect { 134 unsigned short x1; 135 unsigned short y1; 136 unsigned short x2; 137 unsigned short y2; 138}; 139 140/** 141 * Texture region, 142 */ 143struct drm_tex_region { 144 unsigned char next; 145 unsigned char prev; 146 unsigned char in_use; 147 unsigned char padding; 148 unsigned int age; 149}; 150 151/** 152 * Hardware lock. 153 * 154 * The lock structure is a simple cache-line aligned integer. To avoid 155 * processor bus contention on a multiprocessor system, there should not be any 156 * other data stored in the same cache line. 157 */ 158struct drm_hw_lock { 159 __volatile__ unsigned int lock; /**< lock variable */ 160 char padding[60]; /**< Pad to cache line */ 161}; 162 163/* This is beyond ugly, and only works on GCC. However, it allows me to use 164 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real 165 * fix is to use uint32_t instead of size_t, but that fix will break existing 166 * LP64 (i.e., PowerPC64, SPARC64, Alpha, etc.) systems. That *will* 167 * eventually happen, though. I chose 'unsigned long' to be the fallback type 168 * because that works on all the platforms I know about. Hopefully, the 169 * real fix will happen before that bites us. 170 */ 171 172#ifdef __SIZE_TYPE__ 173# define DRM_SIZE_T __SIZE_TYPE__ 174#else 175# warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!" 176# define DRM_SIZE_T unsigned long 177#endif 178 179/** 180 * DRM_IOCTL_VERSION ioctl argument type. 181 * 182 * \sa drmGetVersion(). 183 */ 184struct drm_version { 185 int version_major; /**< Major version */ 186 int version_minor; /**< Minor version */ 187 int version_patchlevel; /**< Patch level */ 188 DRM_SIZE_T name_len; /**< Length of name buffer */ 189 char __user *name; /**< Name of driver */ 190 DRM_SIZE_T date_len; /**< Length of date buffer */ 191 char __user *date; /**< User-space buffer to hold date */ 192 DRM_SIZE_T desc_len; /**< Length of desc buffer */ 193 char __user *desc; /**< User-space buffer to hold desc */ 194}; 195 196/** 197 * DRM_IOCTL_GET_UNIQUE ioctl argument type. 198 * 199 * \sa drmGetBusid() and drmSetBusId(). 200 */ 201struct drm_unique { 202 DRM_SIZE_T unique_len; /**< Length of unique */ 203 char __user *unique; /**< Unique name for driver instantiation */ 204}; 205 206#undef DRM_SIZE_T 207 208struct drm_list { 209 int count; /**< Length of user-space structures */ 210 struct drm_version __user *version; 211}; 212 213struct drm_block { 214 int unused; 215}; 216 217/** 218 * DRM_IOCTL_CONTROL ioctl argument type. 219 * 220 * \sa drmCtlInstHandler() and drmCtlUninstHandler(). 221 */ 222struct drm_control { 223 enum { 224 DRM_ADD_COMMAND, 225 DRM_RM_COMMAND, 226 DRM_INST_HANDLER, 227 DRM_UNINST_HANDLER 228 } func; 229 int irq; 230}; 231 232/** 233 * Type of memory to map. 234 */ 235enum drm_map_type { 236 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ 237 _DRM_REGISTERS = 1, /**< no caching, no core dump */ 238 _DRM_SHM = 2, /**< shared, cached */ 239 _DRM_AGP = 3, /**< AGP/GART */ 240 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ 241 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ 242 _DRM_GEM = 6 /**< GEM */ 243}; 244 245/** 246 * Memory mapping flags. 247 */ 248enum drm_map_flags { 249 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ 250 _DRM_READ_ONLY = 0x02, 251 _DRM_LOCKED = 0x04, /**< shared, cached, locked */ 252 _DRM_KERNEL = 0x08, /**< kernel requires access */ 253 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ 254 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ 255 _DRM_REMOVABLE = 0x40, /**< Removable mapping */ 256 _DRM_DRIVER = 0x80 /**< Managed by driver */ 257}; 258 259struct drm_ctx_priv_map { 260 unsigned int ctx_id; /**< Context requesting private mapping */ 261 void *handle; /**< Handle of map */ 262}; 263 264/** 265 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls 266 * argument type. 267 * 268 * \sa drmAddMap(). 269 */ 270struct drm_map { 271 unsigned long offset; /**< Requested physical address (0 for SAREA)*/ 272 unsigned long size; /**< Requested physical size (bytes) */ 273 enum drm_map_type type; /**< Type of memory to map */ 274 enum drm_map_flags flags; /**< Flags */ 275 void *handle; /**< User-space: "Handle" to pass to mmap() */ 276 /**< Kernel-space: kernel-virtual address */ 277 int mtrr; /**< MTRR slot used */ 278 /* Private data */ 279}; 280 281/** 282 * DRM_IOCTL_GET_CLIENT ioctl argument type. 283 */ 284struct drm_client { 285 int idx; /**< Which client desired? */ 286 int auth; /**< Is client authenticated? */ 287 unsigned long pid; /**< Process ID */ 288 unsigned long uid; /**< User ID */ 289 unsigned long magic; /**< Magic */ 290 unsigned long iocs; /**< Ioctl count */ 291}; 292 293enum drm_stat_type { 294 _DRM_STAT_LOCK, 295 _DRM_STAT_OPENS, 296 _DRM_STAT_CLOSES, 297 _DRM_STAT_IOCTLS, 298 _DRM_STAT_LOCKS, 299 _DRM_STAT_UNLOCKS, 300 _DRM_STAT_VALUE, /**< Generic value */ 301 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ 302 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ 303 304 _DRM_STAT_IRQ, /**< IRQ */ 305 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ 306 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ 307 _DRM_STAT_DMA, /**< DMA */ 308 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ 309 _DRM_STAT_MISSED /**< Missed DMA opportunity */ 310 /* Add to the *END* of the list */ 311}; 312 313/** 314 * DRM_IOCTL_GET_STATS ioctl argument type. 315 */ 316struct drm_stats { 317 unsigned long count; 318 struct { 319 unsigned long value; 320 enum drm_stat_type type; 321 } data[15]; 322}; 323 324/** 325 * Hardware locking flags. 326 */ 327enum drm_lock_flags { 328 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 329 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 330 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 331 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 332 /* These *HALT* flags aren't supported yet 333 -- they will be used to support the 334 full-screen DGA-like mode. */ 335 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 336 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 337}; 338 339/** 340 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. 341 * 342 * \sa drmGetLock() and drmUnlock(). 343 */ 344struct drm_lock { 345 int context; 346 enum drm_lock_flags flags; 347}; 348 349/** 350 * DMA flags 351 * 352 * \warning 353 * These values \e must match xf86drm.h. 354 * 355 * \sa drm_dma. 356 */ 357enum drm_dma_flags { 358 /* Flags for DMA buffer dispatch */ 359 _DRM_DMA_BLOCK = 0x01, /**< 360 * Block until buffer dispatched. 361 * 362 * \note The buffer may not yet have 363 * been processed by the hardware -- 364 * getting a hardware lock with the 365 * hardware quiescent will ensure 366 * that the buffer has been 367 * processed. 368 */ 369 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 370 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 371 372 /* Flags for DMA buffer request */ 373 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 374 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 375 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 376}; 377 378/** 379 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. 380 * 381 * \sa drmAddBufs(). 382 */ 383struct drm_buf_desc { 384 int count; /**< Number of buffers of this size */ 385 int size; /**< Size in bytes */ 386 int low_mark; /**< Low water mark */ 387 int high_mark; /**< High water mark */ 388 enum { 389 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ 390 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ 391 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ 392 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ 393 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ 394 } flags; 395 unsigned long agp_start; /**< 396 * Start address of where the AGP buffers are 397 * in the AGP aperture 398 */ 399}; 400 401/** 402 * DRM_IOCTL_INFO_BUFS ioctl argument type. 403 */ 404struct drm_buf_info { 405 int count; /**< Number of buffers described in list */ 406 struct drm_buf_desc __user *list; /**< List of buffer descriptions */ 407}; 408 409/** 410 * DRM_IOCTL_FREE_BUFS ioctl argument type. 411 */ 412struct drm_buf_free { 413 int count; 414 int __user *list; 415}; 416 417/** 418 * Buffer information 419 * 420 * \sa drm_buf_map. 421 */ 422struct drm_buf_pub { 423 int idx; /**< Index into the master buffer list */ 424 int total; /**< Buffer size */ 425 int used; /**< Amount of buffer in use (for DMA) */ 426 void __user *address; /**< Address of buffer */ 427}; 428 429/** 430 * DRM_IOCTL_MAP_BUFS ioctl argument type. 431 */ 432struct drm_buf_map { 433 int count; /**< Length of the buffer list */ 434#if defined(__cplusplus) 435 void __user *c_virtual; 436#else 437 void __user *virtual; /**< Mmap'd area in user-virtual */ 438#endif 439 struct drm_buf_pub __user *list; /**< Buffer information */ 440}; 441 442/** 443 * DRM_IOCTL_DMA ioctl argument type. 444 * 445 * Indices here refer to the offset into the buffer list in drm_buf_get. 446 * 447 * \sa drmDMA(). 448 */ 449struct drm_dma { 450 int context; /**< Context handle */ 451 int send_count; /**< Number of buffers to send */ 452 int __user *send_indices; /**< List of handles to buffers */ 453 int __user *send_sizes; /**< Lengths of data to send */ 454 enum drm_dma_flags flags; /**< Flags */ 455 int request_count; /**< Number of buffers requested */ 456 int request_size; /**< Desired size for buffers */ 457 int __user *request_indices; /**< Buffer information */ 458 int __user *request_sizes; 459 int granted_count; /**< Number of buffers granted */ 460}; 461 462enum drm_ctx_flags { 463 _DRM_CONTEXT_PRESERVED = 0x01, 464 _DRM_CONTEXT_2DONLY = 0x02 465}; 466 467/** 468 * DRM_IOCTL_ADD_CTX ioctl argument type. 469 * 470 * \sa drmCreateContext() and drmDestroyContext(). 471 */ 472struct drm_ctx { 473 drm_context_t handle; 474 enum drm_ctx_flags flags; 475}; 476 477/** 478 * DRM_IOCTL_RES_CTX ioctl argument type. 479 */ 480struct drm_ctx_res { 481 int count; 482 struct drm_ctx __user *contexts; 483}; 484 485/** 486 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. 487 */ 488struct drm_draw { 489 drm_drawable_t handle; 490}; 491 492/** 493 * DRM_IOCTL_UPDATE_DRAW ioctl argument type. 494 */ 495typedef enum { 496 DRM_DRAWABLE_CLIPRECTS, 497} drm_drawable_info_type_t; 498 499struct drm_update_draw { 500 drm_drawable_t handle; 501 unsigned int type; 502 unsigned int num; 503 unsigned long long data; 504}; 505 506/** 507 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. 508 */ 509struct drm_auth { 510 drm_magic_t magic; 511}; 512 513/** 514 * DRM_IOCTL_IRQ_BUSID ioctl argument type. 515 * 516 * \sa drmGetInterruptFromBusID(). 517 */ 518struct drm_irq_busid { 519 int irq; /**< IRQ number */ 520 int busnum; /**< bus number */ 521 int devnum; /**< device number */ 522 int funcnum; /**< function number */ 523}; 524 525enum drm_vblank_seq_type { 526 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 527 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 528 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, 529 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ 530 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ 531 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 532 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 533 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ 534}; 535#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 536 537#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) 538#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ 539 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) 540 541struct drm_wait_vblank_request { 542 enum drm_vblank_seq_type type; 543 unsigned int sequence; 544 unsigned long signal; 545}; 546 547struct drm_wait_vblank_reply { 548 enum drm_vblank_seq_type type; 549 unsigned int sequence; 550 long tval_sec; 551 long tval_usec; 552}; 553 554/** 555 * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 556 * 557 * \sa drmWaitVBlank(). 558 */ 559union drm_wait_vblank { 560 struct drm_wait_vblank_request request; 561 struct drm_wait_vblank_reply reply; 562}; 563 564 565#define _DRM_PRE_MODESET 1 566#define _DRM_POST_MODESET 2 567 568/** 569 * DRM_IOCTL_MODESET_CTL ioctl argument type 570 * 571 * \sa drmModesetCtl(). 572 */ 573struct drm_modeset_ctl { 574 uint32_t crtc; 575 uint32_t cmd; 576}; 577 578/** 579 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 580 * 581 * \sa drmAgpEnable(). 582 */ 583struct drm_agp_mode { 584 unsigned long mode; /**< AGP mode */ 585}; 586 587/** 588 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. 589 * 590 * \sa drmAgpAlloc() and drmAgpFree(). 591 */ 592struct drm_agp_buffer { 593 unsigned long size; /**< In bytes -- will round to page boundary */ 594 unsigned long handle; /**< Used for binding / unbinding */ 595 unsigned long type; /**< Type of memory to allocate */ 596 unsigned long physical; /**< Physical used by i810 */ 597}; 598 599/** 600 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. 601 * 602 * \sa drmAgpBind() and drmAgpUnbind(). 603 */ 604struct drm_agp_binding { 605 unsigned long handle; /**< From drm_agp_buffer */ 606 unsigned long offset; /**< In bytes -- will round to page boundary */ 607}; 608 609/** 610 * DRM_IOCTL_AGP_INFO ioctl argument type. 611 * 612 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), 613 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), 614 * drmAgpVendorId() and drmAgpDeviceId(). 615 */ 616struct drm_agp_info { 617 int agp_version_major; 618 int agp_version_minor; 619 unsigned long mode; 620 unsigned long aperture_base; /**< physical address */ 621 unsigned long aperture_size; /**< bytes */ 622 unsigned long memory_allowed; /**< bytes */ 623 unsigned long memory_used; 624 625 /** \name PCI information */ 626 /*@{ */ 627 unsigned short id_vendor; 628 unsigned short id_device; 629 /*@} */ 630}; 631 632/** 633 * DRM_IOCTL_SG_ALLOC ioctl argument type. 634 */ 635struct drm_scatter_gather { 636 unsigned long size; /**< In bytes -- will round to page boundary */ 637 unsigned long handle; /**< Used for mapping / unmapping */ 638}; 639 640/** 641 * DRM_IOCTL_SET_VERSION ioctl argument type. 642 */ 643struct drm_set_version { 644 int drm_di_major; 645 int drm_di_minor; 646 int drm_dd_major; 647 int drm_dd_minor; 648}; 649 650#define DRM_FENCE_FLAG_EMIT 0x00000001 651#define DRM_FENCE_FLAG_SHAREABLE 0x00000002 652/** 653 * On hardware with no interrupt events for operation completion, 654 * indicates that the kernel should sleep while waiting for any blocking 655 * operation to complete rather than spinning. 656 * 657 * Has no effect otherwise. 658 */ 659#define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004 660#define DRM_FENCE_FLAG_NO_USER 0x00000010 661 662/* Reserved for driver use */ 663#define DRM_FENCE_MASK_DRIVER 0xFF000000 664 665#define DRM_FENCE_TYPE_EXE 0x00000001 666 667struct drm_fence_arg { 668 unsigned int handle; 669 unsigned int fence_class; 670 unsigned int type; 671 unsigned int flags; 672 unsigned int signaled; 673 unsigned int error; 674 unsigned int sequence; 675 unsigned int pad64; 676 uint64_t expand_pad[2]; /* Future expansion */ 677}; 678 679/* Buffer permissions, referring to how the GPU uses the buffers. 680 * these translate to fence types used for the buffers. 681 * Typically a texture buffer is read, A destination buffer is write and 682 * a command (batch-) buffer is exe. Can be or-ed together. 683 */ 684 685#define DRM_BO_FLAG_READ (1ULL << 0) 686#define DRM_BO_FLAG_WRITE (1ULL << 1) 687#define DRM_BO_FLAG_EXE (1ULL << 2) 688 689/* 690 * All of the bits related to access mode 691 */ 692#define DRM_BO_MASK_ACCESS (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE | DRM_BO_FLAG_EXE) 693/* 694 * Status flags. Can be read to determine the actual state of a buffer. 695 * Can also be set in the buffer mask before validation. 696 */ 697 698/* 699 * Mask: Never evict this buffer. Not even with force. This type of buffer is only 700 * available to root and must be manually removed before buffer manager shutdown 701 * or lock. 702 * Flags: Acknowledge 703 */ 704#define DRM_BO_FLAG_NO_EVICT (1ULL << 4) 705 706/* 707 * Mask: Require that the buffer is placed in mappable memory when validated. 708 * If not set the buffer may or may not be in mappable memory when validated. 709 * Flags: If set, the buffer is in mappable memory. 710 */ 711#define DRM_BO_FLAG_MAPPABLE (1ULL << 5) 712 713/* Mask: The buffer should be shareable with other processes. 714 * Flags: The buffer is shareable with other processes. 715 */ 716#define DRM_BO_FLAG_SHAREABLE (1ULL << 6) 717 718/* Mask: If set, place the buffer in cache-coherent memory if available. 719 * If clear, never place the buffer in cache coherent memory if validated. 720 * Flags: The buffer is currently in cache-coherent memory. 721 */ 722#define DRM_BO_FLAG_CACHED (1ULL << 7) 723 724/* Mask: Make sure that every time this buffer is validated, 725 * it ends up on the same location provided that the memory mask is the same. 726 * The buffer will also not be evicted when claiming space for 727 * other buffers. Basically a pinned buffer but it may be thrown out as 728 * part of buffer manager shutdown or locking. 729 * Flags: Acknowledge. 730 */ 731#define DRM_BO_FLAG_NO_MOVE (1ULL << 8) 732 733/* Mask: Make sure the buffer is in cached memory when mapped. In conjunction 734 * with DRM_BO_FLAG_CACHED it also allows the buffer to be bound into the GART 735 * with unsnooped PTEs instead of snooped, by using chipset-specific cache 736 * flushing at bind time. A better name might be DRM_BO_FLAG_TT_UNSNOOPED, 737 * as the eviction to local memory (TTM unbind) on map is just a side effect 738 * to prevent aggressive cache prefetch from the GPU disturbing the cache 739 * management that the DRM is doing. 740 * 741 * Flags: Acknowledge. 742 * Buffers allocated with this flag should not be used for suballocators 743 * This type may have issues on CPUs with over-aggressive caching 744 * http://marc.info/?l=linux-kernel&m=102376926732464&w=2 745 */ 746#define DRM_BO_FLAG_CACHED_MAPPED (1ULL << 19) 747 748 749/* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set. 750 * Flags: Acknowledge. 751 */ 752#define DRM_BO_FLAG_FORCE_CACHING (1ULL << 13) 753 754/* 755 * Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear. 756 * Flags: Acknowledge. 757 */ 758#define DRM_BO_FLAG_FORCE_MAPPABLE (1ULL << 14) 759#define DRM_BO_FLAG_TILE (1ULL << 15) 760 761/* 762 * Memory type flags that can be or'ed together in the mask, but only 763 * one appears in flags. 764 */ 765 766/* System memory */ 767#define DRM_BO_FLAG_MEM_LOCAL (1ULL << 24) 768/* Translation table memory */ 769#define DRM_BO_FLAG_MEM_TT (1ULL << 25) 770/* Vram memory */ 771#define DRM_BO_FLAG_MEM_VRAM (1ULL << 26) 772/* Up to the driver to define. */ 773#define DRM_BO_FLAG_MEM_PRIV0 (1ULL << 27) 774#define DRM_BO_FLAG_MEM_PRIV1 (1ULL << 28) 775#define DRM_BO_FLAG_MEM_PRIV2 (1ULL << 29) 776#define DRM_BO_FLAG_MEM_PRIV3 (1ULL << 30) 777#define DRM_BO_FLAG_MEM_PRIV4 (1ULL << 31) 778/* We can add more of these now with a 64-bit flag type */ 779 780/* 781 * This is a mask covering all of the memory type flags; easier to just 782 * use a single constant than a bunch of | values. It covers 783 * DRM_BO_FLAG_MEM_LOCAL through DRM_BO_FLAG_MEM_PRIV4 784 */ 785#define DRM_BO_MASK_MEM 0x00000000FF000000ULL 786/* 787 * This adds all of the CPU-mapping options in with the memory 788 * type to label all bits which change how the page gets mapped 789 */ 790#define DRM_BO_MASK_MEMTYPE (DRM_BO_MASK_MEM | \ 791 DRM_BO_FLAG_CACHED_MAPPED | \ 792 DRM_BO_FLAG_CACHED | \ 793 DRM_BO_FLAG_MAPPABLE) 794 795/* Driver-private flags */ 796#define DRM_BO_MASK_DRIVER 0xFFFF000000000000ULL 797 798/* 799 * Don't block on validate and map. Instead, return EBUSY. 800 */ 801#define DRM_BO_HINT_DONT_BLOCK 0x00000002 802/* 803 * Don't place this buffer on the unfenced list. This means 804 * that the buffer will not end up having a fence associated 805 * with it as a result of this operation 806 */ 807#define DRM_BO_HINT_DONT_FENCE 0x00000004 808/** 809 * On hardware with no interrupt events for operation completion, 810 * indicates that the kernel should sleep while waiting for any blocking 811 * operation to complete rather than spinning. 812 * 813 * Has no effect otherwise. 814 */ 815#define DRM_BO_HINT_WAIT_LAZY 0x00000008 816/* 817 * The client has compute relocations refering to this buffer using the 818 * offset in the presumed_offset field. If that offset ends up matching 819 * where this buffer lands, the kernel is free to skip executing those 820 * relocations 821 */ 822#define DRM_BO_HINT_PRESUMED_OFFSET 0x00000010 823 824#define DRM_BO_INIT_MAGIC 0xfe769812 825#define DRM_BO_INIT_MAJOR 1 826#define DRM_BO_INIT_MINOR 0 827#define DRM_BO_INIT_PATCH 0 828 829 830struct drm_bo_info_req { 831 uint64_t mask; 832 uint64_t flags; 833 unsigned int handle; 834 unsigned int hint; 835 unsigned int fence_class; 836 unsigned int desired_tile_stride; 837 unsigned int tile_info; 838 unsigned int pad64; 839 uint64_t presumed_offset; 840}; 841 842struct drm_bo_create_req { 843 uint64_t flags; 844 uint64_t size; 845 uint64_t buffer_start; 846 unsigned int hint; 847 unsigned int page_alignment; 848}; 849 850 851/* 852 * Reply flags 853 */ 854 855#define DRM_BO_REP_BUSY 0x00000001 856 857struct drm_bo_info_rep { 858 uint64_t flags; 859 uint64_t proposed_flags; 860 uint64_t size; 861 uint64_t offset; 862 uint64_t arg_handle; 863 uint64_t buffer_start; 864 unsigned int handle; 865 unsigned int fence_flags; 866 unsigned int rep_flags; 867 unsigned int page_alignment; 868 unsigned int desired_tile_stride; 869 unsigned int hw_tile_stride; 870 unsigned int tile_info; 871 unsigned int pad64; 872 uint64_t expand_pad[4]; /*Future expansion */ 873}; 874 875struct drm_bo_arg_rep { 876 struct drm_bo_info_rep bo_info; 877 int ret; 878 unsigned int pad64; 879}; 880 881struct drm_bo_create_arg { 882 union { 883 struct drm_bo_create_req req; 884 struct drm_bo_info_rep rep; 885 } d; 886}; 887 888struct drm_bo_handle_arg { 889 unsigned int handle; 890}; 891 892struct drm_bo_reference_info_arg { 893 union { 894 struct drm_bo_handle_arg req; 895 struct drm_bo_info_rep rep; 896 } d; 897}; 898 899struct drm_bo_map_wait_idle_arg { 900 union { 901 struct drm_bo_info_req req; 902 struct drm_bo_info_rep rep; 903 } d; 904}; 905 906struct drm_bo_op_req { 907 enum { 908 drm_bo_validate, 909 drm_bo_fence, 910 drm_bo_ref_fence, 911 } op; 912 unsigned int arg_handle; 913 struct drm_bo_info_req bo_req; 914}; 915 916 917struct drm_bo_op_arg { 918 uint64_t next; 919 union { 920 struct drm_bo_op_req req; 921 struct drm_bo_arg_rep rep; 922 } d; 923 int handled; 924 unsigned int pad64; 925}; 926 927 928#define DRM_BO_MEM_LOCAL 0 929#define DRM_BO_MEM_TT 1 930#define DRM_BO_MEM_VRAM 2 931#define DRM_BO_MEM_PRIV0 3 932#define DRM_BO_MEM_PRIV1 4 933#define DRM_BO_MEM_PRIV2 5 934#define DRM_BO_MEM_PRIV3 6 935#define DRM_BO_MEM_PRIV4 7 936 937#define DRM_BO_MEM_TYPES 8 /* For now. */ 938 939#define DRM_BO_LOCK_UNLOCK_BM (1 << 0) 940#define DRM_BO_LOCK_IGNORE_NO_EVICT (1 << 1) 941 942struct drm_bo_version_arg { 943 uint32_t major; 944 uint32_t minor; 945 uint32_t patchlevel; 946}; 947 948struct drm_mm_type_arg { 949 unsigned int mem_type; 950 unsigned int lock_flags; 951}; 952 953struct drm_mm_init_arg { 954 unsigned int magic; 955 unsigned int major; 956 unsigned int minor; 957 unsigned int mem_type; 958 uint64_t p_offset; 959 uint64_t p_size; 960}; 961 962struct drm_mm_info_arg { 963 unsigned int mem_type; 964 uint64_t p_size; 965}; 966 967struct drm_gem_close { 968 /** Handle of the object to be closed. */ 969 uint32_t handle; 970 uint32_t pad; 971}; 972 973struct drm_gem_flink { 974 /** Handle for the object being named */ 975 uint32_t handle; 976 977 /** Returned global name */ 978 uint32_t name; 979}; 980 981struct drm_gem_open { 982 /** Name of object being opened */ 983 uint32_t name; 984 985 /** Returned handle for the object */ 986 uint32_t handle; 987 988 /** Returned size of the object */ 989 uint64_t size; 990}; 991 992struct drm_get_cap { 993 uint64_t capability; 994 uint64_t value; 995}; 996 997struct drm_event { 998 uint32_t type; 999 uint32_t length; 1000}; 1001 1002#define DRM_EVENT_VBLANK 0x01 1003#define DRM_EVENT_FLIP_COMPLETE 0x02 1004 1005struct drm_event_vblank { 1006 struct drm_event base; 1007 uint64_t user_data; 1008 uint32_t tv_sec; 1009 uint32_t tv_usec; 1010 uint32_t sequence; 1011 uint32_t reserved; 1012}; 1013 1014#define DRM_CAP_DUMB_BUFFER 0x1 1015#define DRM_CAP_VBLANK_HIGH_CRTC 0x2 1016#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 1017#define DRM_CAP_DUMB_PREFER_SHADOW 0x4 1018#define DRM_CAP_PRIME 0x5 1019#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 1020 1021#define DRM_PRIME_CAP_IMPORT 0x1 1022#define DRM_PRIME_CAP_EXPORT 0x2 1023 1024#include "drm_mode.h" 1025 1026/** 1027 * \name Ioctls Definitions 1028 */ 1029/*@{*/ 1030 1031#define DRM_IOCTL_BASE 'd' 1032#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 1033#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 1034#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) 1035#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) 1036 1037#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) 1038#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) 1039#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) 1040#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) 1041#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) 1042#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) 1043#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) 1044#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) 1045#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) 1046 1047#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) 1048#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) 1049#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) 1050 1051#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) 1052 1053#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) 1054#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) 1055#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) 1056#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) 1057#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) 1058#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) 1059#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) 1060#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) 1061#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) 1062#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) 1063#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) 1064 1065#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) 1066 1067#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) 1068#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) 1069 1070#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) 1071#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) 1072 1073#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) 1074#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) 1075#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) 1076#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) 1077#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) 1078#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) 1079#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) 1080#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) 1081#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) 1082#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) 1083#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) 1084#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) 1085#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) 1086 1087#define DRM_IOCTL_GEM_PRIME_OPEN DRM_IOWR(0x2e, struct drm_gem_open) 1088 1089#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) 1090#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) 1091#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) 1092#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) 1093#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) 1094#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) 1095#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) 1096#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) 1097 1098#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) 1099#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) 1100 1101#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) 1102 1103#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) 1104 1105#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) 1106#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) 1107#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) 1108#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) 1109#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) 1110#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) 1111#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) 1112#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) 1113#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) 1114#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) 1115 1116#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) 1117#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) 1118#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) 1119#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) 1120#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) 1121#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) 1122#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) 1123#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) 1124 1125#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) 1126#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) 1127#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) 1128#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) 1129#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) 1130#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) 1131#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) 1132#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) 1133#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) 1134 1135#define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg) 1136#define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg) 1137#define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg) 1138#define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg) 1139 1140#define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg) 1141#define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg) 1142#define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg) 1143#define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg) 1144#define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg) 1145#define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg) 1146#define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg) 1147#define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg) 1148 1149#define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg) 1150#define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg) 1151#define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg) 1152#define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg) 1153#define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg) 1154#define DRM_IOCTL_BO_SETSTATUS DRM_IOWR(0xd3, struct drm_bo_map_wait_idle_arg) 1155#define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg) 1156#define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg) 1157#define DRM_IOCTL_BO_VERSION DRM_IOR(0xd6, struct drm_bo_version_arg) 1158#define DRM_IOCTL_MM_INFO DRM_IOWR(0xd7, struct drm_mm_info_arg) 1159 1160/*@}*/ 1161 1162/** 1163 * Device specific ioctls should only be in their respective headers 1164 * The device specific ioctl range is from 0x40 to 0x99. 1165 * Generic IOCTLS restart at 0xA0. 1166 * 1167 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and 1168 * drmCommandReadWrite(). 1169 */ 1170#define DRM_COMMAND_BASE 0x40 1171#define DRM_COMMAND_END 0xA0 1172 1173/* typedef area */ 1174#ifndef __KERNEL__ 1175typedef struct drm_clip_rect drm_clip_rect_t; 1176typedef struct drm_tex_region drm_tex_region_t; 1177typedef struct drm_hw_lock drm_hw_lock_t; 1178typedef struct drm_version drm_version_t; 1179typedef struct drm_unique drm_unique_t; 1180typedef struct drm_list drm_list_t; 1181typedef struct drm_block drm_block_t; 1182typedef struct drm_control drm_control_t; 1183typedef enum drm_map_type drm_map_type_t; 1184typedef enum drm_map_flags drm_map_flags_t; 1185typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; 1186typedef struct drm_map drm_map_t; 1187typedef struct drm_client drm_client_t; 1188typedef enum drm_stat_type drm_stat_type_t; 1189typedef struct drm_stats drm_stats_t; 1190typedef enum drm_lock_flags drm_lock_flags_t; 1191typedef struct drm_lock drm_lock_t; 1192typedef enum drm_dma_flags drm_dma_flags_t; 1193typedef struct drm_buf_desc drm_buf_desc_t; 1194typedef struct drm_buf_info drm_buf_info_t; 1195typedef struct drm_buf_free drm_buf_free_t; 1196typedef struct drm_buf_pub drm_buf_pub_t; 1197typedef struct drm_buf_map drm_buf_map_t; 1198typedef struct drm_dma drm_dma_t; 1199typedef union drm_wait_vblank drm_wait_vblank_t; 1200typedef struct drm_agp_mode drm_agp_mode_t; 1201typedef enum drm_ctx_flags drm_ctx_flags_t; 1202typedef struct drm_ctx drm_ctx_t; 1203typedef struct drm_ctx_res drm_ctx_res_t; 1204typedef struct drm_draw drm_draw_t; 1205typedef struct drm_update_draw drm_update_draw_t; 1206typedef struct drm_auth drm_auth_t; 1207typedef struct drm_irq_busid drm_irq_busid_t; 1208typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; 1209typedef struct drm_agp_buffer drm_agp_buffer_t; 1210typedef struct drm_agp_binding drm_agp_binding_t; 1211typedef struct drm_agp_info drm_agp_info_t; 1212typedef struct drm_scatter_gather drm_scatter_gather_t; 1213typedef struct drm_set_version drm_set_version_t; 1214 1215typedef struct drm_fence_arg drm_fence_arg_t; 1216typedef struct drm_mm_type_arg drm_mm_type_arg_t; 1217typedef struct drm_mm_init_arg drm_mm_init_arg_t; 1218typedef enum drm_bo_type drm_bo_type_t; 1219#endif 1220 1221#endif 1222