radeon_drv.h revision 95693
1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * 30 * $FreeBSD: head/sys/dev/drm/radeon_drv.h 95693 2002-04-29 00:25:10Z anholt $ 31 */ 32 33#ifndef __RADEON_DRV_H__ 34#define __RADEON_DRV_H__ 35 36typedef struct drm_radeon_freelist { 37 unsigned int age; 38 drm_buf_t *buf; 39 struct drm_radeon_freelist *next; 40 struct drm_radeon_freelist *prev; 41} drm_radeon_freelist_t; 42 43typedef struct drm_radeon_ring_buffer { 44 u32 *start; 45 u32 *end; 46 int size; 47 int size_l2qw; 48 49 volatile u32 *head; 50 u32 tail; 51 u32 tail_mask; 52 int space; 53 54 int high_mark; 55} drm_radeon_ring_buffer_t; 56 57typedef struct drm_radeon_depth_clear_t { 58 u32 rb3d_cntl; 59 u32 rb3d_zstencilcntl; 60 u32 se_cntl; 61} drm_radeon_depth_clear_t; 62 63typedef struct drm_radeon_private { 64 drm_radeon_ring_buffer_t ring; 65 drm_radeon_sarea_t *sarea_priv; 66 67 int agp_size; 68 u32 agp_vm_start; 69 unsigned long agp_buffers_offset; 70 71 int cp_mode; 72 int cp_running; 73 74 drm_radeon_freelist_t *head; 75 drm_radeon_freelist_t *tail; 76/* FIXME: ROTATE_BUFS is a hask to cycle through bufs until freelist 77 code is used. Note this hides a problem with the scratch register 78 (used to keep track of last buffer completed) being written to before 79 the last buffer has actually completed rendering. */ 80#define ROTATE_BUFS 1 81#if ROTATE_BUFS 82 int last_buf; 83#endif 84 volatile u32 *scratch; 85 86 int usec_timeout; 87 int is_pci; 88 unsigned long phys_pci_gart; 89#if __REALLY_HAVE_SG 90 dma_addr_t bus_pci_gart; 91#endif 92 93 atomic_t idle_count; 94 95 int page_flipping; 96 int current_page; 97 u32 crtc_offset; 98 u32 crtc_offset_cntl; 99 100 u32 color_fmt; 101 unsigned int front_offset; 102 unsigned int front_pitch; 103 unsigned int back_offset; 104 unsigned int back_pitch; 105 106 u32 depth_fmt; 107 unsigned int depth_offset; 108 unsigned int depth_pitch; 109 110 u32 front_pitch_offset; 111 u32 back_pitch_offset; 112 u32 depth_pitch_offset; 113 114 drm_radeon_depth_clear_t depth_clear; 115 116 drm_map_t *sarea; 117 drm_map_t *fb; 118 drm_map_t *mmio; 119 drm_map_t *cp_ring; 120 drm_map_t *ring_rptr; 121 drm_map_t *buffers; 122 drm_map_t *agp_textures; 123} drm_radeon_private_t; 124 125typedef struct drm_radeon_buf_priv { 126 u32 age; 127 int prim; 128 int discard; 129 int dispatched; 130 drm_radeon_freelist_t *list_entry; 131} drm_radeon_buf_priv_t; 132 133 /* radeon_cp.c */ 134extern int radeon_cp_init( DRM_OS_IOCTL ); 135extern int radeon_cp_start( DRM_OS_IOCTL ); 136extern int radeon_cp_stop( DRM_OS_IOCTL ); 137extern int radeon_cp_reset( DRM_OS_IOCTL ); 138extern int radeon_cp_idle( DRM_OS_IOCTL ); 139extern int radeon_engine_reset( DRM_OS_IOCTL ); 140extern int radeon_fullscreen( DRM_OS_IOCTL ); 141extern int radeon_cp_buffers( DRM_OS_IOCTL ); 142 143extern void radeon_freelist_reset( drm_device_t *dev ); 144extern drm_buf_t *radeon_freelist_get( drm_device_t *dev ); 145 146extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ); 147 148static __inline__ void 149radeon_update_ring_snapshot( drm_radeon_ring_buffer_t *ring ) 150{ 151 ring->space = (*(volatile int *)ring->head - ring->tail) * sizeof(u32); 152 if ( ring->space <= 0 ) 153 ring->space += ring->size; 154} 155 156extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ); 157extern int radeon_do_cleanup_cp( drm_device_t *dev ); 158extern int radeon_do_cleanup_pageflip( drm_device_t *dev ); 159 160 /* radeon_state.c */ 161extern int radeon_cp_clear( DRM_OS_IOCTL ); 162extern int radeon_cp_swap( DRM_OS_IOCTL ); 163extern int radeon_cp_vertex( DRM_OS_IOCTL ); 164extern int radeon_cp_indices( DRM_OS_IOCTL ); 165extern int radeon_cp_texture( DRM_OS_IOCTL ); 166extern int radeon_cp_stipple( DRM_OS_IOCTL ); 167extern int radeon_cp_indirect( DRM_OS_IOCTL ); 168 169/* Register definitions, register access macros and drmAddMap constants 170 * for Radeon kernel driver. 171 */ 172 173#define RADEON_AGP_COMMAND 0x0f60 174#define RADEON_AUX_SCISSOR_CNTL 0x26f0 175# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 176# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 177# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 178# define RADEON_SCISSOR_0_ENABLE (1 << 28) 179# define RADEON_SCISSOR_1_ENABLE (1 << 29) 180# define RADEON_SCISSOR_2_ENABLE (1 << 30) 181 182#define RADEON_BUS_CNTL 0x0030 183# define RADEON_BUS_MASTER_DIS (1 << 6) 184 185#define RADEON_CLOCK_CNTL_DATA 0x000c 186# define RADEON_PLL_WR_EN (1 << 7) 187#define RADEON_CLOCK_CNTL_INDEX 0x0008 188#define RADEON_CONFIG_APER_SIZE 0x0108 189#define RADEON_CRTC_OFFSET 0x0224 190#define RADEON_CRTC_OFFSET_CNTL 0x0228 191# define RADEON_CRTC_TILE_EN (1 << 15) 192# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 193 194#define RADEON_RB3D_COLORPITCH 0x1c48 195#define RADEON_RB3D_DEPTHCLEARVALUE 0x1c30 196#define RADEON_RB3D_DEPTHXY_OFFSET 0x1c60 197 198#define RADEON_DP_GUI_MASTER_CNTL 0x146c 199# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 200# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 201# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 202# define RADEON_GMC_BRUSH_NONE (15 << 4) 203# define RADEON_GMC_DST_16BPP (4 << 8) 204# define RADEON_GMC_DST_24BPP (5 << 8) 205# define RADEON_GMC_DST_32BPP (6 << 8) 206# define RADEON_GMC_DST_DATATYPE_SHIFT 8 207# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 208# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 209# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 210# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 211# define RADEON_GMC_WR_MSK_DIS (1 << 30) 212# define RADEON_ROP3_S 0x00cc0000 213# define RADEON_ROP3_P 0x00f00000 214#define RADEON_DP_WRITE_MASK 0x16cc 215#define RADEON_DST_PITCH_OFFSET 0x142c 216#define RADEON_DST_PITCH_OFFSET_C 0x1c80 217# define RADEON_DST_TILE_LINEAR (0 << 30) 218# define RADEON_DST_TILE_MACRO (1 << 30) 219# define RADEON_DST_TILE_MICRO (2 << 30) 220# define RADEON_DST_TILE_BOTH (3 << 30) 221 222#define RADEON_SCRATCH_REG0 0x15e0 223#define RADEON_SCRATCH_REG1 0x15e4 224#define RADEON_SCRATCH_REG2 0x15e8 225#define RADEON_SCRATCH_REG3 0x15ec 226#define RADEON_SCRATCH_REG4 0x15f0 227#define RADEON_SCRATCH_REG5 0x15f4 228#define RADEON_SCRATCH_UMSK 0x0770 229#define RADEON_SCRATCH_ADDR 0x0774 230 231#define RADEON_HOST_PATH_CNTL 0x0130 232# define RADEON_HDP_SOFT_RESET (1 << 26) 233# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 234# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 235 236#define RADEON_ISYNC_CNTL 0x1724 237# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 238# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 239# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 240# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 241# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 242# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 243 244#define RADEON_MC_AGP_LOCATION 0x014c 245#define RADEON_MC_FB_LOCATION 0x0148 246#define RADEON_MCLK_CNTL 0x0012 247# define RADEON_FORCEON_MCLKA (1 << 16) 248# define RADEON_FORCEON_MCLKB (1 << 17) 249# define RADEON_FORCEON_YCLKA (1 << 18) 250# define RADEON_FORCEON_YCLKB (1 << 19) 251# define RADEON_FORCEON_MC (1 << 20) 252# define RADEON_FORCEON_AIC (1 << 21) 253 254#define RADEON_PP_BORDER_COLOR_0 0x1d40 255#define RADEON_PP_BORDER_COLOR_1 0x1d44 256#define RADEON_PP_BORDER_COLOR_2 0x1d48 257#define RADEON_PP_CNTL 0x1c38 258# define RADEON_SCISSOR_ENABLE (1 << 1) 259#define RADEON_PP_LUM_MATRIX 0x1d00 260#define RADEON_PP_MISC 0x1c14 261#define RADEON_PP_ROT_MATRIX_0 0x1d58 262#define RADEON_PP_TXFILTER_0 0x1c54 263#define RADEON_PP_TXFILTER_1 0x1c6c 264#define RADEON_PP_TXFILTER_2 0x1c84 265 266#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 267# define RADEON_RB2D_DC_FLUSH (3 << 0) 268# define RADEON_RB2D_DC_FREE (3 << 2) 269# define RADEON_RB2D_DC_FLUSH_ALL 0xf 270# define RADEON_RB2D_DC_BUSY (1 << 31) 271#define RADEON_RB3D_CNTL 0x1c3c 272# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 273# define RADEON_PLANE_MASK_ENABLE (1 << 1) 274# define RADEON_DITHER_ENABLE (1 << 2) 275# define RADEON_ROUND_ENABLE (1 << 3) 276# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 277# define RADEON_DITHER_INIT (1 << 5) 278# define RADEON_ROP_ENABLE (1 << 6) 279# define RADEON_STENCIL_ENABLE (1 << 7) 280# define RADEON_Z_ENABLE (1 << 8) 281# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) 282# define RADEON_ZBLOCK8 (0 << 15) 283# define RADEON_ZBLOCK16 (1 << 15) 284#define RADEON_RB3D_DEPTHOFFSET 0x1c24 285#define RADEON_RB3D_PLANEMASK 0x1d84 286#define RADEON_RB3D_STENCILREFMASK 0x1d7c 287#define RADEON_RB3D_ZCACHE_MODE 0x3250 288#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 289# define RADEON_RB3D_ZC_FLUSH (1 << 0) 290# define RADEON_RB3D_ZC_FREE (1 << 2) 291# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 292# define RADEON_RB3D_ZC_BUSY (1 << 31) 293#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 294# define RADEON_Z_TEST_MASK (7 << 4) 295# define RADEON_Z_TEST_ALWAYS (7 << 4) 296# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 297# define RADEON_STENCIL_S_FAIL_KEEP (0 << 16) 298# define RADEON_STENCIL_ZPASS_KEEP (0 << 20) 299# define RADEON_STENCIL_ZFAIL_KEEP (0 << 20) 300# define RADEON_Z_WRITE_ENABLE (1 << 30) 301#define RADEON_RBBM_SOFT_RESET 0x00f0 302# define RADEON_SOFT_RESET_CP (1 << 0) 303# define RADEON_SOFT_RESET_HI (1 << 1) 304# define RADEON_SOFT_RESET_SE (1 << 2) 305# define RADEON_SOFT_RESET_RE (1 << 3) 306# define RADEON_SOFT_RESET_PP (1 << 4) 307# define RADEON_SOFT_RESET_E2 (1 << 5) 308# define RADEON_SOFT_RESET_RB (1 << 6) 309# define RADEON_SOFT_RESET_HDP (1 << 7) 310#define RADEON_RBBM_STATUS 0x0e40 311# define RADEON_RBBM_FIFOCNT_MASK 0x007f 312# define RADEON_RBBM_ACTIVE (1 << 31) 313#define RADEON_RE_LINE_PATTERN 0x1cd0 314#define RADEON_RE_MISC 0x26c4 315#define RADEON_RE_TOP_LEFT 0x26c0 316#define RADEON_RE_WIDTH_HEIGHT 0x1c44 317#define RADEON_RE_STIPPLE_ADDR 0x1cc8 318#define RADEON_RE_STIPPLE_DATA 0x1ccc 319 320#define RADEON_SCISSOR_TL_0 0x1cd8 321#define RADEON_SCISSOR_BR_0 0x1cdc 322#define RADEON_SCISSOR_TL_1 0x1ce0 323#define RADEON_SCISSOR_BR_1 0x1ce4 324#define RADEON_SCISSOR_TL_2 0x1ce8 325#define RADEON_SCISSOR_BR_2 0x1cec 326#define RADEON_SE_COORD_FMT 0x1c50 327#define RADEON_SE_CNTL 0x1c4c 328# define RADEON_FFACE_CULL_CW (0 << 0) 329# define RADEON_BFACE_SOLID (3 << 1) 330# define RADEON_FFACE_SOLID (3 << 3) 331# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 332# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 333# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 334# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 335# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 336# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 337# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 338# define RADEON_FOG_SHADE_FLAT (1 << 14) 339# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 340# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 341# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 342# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 343# define RADEON_ROUND_MODE_TRUNC (0 << 28) 344# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 345#define RADEON_SE_CNTL_STATUS 0x2140 346#define RADEON_SE_LINE_WIDTH 0x1db8 347#define RADEON_SE_VPORT_XSCALE 0x1d98 348#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 349#define RADEON_SURFACE_ACCESS_CLR 0x0bfc 350#define RADEON_SURFACE_CNTL 0x0b00 351# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 352# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 353# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 354# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 355# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 356# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 357# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 358# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 359# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 360#define RADEON_SURFACE0_INFO 0x0b0c 361# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 362# define RADEON_SURF_TILE_MODE_MASK (3 << 16) 363# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 364# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 365# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 366# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 367#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 368#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 369#define RADEON_SURFACE1_INFO 0x0b1c 370#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 371#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 372#define RADEON_SURFACE2_INFO 0x0b2c 373#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 374#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 375#define RADEON_SURFACE3_INFO 0x0b3c 376#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 377#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 378#define RADEON_SURFACE4_INFO 0x0b4c 379#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 380#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 381#define RADEON_SURFACE5_INFO 0x0b5c 382#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 383#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 384#define RADEON_SURFACE6_INFO 0x0b6c 385#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 386#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 387#define RADEON_SURFACE7_INFO 0x0b7c 388#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 389#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 390#define RADEON_SW_SEMAPHORE 0x013c 391 392#define RADEON_WAIT_UNTIL 0x1720 393# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 394# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 395# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 396# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 397 398#define RADEON_RB3D_ZMASKOFFSET 0x1c34 399#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 400# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 401# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 402 403 404/* CP registers */ 405#define RADEON_CP_ME_RAM_ADDR 0x07d4 406#define RADEON_CP_ME_RAM_RADDR 0x07d8 407#define RADEON_CP_ME_RAM_DATAH 0x07dc 408#define RADEON_CP_ME_RAM_DATAL 0x07e0 409 410#define RADEON_CP_RB_BASE 0x0700 411#define RADEON_CP_RB_CNTL 0x0704 412#define RADEON_CP_RB_RPTR_ADDR 0x070c 413#define RADEON_CP_RB_RPTR 0x0710 414#define RADEON_CP_RB_WPTR 0x0714 415 416#define RADEON_CP_RB_WPTR_DELAY 0x0718 417# define RADEON_PRE_WRITE_TIMER_SHIFT 0 418# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 419 420#define RADEON_CP_IB_BASE 0x0738 421 422#define RADEON_CP_CSQ_CNTL 0x0740 423# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 424# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 425# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 426# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 427# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 428# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 429# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 430 431#define RADEON_AIC_CNTL 0x01d0 432# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 433#define RADEON_AIC_STAT 0x01d4 434#define RADEON_AIC_PT_BASE 0x01d8 435#define RADEON_AIC_LO_ADDR 0x01dc 436#define RADEON_AIC_HI_ADDR 0x01e0 437#define RADEON_AIC_TLB_ADDR 0x01e4 438#define RADEON_AIC_TLB_DATA 0x01e8 439 440/* CP command packets */ 441#define RADEON_CP_PACKET0 0x00000000 442# define RADEON_ONE_REG_WR (1 << 15) 443#define RADEON_CP_PACKET1 0x40000000 444#define RADEON_CP_PACKET2 0x80000000 445#define RADEON_CP_PACKET3 0xC0000000 446# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 447# define RADEON_WAIT_FOR_IDLE 0x00002600 448# define RADEON_3D_DRAW_IMMD 0x00002900 449# define RADEON_3D_CLEAR_ZMASK 0x00003200 450# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 451# define RADEON_CNTL_PAINT_MULTI 0x00009A00 452# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 453 454#define RADEON_CP_PACKET_MASK 0xC0000000 455#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 456#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 457#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 458#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 459 460#define RADEON_VTX_Z_PRESENT (1 << 31) 461 462#define RADEON_PRIM_TYPE_NONE (0 << 0) 463#define RADEON_PRIM_TYPE_POINT (1 << 0) 464#define RADEON_PRIM_TYPE_LINE (2 << 0) 465#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 466#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 467#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 468#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 469#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 470#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 471#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 472#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 473#define RADEON_PRIM_WALK_IND (1 << 4) 474#define RADEON_PRIM_WALK_LIST (2 << 4) 475#define RADEON_PRIM_WALK_RING (3 << 4) 476#define RADEON_COLOR_ORDER_BGRA (0 << 6) 477#define RADEON_COLOR_ORDER_RGBA (1 << 6) 478#define RADEON_MAOS_ENABLE (1 << 7) 479#define RADEON_VTX_FMT_R128_MODE (0 << 8) 480#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 481#define RADEON_NUM_VERTICES_SHIFT 16 482 483#define RADEON_COLOR_FORMAT_CI8 2 484#define RADEON_COLOR_FORMAT_ARGB1555 3 485#define RADEON_COLOR_FORMAT_RGB565 4 486#define RADEON_COLOR_FORMAT_ARGB8888 6 487#define RADEON_COLOR_FORMAT_RGB332 7 488#define RADEON_COLOR_FORMAT_RGB8 9 489#define RADEON_COLOR_FORMAT_ARGB4444 15 490 491#define RADEON_TXFORMAT_I8 0 492#define RADEON_TXFORMAT_AI88 1 493#define RADEON_TXFORMAT_RGB332 2 494#define RADEON_TXFORMAT_ARGB1555 3 495#define RADEON_TXFORMAT_RGB565 4 496#define RADEON_TXFORMAT_ARGB4444 5 497#define RADEON_TXFORMAT_ARGB8888 6 498#define RADEON_TXFORMAT_RGBA8888 7 499 500/* Constants */ 501#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 502 503#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 504#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 505#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 506#define RADEON_LAST_DISPATCH 1 507 508#define RADEON_MAX_VB_AGE 0x7fffffff 509#define RADEON_MAX_VB_VERTS (0xffff) 510 511#define RADEON_RING_HIGH_MARK 128 512 513 514#define RADEON_BASE(reg) ((unsigned long)(dev_priv->mmio->handle)) 515#define RADEON_ADDR(reg) (RADEON_BASE( reg ) + reg) 516 517#define RADEON_DEREF(reg) *(volatile u32 *)RADEON_ADDR( reg ) 518#ifdef __alpha__ 519#define RADEON_READ(reg) (_RADEON_READ((u32 *)RADEON_ADDR( reg ))) 520static inline u32 _RADEON_READ(u32 *addr) 521{ 522 DRM_OS_READMEMORYBARRIER; 523 return *(volatile u32 *)addr; 524} 525#define RADEON_WRITE(reg,val) \ 526do { \ 527 DRM_OS_WRITEMEMORYBARRIER; \ 528 RADEON_DEREF(reg) = val; \ 529} while (0) 530#else 531#define RADEON_READ(reg) RADEON_DEREF( reg ) 532#define RADEON_WRITE(reg, val) do { RADEON_DEREF( reg ) = val; } while (0) 533#endif 534 535#define RADEON_DEREF8(reg) *(volatile u8 *)RADEON_ADDR( reg ) 536#ifdef __alpha__ 537#define RADEON_READ8(reg) _RADEON_READ8((u8 *)RADEON_ADDR( reg )) 538static inline u8 _RADEON_READ8(u8 *addr) 539{ 540 DRM_OS_READMEMORYBARRIER; 541 return *(volatile u8 *)addr; 542} 543#define RADEON_WRITE8(reg,val) \ 544do { \ 545 DRM_OS_WRITEMEMORYBARRIER; \ 546 RADEON_DEREF8( reg ) = val; \ 547} while (0) 548#else 549#define RADEON_READ8(reg) RADEON_DEREF8( reg ) 550#define RADEON_WRITE8(reg, val) do { RADEON_DEREF8( reg ) = val; } while (0) 551#endif 552 553#define RADEON_WRITE_PLL( addr, val ) \ 554do { \ 555 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 556 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 557 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 558} while (0) 559 560extern int RADEON_READ_PLL( drm_device_t *dev, int addr ); 561 562 563#define CP_PACKET0( reg, n ) \ 564 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 565#define CP_PACKET0_TABLE( reg, n ) \ 566 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 567#define CP_PACKET1( reg0, reg1 ) \ 568 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 569#define CP_PACKET2() \ 570 (RADEON_CP_PACKET2) 571#define CP_PACKET3( pkt, n ) \ 572 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 573 574 575/* ================================================================ 576 * Engine control helper macros 577 */ 578 579#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 580 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 581 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 582 RADEON_WAIT_HOST_IDLECLEAN) ); \ 583} while (0) 584 585#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 586 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 587 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 588 RADEON_WAIT_HOST_IDLECLEAN) ); \ 589} while (0) 590 591#define RADEON_WAIT_UNTIL_IDLE() do { \ 592 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 593 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 594 RADEON_WAIT_3D_IDLECLEAN | \ 595 RADEON_WAIT_HOST_IDLECLEAN) ); \ 596} while (0) 597 598#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 599 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 600 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 601} while (0) 602 603#define RADEON_FLUSH_CACHE() do { \ 604 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ 605 OUT_RING( RADEON_RB2D_DC_FLUSH ); \ 606} while (0) 607 608#define RADEON_PURGE_CACHE() do { \ 609 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ 610 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \ 611} while (0) 612 613#define RADEON_FLUSH_ZCACHE() do { \ 614 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 615 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 616} while (0) 617 618#define RADEON_PURGE_ZCACHE() do { \ 619 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 620 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ 621} while (0) 622 623 624/* ================================================================ 625 * Misc helper macros 626 */ 627 628#define LOCK_TEST_WITH_RETURN( dev ) \ 629do { \ 630 if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \ 631 dev->lock.pid != DRM_OS_CURRENTPID ) { \ 632 DRM_ERROR( "%s called without lock held\n", \ 633 __FUNCTION__ ); \ 634 return DRM_OS_ERR(EINVAL); \ 635 } \ 636} while (0) 637 638#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 639do { \ 640 drm_radeon_ring_buffer_t *ring = &dev_priv->ring; int i; \ 641 if ( ring->space < ring->high_mark ) { \ 642 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \ 643 radeon_update_ring_snapshot( ring ); \ 644 if ( ring->space >= ring->high_mark ) \ 645 goto __ring_space_done; \ 646 DRM_OS_DELAY( 1 ); \ 647 } \ 648 DRM_ERROR( "ring space check failed!\n" ); \ 649 return DRM_OS_ERR(EBUSY); \ 650 } \ 651 __ring_space_done: \ 652} while (0) 653 654#ifdef __linux__ 655#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 656do { \ 657 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 658 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 659 int __ret = radeon_do_cp_idle( dev_priv ); \ 660 if ( __ret < 0 ) return __ret; \ 661 sarea_priv->last_dispatch = 0; \ 662 radeon_freelist_reset( dev ); \ 663 } \ 664} while (0) 665#endif /* __linux__ */ 666#ifdef __FreeBSD__ 667#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 668do { \ 669 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 670 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 671 int __ret = radeon_do_cp_idle( dev_priv ); \ 672 if ( __ret ) return __ret; \ 673 sarea_priv->last_dispatch = 0; \ 674 radeon_freelist_reset( dev ); \ 675 } \ 676} while (0) 677#endif /* __FreeBSD__ */ 678 679#define RADEON_DISPATCH_AGE( age ) do { \ 680 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 681 OUT_RING( age ); \ 682} while (0) 683 684#define RADEON_FRAME_AGE( age ) do { \ 685 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 686 OUT_RING( age ); \ 687} while (0) 688 689#define RADEON_CLEAR_AGE( age ) do { \ 690 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 691 OUT_RING( age ); \ 692} while (0) 693 694 695/* ================================================================ 696 * Ring control 697 */ 698 699#define radeon_flush_write_combine() DRM_OS_READMEMORYBARRIER 700 701 702#define RADEON_VERBOSE 0 703 704#define RING_LOCALS int write; unsigned int mask; volatile u32 *ring; 705 706#define BEGIN_RING( n ) do { \ 707 if ( RADEON_VERBOSE ) { \ 708 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ 709 n, __FUNCTION__ ); \ 710 } \ 711 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 712 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 713 } \ 714 dev_priv->ring.space -= (n) * sizeof(u32); \ 715 ring = dev_priv->ring.start; \ 716 write = dev_priv->ring.tail; \ 717 mask = dev_priv->ring.tail_mask; \ 718} while (0) 719 720#define ADVANCE_RING() do { \ 721 if ( RADEON_VERBOSE ) { \ 722 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 723 write, dev_priv->ring.tail ); \ 724 } \ 725 radeon_flush_write_combine(); \ 726 dev_priv->ring.tail = write; \ 727 RADEON_WRITE( RADEON_CP_RB_WPTR, write ); \ 728} while (0) 729 730#define OUT_RING( x ) do { \ 731 if ( RADEON_VERBOSE ) { \ 732 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 733 (unsigned int)(x), write ); \ 734 } \ 735 ring[write++] = (x); \ 736 write &= mask; \ 737} while (0) 738 739#define RADEON_PERFORMANCE_BOXES 0 740 741#endif /* __RADEON_DRV_H__ */ 742