radeon_drv.h revision 195501
1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drv.h 195501 2009-07-09 16:39:28Z rnoland $"); 33 34#ifndef __RADEON_DRV_H__ 35#define __RADEON_DRV_H__ 36 37/* General customization: 38 */ 39 40#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 41 42#define DRIVER_NAME "radeon" 43#define DRIVER_DESC "ATI Radeon" 44#define DRIVER_DATE "20080528" 45 46/* Interface history: 47 * 48 * 1.1 - ?? 49 * 1.2 - Add vertex2 ioctl (keith) 50 * - Add stencil capability to clear ioctl (gareth, keith) 51 * - Increase MAX_TEXTURE_LEVELS (brian) 52 * 1.3 - Add cmdbuf ioctl (keith) 53 * - Add support for new radeon packets (keith) 54 * - Add getparam ioctl (keith) 55 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 56 * 1.4 - Add scratch registers to get_param ioctl. 57 * 1.5 - Add r200 packets to cmdbuf ioctl 58 * - Add r200 function to init ioctl 59 * - Add 'scalar2' instruction to cmdbuf 60 * 1.6 - Add static GART memory manager 61 * Add irq handler (won't be turned on unless X server knows to) 62 * Add irq ioctls and irq_active getparam. 63 * Add wait command for cmdbuf ioctl 64 * Add GART offset query for getparam 65 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 66 * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 67 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 68 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 69 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 70 * Add 'GET' queries for starting additional clients on different VT's. 71 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 72 * Add texture rectangle support for r100. 73 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 74 * clients use to tell the DRM where they think the framebuffer is 75 * located in the card's address space 76 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 77 * and GL_EXT_blend_[func|equation]_separate on r200 78 * 1.12- Add R300 CP microcode support - this just loads the CP on r300 79 * (No 3D support yet - just microcode loading). 80 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 81 * - Add hyperz support, add hyperz flags to clear ioctl. 82 * 1.14- Add support for color tiling 83 * - Add R100/R200 surface allocation/free support 84 * 1.15- Add support for texture micro tiling 85 * - Add support for r100 cube maps 86 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 87 * texture filtering on r200 88 * 1.17- Add initial support for R300 (3D). 89 * 1.18- Add support for GL_ATI_fragment_shader, new packets 90 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 91 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 92 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 93 * 1.19- Add support for gart table in FB memory and PCIE r300 94 * 1.20- Add support for r300 texrect 95 * 1.21- Add support for card type getparam 96 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 97 * 1.23- Add new radeon memory map work from benh 98 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 99 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, 100 * new packet type) 101 * 1.26- Add support for variable size PCI(E) gart aperture 102 * 1.27- Add support for IGP GART 103 * 1.28- Add support for VBL on CRTC2 104 * 1.29- R500 3D cmd buffer support 105 */ 106#define DRIVER_MAJOR 1 107#define DRIVER_MINOR 29 108#define DRIVER_PATCHLEVEL 0 109 110/* 111 * Radeon chip families 112 */ 113enum radeon_family { 114 CHIP_R100, 115 CHIP_RV100, 116 CHIP_RS100, 117 CHIP_RV200, 118 CHIP_RS200, 119 CHIP_R200, 120 CHIP_RV250, 121 CHIP_RS300, 122 CHIP_RV280, 123 CHIP_R300, 124 CHIP_R350, 125 CHIP_RV350, 126 CHIP_RV380, 127 CHIP_R420, 128 CHIP_R423, 129 CHIP_RV410, 130 CHIP_RS400, 131 CHIP_RS480, 132 CHIP_RS600, 133 CHIP_RS690, 134 CHIP_RS740, 135 CHIP_RV515, 136 CHIP_R520, 137 CHIP_RV530, 138 CHIP_RV560, 139 CHIP_RV570, 140 CHIP_R580, 141 CHIP_R600, 142 CHIP_RV610, 143 CHIP_RV630, 144 CHIP_RV620, 145 CHIP_RV635, 146 CHIP_RV670, 147 CHIP_RS780, 148 CHIP_RV770, 149 CHIP_RV740, 150 CHIP_RV730, 151 CHIP_RV710, 152 CHIP_LAST, 153}; 154 155enum radeon_cp_microcode_version { 156 UCODE_R100, 157 UCODE_R200, 158 UCODE_R300, 159}; 160 161/* 162 * Chip flags 163 */ 164enum radeon_chip_flags { 165 RADEON_FAMILY_MASK = 0x0000ffffUL, 166 RADEON_FLAGS_MASK = 0xffff0000UL, 167 RADEON_IS_MOBILITY = 0x00010000UL, 168 RADEON_IS_IGP = 0x00020000UL, 169 RADEON_SINGLE_CRTC = 0x00040000UL, 170 RADEON_IS_AGP = 0x00080000UL, 171 RADEON_HAS_HIERZ = 0x00100000UL, 172 RADEON_IS_PCIE = 0x00200000UL, 173 RADEON_NEW_MEMMAP = 0x00400000UL, 174 RADEON_IS_PCI = 0x00800000UL, 175 RADEON_IS_IGPGART = 0x01000000UL, 176}; 177 178typedef struct drm_radeon_freelist { 179 unsigned int age; 180 struct drm_buf *buf; 181 struct drm_radeon_freelist *next; 182 struct drm_radeon_freelist *prev; 183} drm_radeon_freelist_t; 184 185typedef struct drm_radeon_ring_buffer { 186 u32 *start; 187 u32 *end; 188 int size; 189 int size_l2qw; 190 191 int rptr_update; /* Double Words */ 192 int rptr_update_l2qw; /* log2 Quad Words */ 193 194 int fetch_size; /* Double Words */ 195 int fetch_size_l2ow; /* log2 Oct Words */ 196 197 u32 tail; 198 u32 tail_mask; 199 int space; 200 201 int high_mark; 202} drm_radeon_ring_buffer_t; 203 204typedef struct drm_radeon_depth_clear_t { 205 u32 rb3d_cntl; 206 u32 rb3d_zstencilcntl; 207 u32 se_cntl; 208} drm_radeon_depth_clear_t; 209 210struct drm_radeon_driver_file_fields { 211 int64_t radeon_fb_delta; 212}; 213 214struct mem_block { 215 struct mem_block *next; 216 struct mem_block *prev; 217 int start; 218 int size; 219 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 220}; 221 222struct radeon_surface { 223 int refcount; 224 u32 lower; 225 u32 upper; 226 u32 flags; 227}; 228 229struct radeon_virt_surface { 230 int surface_index; 231 u32 lower; 232 u32 upper; 233 u32 flags; 234 struct drm_file *file_priv; 235#define PCIGART_FILE_PRIV ((void *) -1L) 236}; 237 238#define RADEON_FLUSH_EMITED (1 << 0) 239#define RADEON_PURGE_EMITED (1 << 1) 240 241typedef struct drm_radeon_private { 242 drm_radeon_ring_buffer_t ring; 243 drm_radeon_sarea_t *sarea_priv; 244 245 u32 fb_location; 246 u32 fb_size; 247 int new_memmap; 248 249 int gart_size; 250 u32 gart_vm_start; 251 unsigned long gart_buffers_offset; 252 253 int cp_mode; 254 int cp_running; 255 256 drm_radeon_freelist_t *head; 257 drm_radeon_freelist_t *tail; 258 int last_buf; 259 int writeback_works; 260 261 int usec_timeout; 262 263 int microcode_version; 264 265 struct { 266 u32 boxes; 267 int freelist_timeouts; 268 int freelist_loops; 269 int requested_bufs; 270 int last_frame_reads; 271 int last_clear_reads; 272 int clears; 273 int texture_uploads; 274 } stats; 275 276 int do_boxes; 277 int page_flipping; 278 279 u32 color_fmt; 280 unsigned int front_offset; 281 unsigned int front_pitch; 282 unsigned int back_offset; 283 unsigned int back_pitch; 284 285 u32 depth_fmt; 286 unsigned int depth_offset; 287 unsigned int depth_pitch; 288 289 u32 front_pitch_offset; 290 u32 back_pitch_offset; 291 u32 depth_pitch_offset; 292 293 drm_radeon_depth_clear_t depth_clear; 294 295 unsigned long ring_offset; 296 unsigned long ring_rptr_offset; 297 unsigned long buffers_offset; 298 unsigned long gart_textures_offset; 299 300 drm_local_map_t *sarea; 301 drm_local_map_t *cp_ring; 302 drm_local_map_t *ring_rptr; 303 drm_local_map_t *gart_textures; 304 305 struct mem_block *gart_heap; 306 struct mem_block *fb_heap; 307 308 /* SW interrupt */ 309 wait_queue_head_t swi_queue; 310 atomic_t swi_emitted; 311 int vblank_crtc; 312 uint32_t irq_enable_reg; 313 int irq_enabled; 314 uint32_t r500_disp_irq_reg; 315 316 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 317 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 318 319 unsigned long pcigart_offset; 320 unsigned int pcigart_offset_set; 321 struct drm_ati_pcigart_info gart_info; 322 323 u32 scratch_ages[5]; 324 325 /* starting from here on, data is preserved accross an open */ 326 uint32_t flags; /* see radeon_chip_flags */ 327 unsigned long fb_aper_offset; 328 329 int num_gb_pipes; 330 int track_flush; 331 drm_local_map_t *mmio; 332 333 /* r6xx/r7xx pipe/shader config */ 334 int r600_max_pipes; 335 int r600_max_tile_pipes; 336 int r600_max_simds; 337 int r600_max_backends; 338 int r600_max_gprs; 339 int r600_max_threads; 340 int r600_max_stack_entries; 341 int r600_max_hw_contexts; 342 int r600_max_gs_threads; 343 int r600_sx_max_export_size; 344 int r600_sx_max_export_pos_size; 345 int r600_sx_max_export_smx_size; 346 int r600_sq_num_cf_insts; 347 int r700_sx_num_of_sets; 348 int r700_sc_prim_fifo_size; 349 int r700_sc_hiz_tile_fifo_size; 350 int r700_sc_earlyz_tile_fifo_fize; 351 352} drm_radeon_private_t; 353 354typedef struct drm_radeon_buf_priv { 355 u32 age; 356} drm_radeon_buf_priv_t; 357 358typedef struct drm_radeon_kcmd_buffer { 359 int bufsz; 360 char *buf; 361 int nbox; 362 struct drm_clip_rect __user *boxes; 363} drm_radeon_kcmd_buffer_t; 364 365extern int radeon_no_wb; 366extern struct drm_ioctl_desc radeon_ioctls[]; 367extern int radeon_max_ioctl; 368 369extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv); 370extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val); 371 372#define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv) 373#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val) 374 375/* Check whether the given hardware address is inside the framebuffer or the 376 * GART area. 377 */ 378static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, 379 u64 off) 380{ 381 u32 fb_start = dev_priv->fb_location; 382 u32 fb_end = fb_start + dev_priv->fb_size - 1; 383 u32 gart_start = dev_priv->gart_vm_start; 384 u32 gart_end = gart_start + dev_priv->gart_size - 1; 385 386 return ((off >= fb_start && off <= fb_end) || 387 (off >= gart_start && off <= gart_end)); 388} 389 390 /* radeon_cp.c */ 391extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 392extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 393extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 394extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 395extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 396extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); 397extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 398extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 399extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 400extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); 401extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc); 402extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base); 403extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr); 404 405extern void radeon_freelist_reset(struct drm_device * dev); 406extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); 407 408extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 409 410extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 411 412extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags); 413extern int radeon_presetup(struct drm_device *dev); 414extern int radeon_driver_postcleanup(struct drm_device *dev); 415 416extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); 417extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); 418extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); 419extern void radeon_mem_takedown(struct mem_block **heap); 420extern void radeon_mem_release(struct drm_file *file_priv, 421 struct mem_block *heap); 422 423extern void radeon_enable_bm(struct drm_radeon_private *dev_priv); 424extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off); 425extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val); 426 427 /* radeon_irq.c */ 428extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); 429extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); 430extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); 431 432extern void radeon_do_release(struct drm_device * dev); 433extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); 434extern int radeon_enable_vblank(struct drm_device *dev, int crtc); 435extern void radeon_disable_vblank(struct drm_device *dev, int crtc); 436extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 437extern void radeon_driver_irq_preinstall(struct drm_device * dev); 438extern int radeon_driver_irq_postinstall(struct drm_device *dev); 439extern void radeon_driver_irq_uninstall(struct drm_device * dev); 440extern void radeon_enable_interrupt(struct drm_device *dev); 441extern int radeon_vblank_crtc_get(struct drm_device *dev); 442extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 443 444extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 445extern int radeon_driver_unload(struct drm_device *dev); 446extern int radeon_driver_firstopen(struct drm_device *dev); 447extern void radeon_driver_preclose(struct drm_device *dev, 448 struct drm_file *file_priv); 449extern void radeon_driver_postclose(struct drm_device *dev, 450 struct drm_file *file_priv); 451extern void radeon_driver_lastclose(struct drm_device * dev); 452extern int radeon_driver_open(struct drm_device *dev, 453 struct drm_file *file_priv); 454extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 455 unsigned long arg); 456 457/* r300_cmdbuf.c */ 458extern void r300_init_reg_flags(struct drm_device *dev); 459 460extern int r300_do_cp_cmdbuf(struct drm_device *dev, 461 struct drm_file *file_priv, 462 drm_radeon_kcmd_buffer_t *cmdbuf); 463 464/* r600_cp.c */ 465extern int r600_do_engine_reset(struct drm_device *dev); 466extern int r600_do_cleanup_cp(struct drm_device *dev); 467extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 468 struct drm_file *file_priv); 469extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv); 470extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv); 471extern void r600_do_cp_start(drm_radeon_private_t *dev_priv); 472extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv); 473extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv); 474extern int r600_cp_dispatch_indirect(struct drm_device *dev, 475 struct drm_buf *buf, int start, int end); 476extern int r600_page_table_init(struct drm_device *dev); 477extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); 478 479/* Flags for stats.boxes 480 */ 481#define RADEON_BOX_DMA_IDLE 0x1 482#define RADEON_BOX_RING_FULL 0x2 483#define RADEON_BOX_FLIP 0x4 484#define RADEON_BOX_WAIT_IDLE 0x8 485#define RADEON_BOX_TEXTURE_LOAD 0x10 486 487/* Register definitions, register access macros and drmAddMap constants 488 * for Radeon kernel driver. 489 */ 490#define RADEON_MM_INDEX 0x0000 491#define RADEON_MM_DATA 0x0004 492 493#define RADEON_AGP_COMMAND 0x0f60 494#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 495# define RADEON_AGP_ENABLE (1<<8) 496#define RADEON_AUX_SCISSOR_CNTL 0x26f0 497# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 498# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 499# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 500# define RADEON_SCISSOR_0_ENABLE (1 << 28) 501# define RADEON_SCISSOR_1_ENABLE (1 << 29) 502# define RADEON_SCISSOR_2_ENABLE (1 << 30) 503 504/* 505 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx) 506 * don't have an explicit bus mastering disable bit. It's handled 507 * by the PCI D-states. PMI_BM_DIS disables D-state bus master 508 * handling, not bus mastering itself. 509 */ 510#define RADEON_BUS_CNTL 0x0030 511/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 512# define RADEON_BUS_MASTER_DIS (1 << 6) 513/* rs600/rs690/rs740 */ 514# define RS600_BUS_MASTER_DIS (1 << 14) 515# define RS600_MSI_REARM (1 << 20) 516/* see RS400_MSI_REARM in AIC_CNTL for rs480 */ 517 518#define RADEON_BUS_CNTL1 0x0034 519# define RADEON_PMI_BM_DIS (1 << 2) 520# define RADEON_PMI_INT_DIS (1 << 3) 521 522#define RV370_BUS_CNTL 0x004c 523# define RV370_PMI_BM_DIS (1 << 5) 524# define RV370_PMI_INT_DIS (1 << 6) 525 526#define RADEON_MSI_REARM_EN 0x0160 527/* rv370/rv380, rv410, r423/r430/r480, r5xx */ 528# define RV370_MSI_REARM_EN (1 << 0) 529 530#define RADEON_CLOCK_CNTL_DATA 0x000c 531# define RADEON_PLL_WR_EN (1 << 7) 532#define RADEON_CLOCK_CNTL_INDEX 0x0008 533#define RADEON_CONFIG_APER_SIZE 0x0108 534#define RADEON_CONFIG_MEMSIZE 0x00f8 535#define RADEON_CRTC_OFFSET 0x0224 536#define RADEON_CRTC_OFFSET_CNTL 0x0228 537# define RADEON_CRTC_TILE_EN (1 << 15) 538# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 539#define RADEON_CRTC2_OFFSET 0x0324 540#define RADEON_CRTC2_OFFSET_CNTL 0x0328 541 542#define RADEON_PCIE_INDEX 0x0030 543#define RADEON_PCIE_DATA 0x0034 544#define RADEON_PCIE_TX_GART_CNTL 0x10 545# define RADEON_PCIE_TX_GART_EN (1 << 0) 546# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) 547# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) 548# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) 549# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) 550# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) 551# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) 552# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) 553#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 554#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 555#define RADEON_PCIE_TX_GART_BASE 0x13 556#define RADEON_PCIE_TX_GART_START_LO 0x14 557#define RADEON_PCIE_TX_GART_START_HI 0x15 558#define RADEON_PCIE_TX_GART_END_LO 0x16 559#define RADEON_PCIE_TX_GART_END_HI 0x17 560 561#define RS480_NB_MC_INDEX 0x168 562# define RS480_NB_MC_IND_WR_EN (1 << 8) 563#define RS480_NB_MC_DATA 0x16c 564 565#define RS690_MC_INDEX 0x78 566# define RS690_MC_INDEX_MASK 0x1ff 567# define RS690_MC_INDEX_WR_EN (1 << 9) 568# define RS690_MC_INDEX_WR_ACK 0x7f 569#define RS690_MC_DATA 0x7c 570 571/* MC indirect registers */ 572#define RS480_MC_MISC_CNTL 0x18 573# define RS480_DISABLE_GTW (1 << 1) 574/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ 575# define RS480_GART_INDEX_REG_EN (1 << 12) 576# define RS690_BLOCK_GFX_D3_EN (1 << 14) 577#define RS480_K8_FB_LOCATION 0x1e 578#define RS480_GART_FEATURE_ID 0x2b 579# define RS480_HANG_EN (1 << 11) 580# define RS480_TLB_ENABLE (1 << 18) 581# define RS480_P2P_ENABLE (1 << 19) 582# define RS480_GTW_LAC_EN (1 << 25) 583# define RS480_2LEVEL_GART (0 << 30) 584# define RS480_1LEVEL_GART (1 << 30) 585# define RS480_PDC_EN (1 << 31) 586#define RS480_GART_BASE 0x2c 587#define RS480_GART_CACHE_CNTRL 0x2e 588# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 589#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 590# define RS480_GART_EN (1 << 0) 591# define RS480_VA_SIZE_32MB (0 << 1) 592# define RS480_VA_SIZE_64MB (1 << 1) 593# define RS480_VA_SIZE_128MB (2 << 1) 594# define RS480_VA_SIZE_256MB (3 << 1) 595# define RS480_VA_SIZE_512MB (4 << 1) 596# define RS480_VA_SIZE_1GB (5 << 1) 597# define RS480_VA_SIZE_2GB (6 << 1) 598#define RS480_AGP_MODE_CNTL 0x39 599# define RS480_POST_GART_Q_SIZE (1 << 18) 600# define RS480_NONGART_SNOOP (1 << 19) 601# define RS480_AGP_RD_BUF_SIZE (1 << 20) 602# define RS480_REQ_TYPE_SNOOP_SHIFT 22 603# define RS480_REQ_TYPE_SNOOP_MASK 0x3 604# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 605#define RS480_MC_MISC_UMA_CNTL 0x5f 606#define RS480_MC_MCLK_CNTL 0x7a 607#define RS480_MC_UMA_DUALCH_CNTL 0x86 608 609#define RS690_MC_FB_LOCATION 0x100 610#define RS690_MC_AGP_LOCATION 0x101 611#define RS690_MC_AGP_BASE 0x102 612#define RS690_MC_AGP_BASE_2 0x103 613 614#define RS600_MC_INDEX 0x70 615# define RS600_MC_ADDR_MASK 0xffff 616# define RS600_MC_IND_SEQ_RBS_0 (1 << 16) 617# define RS600_MC_IND_SEQ_RBS_1 (1 << 17) 618# define RS600_MC_IND_SEQ_RBS_2 (1 << 18) 619# define RS600_MC_IND_SEQ_RBS_3 (1 << 19) 620# define RS600_MC_IND_AIC_RBS (1 << 20) 621# define RS600_MC_IND_CITF_ARB0 (1 << 21) 622# define RS600_MC_IND_CITF_ARB1 (1 << 22) 623# define RS600_MC_IND_WR_EN (1 << 23) 624#define RS600_MC_DATA 0x74 625 626#define RS600_MC_STATUS 0x0 627# define RS600_MC_IDLE (1 << 1) 628#define RS600_MC_FB_LOCATION 0x4 629#define RS600_MC_AGP_LOCATION 0x5 630#define RS600_AGP_BASE 0x6 631#define RS600_AGP_BASE_2 0x7 632#define RS600_MC_CNTL1 0x9 633# define RS600_ENABLE_PAGE_TABLES (1 << 26) 634#define RS600_MC_PT0_CNTL 0x100 635# define RS600_ENABLE_PT (1 << 0) 636# define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) 637# define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) 638# define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) 639# define RS600_INVALIDATE_L2_CACHE (1 << 29) 640#define RS600_MC_PT0_CONTEXT0_CNTL 0x102 641# define RS600_ENABLE_PAGE_TABLE (1 << 0) 642# define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) 643#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 644#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 645#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c 646#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c 647#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c 648#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c 649#define RS600_MC_PT0_CLIENT0_CNTL 0x16c 650# define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) 651# define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) 652# define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) 653# define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) 654# define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) 655# define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) 656# define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) 657# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) 658# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) 659# define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) 660# define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) 661# define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 662# define RS600_INVALIDATE_L1_TLB (1 << 20) 663 664#define R520_MC_IND_INDEX 0x70 665#define R520_MC_IND_WR_EN (1 << 24) 666#define R520_MC_IND_DATA 0x74 667 668#define RV515_MC_FB_LOCATION 0x01 669#define RV515_MC_AGP_LOCATION 0x02 670#define RV515_MC_AGP_BASE 0x03 671#define RV515_MC_AGP_BASE_2 0x04 672 673#define R520_MC_FB_LOCATION 0x04 674#define R520_MC_AGP_LOCATION 0x05 675#define R520_MC_AGP_BASE 0x06 676#define R520_MC_AGP_BASE_2 0x07 677 678#define RADEON_MPP_TB_CONFIG 0x01c0 679#define RADEON_MEM_CNTL 0x0140 680#define RADEON_MEM_SDRAM_MODE_REG 0x0158 681#define RADEON_AGP_BASE_2 0x015c /* r200+ only */ 682#define RS480_AGP_BASE_2 0x0164 683#define RADEON_AGP_BASE 0x0170 684 685/* pipe config regs */ 686#define R400_GB_PIPE_SELECT 0x402c 687#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 688#define R300_GB_TILE_CONFIG 0x4018 689# define R300_ENABLE_TILING (1 << 0) 690# define R300_PIPE_COUNT_RV350 (0 << 1) 691# define R300_PIPE_COUNT_R300 (3 << 1) 692# define R300_PIPE_COUNT_R420_3P (6 << 1) 693# define R300_PIPE_COUNT_R420 (7 << 1) 694# define R300_TILE_SIZE_8 (0 << 4) 695# define R300_TILE_SIZE_16 (1 << 4) 696# define R300_TILE_SIZE_32 (2 << 4) 697# define R300_SUBPIXEL_1_12 (0 << 16) 698# define R300_SUBPIXEL_1_16 (1 << 16) 699#define R300_DST_PIPE_CONFIG 0x170c 700# define R300_PIPE_AUTO_CONFIG (1 << 31) 701#define R300_RB2D_DSTCACHE_MODE 0x3428 702# define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 703# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 704 705#define RADEON_RB3D_COLOROFFSET 0x1c40 706#define RADEON_RB3D_COLORPITCH 0x1c48 707 708#define RADEON_SRC_X_Y 0x1590 709 710#define RADEON_DP_GUI_MASTER_CNTL 0x146c 711# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 712# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 713# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 714# define RADEON_GMC_BRUSH_NONE (15 << 4) 715# define RADEON_GMC_DST_16BPP (4 << 8) 716# define RADEON_GMC_DST_24BPP (5 << 8) 717# define RADEON_GMC_DST_32BPP (6 << 8) 718# define RADEON_GMC_DST_DATATYPE_SHIFT 8 719# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 720# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 721# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 722# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 723# define RADEON_GMC_WR_MSK_DIS (1 << 30) 724# define RADEON_ROP3_S 0x00cc0000 725# define RADEON_ROP3_P 0x00f00000 726#define RADEON_DP_WRITE_MASK 0x16cc 727#define RADEON_SRC_PITCH_OFFSET 0x1428 728#define RADEON_DST_PITCH_OFFSET 0x142c 729#define RADEON_DST_PITCH_OFFSET_C 0x1c80 730# define RADEON_DST_TILE_LINEAR (0 << 30) 731# define RADEON_DST_TILE_MACRO (1 << 30) 732# define RADEON_DST_TILE_MICRO (2 << 30) 733# define RADEON_DST_TILE_BOTH (3 << 30) 734 735#define RADEON_SCRATCH_REG0 0x15e0 736#define RADEON_SCRATCH_REG1 0x15e4 737#define RADEON_SCRATCH_REG2 0x15e8 738#define RADEON_SCRATCH_REG3 0x15ec 739#define RADEON_SCRATCH_REG4 0x15f0 740#define RADEON_SCRATCH_REG5 0x15f4 741#define RADEON_SCRATCH_UMSK 0x0770 742#define RADEON_SCRATCH_ADDR 0x0774 743 744#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 745 746extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); 747 748#define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x) 749 750#define R600_SCRATCH_REG0 0x8500 751#define R600_SCRATCH_REG1 0x8504 752#define R600_SCRATCH_REG2 0x8508 753#define R600_SCRATCH_REG3 0x850c 754#define R600_SCRATCH_REG4 0x8510 755#define R600_SCRATCH_REG5 0x8514 756#define R600_SCRATCH_REG6 0x8518 757#define R600_SCRATCH_REG7 0x851c 758#define R600_SCRATCH_UMSK 0x8540 759#define R600_SCRATCH_ADDR 0x8544 760 761#define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x)) 762 763#define RADEON_GEN_INT_CNTL 0x0040 764# define RADEON_CRTC_VBLANK_MASK (1 << 0) 765# define RADEON_CRTC2_VBLANK_MASK (1 << 9) 766# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 767# define RADEON_SW_INT_ENABLE (1 << 25) 768 769#define RADEON_GEN_INT_STATUS 0x0044 770# define RADEON_CRTC_VBLANK_STAT (1 << 0) 771# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 772# define RADEON_CRTC2_VBLANK_STAT (1 << 9) 773# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 774# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 775# define RADEON_SW_INT_TEST (1 << 25) 776# define RADEON_SW_INT_TEST_ACK (1 << 25) 777# define RADEON_SW_INT_FIRE (1 << 26) 778# define R500_DISPLAY_INT_STATUS (1 << 0) 779 780#define RADEON_HOST_PATH_CNTL 0x0130 781# define RADEON_HDP_SOFT_RESET (1 << 26) 782# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 783# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 784 785#define RADEON_ISYNC_CNTL 0x1724 786# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 787# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 788# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 789# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 790# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 791# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 792 793#define RADEON_RBBM_GUICNTL 0x172c 794# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 795# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 796# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 797# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 798 799#define RADEON_MC_AGP_LOCATION 0x014c 800#define RADEON_MC_FB_LOCATION 0x0148 801#define RADEON_MCLK_CNTL 0x0012 802# define RADEON_FORCEON_MCLKA (1 << 16) 803# define RADEON_FORCEON_MCLKB (1 << 17) 804# define RADEON_FORCEON_YCLKA (1 << 18) 805# define RADEON_FORCEON_YCLKB (1 << 19) 806# define RADEON_FORCEON_MC (1 << 20) 807# define RADEON_FORCEON_AIC (1 << 21) 808 809#define RADEON_PP_BORDER_COLOR_0 0x1d40 810#define RADEON_PP_BORDER_COLOR_1 0x1d44 811#define RADEON_PP_BORDER_COLOR_2 0x1d48 812#define RADEON_PP_CNTL 0x1c38 813# define RADEON_SCISSOR_ENABLE (1 << 1) 814#define RADEON_PP_LUM_MATRIX 0x1d00 815#define RADEON_PP_MISC 0x1c14 816#define RADEON_PP_ROT_MATRIX_0 0x1d58 817#define RADEON_PP_TXFILTER_0 0x1c54 818#define RADEON_PP_TXOFFSET_0 0x1c5c 819#define RADEON_PP_TXFILTER_1 0x1c6c 820#define RADEON_PP_TXFILTER_2 0x1c84 821 822#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ 823#define R300_DSTCACHE_CTLSTAT 0x1714 824# define R300_RB2D_DC_FLUSH (3 << 0) 825# define R300_RB2D_DC_FREE (3 << 2) 826# define R300_RB2D_DC_FLUSH_ALL 0xf 827# define R300_RB2D_DC_BUSY (1 << 31) 828#define RADEON_RB3D_CNTL 0x1c3c 829# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 830# define RADEON_PLANE_MASK_ENABLE (1 << 1) 831# define RADEON_DITHER_ENABLE (1 << 2) 832# define RADEON_ROUND_ENABLE (1 << 3) 833# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 834# define RADEON_DITHER_INIT (1 << 5) 835# define RADEON_ROP_ENABLE (1 << 6) 836# define RADEON_STENCIL_ENABLE (1 << 7) 837# define RADEON_Z_ENABLE (1 << 8) 838# define RADEON_ZBLOCK16 (1 << 15) 839#define RADEON_RB3D_DEPTHOFFSET 0x1c24 840#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 841#define RADEON_RB3D_DEPTHPITCH 0x1c28 842#define RADEON_RB3D_PLANEMASK 0x1d84 843#define RADEON_RB3D_STENCILREFMASK 0x1d7c 844#define RADEON_RB3D_ZCACHE_MODE 0x3250 845#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 846# define RADEON_RB3D_ZC_FLUSH (1 << 0) 847# define RADEON_RB3D_ZC_FREE (1 << 2) 848# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 849# define RADEON_RB3D_ZC_BUSY (1 << 31) 850#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 851# define R300_ZC_FLUSH (1 << 0) 852# define R300_ZC_FREE (1 << 1) 853# define R300_ZC_BUSY (1 << 31) 854#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 855# define RADEON_RB3D_DC_FLUSH (3 << 0) 856# define RADEON_RB3D_DC_FREE (3 << 2) 857# define RADEON_RB3D_DC_FLUSH_ALL 0xf 858# define RADEON_RB3D_DC_BUSY (1 << 31) 859#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 860# define R300_RB3D_DC_FLUSH (2 << 0) 861# define R300_RB3D_DC_FREE (2 << 2) 862# define R300_RB3D_DC_FINISH (1 << 4) 863#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 864# define RADEON_Z_TEST_MASK (7 << 4) 865# define RADEON_Z_TEST_ALWAYS (7 << 4) 866# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 867# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 868# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 869# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 870# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 871# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 872# define RADEON_FORCE_Z_DIRTY (1 << 29) 873# define RADEON_Z_WRITE_ENABLE (1 << 30) 874# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 875#define RADEON_RBBM_SOFT_RESET 0x00f0 876# define RADEON_SOFT_RESET_CP (1 << 0) 877# define RADEON_SOFT_RESET_HI (1 << 1) 878# define RADEON_SOFT_RESET_SE (1 << 2) 879# define RADEON_SOFT_RESET_RE (1 << 3) 880# define RADEON_SOFT_RESET_PP (1 << 4) 881# define RADEON_SOFT_RESET_E2 (1 << 5) 882# define RADEON_SOFT_RESET_RB (1 << 6) 883# define RADEON_SOFT_RESET_HDP (1 << 7) 884/* 885 * 6:0 Available slots in the FIFO 886 * 8 Host Interface active 887 * 9 CP request active 888 * 10 FIFO request active 889 * 11 Host Interface retry active 890 * 12 CP retry active 891 * 13 FIFO retry active 892 * 14 FIFO pipeline busy 893 * 15 Event engine busy 894 * 16 CP command stream busy 895 * 17 2D engine busy 896 * 18 2D portion of render backend busy 897 * 20 3D setup engine busy 898 * 26 GA engine busy 899 * 27 CBA 2D engine busy 900 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or 901 * command stream queue not empty or Ring Buffer not empty 902 */ 903#define RADEON_RBBM_STATUS 0x0e40 904/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ 905/* #define RADEON_RBBM_STATUS 0x1740 */ 906/* bits 6:0 are dword slots available in the cmd fifo */ 907# define RADEON_RBBM_FIFOCNT_MASK 0x007f 908# define RADEON_HIRQ_ON_RBB (1 << 8) 909# define RADEON_CPRQ_ON_RBB (1 << 9) 910# define RADEON_CFRQ_ON_RBB (1 << 10) 911# define RADEON_HIRQ_IN_RTBUF (1 << 11) 912# define RADEON_CPRQ_IN_RTBUF (1 << 12) 913# define RADEON_CFRQ_IN_RTBUF (1 << 13) 914# define RADEON_PIPE_BUSY (1 << 14) 915# define RADEON_ENG_EV_BUSY (1 << 15) 916# define RADEON_CP_CMDSTRM_BUSY (1 << 16) 917# define RADEON_E2_BUSY (1 << 17) 918# define RADEON_RB2D_BUSY (1 << 18) 919# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ 920# define RADEON_VAP_BUSY (1 << 20) 921# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ 922# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ 923# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ 924# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ 925# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ 926# define RADEON_GA_BUSY (1 << 26) 927# define RADEON_CBA2D_BUSY (1 << 27) 928# define RADEON_RBBM_ACTIVE (1 << 31) 929#define RADEON_RE_LINE_PATTERN 0x1cd0 930#define RADEON_RE_MISC 0x26c4 931#define RADEON_RE_TOP_LEFT 0x26c0 932#define RADEON_RE_WIDTH_HEIGHT 0x1c44 933#define RADEON_RE_STIPPLE_ADDR 0x1cc8 934#define RADEON_RE_STIPPLE_DATA 0x1ccc 935 936#define RADEON_SCISSOR_TL_0 0x1cd8 937#define RADEON_SCISSOR_BR_0 0x1cdc 938#define RADEON_SCISSOR_TL_1 0x1ce0 939#define RADEON_SCISSOR_BR_1 0x1ce4 940#define RADEON_SCISSOR_TL_2 0x1ce8 941#define RADEON_SCISSOR_BR_2 0x1cec 942#define RADEON_SE_COORD_FMT 0x1c50 943#define RADEON_SE_CNTL 0x1c4c 944# define RADEON_FFACE_CULL_CW (0 << 0) 945# define RADEON_BFACE_SOLID (3 << 1) 946# define RADEON_FFACE_SOLID (3 << 3) 947# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 948# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 949# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 950# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 951# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 952# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 953# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 954# define RADEON_FOG_SHADE_FLAT (1 << 14) 955# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 956# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 957# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 958# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 959# define RADEON_ROUND_MODE_TRUNC (0 << 28) 960# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 961#define RADEON_SE_CNTL_STATUS 0x2140 962#define RADEON_SE_LINE_WIDTH 0x1db8 963#define RADEON_SE_VPORT_XSCALE 0x1d98 964#define RADEON_SE_ZBIAS_FACTOR 0x1db0 965#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 966#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 967#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 968# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 969# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 970#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 971#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 972# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 973#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 974#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 975#define RADEON_SURFACE_ACCESS_CLR 0x0bfc 976#define RADEON_SURFACE_CNTL 0x0b00 977# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 978# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 979# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 980# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 981# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 982# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 983# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 984# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 985# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 986#define RADEON_SURFACE0_INFO 0x0b0c 987# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 988# define RADEON_SURF_TILE_MODE_MASK (3 << 16) 989# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 990# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 991# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 992# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 993#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 994#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 995# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 996#define RADEON_SURFACE1_INFO 0x0b1c 997#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 998#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 999#define RADEON_SURFACE2_INFO 0x0b2c 1000#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 1001#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 1002#define RADEON_SURFACE3_INFO 0x0b3c 1003#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 1004#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 1005#define RADEON_SURFACE4_INFO 0x0b4c 1006#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 1007#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 1008#define RADEON_SURFACE5_INFO 0x0b5c 1009#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 1010#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 1011#define RADEON_SURFACE6_INFO 0x0b6c 1012#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 1013#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 1014#define RADEON_SURFACE7_INFO 0x0b7c 1015#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 1016#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 1017#define RADEON_SW_SEMAPHORE 0x013c 1018 1019#define RADEON_WAIT_UNTIL 0x1720 1020# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 1021# define RADEON_WAIT_2D_IDLE (1 << 14) 1022# define RADEON_WAIT_3D_IDLE (1 << 15) 1023# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 1024# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 1025# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 1026 1027#define RADEON_RB3D_ZMASKOFFSET 0x3234 1028#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 1029# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1030# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1031 1032/* CP registers */ 1033#define RADEON_CP_ME_RAM_ADDR 0x07d4 1034#define RADEON_CP_ME_RAM_RADDR 0x07d8 1035#define RADEON_CP_ME_RAM_DATAH 0x07dc 1036#define RADEON_CP_ME_RAM_DATAL 0x07e0 1037 1038#define RADEON_CP_RB_BASE 0x0700 1039#define RADEON_CP_RB_CNTL 0x0704 1040# define RADEON_BUF_SWAP_32BIT (2 << 16) 1041# define RADEON_RB_NO_UPDATE (1 << 27) 1042# define RADEON_RB_RPTR_WR_ENA (1 << 31) 1043#define RADEON_CP_RB_RPTR_ADDR 0x070c 1044#define RADEON_CP_RB_RPTR 0x0710 1045#define RADEON_CP_RB_WPTR 0x0714 1046 1047#define RADEON_CP_RB_WPTR_DELAY 0x0718 1048# define RADEON_PRE_WRITE_TIMER_SHIFT 0 1049# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 1050 1051#define RADEON_CP_IB_BASE 0x0738 1052 1053#define RADEON_CP_CSQ_CNTL 0x0740 1054# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 1055# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 1056# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 1057# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 1058# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 1059# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 1060# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 1061 1062#define RADEON_AIC_CNTL 0x01d0 1063# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 1064# define RS400_MSI_REARM (1 << 3) 1065#define RADEON_AIC_STAT 0x01d4 1066#define RADEON_AIC_PT_BASE 0x01d8 1067#define RADEON_AIC_LO_ADDR 0x01dc 1068#define RADEON_AIC_HI_ADDR 0x01e0 1069#define RADEON_AIC_TLB_ADDR 0x01e4 1070#define RADEON_AIC_TLB_DATA 0x01e8 1071 1072/* CP command packets */ 1073#define RADEON_CP_PACKET0 0x00000000 1074# define RADEON_ONE_REG_WR (1 << 15) 1075#define RADEON_CP_PACKET1 0x40000000 1076#define RADEON_CP_PACKET2 0x80000000 1077#define RADEON_CP_PACKET3 0xC0000000 1078# define RADEON_CP_NOP 0x00001000 1079# define RADEON_CP_NEXT_CHAR 0x00001900 1080# define RADEON_CP_PLY_NEXTSCAN 0x00001D00 1081# define RADEON_CP_SET_SCISSORS 0x00001E00 1082 /* GEN_INDX_PRIM is unsupported starting with R300 */ 1083# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 1084# define RADEON_WAIT_FOR_IDLE 0x00002600 1085# define RADEON_3D_DRAW_VBUF 0x00002800 1086# define RADEON_3D_DRAW_IMMD 0x00002900 1087# define RADEON_3D_DRAW_INDX 0x00002A00 1088# define RADEON_CP_LOAD_PALETTE 0x00002C00 1089# define RADEON_3D_LOAD_VBPNTR 0x00002F00 1090# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 1091# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 1092# define RADEON_3D_CLEAR_ZMASK 0x00003200 1093# define RADEON_CP_INDX_BUFFER 0x00003300 1094# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 1095# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 1096# define RADEON_CP_3D_DRAW_INDX_2 0x00003600 1097# define RADEON_3D_CLEAR_HIZ 0x00003700 1098# define RADEON_CP_3D_CLEAR_CMASK 0x00003802 1099# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 1100# define RADEON_CNTL_PAINT_MULTI 0x00009A00 1101# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 1102# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 1103 1104# define R600_IT_INDIRECT_BUFFER 0x00003200 1105# define R600_IT_ME_INITIALIZE 0x00004400 1106# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1107# define R600_IT_EVENT_WRITE 0x00004600 1108# define R600_IT_SET_CONFIG_REG 0x00006800 1109# define R600_SET_CONFIG_REG_OFFSET 0x00008000 1110# define R600_SET_CONFIG_REG_END 0x0000ac00 1111 1112#define RADEON_CP_PACKET_MASK 0xC0000000 1113#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 1114#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 1115#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 1116#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 1117 1118#define RADEON_VTX_Z_PRESENT (1 << 31) 1119#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 1120 1121#define RADEON_PRIM_TYPE_NONE (0 << 0) 1122#define RADEON_PRIM_TYPE_POINT (1 << 0) 1123#define RADEON_PRIM_TYPE_LINE (2 << 0) 1124#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 1125#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 1126#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 1127#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 1128#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 1129#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 1130#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 1131#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 1132#define RADEON_PRIM_TYPE_MASK 0xf 1133#define RADEON_PRIM_WALK_IND (1 << 4) 1134#define RADEON_PRIM_WALK_LIST (2 << 4) 1135#define RADEON_PRIM_WALK_RING (3 << 4) 1136#define RADEON_COLOR_ORDER_BGRA (0 << 6) 1137#define RADEON_COLOR_ORDER_RGBA (1 << 6) 1138#define RADEON_MAOS_ENABLE (1 << 7) 1139#define RADEON_VTX_FMT_R128_MODE (0 << 8) 1140#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 1141#define RADEON_NUM_VERTICES_SHIFT 16 1142 1143#define RADEON_COLOR_FORMAT_CI8 2 1144#define RADEON_COLOR_FORMAT_ARGB1555 3 1145#define RADEON_COLOR_FORMAT_RGB565 4 1146#define RADEON_COLOR_FORMAT_ARGB8888 6 1147#define RADEON_COLOR_FORMAT_RGB332 7 1148#define RADEON_COLOR_FORMAT_RGB8 9 1149#define RADEON_COLOR_FORMAT_ARGB4444 15 1150 1151#define RADEON_TXFORMAT_I8 0 1152#define RADEON_TXFORMAT_AI88 1 1153#define RADEON_TXFORMAT_RGB332 2 1154#define RADEON_TXFORMAT_ARGB1555 3 1155#define RADEON_TXFORMAT_RGB565 4 1156#define RADEON_TXFORMAT_ARGB4444 5 1157#define RADEON_TXFORMAT_ARGB8888 6 1158#define RADEON_TXFORMAT_RGBA8888 7 1159#define RADEON_TXFORMAT_Y8 8 1160#define RADEON_TXFORMAT_VYUY422 10 1161#define RADEON_TXFORMAT_YVYU422 11 1162#define RADEON_TXFORMAT_DXT1 12 1163#define RADEON_TXFORMAT_DXT23 14 1164#define RADEON_TXFORMAT_DXT45 15 1165 1166#define R200_PP_TXCBLEND_0 0x2f00 1167#define R200_PP_TXCBLEND_1 0x2f10 1168#define R200_PP_TXCBLEND_2 0x2f20 1169#define R200_PP_TXCBLEND_3 0x2f30 1170#define R200_PP_TXCBLEND_4 0x2f40 1171#define R200_PP_TXCBLEND_5 0x2f50 1172#define R200_PP_TXCBLEND_6 0x2f60 1173#define R200_PP_TXCBLEND_7 0x2f70 1174#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 1175#define R200_PP_TFACTOR_0 0x2ee0 1176#define R200_SE_VTX_FMT_0 0x2088 1177#define R200_SE_VAP_CNTL 0x2080 1178#define R200_SE_TCL_MATRIX_SEL_0 0x2230 1179#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 1180#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 1181#define R200_PP_TXFILTER_5 0x2ca0 1182#define R200_PP_TXFILTER_4 0x2c80 1183#define R200_PP_TXFILTER_3 0x2c60 1184#define R200_PP_TXFILTER_2 0x2c40 1185#define R200_PP_TXFILTER_1 0x2c20 1186#define R200_PP_TXFILTER_0 0x2c00 1187#define R200_PP_TXOFFSET_5 0x2d78 1188#define R200_PP_TXOFFSET_4 0x2d60 1189#define R200_PP_TXOFFSET_3 0x2d48 1190#define R200_PP_TXOFFSET_2 0x2d30 1191#define R200_PP_TXOFFSET_1 0x2d18 1192#define R200_PP_TXOFFSET_0 0x2d00 1193 1194#define R200_PP_CUBIC_FACES_0 0x2c18 1195#define R200_PP_CUBIC_FACES_1 0x2c38 1196#define R200_PP_CUBIC_FACES_2 0x2c58 1197#define R200_PP_CUBIC_FACES_3 0x2c78 1198#define R200_PP_CUBIC_FACES_4 0x2c98 1199#define R200_PP_CUBIC_FACES_5 0x2cb8 1200#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 1201#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 1202#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 1203#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 1204#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 1205#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 1206#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 1207#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 1208#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 1209#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 1210#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 1211#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 1212#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 1213#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 1214#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 1215#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 1216#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 1217#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 1218#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 1219#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 1220#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 1221#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 1222#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 1223#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 1224#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 1225#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 1226#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 1227#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 1228#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 1229#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 1230 1231#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1232#define R200_SE_VTE_CNTL 0x20b0 1233#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 1234#define R200_PP_TAM_DEBUG3 0x2d9c 1235#define R200_PP_CNTL_X 0x2cc4 1236#define R200_SE_VAP_CNTL_STATUS 0x2140 1237#define R200_RE_SCISSOR_TL_0 0x1cd8 1238#define R200_RE_SCISSOR_TL_1 0x1ce0 1239#define R200_RE_SCISSOR_TL_2 0x1ce8 1240#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 1241#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1242#define R200_SE_VTX_STATE_CNTL 0x2180 1243#define R200_RE_POINTSIZE 0x2648 1244#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 1245 1246#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1247#define RADEON_PP_TEX_SIZE_1 0x1d0c 1248#define RADEON_PP_TEX_SIZE_2 0x1d14 1249 1250#define RADEON_PP_CUBIC_FACES_0 0x1d24 1251#define RADEON_PP_CUBIC_FACES_1 0x1d28 1252#define RADEON_PP_CUBIC_FACES_2 0x1d2c 1253#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1254#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 1255#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 1256 1257#define RADEON_SE_TCL_STATE_FLUSH 0x2284 1258 1259#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 1260#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 1261#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 1262#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 1263#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 1264#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 1265#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 1266#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 1267#define R200_3D_DRAW_IMMD_2 0xC0003500 1268#define R200_SE_VTX_FMT_1 0x208c 1269#define R200_RE_CNTL 0x1c50 1270 1271#define R200_RB3D_BLENDCOLOR 0x3218 1272 1273#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 1274 1275#define R200_PP_TRI_PERF 0x2cf8 1276 1277#define R200_PP_AFS_0 0x2f80 1278#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 1279 1280#define R200_VAP_PVS_CNTL_1 0x22D0 1281 1282#define RADEON_CRTC_CRNT_FRAME 0x0214 1283#define RADEON_CRTC2_CRNT_FRAME 0x0314 1284 1285#define R500_D1CRTC_STATUS 0x609c 1286#define R500_D2CRTC_STATUS 0x689c 1287#define R500_CRTC_V_BLANK (1<<0) 1288 1289#define R500_D1CRTC_FRAME_COUNT 0x60a4 1290#define R500_D2CRTC_FRAME_COUNT 0x68a4 1291 1292#define R500_D1MODE_V_COUNTER 0x6530 1293#define R500_D2MODE_V_COUNTER 0x6d30 1294 1295#define R500_D1MODE_VBLANK_STATUS 0x6534 1296#define R500_D2MODE_VBLANK_STATUS 0x6d34 1297#define R500_VBLANK_OCCURED (1<<0) 1298#define R500_VBLANK_ACK (1<<4) 1299#define R500_VBLANK_STAT (1<<12) 1300#define R500_VBLANK_INT (1<<16) 1301 1302#define R500_DxMODE_INT_MASK 0x6540 1303#define R500_D1MODE_INT_MASK (1<<0) 1304#define R500_D2MODE_INT_MASK (1<<8) 1305 1306#define R500_DISP_INTERRUPT_STATUS 0x7edc 1307#define R500_D1_VBLANK_INTERRUPT (1 << 4) 1308#define R500_D2_VBLANK_INTERRUPT (1 << 5) 1309 1310/* R6xx/R7xx registers */ 1311#define R600_MC_VM_FB_LOCATION 0x2180 1312#define R600_MC_VM_AGP_TOP 0x2184 1313#define R600_MC_VM_AGP_BOT 0x2188 1314#define R600_MC_VM_AGP_BASE 0x218c 1315#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 1316#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 1317#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 1318 1319#define R700_MC_VM_FB_LOCATION 0x2024 1320#define R700_MC_VM_AGP_TOP 0x2028 1321#define R700_MC_VM_AGP_BOT 0x202c 1322#define R700_MC_VM_AGP_BASE 0x2030 1323#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 1324#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 1325#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c 1326 1327#define R600_MCD_RD_A_CNTL 0x219c 1328#define R600_MCD_RD_B_CNTL 0x21a0 1329 1330#define R600_MCD_WR_A_CNTL 0x21a4 1331#define R600_MCD_WR_B_CNTL 0x21a8 1332 1333#define R600_MCD_RD_SYS_CNTL 0x2200 1334#define R600_MCD_WR_SYS_CNTL 0x2214 1335 1336#define R600_MCD_RD_GFX_CNTL 0x21fc 1337#define R600_MCD_RD_HDP_CNTL 0x2204 1338#define R600_MCD_RD_PDMA_CNTL 0x2208 1339#define R600_MCD_RD_SEM_CNTL 0x220c 1340#define R600_MCD_WR_GFX_CNTL 0x2210 1341#define R600_MCD_WR_HDP_CNTL 0x2218 1342#define R600_MCD_WR_PDMA_CNTL 0x221c 1343#define R600_MCD_WR_SEM_CNTL 0x2220 1344 1345# define R600_MCD_L1_TLB (1 << 0) 1346# define R600_MCD_L1_FRAG_PROC (1 << 1) 1347# define R600_MCD_L1_STRICT_ORDERING (1 << 2) 1348 1349# define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6) 1350# define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 1351# define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 1352# define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 1353# define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 1354 1355# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 1356# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 1357 1358# define R600_MCD_SEMAPHORE_MODE (1 << 10) 1359# define R600_MCD_WAIT_L2_QUERY (1 << 11) 1360# define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12) 1361# define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 1362 1363#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654 1364#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658 1365#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c 1366 1367#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234 1368#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238 1369#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c 1370#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240 1371 1372# define R700_ENABLE_L1_TLB (1 << 0) 1373# define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 1374# define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 1375# define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 1376# define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15) 1377# define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18) 1378 1379#define R700_MC_ARB_RAMCFG 0x2760 1380# define R700_NOOFBANK_SHIFT 0 1381# define R700_NOOFBANK_MASK 0x3 1382# define R700_NOOFRANK_SHIFT 2 1383# define R700_NOOFRANK_MASK 0x1 1384# define R700_NOOFROWS_SHIFT 3 1385# define R700_NOOFROWS_MASK 0x7 1386# define R700_NOOFCOLS_SHIFT 6 1387# define R700_NOOFCOLS_MASK 0x3 1388# define R700_CHANSIZE_SHIFT 8 1389# define R700_CHANSIZE_MASK 0x1 1390# define R700_BURSTLENGTH_SHIFT 9 1391# define R700_BURSTLENGTH_MASK 0x1 1392#define R600_RAMCFG 0x2408 1393# define R600_NOOFBANK_SHIFT 0 1394# define R600_NOOFBANK_MASK 0x1 1395# define R600_NOOFRANK_SHIFT 1 1396# define R600_NOOFRANK_MASK 0x1 1397# define R600_NOOFROWS_SHIFT 2 1398# define R600_NOOFROWS_MASK 0x7 1399# define R600_NOOFCOLS_SHIFT 5 1400# define R600_NOOFCOLS_MASK 0x3 1401# define R600_CHANSIZE_SHIFT 7 1402# define R600_CHANSIZE_MASK 0x1 1403# define R600_BURSTLENGTH_SHIFT 8 1404# define R600_BURSTLENGTH_MASK 0x1 1405 1406#define R600_VM_L2_CNTL 0x1400 1407# define R600_VM_L2_CACHE_EN (1 << 0) 1408# define R600_VM_L2_FRAG_PROC (1 << 1) 1409# define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9) 1410# define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13) 1411# define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14) 1412 1413#define R600_VM_L2_CNTL2 0x1404 1414# define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0) 1415# define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1) 1416#define R600_VM_L2_CNTL3 0x1408 1417# define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0) 1418# define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5) 1419# define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10) 1420# define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0) 1421# define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6) 1422 1423#define R600_VM_L2_STATUS 0x140c 1424 1425#define R600_VM_CONTEXT0_CNTL 0x1410 1426# define R600_VM_ENABLE_CONTEXT (1 << 0) 1427# define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1) 1428 1429#define R600_VM_CONTEXT0_CNTL2 0x1430 1430#define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470 1431#define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 1432#define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0 1433#define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 1434#define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 1435#define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4 1436 1437#define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 1438#define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 1439#define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c 1440 1441#define R600_HDP_HOST_PATH_CNTL 0x2c00 1442 1443#define R600_GRBM_CNTL 0x8000 1444# define R600_GRBM_READ_TIMEOUT(x) ((x) << 0) 1445 1446#define R600_GRBM_STATUS 0x8010 1447# define R600_CMDFIFO_AVAIL_MASK 0x1f 1448# define R700_CMDFIFO_AVAIL_MASK 0xf 1449# define R600_GUI_ACTIVE (1 << 31) 1450#define R600_GRBM_STATUS2 0x8014 1451#define R600_GRBM_SOFT_RESET 0x8020 1452# define R600_SOFT_RESET_CP (1 << 0) 1453#define R600_WAIT_UNTIL 0x8040 1454 1455#define R600_CP_SEM_WAIT_TIMER 0x85bc 1456#define R600_CP_ME_CNTL 0x86d8 1457# define R600_CP_ME_HALT (1 << 28) 1458#define R600_CP_QUEUE_THRESHOLDS 0x8760 1459# define R600_ROQ_IB1_START(x) ((x) << 0) 1460# define R600_ROQ_IB2_START(x) ((x) << 8) 1461#define R600_CP_MEQ_THRESHOLDS 0x8764 1462# define R700_STQ_SPLIT(x) ((x) << 0) 1463# define R600_MEQ_END(x) ((x) << 16) 1464# define R600_ROQ_END(x) ((x) << 24) 1465#define R600_CP_PERFMON_CNTL 0x87fc 1466#define R600_CP_RB_BASE 0xc100 1467#define R600_CP_RB_CNTL 0xc104 1468# define R600_RB_BUFSZ(x) ((x) << 0) 1469# define R600_RB_BLKSZ(x) ((x) << 8) 1470# define R600_RB_NO_UPDATE (1 << 27) 1471# define R600_RB_RPTR_WR_ENA (1 << 31) 1472#define R600_CP_RB_RPTR_WR 0xc108 1473#define R600_CP_RB_RPTR_ADDR 0xc10c 1474#define R600_CP_RB_RPTR_ADDR_HI 0xc110 1475#define R600_CP_RB_WPTR 0xc114 1476#define R600_CP_RB_WPTR_ADDR 0xc118 1477#define R600_CP_RB_WPTR_ADDR_HI 0xc11c 1478#define R600_CP_RB_RPTR 0x8700 1479#define R600_CP_RB_WPTR_DELAY 0x8704 1480#define R600_CP_PFP_UCODE_ADDR 0xc150 1481#define R600_CP_PFP_UCODE_DATA 0xc154 1482#define R600_CP_ME_RAM_RADDR 0xc158 1483#define R600_CP_ME_RAM_WADDR 0xc15c 1484#define R600_CP_ME_RAM_DATA 0xc160 1485#define R600_CP_DEBUG 0xc1fc 1486 1487#define R600_PA_CL_ENHANCE 0x8a14 1488# define R600_CLIP_VTX_REORDER_ENA (1 << 0) 1489# define R600_NUM_CLIP_SEQ(x) ((x) << 1) 1490#define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10 1491#define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20 1492#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24 1493# define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1494# define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 1495#define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40 1496#define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44 1497#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48 1498#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c 1499# define R600_S0_X(x) ((x) << 0) 1500# define R600_S0_Y(x) ((x) << 4) 1501# define R600_S1_X(x) ((x) << 8) 1502# define R600_S1_Y(x) ((x) << 12) 1503# define R600_S2_X(x) ((x) << 16) 1504# define R600_S2_Y(x) ((x) << 20) 1505# define R600_S3_X(x) ((x) << 24) 1506# define R600_S3_Y(x) ((x) << 28) 1507# define R600_S4_X(x) ((x) << 0) 1508# define R600_S4_Y(x) ((x) << 4) 1509# define R600_S5_X(x) ((x) << 8) 1510# define R600_S5_Y(x) ((x) << 12) 1511# define R600_S6_X(x) ((x) << 16) 1512# define R600_S6_Y(x) ((x) << 20) 1513# define R600_S7_X(x) ((x) << 24) 1514# define R600_S7_Y(x) ((x) << 28) 1515#define R600_PA_SC_FIFO_SIZE 0x8bd0 1516# define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1517# define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8) 1518# define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16) 1519#define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc 1520# define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1521# define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 1522# define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 1523#define R600_PA_SC_ENHANCE 0x8bf0 1524# define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1525# define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 1526#define R600_PA_SC_CLIPRECT_RULE 0x2820c 1527#define R700_PA_SC_EDGERULE 0x28230 1528#define R600_PA_SC_LINE_STIPPLE 0x28a0c 1529#define R600_PA_SC_MODE_CNTL 0x28a4c 1530#define R600_PA_SC_AA_CONFIG 0x28c04 1531 1532#define R600_SX_EXPORT_BUFFER_SIZES 0x900c 1533# define R600_COLOR_BUFFER_SIZE(x) ((x) << 0) 1534# define R600_POSITION_BUFFER_SIZE(x) ((x) << 8) 1535# define R600_SMX_BUFFER_SIZE(x) ((x) << 16) 1536#define R600_SX_DEBUG_1 0x9054 1537# define R600_SMX_EVENT_RELEASE (1 << 0) 1538# define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1539#define R700_SX_DEBUG_1 0x9058 1540# define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1541#define R600_SX_MISC 0x28350 1542 1543#define R600_DB_DEBUG 0x9830 1544# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 1545#define R600_DB_WATERMARKS 0x9838 1546# define R600_DEPTH_FREE(x) ((x) << 0) 1547# define R600_DEPTH_FLUSH(x) ((x) << 5) 1548# define R600_DEPTH_PENDING_FREE(x) ((x) << 15) 1549# define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20) 1550#define R700_DB_DEBUG3 0x98b0 1551# define R700_DB_CLK_OFF_DELAY(x) ((x) << 11) 1552#define RV700_DB_DEBUG4 0x9b8c 1553# define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 1554 1555#define R600_VGT_CACHE_INVALIDATION 0x88c4 1556# define R600_CACHE_INVALIDATION(x) ((x) << 0) 1557# define R600_VC_ONLY 0 1558# define R600_TC_ONLY 1 1559# define R600_VC_AND_TC 2 1560# define R700_AUTO_INVLD_EN(x) ((x) << 6) 1561# define R700_NO_AUTO 0 1562# define R700_ES_AUTO 1 1563# define R700_GS_AUTO 2 1564# define R700_ES_AND_GS_AUTO 3 1565#define R600_VGT_GS_PER_ES 0x88c8 1566#define R600_VGT_ES_PER_GS 0x88cc 1567#define R600_VGT_GS_PER_VS 0x88e8 1568#define R600_VGT_GS_VERTEX_REUSE 0x88d4 1569#define R600_VGT_NUM_INSTANCES 0x8974 1570#define R600_VGT_STRMOUT_EN 0x28ab0 1571#define R600_VGT_EVENT_INITIATOR 0x28a90 1572# define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 1573#define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58 1574# define R600_VTX_REUSE_DEPTH_MASK 0xff 1575#define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c 1576# define R600_DEALLOC_DIST_MASK 0x7f 1577 1578#define R600_CB_COLOR0_BASE 0x28040 1579#define R600_CB_COLOR1_BASE 0x28044 1580#define R600_CB_COLOR2_BASE 0x28048 1581#define R600_CB_COLOR3_BASE 0x2804c 1582#define R600_CB_COLOR4_BASE 0x28050 1583#define R600_CB_COLOR5_BASE 0x28054 1584#define R600_CB_COLOR6_BASE 0x28058 1585#define R600_CB_COLOR7_BASE 0x2805c 1586#define R600_CB_COLOR7_FRAG 0x280fc 1587 1588#define R600_TC_CNTL 0x9608 1589# define R600_TC_L2_SIZE(x) ((x) << 5) 1590# define R600_L2_DISABLE_LATE_HIT (1 << 9) 1591 1592#define R600_ARB_POP 0x2418 1593# define R600_ENABLE_TC128 (1 << 30) 1594#define R600_ARB_GDEC_RD_CNTL 0x246c 1595 1596#define R600_TA_CNTL_AUX 0x9508 1597# define R600_DISABLE_CUBE_WRAP (1 << 0) 1598# define R600_DISABLE_CUBE_ANISO (1 << 1) 1599# define R700_GETLOD_SELECT(x) ((x) << 2) 1600# define R600_SYNC_GRADIENT (1 << 24) 1601# define R600_SYNC_WALKER (1 << 25) 1602# define R600_SYNC_ALIGNER (1 << 26) 1603# define R600_BILINEAR_PRECISION_6_BIT (0 << 31) 1604# define R600_BILINEAR_PRECISION_8_BIT (1 << 31) 1605 1606#define R700_TCP_CNTL 0x9610 1607 1608#define R600_SMX_DC_CTL0 0xa020 1609# define R700_USE_HASH_FUNCTION (1 << 0) 1610# define R700_CACHE_DEPTH(x) ((x) << 1) 1611# define R700_FLUSH_ALL_ON_EVENT (1 << 10) 1612# define R700_STALL_ON_EVENT (1 << 11) 1613#define R700_SMX_EVENT_CTL 0xa02c 1614# define R700_ES_FLUSH_CTL(x) ((x) << 0) 1615# define R700_GS_FLUSH_CTL(x) ((x) << 3) 1616# define R700_ACK_FLUSH_CTL(x) ((x) << 6) 1617# define R700_SYNC_FLUSH_CTL (1 << 8) 1618 1619#define R600_SQ_CONFIG 0x8c00 1620# define R600_VC_ENABLE (1 << 0) 1621# define R600_EXPORT_SRC_C (1 << 1) 1622# define R600_DX9_CONSTS (1 << 2) 1623# define R600_ALU_INST_PREFER_VECTOR (1 << 3) 1624# define R600_DX10_CLAMP (1 << 4) 1625# define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8) 1626# define R600_PS_PRIO(x) ((x) << 24) 1627# define R600_VS_PRIO(x) ((x) << 26) 1628# define R600_GS_PRIO(x) ((x) << 28) 1629# define R600_ES_PRIO(x) ((x) << 30) 1630#define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04 1631# define R600_NUM_PS_GPRS(x) ((x) << 0) 1632# define R600_NUM_VS_GPRS(x) ((x) << 16) 1633# define R700_DYN_GPR_ENABLE (1 << 27) 1634# define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 1635#define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08 1636# define R600_NUM_GS_GPRS(x) ((x) << 0) 1637# define R600_NUM_ES_GPRS(x) ((x) << 16) 1638#define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c 1639# define R600_NUM_PS_THREADS(x) ((x) << 0) 1640# define R600_NUM_VS_THREADS(x) ((x) << 8) 1641# define R600_NUM_GS_THREADS(x) ((x) << 16) 1642# define R600_NUM_ES_THREADS(x) ((x) << 24) 1643#define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10 1644# define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0) 1645# define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16) 1646#define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14 1647# define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0) 1648# define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16) 1649#define R600_SQ_MS_FIFO_SIZES 0x8cf0 1650# define R600_CACHE_FIFO_SIZE(x) ((x) << 0) 1651# define R600_FETCH_FIFO_HIWATER(x) ((x) << 8) 1652# define R600_DONE_FIFO_HIWATER(x) ((x) << 16) 1653# define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 1654#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0 1655# define R700_SIMDA_RING0(x) ((x) << 0) 1656# define R700_SIMDA_RING1(x) ((x) << 8) 1657# define R700_SIMDB_RING0(x) ((x) << 16) 1658# define R700_SIMDB_RING1(x) ((x) << 24) 1659#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4 1660#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8 1661#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc 1662#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0 1663#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4 1664#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8 1665#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc 1666 1667#define R600_SPI_PS_IN_CONTROL_0 0x286cc 1668# define R600_NUM_INTERP(x) ((x) << 0) 1669# define R600_POSITION_ENA (1 << 8) 1670# define R600_POSITION_CENTROID (1 << 9) 1671# define R600_POSITION_ADDR(x) ((x) << 10) 1672# define R600_PARAM_GEN(x) ((x) << 15) 1673# define R600_PARAM_GEN_ADDR(x) ((x) << 19) 1674# define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26) 1675# define R600_PERSP_GRADIENT_ENA (1 << 28) 1676# define R600_LINEAR_GRADIENT_ENA (1 << 29) 1677# define R600_POSITION_SAMPLE (1 << 30) 1678# define R600_BARYC_AT_SAMPLE_ENA (1 << 31) 1679#define R600_SPI_PS_IN_CONTROL_1 0x286d0 1680# define R600_GEN_INDEX_PIX (1 << 0) 1681# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1) 1682# define R600_FRONT_FACE_ENA (1 << 8) 1683# define R600_FRONT_FACE_CHAN(x) ((x) << 9) 1684# define R600_FRONT_FACE_ALL_BITS (1 << 11) 1685# define R600_FRONT_FACE_ADDR(x) ((x) << 12) 1686# define R600_FOG_ADDR(x) ((x) << 17) 1687# define R600_FIXED_PT_POSITION_ENA (1 << 24) 1688# define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25) 1689# define R700_POSITION_ULC (1 << 30) 1690#define R600_SPI_INPUT_Z 0x286d8 1691 1692#define R600_SPI_CONFIG_CNTL 0x9100 1693# define R600_GPR_WRITE_PRIORITY(x) ((x) << 0) 1694# define R600_DISABLE_INTERP_1 (1 << 5) 1695#define R600_SPI_CONFIG_CNTL_1 0x913c 1696# define R600_VTX_DONE_DELAY(x) ((x) << 0) 1697# define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4) 1698 1699#define R600_GB_TILING_CONFIG 0x98f0 1700# define R600_PIPE_TILING(x) ((x) << 1) 1701# define R600_BANK_TILING(x) ((x) << 4) 1702# define R600_GROUP_SIZE(x) ((x) << 6) 1703# define R600_ROW_TILING(x) ((x) << 8) 1704# define R600_BANK_SWAPS(x) ((x) << 11) 1705# define R600_SAMPLE_SPLIT(x) ((x) << 14) 1706# define R600_BACKEND_MAP(x) ((x) << 16) 1707#define R600_DCP_TILING_CONFIG 0x6ca0 1708#define R600_HDP_TILING_CONFIG 0x2f3c 1709 1710#define R600_CC_RB_BACKEND_DISABLE 0x98f4 1711#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88 1712# define R600_BACKEND_DISABLE(x) ((x) << 16) 1713 1714#define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950 1715#define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954 1716# define R600_INACTIVE_QD_PIPES(x) ((x) << 8) 1717# define R600_INACTIVE_QD_PIPES_MASK (0xff << 8) 1718# define R600_INACTIVE_SIMDS(x) ((x) << 16) 1719# define R600_INACTIVE_SIMDS_MASK (0xff << 16) 1720 1721#define R700_CGTS_SYS_TCC_DISABLE 0x3f90 1722#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94 1723#define R700_CGTS_TCC_DISABLE 0x9148 1724#define R700_CGTS_USER_TCC_DISABLE 0x914c 1725 1726/* Constants */ 1727#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1728 1729#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 1730#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 1731#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 1732#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 1733#define RADEON_LAST_DISPATCH 1 1734 1735#define R600_LAST_FRAME_REG R600_SCRATCH_REG0 1736#define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1 1737#define R600_LAST_CLEAR_REG R600_SCRATCH_REG2 1738#define R600_LAST_SWI_REG R600_SCRATCH_REG3 1739 1740#define RADEON_MAX_VB_AGE 0x7fffffff 1741#define RADEON_MAX_VB_VERTS (0xffff) 1742 1743#define RADEON_RING_HIGH_MARK 128 1744 1745#define RADEON_PCIGART_TABLE_SIZE (32*1024) 1746 1747#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 1748#define RADEON_WRITE(reg, val) \ 1749do { \ 1750 if (reg < 0x10000) { \ 1751 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \ 1752 } else { \ 1753 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \ 1754 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \ 1755 } \ 1756} while (0) 1757#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1758#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1759 1760#define RADEON_WRITE_PLL(addr, val) \ 1761do { \ 1762 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \ 1763 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1764 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \ 1765} while (0) 1766 1767#define RADEON_WRITE_PCIE(addr, val) \ 1768do { \ 1769 RADEON_WRITE8(RADEON_PCIE_INDEX, \ 1770 ((addr) & 0xff)); \ 1771 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \ 1772} while (0) 1773 1774#define R500_WRITE_MCIND(addr, val) \ 1775do { \ 1776 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1777 RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1778 RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1779} while (0) 1780 1781#define RS480_WRITE_MCIND(addr, val) \ 1782do { \ 1783 RADEON_WRITE(RS480_NB_MC_INDEX, \ 1784 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ 1785 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \ 1786 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \ 1787} while (0) 1788 1789#define RS690_WRITE_MCIND(addr, val) \ 1790do { \ 1791 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1792 RADEON_WRITE(RS690_MC_DATA, val); \ 1793 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1794} while (0) 1795 1796#define RS600_WRITE_MCIND(addr, val) \ 1797do { \ 1798 RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \ 1799 RADEON_WRITE(RS600_MC_DATA, val); \ 1800} while (0) 1801 1802#define IGP_WRITE_MCIND(addr, val) \ 1803do { \ 1804 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ 1805 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ 1806 RS690_WRITE_MCIND(addr, val); \ 1807 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \ 1808 RS600_WRITE_MCIND(addr, val); \ 1809 else \ 1810 RS480_WRITE_MCIND(addr, val); \ 1811} while (0) 1812 1813#define CP_PACKET0( reg, n ) \ 1814 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1815#define CP_PACKET0_TABLE( reg, n ) \ 1816 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 1817#define CP_PACKET1( reg0, reg1 ) \ 1818 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 1819#define CP_PACKET2() \ 1820 (RADEON_CP_PACKET2) 1821#define CP_PACKET3( pkt, n ) \ 1822 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1823 1824/* ================================================================ 1825 * Engine control helper macros 1826 */ 1827 1828#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 1829 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1830 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1831 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1832} while (0) 1833 1834#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 1835 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1836 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1837 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1838} while (0) 1839 1840#define RADEON_WAIT_UNTIL_IDLE() do { \ 1841 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1842 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1843 RADEON_WAIT_3D_IDLECLEAN | \ 1844 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1845} while (0) 1846 1847#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 1848 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1849 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1850} while (0) 1851 1852#define RADEON_FLUSH_CACHE() do { \ 1853 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1854 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1855 OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1856 } else { \ 1857 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1858 OUT_RING(R300_RB3D_DC_FLUSH); \ 1859 } \ 1860} while (0) 1861 1862#define RADEON_PURGE_CACHE() do { \ 1863 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1864 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1865 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ 1866 } else { \ 1867 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1868 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \ 1869 } \ 1870} while (0) 1871 1872#define RADEON_FLUSH_ZCACHE() do { \ 1873 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1874 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1875 OUT_RING(RADEON_RB3D_ZC_FLUSH); \ 1876 } else { \ 1877 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1878 OUT_RING(R300_ZC_FLUSH); \ 1879 } \ 1880} while (0) 1881 1882#define RADEON_PURGE_ZCACHE() do { \ 1883 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1884 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1885 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ 1886 } else { \ 1887 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1888 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ 1889 } \ 1890} while (0) 1891 1892/* ================================================================ 1893 * Misc helper macros 1894 */ 1895 1896/* Perfbox functionality only. 1897 */ 1898#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 1899do { \ 1900 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 1901 u32 head = GET_RING_HEAD( dev_priv ); \ 1902 if (head == dev_priv->ring.tail) \ 1903 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 1904 } \ 1905} while (0) 1906 1907#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 1908do { \ 1909 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 1910 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 1911 int __ret; \ 1912 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1913 __ret = r600_do_cp_idle(dev_priv); \ 1914 else \ 1915 __ret = radeon_do_cp_idle(dev_priv); \ 1916 if ( __ret ) return __ret; \ 1917 sarea_priv->last_dispatch = 0; \ 1918 radeon_freelist_reset( dev ); \ 1919 } \ 1920} while (0) 1921 1922#define RADEON_DISPATCH_AGE( age ) do { \ 1923 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 1924 OUT_RING( age ); \ 1925} while (0) 1926 1927#define RADEON_FRAME_AGE( age ) do { \ 1928 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 1929 OUT_RING( age ); \ 1930} while (0) 1931 1932#define RADEON_CLEAR_AGE( age ) do { \ 1933 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 1934 OUT_RING( age ); \ 1935} while (0) 1936 1937#define R600_DISPATCH_AGE(age) do { \ 1938 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 1939 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 1940 OUT_RING(age); \ 1941} while (0) 1942 1943#define R600_FRAME_AGE(age) do { \ 1944 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 1945 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 1946 OUT_RING(age); \ 1947} while (0) 1948 1949#define R600_CLEAR_AGE(age) do { \ 1950 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 1951 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 1952 OUT_RING(age); \ 1953} while (0) 1954 1955/* ================================================================ 1956 * Ring control 1957 */ 1958 1959#define RADEON_VERBOSE 0 1960 1961#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring; 1962 1963#define BEGIN_RING( n ) do { \ 1964 if ( RADEON_VERBOSE ) { \ 1965 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 1966 } \ 1967 _align_nr = (n + 0xf) & ~0xf; \ 1968 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \ 1969 COMMIT_RING(); \ 1970 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \ 1971 } \ 1972 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 1973 ring = dev_priv->ring.start; \ 1974 write = dev_priv->ring.tail; \ 1975 mask = dev_priv->ring.tail_mask; \ 1976} while (0) 1977 1978#define ADVANCE_RING() do { \ 1979 if ( RADEON_VERBOSE ) { \ 1980 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 1981 write, dev_priv->ring.tail ); \ 1982 } \ 1983 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 1984 DRM_ERROR( \ 1985 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 1986 ((dev_priv->ring.tail + _nr) & mask), \ 1987 write, __LINE__); \ 1988 } else \ 1989 dev_priv->ring.tail = write; \ 1990} while (0) 1991 1992extern void radeon_commit_ring(drm_radeon_private_t *dev_priv); 1993 1994#define COMMIT_RING() do { \ 1995 radeon_commit_ring(dev_priv); \ 1996 } while(0) 1997 1998#define OUT_RING( x ) do { \ 1999 if ( RADEON_VERBOSE ) { \ 2000 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 2001 (unsigned int)(x), write ); \ 2002 } \ 2003 ring[write++] = (x); \ 2004 write &= mask; \ 2005} while (0) 2006 2007#define OUT_RING_REG( reg, val ) do { \ 2008 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 2009 OUT_RING( val ); \ 2010} while (0) 2011 2012#define OUT_RING_TABLE( tab, sz ) do { \ 2013 int _size = (sz); \ 2014 int *_tab = (int *)(tab); \ 2015 \ 2016 if (write + _size > mask) { \ 2017 int _i = (mask+1) - write; \ 2018 _size -= _i; \ 2019 while (_i > 0 ) { \ 2020 *(int *)(ring + write) = *_tab++; \ 2021 write++; \ 2022 _i--; \ 2023 } \ 2024 write = 0; \ 2025 _tab += _i; \ 2026 } \ 2027 while (_size > 0) { \ 2028 *(ring + write) = *_tab++; \ 2029 write++; \ 2030 _size--; \ 2031 } \ 2032 write &= mask; \ 2033} while (0) 2034 2035#endif /* __RADEON_DRV_H__ */ 2036