radeon_drv.h revision 184374
1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drv.h 184374 2008-10-27 21:21:36Z rnoland $"); 33 34#ifndef __RADEON_DRV_H__ 35#define __RADEON_DRV_H__ 36 37/* General customization: 38 */ 39 40#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 41 42#define DRIVER_NAME "radeon" 43#define DRIVER_DESC "ATI Radeon" 44#define DRIVER_DATE "20080613" 45 46/* Interface history: 47 * 48 * 1.1 - ?? 49 * 1.2 - Add vertex2 ioctl (keith) 50 * - Add stencil capability to clear ioctl (gareth, keith) 51 * - Increase MAX_TEXTURE_LEVELS (brian) 52 * 1.3 - Add cmdbuf ioctl (keith) 53 * - Add support for new radeon packets (keith) 54 * - Add getparam ioctl (keith) 55 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 56 * 1.4 - Add scratch registers to get_param ioctl. 57 * 1.5 - Add r200 packets to cmdbuf ioctl 58 * - Add r200 function to init ioctl 59 * - Add 'scalar2' instruction to cmdbuf 60 * 1.6 - Add static GART memory manager 61 * Add irq handler (won't be turned on unless X server knows to) 62 * Add irq ioctls and irq_active getparam. 63 * Add wait command for cmdbuf ioctl 64 * Add GART offset query for getparam 65 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 66 * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 67 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 68 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 69 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 70 * Add 'GET' queries for starting additional clients on different VT's. 71 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 72 * Add texture rectangle support for r100. 73 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 74 * clients use to tell the DRM where they think the framebuffer is 75 * located in the card's address space 76 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 77 * and GL_EXT_blend_[func|equation]_separate on r200 78 * 1.12- Add R300 CP microcode support - this just loads the CP on r300 79 * (No 3D support yet - just microcode loading). 80 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 81 * - Add hyperz support, add hyperz flags to clear ioctl. 82 * 1.14- Add support for color tiling 83 * - Add R100/R200 surface allocation/free support 84 * 1.15- Add support for texture micro tiling 85 * - Add support for r100 cube maps 86 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 87 * texture filtering on r200 88 * 1.17- Add initial support for R300 (3D). 89 * 1.18- Add support for GL_ATI_fragment_shader, new packets 90 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 91 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 92 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 93 * 1.19- Add support for gart table in FB memory and PCIE r300 94 * 1.20- Add support for r300 texrect 95 * 1.21- Add support for card type getparam 96 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 97 * 1.23- Add new radeon memory map work from benh 98 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 99 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, 100 * new packet type) 101 * 1.26- Add support for variable size PCI(E) gart aperture 102 * 1.27- Add support for IGP GART 103 * 1.28- Add support for VBL on CRTC2 104 * 1.29- R500 3D cmd buffer support 105 */ 106 107#define DRIVER_MAJOR 1 108#define DRIVER_MINOR 29 109#define DRIVER_PATCHLEVEL 0 110 111/* 112 * Radeon chip families 113 */ 114enum radeon_family { 115 CHIP_R100, 116 CHIP_RV100, 117 CHIP_RS100, 118 CHIP_RV200, 119 CHIP_RS200, 120 CHIP_R200, 121 CHIP_RV250, 122 CHIP_RS300, 123 CHIP_RV280, 124 CHIP_R300, 125 CHIP_R350, 126 CHIP_RV350, 127 CHIP_RV380, 128 CHIP_R420, 129 CHIP_R423, 130 CHIP_RV410, 131 CHIP_RS400, 132 CHIP_RS480, 133 CHIP_RS690, 134 CHIP_RS740, 135 CHIP_RV515, 136 CHIP_R520, 137 CHIP_RV530, 138 CHIP_RV560, 139 CHIP_RV570, 140 CHIP_R580, 141 CHIP_LAST, 142}; 143 144/* 145 * Chip flags 146 */ 147enum radeon_chip_flags { 148 RADEON_FAMILY_MASK = 0x0000ffffUL, 149 RADEON_FLAGS_MASK = 0xffff0000UL, 150 RADEON_IS_MOBILITY = 0x00010000UL, 151 RADEON_IS_IGP = 0x00020000UL, 152 RADEON_SINGLE_CRTC = 0x00040000UL, 153 RADEON_IS_AGP = 0x00080000UL, 154 RADEON_HAS_HIERZ = 0x00100000UL, 155 RADEON_IS_PCIE = 0x00200000UL, 156 RADEON_NEW_MEMMAP = 0x00400000UL, 157 RADEON_IS_PCI = 0x00800000UL, 158 RADEON_IS_IGPGART = 0x01000000UL, 159}; 160 161#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ 162 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR)) 163#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) 164 165typedef struct drm_radeon_freelist { 166 unsigned int age; 167 struct drm_buf *buf; 168 struct drm_radeon_freelist *next; 169 struct drm_radeon_freelist *prev; 170} drm_radeon_freelist_t; 171 172typedef struct drm_radeon_ring_buffer { 173 u32 *start; 174 u32 *end; 175 int size; /* Double Words */ 176 int size_l2qw; /* log2 Quad Words */ 177 178 int rptr_update; /* Double Words */ 179 int rptr_update_l2qw; /* log2 Quad Words */ 180 181 int fetch_size; /* Double Words */ 182 int fetch_size_l2ow; /* log2 Oct Words */ 183 184 u32 tail; 185 u32 tail_mask; 186 int space; 187 188 int high_mark; 189} drm_radeon_ring_buffer_t; 190 191typedef struct drm_radeon_depth_clear_t { 192 u32 rb3d_cntl; 193 u32 rb3d_zstencilcntl; 194 u32 se_cntl; 195} drm_radeon_depth_clear_t; 196 197struct drm_radeon_driver_file_fields { 198 int64_t radeon_fb_delta; 199}; 200 201struct mem_block { 202 struct mem_block *next; 203 struct mem_block *prev; 204 int start; 205 int size; 206 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 207}; 208 209struct radeon_surface { 210 int refcount; 211 u32 lower; 212 u32 upper; 213 u32 flags; 214}; 215 216struct radeon_virt_surface { 217 int surface_index; 218 u32 lower; 219 u32 upper; 220 u32 flags; 221 struct drm_file *file_priv; 222}; 223 224#define RADEON_FLUSH_EMITED (1 < 0) 225#define RADEON_PURGE_EMITED (1 < 1) 226 227typedef struct drm_radeon_private { 228 229 drm_radeon_ring_buffer_t ring; 230 drm_radeon_sarea_t *sarea_priv; 231 232 u32 fb_location; 233 u32 fb_size; 234 int new_memmap; 235 236 int gart_size; 237 u32 gart_vm_start; 238 unsigned long gart_buffers_offset; 239 240 int cp_mode; 241 int cp_running; 242 243 drm_radeon_freelist_t *head; 244 drm_radeon_freelist_t *tail; 245 int last_buf; 246 volatile u32 *scratch; 247 int writeback_works; 248 249 int usec_timeout; 250 251 struct { 252 u32 boxes; 253 int freelist_timeouts; 254 int freelist_loops; 255 int requested_bufs; 256 int last_frame_reads; 257 int last_clear_reads; 258 int clears; 259 int texture_uploads; 260 } stats; 261 262 int do_boxes; 263 int page_flipping; 264 265 u32 color_fmt; 266 unsigned int front_offset; 267 unsigned int front_pitch; 268 unsigned int back_offset; 269 unsigned int back_pitch; 270 271 u32 depth_fmt; 272 unsigned int depth_offset; 273 unsigned int depth_pitch; 274 275 u32 front_pitch_offset; 276 u32 back_pitch_offset; 277 u32 depth_pitch_offset; 278 279 drm_radeon_depth_clear_t depth_clear; 280 281 unsigned long ring_offset; 282 unsigned long ring_rptr_offset; 283 unsigned long buffers_offset; 284 unsigned long gart_textures_offset; 285 286 drm_local_map_t *sarea; 287 drm_local_map_t *mmio; 288 drm_local_map_t *cp_ring; 289 drm_local_map_t *ring_rptr; 290 drm_local_map_t *gart_textures; 291 292 struct mem_block *gart_heap; 293 struct mem_block *fb_heap; 294 295 /* SW interrupt */ 296 wait_queue_head_t swi_queue; 297 atomic_t swi_emitted; 298 int vblank_crtc; 299 uint32_t irq_enable_reg; 300 int irq_enabled; 301 uint32_t r500_disp_irq_reg; 302 303 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 304 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 305 306 unsigned long pcigart_offset; 307 unsigned int pcigart_offset_set; 308 struct drm_ati_pcigart_info gart_info; 309 310 u32 scratch_ages[5]; 311 312 unsigned int crtc_last_cnt; 313 unsigned int crtc2_last_cnt; 314 315 /* starting from here on, data is preserved accross an open */ 316 uint32_t flags; /* see radeon_chip_flags */ 317 unsigned long fb_aper_offset; 318 319 int num_gb_pipes; 320 int track_flush; 321 uint32_t chip_family; /* extract from flags */ 322} drm_radeon_private_t; 323 324typedef struct drm_radeon_buf_priv { 325 u32 age; 326} drm_radeon_buf_priv_t; 327 328typedef struct drm_radeon_kcmd_buffer { 329 int bufsz; 330 char *buf; 331 int nbox; 332 struct drm_clip_rect __user *boxes; 333} drm_radeon_kcmd_buffer_t; 334 335extern int radeon_no_wb; 336extern struct drm_ioctl_desc radeon_ioctls[]; 337extern int radeon_max_ioctl; 338 339/* Check whether the given hardware address is inside the framebuffer or the 340 * GART area. 341 */ 342static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, 343 u64 off) 344{ 345 u32 fb_start = dev_priv->fb_location; 346 u32 fb_end = fb_start + dev_priv->fb_size - 1; 347 u32 gart_start = dev_priv->gart_vm_start; 348 u32 gart_end = gart_start + dev_priv->gart_size - 1; 349 350 return ((off >= fb_start && off <= fb_end) || 351 (off >= gart_start && off <= gart_end)); 352} 353 354 /* radeon_cp.c */ 355extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 356extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 357extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 358extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 359extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 360extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); 361extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 362extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 363extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 364extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); 365 366extern void radeon_freelist_reset(struct drm_device * dev); 367extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); 368 369extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 370 371extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 372 373extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); 374extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); 375extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); 376extern void radeon_mem_takedown(struct mem_block **heap); 377extern void radeon_mem_release(struct drm_file *file_priv, 378 struct mem_block *heap); 379 380 /* radeon_irq.c */ 381extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); 382extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); 383extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); 384 385extern void radeon_do_release(struct drm_device * dev); 386extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); 387extern int radeon_enable_vblank(struct drm_device *dev, int crtc); 388extern void radeon_disable_vblank(struct drm_device *dev, int crtc); 389extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 390extern void radeon_driver_irq_preinstall(struct drm_device * dev); 391extern int radeon_driver_irq_postinstall(struct drm_device * dev); 392extern void radeon_driver_irq_uninstall(struct drm_device * dev); 393extern int radeon_vblank_crtc_get(struct drm_device *dev); 394extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 395 396extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 397extern int radeon_driver_unload(struct drm_device *dev); 398extern int radeon_driver_firstopen(struct drm_device *dev); 399extern void radeon_driver_preclose(struct drm_device * dev, 400 struct drm_file *file_priv); 401extern void radeon_driver_postclose(struct drm_device * dev, 402 struct drm_file *file_priv); 403extern void radeon_driver_lastclose(struct drm_device * dev); 404extern int radeon_driver_open(struct drm_device * dev, 405 struct drm_file * file_priv); 406extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 407 unsigned long arg); 408 409/* r300_cmdbuf.c */ 410extern void r300_init_reg_flags(struct drm_device *dev); 411 412extern int r300_do_cp_cmdbuf(struct drm_device *dev, 413 struct drm_file *file_priv, 414 drm_radeon_kcmd_buffer_t *cmdbuf); 415 416/* Flags for stats.boxes 417 */ 418#define RADEON_BOX_DMA_IDLE 0x1 419#define RADEON_BOX_RING_FULL 0x2 420#define RADEON_BOX_FLIP 0x4 421#define RADEON_BOX_WAIT_IDLE 0x8 422#define RADEON_BOX_TEXTURE_LOAD 0x10 423 424/* Register definitions, register access macros and drmAddMap constants 425 * for Radeon kernel driver. 426 */ 427#define RADEON_AGP_COMMAND 0x0f60 428#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 429# define RADEON_AGP_ENABLE (1<<8) 430#define RADEON_AUX_SCISSOR_CNTL 0x26f0 431# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 432# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 433# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 434# define RADEON_SCISSOR_0_ENABLE (1 << 28) 435# define RADEON_SCISSOR_1_ENABLE (1 << 29) 436# define RADEON_SCISSOR_2_ENABLE (1 << 30) 437 438/* 439 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx) 440 * don't have an explicit bus mastering disable bit. It's handled 441 * by the PCI D-states. PMI_BM_DIS disables D-state bus master 442 * handling, not bus mastering itself. 443 */ 444#define RADEON_BUS_CNTL 0x0030 445/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 446# define RADEON_BUS_MASTER_DIS (1 << 6) 447/* rs600/rs690/rs740 */ 448# define RS600_BUS_MASTER_DIS (1 << 14) 449# define RS600_MSI_REARM (1 << 20) 450/* see RS480_MSI_REARM in AIC_CNTL for rs480 */ 451 452#define RADEON_BUS_CNTL1 0x0034 453# define RADEON_PMI_BM_DIS (1 << 2) 454# define RADEON_PMI_INT_DIS (1 << 3) 455 456#define RV370_BUS_CNTL 0x004c 457# define RV370_PMI_BM_DIS (1 << 5) 458# define RV370_PMI_INT_DIS (1 << 6) 459 460#define RADEON_MSI_REARM_EN 0x0160 461/* rv370/rv380, rv410, r423/r430/r480, r5xx */ 462# define RV370_MSI_REARM_EN (1 << 0) 463 464#define RADEON_CLOCK_CNTL_DATA 0x000c 465# define RADEON_PLL_WR_EN (1 << 7) 466#define RADEON_CLOCK_CNTL_INDEX 0x0008 467#define RADEON_CONFIG_APER_SIZE 0x0108 468#define RADEON_CONFIG_MEMSIZE 0x00f8 469#define RADEON_CRTC_OFFSET 0x0224 470#define RADEON_CRTC_OFFSET_CNTL 0x0228 471# define RADEON_CRTC_TILE_EN (1 << 15) 472# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 473#define RADEON_CRTC2_OFFSET 0x0324 474#define RADEON_CRTC2_OFFSET_CNTL 0x0328 475 476#define RADEON_PCIE_INDEX 0x0030 477#define RADEON_PCIE_DATA 0x0034 478#define RADEON_PCIE_TX_GART_CNTL 0x10 479# define RADEON_PCIE_TX_GART_EN (1 << 0) 480# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) 481# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) 482# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) 483# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) 484# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) 485# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) 486# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) 487#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 488#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 489#define RADEON_PCIE_TX_GART_BASE 0x13 490#define RADEON_PCIE_TX_GART_START_LO 0x14 491#define RADEON_PCIE_TX_GART_START_HI 0x15 492#define RADEON_PCIE_TX_GART_END_LO 0x16 493#define RADEON_PCIE_TX_GART_END_HI 0x17 494 495#define RS480_NB_MC_INDEX 0x168 496# define RS480_NB_MC_IND_WR_EN (1 << 8) 497#define RS480_NB_MC_DATA 0x16c 498 499#define RS690_MC_INDEX 0x78 500# define RS690_MC_INDEX_MASK 0x1ff 501# define RS690_MC_INDEX_WR_EN (1 << 9) 502# define RS690_MC_INDEX_WR_ACK 0x7f 503#define RS690_MC_DATA 0x7c 504 505/* MC indirect registers */ 506#define RS480_MC_MISC_CNTL 0x18 507# define RS480_DISABLE_GTW (1 << 1) 508/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ 509# define RS480_GART_INDEX_REG_EN (1 << 12) 510# define RS690_BLOCK_GFX_D3_EN (1 << 14) 511#define RS480_K8_FB_LOCATION 0x1e 512#define RS480_GART_FEATURE_ID 0x2b 513# define RS480_HANG_EN (1 << 11) 514# define RS480_TLB_ENABLE (1 << 18) 515# define RS480_P2P_ENABLE (1 << 19) 516# define RS480_GTW_LAC_EN (1 << 25) 517# define RS480_2LEVEL_GART (0 << 30) 518# define RS480_1LEVEL_GART (1 << 30) 519# define RS480_PDC_EN (1 << 31) 520#define RS480_GART_BASE 0x2c 521#define RS480_GART_CACHE_CNTRL 0x2e 522# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 523#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 524# define RS480_GART_EN (1 << 0) 525# define RS480_VA_SIZE_32MB (0 << 1) 526# define RS480_VA_SIZE_64MB (1 << 1) 527# define RS480_VA_SIZE_128MB (2 << 1) 528# define RS480_VA_SIZE_256MB (3 << 1) 529# define RS480_VA_SIZE_512MB (4 << 1) 530# define RS480_VA_SIZE_1GB (5 << 1) 531# define RS480_VA_SIZE_2GB (6 << 1) 532#define RS480_AGP_MODE_CNTL 0x39 533# define RS480_POST_GART_Q_SIZE (1 << 18) 534# define RS480_NONGART_SNOOP (1 << 19) 535# define RS480_AGP_RD_BUF_SIZE (1 << 20) 536# define RS480_REQ_TYPE_SNOOP_SHIFT 22 537# define RS480_REQ_TYPE_SNOOP_MASK 0x3 538# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 539#define RS480_MC_MISC_UMA_CNTL 0x5f 540#define RS480_MC_MCLK_CNTL 0x7a 541#define RS480_MC_UMA_DUALCH_CNTL 0x86 542 543#define RS690_MC_FB_LOCATION 0x100 544#define RS690_MC_AGP_LOCATION 0x101 545#define RS690_MC_AGP_BASE 0x102 546#define RS690_MC_AGP_BASE_2 0x103 547 548#define R520_MC_IND_INDEX 0x70 549#define R520_MC_IND_WR_EN (1 << 24) 550#define R520_MC_IND_DATA 0x74 551 552#define RV515_MC_FB_LOCATION 0x01 553#define RV515_MC_AGP_LOCATION 0x02 554#define RV515_MC_AGP_BASE 0x03 555#define RV515_MC_AGP_BASE_2 0x04 556 557#define R520_MC_FB_LOCATION 0x04 558#define R520_MC_AGP_LOCATION 0x05 559#define R520_MC_AGP_BASE 0x06 560#define R520_MC_AGP_BASE_2 0x07 561 562#define RADEON_MPP_TB_CONFIG 0x01c0 563#define RADEON_MEM_CNTL 0x0140 564#define RADEON_MEM_SDRAM_MODE_REG 0x0158 565#define RADEON_AGP_BASE_2 0x015c /* r200+ only */ 566#define RS480_AGP_BASE_2 0x0164 567#define RADEON_AGP_BASE 0x0170 568 569/* pipe config regs */ 570#define R400_GB_PIPE_SELECT 0x402c 571#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 572#define R500_SU_REG_DEST 0x42c8 573#define R300_GB_TILE_CONFIG 0x4018 574# define R300_ENABLE_TILING (1 << 0) 575# define R300_PIPE_COUNT_RV350 (0 << 1) 576# define R300_PIPE_COUNT_R300 (3 << 1) 577# define R300_PIPE_COUNT_R420_3P (6 << 1) 578# define R300_PIPE_COUNT_R420 (7 << 1) 579# define R300_TILE_SIZE_8 (0 << 4) 580# define R300_TILE_SIZE_16 (1 << 4) 581# define R300_TILE_SIZE_32 (2 << 4) 582# define R300_SUBPIXEL_1_12 (0 << 16) 583# define R300_SUBPIXEL_1_16 (1 << 16) 584#define R300_DST_PIPE_CONFIG 0x170c 585# define R300_PIPE_AUTO_CONFIG (1 << 31) 586#define R300_RB2D_DSTCACHE_MODE 0x3428 587# define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 588# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 589 590#define RADEON_RB3D_COLOROFFSET 0x1c40 591#define RADEON_RB3D_COLORPITCH 0x1c48 592 593#define RADEON_SRC_X_Y 0x1590 594 595#define RADEON_DP_GUI_MASTER_CNTL 0x146c 596# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 597# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 598# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 599# define RADEON_GMC_BRUSH_NONE (15 << 4) 600# define RADEON_GMC_DST_16BPP (4 << 8) 601# define RADEON_GMC_DST_24BPP (5 << 8) 602# define RADEON_GMC_DST_32BPP (6 << 8) 603# define RADEON_GMC_DST_DATATYPE_SHIFT 8 604# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 605# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 606# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 607# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 608# define RADEON_GMC_WR_MSK_DIS (1 << 30) 609# define RADEON_ROP3_S 0x00cc0000 610# define RADEON_ROP3_P 0x00f00000 611#define RADEON_DP_WRITE_MASK 0x16cc 612#define RADEON_SRC_PITCH_OFFSET 0x1428 613#define RADEON_DST_PITCH_OFFSET 0x142c 614#define RADEON_DST_PITCH_OFFSET_C 0x1c80 615# define RADEON_DST_TILE_LINEAR (0 << 30) 616# define RADEON_DST_TILE_MACRO (1 << 30) 617# define RADEON_DST_TILE_MICRO (2 << 30) 618# define RADEON_DST_TILE_BOTH (3 << 30) 619 620#define RADEON_SCRATCH_REG0 0x15e0 621#define RADEON_SCRATCH_REG1 0x15e4 622#define RADEON_SCRATCH_REG2 0x15e8 623#define RADEON_SCRATCH_REG3 0x15ec 624#define RADEON_SCRATCH_REG4 0x15f0 625#define RADEON_SCRATCH_REG5 0x15f4 626#define RADEON_SCRATCH_UMSK 0x0770 627#define RADEON_SCRATCH_ADDR 0x0774 628 629#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 630 631#define GET_SCRATCH( x ) (dev_priv->writeback_works \ 632 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ 633 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) 634 635#define RADEON_CRTC_CRNT_FRAME 0x0214 636#define RADEON_CRTC2_CRNT_FRAME 0x0314 637 638#define RADEON_CRTC_STATUS 0x005c 639#define RADEON_CRTC2_STATUS 0x03fc 640 641#define RADEON_GEN_INT_CNTL 0x0040 642# define RADEON_CRTC_VBLANK_MASK (1 << 0) 643# define RADEON_CRTC2_VBLANK_MASK (1 << 9) 644# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 645# define RADEON_SW_INT_ENABLE (1 << 25) 646 647#define RADEON_GEN_INT_STATUS 0x0044 648# define RADEON_CRTC_VBLANK_STAT (1 << 0) 649# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 650# define RADEON_CRTC2_VBLANK_STAT (1 << 9) 651# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 652# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 653# define RADEON_SW_INT_TEST (1 << 25) 654# define RADEON_SW_INT_TEST_ACK (1 << 25) 655# define RADEON_SW_INT_FIRE (1 << 26) 656# define R500_DISPLAY_INT_STATUS (1 << 0) 657 658 659#define RADEON_HOST_PATH_CNTL 0x0130 660# define RADEON_HDP_SOFT_RESET (1 << 26) 661# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 662# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 663 664#define RADEON_ISYNC_CNTL 0x1724 665# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 666# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 667# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 668# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 669# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 670# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 671 672#define RADEON_RBBM_GUICNTL 0x172c 673# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 674# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 675# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 676# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 677 678#define RADEON_MC_AGP_LOCATION 0x014c 679#define RADEON_MC_FB_LOCATION 0x0148 680#define RADEON_MCLK_CNTL 0x0012 681# define RADEON_FORCEON_MCLKA (1 << 16) 682# define RADEON_FORCEON_MCLKB (1 << 17) 683# define RADEON_FORCEON_YCLKA (1 << 18) 684# define RADEON_FORCEON_YCLKB (1 << 19) 685# define RADEON_FORCEON_MC (1 << 20) 686# define RADEON_FORCEON_AIC (1 << 21) 687 688#define RADEON_PP_BORDER_COLOR_0 0x1d40 689#define RADEON_PP_BORDER_COLOR_1 0x1d44 690#define RADEON_PP_BORDER_COLOR_2 0x1d48 691#define RADEON_PP_CNTL 0x1c38 692# define RADEON_SCISSOR_ENABLE (1 << 1) 693#define RADEON_PP_LUM_MATRIX 0x1d00 694#define RADEON_PP_MISC 0x1c14 695#define RADEON_PP_ROT_MATRIX_0 0x1d58 696#define RADEON_PP_TXFILTER_0 0x1c54 697#define RADEON_PP_TXOFFSET_0 0x1c5c 698#define RADEON_PP_TXFILTER_1 0x1c6c 699#define RADEON_PP_TXFILTER_2 0x1c84 700 701#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ 702#define R300_DSTCACHE_CTLSTAT 0x1714 703# define R300_RB2D_DC_FLUSH (3 << 0) 704# define R300_RB2D_DC_FREE (3 << 2) 705# define R300_RB2D_DC_FLUSH_ALL 0xf 706# define R300_RB2D_DC_BUSY (1 << 31) 707#define RADEON_RB3D_CNTL 0x1c3c 708# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 709# define RADEON_PLANE_MASK_ENABLE (1 << 1) 710# define RADEON_DITHER_ENABLE (1 << 2) 711# define RADEON_ROUND_ENABLE (1 << 3) 712# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 713# define RADEON_DITHER_INIT (1 << 5) 714# define RADEON_ROP_ENABLE (1 << 6) 715# define RADEON_STENCIL_ENABLE (1 << 7) 716# define RADEON_Z_ENABLE (1 << 8) 717# define RADEON_ZBLOCK16 (1 << 15) 718#define RADEON_RB3D_DEPTHOFFSET 0x1c24 719#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 720#define RADEON_RB3D_DEPTHPITCH 0x1c28 721#define RADEON_RB3D_PLANEMASK 0x1d84 722#define RADEON_RB3D_STENCILREFMASK 0x1d7c 723#define RADEON_RB3D_ZCACHE_MODE 0x3250 724#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 725# define RADEON_RB3D_ZC_FLUSH (1 << 0) 726# define RADEON_RB3D_ZC_FREE (1 << 2) 727# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 728# define RADEON_RB3D_ZC_BUSY (1 << 31) 729#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 730# define R300_ZC_FLUSH (1 << 0) 731# define R300_ZC_FREE (1 << 1) 732# define R300_ZC_BUSY (1 << 31) 733#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 734# define RADEON_RB3D_DC_FLUSH (3 << 0) 735# define RADEON_RB3D_DC_FREE (3 << 2) 736# define RADEON_RB3D_DC_FLUSH_ALL 0xf 737# define RADEON_RB3D_DC_BUSY (1 << 31) 738#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 739# define R300_RB3D_DC_FLUSH (2 << 0) 740# define R300_RB3D_DC_FREE (2 << 2) 741# define R300_RB3D_DC_FINISH (1 << 4) 742#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 743# define RADEON_Z_TEST_MASK (7 << 4) 744# define RADEON_Z_TEST_ALWAYS (7 << 4) 745# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 746# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 747# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 748# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 749# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 750# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 751# define RADEON_FORCE_Z_DIRTY (1 << 29) 752# define RADEON_Z_WRITE_ENABLE (1 << 30) 753# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 754#define RADEON_RBBM_SOFT_RESET 0x00f0 755# define RADEON_SOFT_RESET_CP (1 << 0) 756# define RADEON_SOFT_RESET_HI (1 << 1) 757# define RADEON_SOFT_RESET_SE (1 << 2) 758# define RADEON_SOFT_RESET_RE (1 << 3) 759# define RADEON_SOFT_RESET_PP (1 << 4) 760# define RADEON_SOFT_RESET_E2 (1 << 5) 761# define RADEON_SOFT_RESET_RB (1 << 6) 762# define RADEON_SOFT_RESET_HDP (1 << 7) 763/* 764 * 6:0 Available slots in the FIFO 765 * 8 Host Interface active 766 * 9 CP request active 767 * 10 FIFO request active 768 * 11 Host Interface retry active 769 * 12 CP retry active 770 * 13 FIFO retry active 771 * 14 FIFO pipeline busy 772 * 15 Event engine busy 773 * 16 CP command stream busy 774 * 17 2D engine busy 775 * 18 2D portion of render backend busy 776 * 20 3D setup engine busy 777 * 26 GA engine busy 778 * 27 CBA 2D engine busy 779 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or 780 * command stream queue not empty or Ring Buffer not empty 781 */ 782#define RADEON_RBBM_STATUS 0x0e40 783/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ 784/* #define RADEON_RBBM_STATUS 0x1740 */ 785/* bits 6:0 are dword slots available in the cmd fifo */ 786# define RADEON_RBBM_FIFOCNT_MASK 0x007f 787# define RADEON_HIRQ_ON_RBB (1 << 8) 788# define RADEON_CPRQ_ON_RBB (1 << 9) 789# define RADEON_CFRQ_ON_RBB (1 << 10) 790# define RADEON_HIRQ_IN_RTBUF (1 << 11) 791# define RADEON_CPRQ_IN_RTBUF (1 << 12) 792# define RADEON_CFRQ_IN_RTBUF (1 << 13) 793# define RADEON_PIPE_BUSY (1 << 14) 794# define RADEON_ENG_EV_BUSY (1 << 15) 795# define RADEON_CP_CMDSTRM_BUSY (1 << 16) 796# define RADEON_E2_BUSY (1 << 17) 797# define RADEON_RB2D_BUSY (1 << 18) 798# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ 799# define RADEON_VAP_BUSY (1 << 20) 800# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ 801# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ 802# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ 803# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ 804# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ 805# define RADEON_GA_BUSY (1 << 26) 806# define RADEON_CBA2D_BUSY (1 << 27) 807# define RADEON_RBBM_ACTIVE (1 << 31) 808#define RADEON_RE_LINE_PATTERN 0x1cd0 809#define RADEON_RE_MISC 0x26c4 810#define RADEON_RE_TOP_LEFT 0x26c0 811#define RADEON_RE_WIDTH_HEIGHT 0x1c44 812#define RADEON_RE_STIPPLE_ADDR 0x1cc8 813#define RADEON_RE_STIPPLE_DATA 0x1ccc 814 815#define RADEON_SCISSOR_TL_0 0x1cd8 816#define RADEON_SCISSOR_BR_0 0x1cdc 817#define RADEON_SCISSOR_TL_1 0x1ce0 818#define RADEON_SCISSOR_BR_1 0x1ce4 819#define RADEON_SCISSOR_TL_2 0x1ce8 820#define RADEON_SCISSOR_BR_2 0x1cec 821#define RADEON_SE_COORD_FMT 0x1c50 822#define RADEON_SE_CNTL 0x1c4c 823# define RADEON_FFACE_CULL_CW (0 << 0) 824# define RADEON_BFACE_SOLID (3 << 1) 825# define RADEON_FFACE_SOLID (3 << 3) 826# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 827# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 828# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 829# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 830# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 831# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 832# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 833# define RADEON_FOG_SHADE_FLAT (1 << 14) 834# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 835# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 836# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 837# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 838# define RADEON_ROUND_MODE_TRUNC (0 << 28) 839# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 840#define RADEON_SE_CNTL_STATUS 0x2140 841#define RADEON_SE_LINE_WIDTH 0x1db8 842#define RADEON_SE_VPORT_XSCALE 0x1d98 843#define RADEON_SE_ZBIAS_FACTOR 0x1db0 844#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 845#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 846#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 847# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 848# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 849#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 850#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 851# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 852#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 853#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 854#define RADEON_SURFACE_ACCESS_CLR 0x0bfc 855#define RADEON_SURFACE_CNTL 0x0b00 856# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 857# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 858# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 859# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 860# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 861# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 862# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 863# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 864# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 865#define RADEON_SURFACE0_INFO 0x0b0c 866# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 867# define RADEON_SURF_TILE_MODE_MASK (3 << 16) 868# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 869# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 870# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 871# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 872#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 873#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 874# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 875#define RADEON_SURFACE1_INFO 0x0b1c 876#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 877#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 878#define RADEON_SURFACE2_INFO 0x0b2c 879#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 880#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 881#define RADEON_SURFACE3_INFO 0x0b3c 882#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 883#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 884#define RADEON_SURFACE4_INFO 0x0b4c 885#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 886#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 887#define RADEON_SURFACE5_INFO 0x0b5c 888#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 889#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 890#define RADEON_SURFACE6_INFO 0x0b6c 891#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 892#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 893#define RADEON_SURFACE7_INFO 0x0b7c 894#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 895#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 896#define RADEON_SW_SEMAPHORE 0x013c 897 898#define RADEON_WAIT_UNTIL 0x1720 899# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 900# define RADEON_WAIT_2D_IDLE (1 << 14) 901# define RADEON_WAIT_3D_IDLE (1 << 15) 902# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 903# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 904# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 905 906#define RADEON_RB3D_ZMASKOFFSET 0x3234 907#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 908# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 909# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 910 911/* CP registers */ 912#define RADEON_CP_ME_RAM_ADDR 0x07d4 913#define RADEON_CP_ME_RAM_RADDR 0x07d8 914#define RADEON_CP_ME_RAM_DATAH 0x07dc 915#define RADEON_CP_ME_RAM_DATAL 0x07e0 916 917#define RADEON_CP_RB_BASE 0x0700 918#define RADEON_CP_RB_CNTL 0x0704 919# define RADEON_BUF_SWAP_32BIT (2 << 16) 920# define RADEON_RB_NO_UPDATE (1 << 27) 921#define RADEON_CP_RB_RPTR_ADDR 0x070c 922#define RADEON_CP_RB_RPTR 0x0710 923#define RADEON_CP_RB_WPTR 0x0714 924 925#define RADEON_CP_RB_WPTR_DELAY 0x0718 926# define RADEON_PRE_WRITE_TIMER_SHIFT 0 927# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 928 929#define RADEON_CP_IB_BASE 0x0738 930 931#define RADEON_CP_CSQ_CNTL 0x0740 932# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 933# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 934# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 935# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 936# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 937# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 938# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 939 940#define RADEON_AIC_CNTL 0x01d0 941# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 942# define RS400_MSI_REARM (1 << 3) 943#define RADEON_AIC_STAT 0x01d4 944#define RADEON_AIC_PT_BASE 0x01d8 945#define RADEON_AIC_LO_ADDR 0x01dc 946#define RADEON_AIC_HI_ADDR 0x01e0 947#define RADEON_AIC_TLB_ADDR 0x01e4 948#define RADEON_AIC_TLB_DATA 0x01e8 949 950/* CP command packets */ 951#define RADEON_CP_PACKET0 0x00000000 952# define RADEON_ONE_REG_WR (1 << 15) 953#define RADEON_CP_PACKET1 0x40000000 954#define RADEON_CP_PACKET2 0x80000000 955#define RADEON_CP_PACKET3 0xC0000000 956# define RADEON_CP_NOP 0x00001000 957# define RADEON_CP_NEXT_CHAR 0x00001900 958# define RADEON_CP_PLY_NEXTSCAN 0x00001D00 959# define RADEON_CP_SET_SCISSORS 0x00001E00 960 /* GEN_INDX_PRIM is unsupported starting with R300 */ 961# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 962# define RADEON_WAIT_FOR_IDLE 0x00002600 963# define RADEON_3D_DRAW_VBUF 0x00002800 964# define RADEON_3D_DRAW_IMMD 0x00002900 965# define RADEON_3D_DRAW_INDX 0x00002A00 966# define RADEON_CP_LOAD_PALETTE 0x00002C00 967# define RADEON_3D_LOAD_VBPNTR 0x00002F00 968# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 969# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 970# define RADEON_3D_CLEAR_ZMASK 0x00003200 971# define RADEON_CP_INDX_BUFFER 0x00003300 972# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 973# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 974# define RADEON_CP_3D_DRAW_INDX_2 0x00003600 975# define RADEON_3D_CLEAR_HIZ 0x00003700 976# define RADEON_CP_3D_CLEAR_CMASK 0x00003802 977# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 978# define RADEON_CNTL_PAINT_MULTI 0x00009A00 979# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 980# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 981 982#define RADEON_CP_PACKET_MASK 0xC0000000 983#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 984#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 985#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 986#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 987 988#define RADEON_VTX_Z_PRESENT (1 << 31) 989#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 990 991#define RADEON_PRIM_TYPE_NONE (0 << 0) 992#define RADEON_PRIM_TYPE_POINT (1 << 0) 993#define RADEON_PRIM_TYPE_LINE (2 << 0) 994#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 995#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 996#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 997#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 998#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 999#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 1000#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 1001#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 1002#define RADEON_PRIM_TYPE_MASK 0xf 1003#define RADEON_PRIM_WALK_IND (1 << 4) 1004#define RADEON_PRIM_WALK_LIST (2 << 4) 1005#define RADEON_PRIM_WALK_RING (3 << 4) 1006#define RADEON_COLOR_ORDER_BGRA (0 << 6) 1007#define RADEON_COLOR_ORDER_RGBA (1 << 6) 1008#define RADEON_MAOS_ENABLE (1 << 7) 1009#define RADEON_VTX_FMT_R128_MODE (0 << 8) 1010#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 1011#define RADEON_NUM_VERTICES_SHIFT 16 1012 1013#define RADEON_COLOR_FORMAT_CI8 2 1014#define RADEON_COLOR_FORMAT_ARGB1555 3 1015#define RADEON_COLOR_FORMAT_RGB565 4 1016#define RADEON_COLOR_FORMAT_ARGB8888 6 1017#define RADEON_COLOR_FORMAT_RGB332 7 1018#define RADEON_COLOR_FORMAT_RGB8 9 1019#define RADEON_COLOR_FORMAT_ARGB4444 15 1020 1021#define RADEON_TXFORMAT_I8 0 1022#define RADEON_TXFORMAT_AI88 1 1023#define RADEON_TXFORMAT_RGB332 2 1024#define RADEON_TXFORMAT_ARGB1555 3 1025#define RADEON_TXFORMAT_RGB565 4 1026#define RADEON_TXFORMAT_ARGB4444 5 1027#define RADEON_TXFORMAT_ARGB8888 6 1028#define RADEON_TXFORMAT_RGBA8888 7 1029#define RADEON_TXFORMAT_Y8 8 1030#define RADEON_TXFORMAT_VYUY422 10 1031#define RADEON_TXFORMAT_YVYU422 11 1032#define RADEON_TXFORMAT_DXT1 12 1033#define RADEON_TXFORMAT_DXT23 14 1034#define RADEON_TXFORMAT_DXT45 15 1035 1036#define R200_PP_TXCBLEND_0 0x2f00 1037#define R200_PP_TXCBLEND_1 0x2f10 1038#define R200_PP_TXCBLEND_2 0x2f20 1039#define R200_PP_TXCBLEND_3 0x2f30 1040#define R200_PP_TXCBLEND_4 0x2f40 1041#define R200_PP_TXCBLEND_5 0x2f50 1042#define R200_PP_TXCBLEND_6 0x2f60 1043#define R200_PP_TXCBLEND_7 0x2f70 1044#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 1045#define R200_PP_TFACTOR_0 0x2ee0 1046#define R200_SE_VTX_FMT_0 0x2088 1047#define R200_SE_VAP_CNTL 0x2080 1048#define R200_SE_TCL_MATRIX_SEL_0 0x2230 1049#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 1050#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 1051#define R200_PP_TXFILTER_5 0x2ca0 1052#define R200_PP_TXFILTER_4 0x2c80 1053#define R200_PP_TXFILTER_3 0x2c60 1054#define R200_PP_TXFILTER_2 0x2c40 1055#define R200_PP_TXFILTER_1 0x2c20 1056#define R200_PP_TXFILTER_0 0x2c00 1057#define R200_PP_TXOFFSET_5 0x2d78 1058#define R200_PP_TXOFFSET_4 0x2d60 1059#define R200_PP_TXOFFSET_3 0x2d48 1060#define R200_PP_TXOFFSET_2 0x2d30 1061#define R200_PP_TXOFFSET_1 0x2d18 1062#define R200_PP_TXOFFSET_0 0x2d00 1063 1064#define R200_PP_CUBIC_FACES_0 0x2c18 1065#define R200_PP_CUBIC_FACES_1 0x2c38 1066#define R200_PP_CUBIC_FACES_2 0x2c58 1067#define R200_PP_CUBIC_FACES_3 0x2c78 1068#define R200_PP_CUBIC_FACES_4 0x2c98 1069#define R200_PP_CUBIC_FACES_5 0x2cb8 1070#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 1071#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 1072#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 1073#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 1074#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 1075#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 1076#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 1077#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 1078#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 1079#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 1080#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 1081#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 1082#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 1083#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 1084#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 1085#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 1086#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 1087#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 1088#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 1089#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 1090#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 1091#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 1092#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 1093#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 1094#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 1095#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 1096#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 1097#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 1098#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 1099#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 1100 1101#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1102#define R200_SE_VTE_CNTL 0x20b0 1103#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 1104#define R200_PP_TAM_DEBUG3 0x2d9c 1105#define R200_PP_CNTL_X 0x2cc4 1106#define R200_SE_VAP_CNTL_STATUS 0x2140 1107#define R200_RE_SCISSOR_TL_0 0x1cd8 1108#define R200_RE_SCISSOR_TL_1 0x1ce0 1109#define R200_RE_SCISSOR_TL_2 0x1ce8 1110#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 1111#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1112#define R200_SE_VTX_STATE_CNTL 0x2180 1113#define R200_RE_POINTSIZE 0x2648 1114#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 1115 1116#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1117#define RADEON_PP_TEX_SIZE_1 0x1d0c 1118#define RADEON_PP_TEX_SIZE_2 0x1d14 1119 1120#define RADEON_PP_CUBIC_FACES_0 0x1d24 1121#define RADEON_PP_CUBIC_FACES_1 0x1d28 1122#define RADEON_PP_CUBIC_FACES_2 0x1d2c 1123#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1124#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 1125#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 1126 1127#define RADEON_SE_TCL_STATE_FLUSH 0x2284 1128 1129#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 1130#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 1131#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 1132#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 1133#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 1134#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 1135#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 1136#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 1137#define R200_3D_DRAW_IMMD_2 0xC0003500 1138#define R200_SE_VTX_FMT_1 0x208c 1139#define R200_RE_CNTL 0x1c50 1140 1141#define R200_RB3D_BLENDCOLOR 0x3218 1142 1143#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 1144 1145#define R200_PP_TRI_PERF 0x2cf8 1146 1147#define R200_PP_AFS_0 0x2f80 1148#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 1149 1150#define R200_VAP_PVS_CNTL_1 0x22D0 1151 1152/* MPEG settings from VHA code */ 1153#define RADEON_VHA_SETTO16_1 0x2694 1154#define RADEON_VHA_SETTO16_2 0x2680 1155#define RADEON_VHA_SETTO0_1 0x1840 1156#define RADEON_VHA_FB_OFFSET 0x19e4 1157#define RADEON_VHA_SETTO1AND70S 0x19d8 1158#define RADEON_VHA_DST_PITCH 0x1408 1159 1160// set as reference header 1161#define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840 1162#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844 1163#define RADEON_VHA_BACKFRAME0_OFF_U 0x1848 1164#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c 1165#define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850 1166#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854 1167#define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858 1168#define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c 1169#define RADEON_VHA_FORWFRAME0_OFF_U 0x1860 1170#define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864 1171#define RADEON_VHA_FORWFRAME0_OFF_V 0x1868 1172#define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880 1173#define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884 1174#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888 1175#define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c 1176#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890 1177#define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894 1178#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898 1179 1180#define R500_D1CRTC_STATUS 0x609c 1181#define R500_D2CRTC_STATUS 0x689c 1182#define R500_CRTC_V_BLANK (1<<0) 1183 1184#define R500_D1CRTC_FRAME_COUNT 0x60a4 1185#define R500_D2CRTC_FRAME_COUNT 0x68a4 1186 1187#define R500_D1MODE_V_COUNTER 0x6530 1188#define R500_D2MODE_V_COUNTER 0x6d30 1189 1190#define R500_D1MODE_VBLANK_STATUS 0x6534 1191#define R500_D2MODE_VBLANK_STATUS 0x6d34 1192#define R500_VBLANK_OCCURED (1<<0) 1193#define R500_VBLANK_ACK (1<<4) 1194#define R500_VBLANK_STAT (1<<12) 1195#define R500_VBLANK_INT (1<<16) 1196 1197#define R500_DxMODE_INT_MASK 0x6540 1198#define R500_D1MODE_INT_MASK (1<<0) 1199#define R500_D2MODE_INT_MASK (1<<8) 1200 1201#define R500_DISP_INTERRUPT_STATUS 0x7edc 1202#define R500_D1_VBLANK_INTERRUPT (1 << 4) 1203#define R500_D2_VBLANK_INTERRUPT (1 << 5) 1204 1205/* Constants */ 1206#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1207 1208#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 1209#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 1210#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 1211#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 1212#define RADEON_LAST_DISPATCH 1 1213 1214#define RADEON_MAX_VB_AGE 0x7fffffff 1215#define RADEON_MAX_VB_VERTS (0xffff) 1216 1217#define RADEON_RING_HIGH_MARK 128 1218 1219#define RADEON_PCIGART_TABLE_SIZE (32*1024) 1220 1221#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 1222#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) 1223#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1224#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1225 1226#define RADEON_WRITE_PLL( addr, val ) \ 1227do { \ 1228 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 1229 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1230 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 1231} while (0) 1232 1233#define RADEON_WRITE_PCIE( addr, val ) \ 1234do { \ 1235 RADEON_WRITE8( RADEON_PCIE_INDEX, \ 1236 ((addr) & 0xff)); \ 1237 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ 1238} while (0) 1239 1240#define R500_WRITE_MCIND( addr, val ) \ 1241do { \ 1242 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1243 RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1244 RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1245} while (0) 1246 1247#define RS480_WRITE_MCIND( addr, val ) \ 1248do { \ 1249 RADEON_WRITE( RS480_NB_MC_INDEX, \ 1250 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ 1251 RADEON_WRITE( RS480_NB_MC_DATA, (val) ); \ 1252 RADEON_WRITE( RS480_NB_MC_INDEX, 0xff ); \ 1253} while (0) 1254 1255#define RS690_WRITE_MCIND( addr, val ) \ 1256do { \ 1257 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1258 RADEON_WRITE(RS690_MC_DATA, val); \ 1259 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1260} while (0) 1261 1262#define IGP_WRITE_MCIND( addr, val ) \ 1263do { \ 1264 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ 1265 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ 1266 RS690_WRITE_MCIND( addr, val ); \ 1267 else \ 1268 RS480_WRITE_MCIND( addr, val ); \ 1269} while (0) 1270 1271#define CP_PACKET0( reg, n ) \ 1272 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1273#define CP_PACKET0_TABLE( reg, n ) \ 1274 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 1275#define CP_PACKET1( reg0, reg1 ) \ 1276 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 1277#define CP_PACKET2() \ 1278 (RADEON_CP_PACKET2) 1279#define CP_PACKET3( pkt, n ) \ 1280 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1281 1282/* ================================================================ 1283 * Engine control helper macros 1284 */ 1285 1286#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 1287 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1288 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1289 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1290} while (0) 1291 1292#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 1293 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1294 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1295 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1296} while (0) 1297 1298#define RADEON_WAIT_UNTIL_IDLE() do { \ 1299 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1300 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1301 RADEON_WAIT_3D_IDLECLEAN | \ 1302 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1303} while (0) 1304 1305#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 1306 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1307 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1308} while (0) 1309 1310#define RADEON_FLUSH_CACHE() do { \ 1311 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1312 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1313 OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1314 } else { \ 1315 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1316 OUT_RING(R300_RB3D_DC_FLUSH); \ 1317 } \ 1318} while (0) 1319 1320#define RADEON_PURGE_CACHE() do { \ 1321 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1322 OUT_RING(CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1323 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ 1324 } else { \ 1325 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1326 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE ); \ 1327 } \ 1328} while (0) 1329 1330#define RADEON_FLUSH_ZCACHE() do { \ 1331 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1332 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1333 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 1334 } else { \ 1335 OUT_RING( CP_PACKET0( R300_ZB_ZCACHE_CTLSTAT, 0 ) ); \ 1336 OUT_RING( R300_ZC_FLUSH ); \ 1337 } \ 1338} while (0) 1339 1340#define RADEON_PURGE_ZCACHE() do { \ 1341 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1342 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1343 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ 1344 } else { \ 1345 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1346 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ 1347 } \ 1348} while (0) 1349 1350/* ================================================================ 1351 * Misc helper macros 1352 */ 1353 1354/* Perfbox functionality only. 1355 */ 1356#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 1357do { \ 1358 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 1359 u32 head = GET_RING_HEAD( dev_priv ); \ 1360 if (head == dev_priv->ring.tail) \ 1361 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 1362 } \ 1363} while (0) 1364 1365#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 1366do { \ 1367 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 1368 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 1369 int __ret = radeon_do_cp_idle( dev_priv ); \ 1370 if ( __ret ) return __ret; \ 1371 sarea_priv->last_dispatch = 0; \ 1372 radeon_freelist_reset( dev ); \ 1373 } \ 1374} while (0) 1375 1376#define RADEON_DISPATCH_AGE( age ) do { \ 1377 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 1378 OUT_RING( age ); \ 1379} while (0) 1380 1381#define RADEON_FRAME_AGE( age ) do { \ 1382 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 1383 OUT_RING( age ); \ 1384} while (0) 1385 1386#define RADEON_CLEAR_AGE( age ) do { \ 1387 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 1388 OUT_RING( age ); \ 1389} while (0) 1390 1391/* ================================================================ 1392 * Ring control 1393 */ 1394 1395#define RADEON_VERBOSE 0 1396 1397#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; 1398 1399#define BEGIN_RING( n ) do { \ 1400 if ( RADEON_VERBOSE ) { \ 1401 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 1402 } \ 1403 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 1404 COMMIT_RING(); \ 1405 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 1406 } \ 1407 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 1408 ring = dev_priv->ring.start; \ 1409 write = dev_priv->ring.tail; \ 1410 mask = dev_priv->ring.tail_mask; \ 1411} while (0) 1412 1413#define ADVANCE_RING() do { \ 1414 if ( RADEON_VERBOSE ) { \ 1415 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 1416 write, dev_priv->ring.tail ); \ 1417 } \ 1418 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 1419 DRM_ERROR( \ 1420 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 1421 ((dev_priv->ring.tail + _nr) & mask), \ 1422 write, __LINE__); \ 1423 } else \ 1424 dev_priv->ring.tail = write; \ 1425} while (0) 1426 1427#define COMMIT_RING() do { \ 1428 /* Flush writes to ring */ \ 1429 DRM_MEMORYBARRIER(); \ 1430 GET_RING_HEAD( dev_priv ); \ 1431 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ 1432 /* read from PCI bus to ensure correct posting */ \ 1433 RADEON_READ( RADEON_CP_RB_RPTR ); \ 1434} while (0) 1435 1436#define OUT_RING( x ) do { \ 1437 if ( RADEON_VERBOSE ) { \ 1438 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 1439 (unsigned int)(x), write ); \ 1440 } \ 1441 ring[write++] = (x); \ 1442 write &= mask; \ 1443} while (0) 1444 1445#define OUT_RING_REG( reg, val ) do { \ 1446 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 1447 OUT_RING( val ); \ 1448} while (0) 1449 1450#define OUT_RING_TABLE( tab, sz ) do { \ 1451 int _size = (sz); \ 1452 int *_tab = (int *)(tab); \ 1453 \ 1454 if (write + _size > mask) { \ 1455 int _i = (mask+1) - write; \ 1456 _size -= _i; \ 1457 while (_i > 0) { \ 1458 *(int *)(ring + write) = *_tab++; \ 1459 write++; \ 1460 _i--; \ 1461 } \ 1462 write = 0; \ 1463 _tab += _i; \ 1464 } \ 1465 while (_size > 0) { \ 1466 *(ring + write) = *_tab++; \ 1467 write++; \ 1468 _size--; \ 1469 } \ 1470 write &= mask; \ 1471} while (0) 1472 1473#endif /* __RADEON_DRV_H__ */ 1474