radeon_drv.h revision 183828
1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drv.h 183828 2008-10-13 17:38:04Z rnoland $"); 33 34#ifndef __RADEON_DRV_H__ 35#define __RADEON_DRV_H__ 36 37/* General customization: 38 */ 39 40#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 41 42#define DRIVER_NAME "radeon" 43#define DRIVER_DESC "ATI Radeon" 44#define DRIVER_DATE "20080613" 45 46/* Interface history: 47 * 48 * 1.1 - ?? 49 * 1.2 - Add vertex2 ioctl (keith) 50 * - Add stencil capability to clear ioctl (gareth, keith) 51 * - Increase MAX_TEXTURE_LEVELS (brian) 52 * 1.3 - Add cmdbuf ioctl (keith) 53 * - Add support for new radeon packets (keith) 54 * - Add getparam ioctl (keith) 55 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 56 * 1.4 - Add scratch registers to get_param ioctl. 57 * 1.5 - Add r200 packets to cmdbuf ioctl 58 * - Add r200 function to init ioctl 59 * - Add 'scalar2' instruction to cmdbuf 60 * 1.6 - Add static GART memory manager 61 * Add irq handler (won't be turned on unless X server knows to) 62 * Add irq ioctls and irq_active getparam. 63 * Add wait command for cmdbuf ioctl 64 * Add GART offset query for getparam 65 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 66 * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 67 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 68 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 69 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 70 * Add 'GET' queries for starting additional clients on different VT's. 71 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 72 * Add texture rectangle support for r100. 73 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 74 * clients use to tell the DRM where they think the framebuffer is 75 * located in the card's address space 76 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 77 * and GL_EXT_blend_[func|equation]_separate on r200 78 * 1.12- Add R300 CP microcode support - this just loads the CP on r300 79 * (No 3D support yet - just microcode loading). 80 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 81 * - Add hyperz support, add hyperz flags to clear ioctl. 82 * 1.14- Add support for color tiling 83 * - Add R100/R200 surface allocation/free support 84 * 1.15- Add support for texture micro tiling 85 * - Add support for r100 cube maps 86 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 87 * texture filtering on r200 88 * 1.17- Add initial support for R300 (3D). 89 * 1.18- Add support for GL_ATI_fragment_shader, new packets 90 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 91 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 92 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 93 * 1.19- Add support for gart table in FB memory and PCIE r300 94 * 1.20- Add support for r300 texrect 95 * 1.21- Add support for card type getparam 96 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 97 * 1.23- Add new radeon memory map work from benh 98 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 99 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, 100 * new packet type) 101 * 1.26- Add support for variable size PCI(E) gart aperture 102 * 1.27- Add support for IGP GART 103 * 1.28- Add support for VBL on CRTC2 104 * 1.29- R500 3D cmd buffer support 105 */ 106 107#define DRIVER_MAJOR 1 108#define DRIVER_MINOR 29 109#define DRIVER_PATCHLEVEL 0 110 111/* 112 * Radeon chip families 113 */ 114enum radeon_family { 115 CHIP_R100, 116 CHIP_RV100, 117 CHIP_RS100, 118 CHIP_RV200, 119 CHIP_RS200, 120 CHIP_R200, 121 CHIP_RV250, 122 CHIP_RS300, 123 CHIP_RV280, 124 CHIP_R300, 125 CHIP_R350, 126 CHIP_RV350, 127 CHIP_RV380, 128 CHIP_R420, 129 CHIP_RV410, 130 CHIP_RS400, 131 CHIP_RS480, 132 CHIP_RS690, 133 CHIP_RS740, 134 CHIP_RV515, 135 CHIP_R520, 136 CHIP_RV530, 137 CHIP_RV560, 138 CHIP_RV570, 139 CHIP_R580, 140 CHIP_LAST, 141}; 142 143/* 144 * Chip flags 145 */ 146enum radeon_chip_flags { 147 RADEON_FAMILY_MASK = 0x0000ffffUL, 148 RADEON_FLAGS_MASK = 0xffff0000UL, 149 RADEON_IS_MOBILITY = 0x00010000UL, 150 RADEON_IS_IGP = 0x00020000UL, 151 RADEON_SINGLE_CRTC = 0x00040000UL, 152 RADEON_IS_AGP = 0x00080000UL, 153 RADEON_HAS_HIERZ = 0x00100000UL, 154 RADEON_IS_PCIE = 0x00200000UL, 155 RADEON_NEW_MEMMAP = 0x00400000UL, 156 RADEON_IS_PCI = 0x00800000UL, 157 RADEON_IS_IGPGART = 0x01000000UL, 158}; 159 160#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ 161 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR)) 162#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) 163 164typedef struct drm_radeon_freelist { 165 unsigned int age; 166 struct drm_buf *buf; 167 struct drm_radeon_freelist *next; 168 struct drm_radeon_freelist *prev; 169} drm_radeon_freelist_t; 170 171typedef struct drm_radeon_ring_buffer { 172 u32 *start; 173 u32 *end; 174 int size; /* Double Words */ 175 int size_l2qw; /* log2 Quad Words */ 176 177 int rptr_update; /* Double Words */ 178 int rptr_update_l2qw; /* log2 Quad Words */ 179 180 int fetch_size; /* Double Words */ 181 int fetch_size_l2ow; /* log2 Oct Words */ 182 183 u32 tail; 184 u32 tail_mask; 185 int space; 186 187 int high_mark; 188} drm_radeon_ring_buffer_t; 189 190typedef struct drm_radeon_depth_clear_t { 191 u32 rb3d_cntl; 192 u32 rb3d_zstencilcntl; 193 u32 se_cntl; 194} drm_radeon_depth_clear_t; 195 196struct drm_radeon_driver_file_fields { 197 int64_t radeon_fb_delta; 198}; 199 200struct mem_block { 201 struct mem_block *next; 202 struct mem_block *prev; 203 int start; 204 int size; 205 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 206}; 207 208struct radeon_surface { 209 int refcount; 210 u32 lower; 211 u32 upper; 212 u32 flags; 213}; 214 215struct radeon_virt_surface { 216 int surface_index; 217 u32 lower; 218 u32 upper; 219 u32 flags; 220 struct drm_file *file_priv; 221}; 222 223#define RADEON_FLUSH_EMITED (1 < 0) 224#define RADEON_PURGE_EMITED (1 < 1) 225 226typedef struct drm_radeon_private { 227 228 drm_radeon_ring_buffer_t ring; 229 drm_radeon_sarea_t *sarea_priv; 230 231 u32 fb_location; 232 u32 fb_size; 233 int new_memmap; 234 235 int gart_size; 236 u32 gart_vm_start; 237 unsigned long gart_buffers_offset; 238 239 int cp_mode; 240 int cp_running; 241 242 drm_radeon_freelist_t *head; 243 drm_radeon_freelist_t *tail; 244 int last_buf; 245 volatile u32 *scratch; 246 int writeback_works; 247 248 int usec_timeout; 249 250 struct { 251 u32 boxes; 252 int freelist_timeouts; 253 int freelist_loops; 254 int requested_bufs; 255 int last_frame_reads; 256 int last_clear_reads; 257 int clears; 258 int texture_uploads; 259 } stats; 260 261 int do_boxes; 262 int page_flipping; 263 264 u32 color_fmt; 265 unsigned int front_offset; 266 unsigned int front_pitch; 267 unsigned int back_offset; 268 unsigned int back_pitch; 269 270 u32 depth_fmt; 271 unsigned int depth_offset; 272 unsigned int depth_pitch; 273 274 u32 front_pitch_offset; 275 u32 back_pitch_offset; 276 u32 depth_pitch_offset; 277 278 drm_radeon_depth_clear_t depth_clear; 279 280 unsigned long ring_offset; 281 unsigned long ring_rptr_offset; 282 unsigned long buffers_offset; 283 unsigned long gart_textures_offset; 284 285 drm_local_map_t *sarea; 286 drm_local_map_t *mmio; 287 drm_local_map_t *cp_ring; 288 drm_local_map_t *ring_rptr; 289 drm_local_map_t *gart_textures; 290 291 struct mem_block *gart_heap; 292 struct mem_block *fb_heap; 293 294 /* SW interrupt */ 295 wait_queue_head_t swi_queue; 296 atomic_t swi_emitted; 297 int vblank_crtc; 298 uint32_t irq_enable_reg; 299 int irq_enabled; 300 uint32_t r500_disp_irq_reg; 301 302 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 303 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 304 305 unsigned long pcigart_offset; 306 unsigned int pcigart_offset_set; 307 struct drm_ati_pcigart_info gart_info; 308 309 u32 scratch_ages[5]; 310 311 unsigned int crtc_last_cnt; 312 unsigned int crtc2_last_cnt; 313 314 /* starting from here on, data is preserved accross an open */ 315 uint32_t flags; /* see radeon_chip_flags */ 316 unsigned long fb_aper_offset; 317 318 int num_gb_pipes; 319 int track_flush; 320 uint32_t chip_family; /* extract from flags */ 321} drm_radeon_private_t; 322 323typedef struct drm_radeon_buf_priv { 324 u32 age; 325} drm_radeon_buf_priv_t; 326 327typedef struct drm_radeon_kcmd_buffer { 328 int bufsz; 329 char *buf; 330 int nbox; 331 struct drm_clip_rect __user *boxes; 332} drm_radeon_kcmd_buffer_t; 333 334extern int radeon_no_wb; 335extern struct drm_ioctl_desc radeon_ioctls[]; 336extern int radeon_max_ioctl; 337 338/* Check whether the given hardware address is inside the framebuffer or the 339 * GART area. 340 */ 341static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, 342 u64 off) 343{ 344 u32 fb_start = dev_priv->fb_location; 345 u32 fb_end = fb_start + dev_priv->fb_size - 1; 346 u32 gart_start = dev_priv->gart_vm_start; 347 u32 gart_end = gart_start + dev_priv->gart_size - 1; 348 349 return ((off >= fb_start && off <= fb_end) || 350 (off >= gart_start && off <= gart_end)); 351} 352 353 /* radeon_cp.c */ 354extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 355extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 356extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 357extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 358extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 359extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); 360extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 361extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 362extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 363extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); 364 365extern void radeon_freelist_reset(struct drm_device * dev); 366extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); 367 368extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 369 370extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 371 372extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); 373extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); 374extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); 375extern void radeon_mem_takedown(struct mem_block **heap); 376extern void radeon_mem_release(struct drm_file *file_priv, 377 struct mem_block *heap); 378 379 /* radeon_irq.c */ 380extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); 381extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); 382extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); 383 384extern void radeon_do_release(struct drm_device * dev); 385extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); 386extern int radeon_enable_vblank(struct drm_device *dev, int crtc); 387extern void radeon_disable_vblank(struct drm_device *dev, int crtc); 388extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 389extern void radeon_driver_irq_preinstall(struct drm_device * dev); 390extern int radeon_driver_irq_postinstall(struct drm_device * dev); 391extern void radeon_driver_irq_uninstall(struct drm_device * dev); 392extern int radeon_vblank_crtc_get(struct drm_device *dev); 393extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 394 395extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 396extern int radeon_driver_unload(struct drm_device *dev); 397extern int radeon_driver_firstopen(struct drm_device *dev); 398extern void radeon_driver_preclose(struct drm_device * dev, 399 struct drm_file *file_priv); 400extern void radeon_driver_postclose(struct drm_device * dev, 401 struct drm_file *file_priv); 402extern void radeon_driver_lastclose(struct drm_device * dev); 403extern int radeon_driver_open(struct drm_device * dev, 404 struct drm_file * file_priv); 405extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 406 unsigned long arg); 407 408/* r300_cmdbuf.c */ 409extern void r300_init_reg_flags(struct drm_device *dev); 410 411extern int r300_do_cp_cmdbuf(struct drm_device *dev, 412 struct drm_file *file_priv, 413 drm_radeon_kcmd_buffer_t *cmdbuf); 414 415/* Flags for stats.boxes 416 */ 417#define RADEON_BOX_DMA_IDLE 0x1 418#define RADEON_BOX_RING_FULL 0x2 419#define RADEON_BOX_FLIP 0x4 420#define RADEON_BOX_WAIT_IDLE 0x8 421#define RADEON_BOX_TEXTURE_LOAD 0x10 422 423/* Register definitions, register access macros and drmAddMap constants 424 * for Radeon kernel driver. 425 */ 426#define RADEON_AGP_COMMAND 0x0f60 427#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 428# define RADEON_AGP_ENABLE (1<<8) 429#define RADEON_AUX_SCISSOR_CNTL 0x26f0 430# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 431# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 432# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 433# define RADEON_SCISSOR_0_ENABLE (1 << 28) 434# define RADEON_SCISSOR_1_ENABLE (1 << 29) 435# define RADEON_SCISSOR_2_ENABLE (1 << 30) 436 437#define RADEON_BUS_CNTL 0x0030 438# define RADEON_BUS_MASTER_DIS (1 << 6) 439 440#define RADEON_CLOCK_CNTL_DATA 0x000c 441# define RADEON_PLL_WR_EN (1 << 7) 442#define RADEON_CLOCK_CNTL_INDEX 0x0008 443#define RADEON_CONFIG_APER_SIZE 0x0108 444#define RADEON_CONFIG_MEMSIZE 0x00f8 445#define RADEON_CRTC_OFFSET 0x0224 446#define RADEON_CRTC_OFFSET_CNTL 0x0228 447# define RADEON_CRTC_TILE_EN (1 << 15) 448# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 449#define RADEON_CRTC2_OFFSET 0x0324 450#define RADEON_CRTC2_OFFSET_CNTL 0x0328 451 452#define RADEON_PCIE_INDEX 0x0030 453#define RADEON_PCIE_DATA 0x0034 454#define RADEON_PCIE_TX_GART_CNTL 0x10 455# define RADEON_PCIE_TX_GART_EN (1 << 0) 456# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) 457# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) 458# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) 459# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) 460# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) 461# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) 462# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) 463#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 464#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 465#define RADEON_PCIE_TX_GART_BASE 0x13 466#define RADEON_PCIE_TX_GART_START_LO 0x14 467#define RADEON_PCIE_TX_GART_START_HI 0x15 468#define RADEON_PCIE_TX_GART_END_LO 0x16 469#define RADEON_PCIE_TX_GART_END_HI 0x17 470 471#define RS480_NB_MC_INDEX 0x168 472# define RS480_NB_MC_IND_WR_EN (1 << 8) 473#define RS480_NB_MC_DATA 0x16c 474 475#define RS690_MC_INDEX 0x78 476# define RS690_MC_INDEX_MASK 0x1ff 477# define RS690_MC_INDEX_WR_EN (1 << 9) 478# define RS690_MC_INDEX_WR_ACK 0x7f 479#define RS690_MC_DATA 0x7c 480 481/* MC indirect registers */ 482#define RS480_MC_MISC_CNTL 0x18 483# define RS480_DISABLE_GTW (1 << 1) 484/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ 485# define RS480_GART_INDEX_REG_EN (1 << 12) 486# define RS690_BLOCK_GFX_D3_EN (1 << 14) 487#define RS480_K8_FB_LOCATION 0x1e 488#define RS480_GART_FEATURE_ID 0x2b 489# define RS480_HANG_EN (1 << 11) 490# define RS480_TLB_ENABLE (1 << 18) 491# define RS480_P2P_ENABLE (1 << 19) 492# define RS480_GTW_LAC_EN (1 << 25) 493# define RS480_2LEVEL_GART (0 << 30) 494# define RS480_1LEVEL_GART (1 << 30) 495# define RS480_PDC_EN (1 << 31) 496#define RS480_GART_BASE 0x2c 497#define RS480_GART_CACHE_CNTRL 0x2e 498# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 499#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 500# define RS480_GART_EN (1 << 0) 501# define RS480_VA_SIZE_32MB (0 << 1) 502# define RS480_VA_SIZE_64MB (1 << 1) 503# define RS480_VA_SIZE_128MB (2 << 1) 504# define RS480_VA_SIZE_256MB (3 << 1) 505# define RS480_VA_SIZE_512MB (4 << 1) 506# define RS480_VA_SIZE_1GB (5 << 1) 507# define RS480_VA_SIZE_2GB (6 << 1) 508#define RS480_AGP_MODE_CNTL 0x39 509# define RS480_POST_GART_Q_SIZE (1 << 18) 510# define RS480_NONGART_SNOOP (1 << 19) 511# define RS480_AGP_RD_BUF_SIZE (1 << 20) 512# define RS480_REQ_TYPE_SNOOP_SHIFT 22 513# define RS480_REQ_TYPE_SNOOP_MASK 0x3 514# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 515#define RS480_MC_MISC_UMA_CNTL 0x5f 516#define RS480_MC_MCLK_CNTL 0x7a 517#define RS480_MC_UMA_DUALCH_CNTL 0x86 518 519#define RS690_MC_FB_LOCATION 0x100 520#define RS690_MC_AGP_LOCATION 0x101 521#define RS690_MC_AGP_BASE 0x102 522#define RS690_MC_AGP_BASE_2 0x103 523 524#define R520_MC_IND_INDEX 0x70 525#define R520_MC_IND_WR_EN (1 << 24) 526#define R520_MC_IND_DATA 0x74 527 528#define RV515_MC_FB_LOCATION 0x01 529#define RV515_MC_AGP_LOCATION 0x02 530#define RV515_MC_AGP_BASE 0x03 531#define RV515_MC_AGP_BASE_2 0x04 532 533#define R520_MC_FB_LOCATION 0x04 534#define R520_MC_AGP_LOCATION 0x05 535#define R520_MC_AGP_BASE 0x06 536#define R520_MC_AGP_BASE_2 0x07 537 538#define RADEON_MPP_TB_CONFIG 0x01c0 539#define RADEON_MEM_CNTL 0x0140 540#define RADEON_MEM_SDRAM_MODE_REG 0x0158 541#define RADEON_AGP_BASE_2 0x015c /* r200+ only */ 542#define RS480_AGP_BASE_2 0x0164 543#define RADEON_AGP_BASE 0x0170 544 545/* pipe config regs */ 546#define R400_GB_PIPE_SELECT 0x402c 547#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 548#define R500_SU_REG_DEST 0x42c8 549#define R300_GB_TILE_CONFIG 0x4018 550# define R300_ENABLE_TILING (1 << 0) 551# define R300_PIPE_COUNT_RV350 (0 << 1) 552# define R300_PIPE_COUNT_R300 (3 << 1) 553# define R300_PIPE_COUNT_R420_3P (6 << 1) 554# define R300_PIPE_COUNT_R420 (7 << 1) 555# define R300_TILE_SIZE_8 (0 << 4) 556# define R300_TILE_SIZE_16 (1 << 4) 557# define R300_TILE_SIZE_32 (2 << 4) 558# define R300_SUBPIXEL_1_12 (0 << 16) 559# define R300_SUBPIXEL_1_16 (1 << 16) 560#define R300_DST_PIPE_CONFIG 0x170c 561# define R300_PIPE_AUTO_CONFIG (1 << 31) 562#define R300_RB2D_DSTCACHE_MODE 0x3428 563# define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 564# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 565 566#define RADEON_RB3D_COLOROFFSET 0x1c40 567#define RADEON_RB3D_COLORPITCH 0x1c48 568 569#define RADEON_SRC_X_Y 0x1590 570 571#define RADEON_DP_GUI_MASTER_CNTL 0x146c 572# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 573# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 574# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 575# define RADEON_GMC_BRUSH_NONE (15 << 4) 576# define RADEON_GMC_DST_16BPP (4 << 8) 577# define RADEON_GMC_DST_24BPP (5 << 8) 578# define RADEON_GMC_DST_32BPP (6 << 8) 579# define RADEON_GMC_DST_DATATYPE_SHIFT 8 580# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 581# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 582# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 583# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 584# define RADEON_GMC_WR_MSK_DIS (1 << 30) 585# define RADEON_ROP3_S 0x00cc0000 586# define RADEON_ROP3_P 0x00f00000 587#define RADEON_DP_WRITE_MASK 0x16cc 588#define RADEON_SRC_PITCH_OFFSET 0x1428 589#define RADEON_DST_PITCH_OFFSET 0x142c 590#define RADEON_DST_PITCH_OFFSET_C 0x1c80 591# define RADEON_DST_TILE_LINEAR (0 << 30) 592# define RADEON_DST_TILE_MACRO (1 << 30) 593# define RADEON_DST_TILE_MICRO (2 << 30) 594# define RADEON_DST_TILE_BOTH (3 << 30) 595 596#define RADEON_SCRATCH_REG0 0x15e0 597#define RADEON_SCRATCH_REG1 0x15e4 598#define RADEON_SCRATCH_REG2 0x15e8 599#define RADEON_SCRATCH_REG3 0x15ec 600#define RADEON_SCRATCH_REG4 0x15f0 601#define RADEON_SCRATCH_REG5 0x15f4 602#define RADEON_SCRATCH_UMSK 0x0770 603#define RADEON_SCRATCH_ADDR 0x0774 604 605#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 606 607#define GET_SCRATCH( x ) (dev_priv->writeback_works \ 608 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ 609 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) 610 611#define RADEON_CRTC_CRNT_FRAME 0x0214 612#define RADEON_CRTC2_CRNT_FRAME 0x0314 613 614#define RADEON_CRTC_STATUS 0x005c 615#define RADEON_CRTC2_STATUS 0x03fc 616 617#define RADEON_GEN_INT_CNTL 0x0040 618# define RADEON_CRTC_VBLANK_MASK (1 << 0) 619# define RADEON_CRTC2_VBLANK_MASK (1 << 9) 620# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 621# define RADEON_SW_INT_ENABLE (1 << 25) 622 623#define RADEON_GEN_INT_STATUS 0x0044 624# define RADEON_CRTC_VBLANK_STAT (1 << 0) 625# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 626# define RADEON_CRTC2_VBLANK_STAT (1 << 9) 627# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 628# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 629# define RADEON_SW_INT_TEST (1 << 25) 630# define RADEON_SW_INT_TEST_ACK (1 << 25) 631# define RADEON_SW_INT_FIRE (1 << 26) 632# define R500_DISPLAY_INT_STATUS (1 << 0) 633 634 635#define RADEON_HOST_PATH_CNTL 0x0130 636# define RADEON_HDP_SOFT_RESET (1 << 26) 637# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 638# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 639 640#define RADEON_ISYNC_CNTL 0x1724 641# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 642# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 643# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 644# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 645# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 646# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 647 648#define RADEON_RBBM_GUICNTL 0x172c 649# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 650# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 651# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 652# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 653 654#define RADEON_MC_AGP_LOCATION 0x014c 655#define RADEON_MC_FB_LOCATION 0x0148 656#define RADEON_MCLK_CNTL 0x0012 657# define RADEON_FORCEON_MCLKA (1 << 16) 658# define RADEON_FORCEON_MCLKB (1 << 17) 659# define RADEON_FORCEON_YCLKA (1 << 18) 660# define RADEON_FORCEON_YCLKB (1 << 19) 661# define RADEON_FORCEON_MC (1 << 20) 662# define RADEON_FORCEON_AIC (1 << 21) 663 664#define RADEON_PP_BORDER_COLOR_0 0x1d40 665#define RADEON_PP_BORDER_COLOR_1 0x1d44 666#define RADEON_PP_BORDER_COLOR_2 0x1d48 667#define RADEON_PP_CNTL 0x1c38 668# define RADEON_SCISSOR_ENABLE (1 << 1) 669#define RADEON_PP_LUM_MATRIX 0x1d00 670#define RADEON_PP_MISC 0x1c14 671#define RADEON_PP_ROT_MATRIX_0 0x1d58 672#define RADEON_PP_TXFILTER_0 0x1c54 673#define RADEON_PP_TXOFFSET_0 0x1c5c 674#define RADEON_PP_TXFILTER_1 0x1c6c 675#define RADEON_PP_TXFILTER_2 0x1c84 676 677#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ 678#define R300_DSTCACHE_CTLSTAT 0x1714 679# define R300_RB2D_DC_FLUSH (3 << 0) 680# define R300_RB2D_DC_FREE (3 << 2) 681# define R300_RB2D_DC_FLUSH_ALL 0xf 682# define R300_RB2D_DC_BUSY (1 << 31) 683#define RADEON_RB3D_CNTL 0x1c3c 684# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 685# define RADEON_PLANE_MASK_ENABLE (1 << 1) 686# define RADEON_DITHER_ENABLE (1 << 2) 687# define RADEON_ROUND_ENABLE (1 << 3) 688# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 689# define RADEON_DITHER_INIT (1 << 5) 690# define RADEON_ROP_ENABLE (1 << 6) 691# define RADEON_STENCIL_ENABLE (1 << 7) 692# define RADEON_Z_ENABLE (1 << 8) 693# define RADEON_ZBLOCK16 (1 << 15) 694#define RADEON_RB3D_DEPTHOFFSET 0x1c24 695#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 696#define RADEON_RB3D_DEPTHPITCH 0x1c28 697#define RADEON_RB3D_PLANEMASK 0x1d84 698#define RADEON_RB3D_STENCILREFMASK 0x1d7c 699#define RADEON_RB3D_ZCACHE_MODE 0x3250 700#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 701# define RADEON_RB3D_ZC_FLUSH (1 << 0) 702# define RADEON_RB3D_ZC_FREE (1 << 2) 703# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 704# define RADEON_RB3D_ZC_BUSY (1 << 31) 705#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 706# define R300_ZC_FLUSH (1 << 0) 707# define R300_ZC_FREE (1 << 1) 708# define R300_ZC_BUSY (1 << 31) 709#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 710# define RADEON_RB3D_DC_FLUSH (3 << 0) 711# define RADEON_RB3D_DC_FREE (3 << 2) 712# define RADEON_RB3D_DC_FLUSH_ALL 0xf 713# define RADEON_RB3D_DC_BUSY (1 << 31) 714#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 715# define R300_RB3D_DC_FLUSH (2 << 0) 716# define R300_RB3D_DC_FREE (2 << 2) 717# define R300_RB3D_DC_FINISH (1 << 4) 718#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 719# define RADEON_Z_TEST_MASK (7 << 4) 720# define RADEON_Z_TEST_ALWAYS (7 << 4) 721# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 722# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 723# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 724# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 725# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 726# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 727# define RADEON_FORCE_Z_DIRTY (1 << 29) 728# define RADEON_Z_WRITE_ENABLE (1 << 30) 729# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 730#define RADEON_RBBM_SOFT_RESET 0x00f0 731# define RADEON_SOFT_RESET_CP (1 << 0) 732# define RADEON_SOFT_RESET_HI (1 << 1) 733# define RADEON_SOFT_RESET_SE (1 << 2) 734# define RADEON_SOFT_RESET_RE (1 << 3) 735# define RADEON_SOFT_RESET_PP (1 << 4) 736# define RADEON_SOFT_RESET_E2 (1 << 5) 737# define RADEON_SOFT_RESET_RB (1 << 6) 738# define RADEON_SOFT_RESET_HDP (1 << 7) 739/* 740 * 6:0 Available slots in the FIFO 741 * 8 Host Interface active 742 * 9 CP request active 743 * 10 FIFO request active 744 * 11 Host Interface retry active 745 * 12 CP retry active 746 * 13 FIFO retry active 747 * 14 FIFO pipeline busy 748 * 15 Event engine busy 749 * 16 CP command stream busy 750 * 17 2D engine busy 751 * 18 2D portion of render backend busy 752 * 20 3D setup engine busy 753 * 26 GA engine busy 754 * 27 CBA 2D engine busy 755 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or 756 * command stream queue not empty or Ring Buffer not empty 757 */ 758#define RADEON_RBBM_STATUS 0x0e40 759/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ 760/* #define RADEON_RBBM_STATUS 0x1740 */ 761/* bits 6:0 are dword slots available in the cmd fifo */ 762# define RADEON_RBBM_FIFOCNT_MASK 0x007f 763# define RADEON_HIRQ_ON_RBB (1 << 8) 764# define RADEON_CPRQ_ON_RBB (1 << 9) 765# define RADEON_CFRQ_ON_RBB (1 << 10) 766# define RADEON_HIRQ_IN_RTBUF (1 << 11) 767# define RADEON_CPRQ_IN_RTBUF (1 << 12) 768# define RADEON_CFRQ_IN_RTBUF (1 << 13) 769# define RADEON_PIPE_BUSY (1 << 14) 770# define RADEON_ENG_EV_BUSY (1 << 15) 771# define RADEON_CP_CMDSTRM_BUSY (1 << 16) 772# define RADEON_E2_BUSY (1 << 17) 773# define RADEON_RB2D_BUSY (1 << 18) 774# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ 775# define RADEON_VAP_BUSY (1 << 20) 776# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ 777# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ 778# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ 779# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ 780# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ 781# define RADEON_GA_BUSY (1 << 26) 782# define RADEON_CBA2D_BUSY (1 << 27) 783# define RADEON_RBBM_ACTIVE (1 << 31) 784#define RADEON_RE_LINE_PATTERN 0x1cd0 785#define RADEON_RE_MISC 0x26c4 786#define RADEON_RE_TOP_LEFT 0x26c0 787#define RADEON_RE_WIDTH_HEIGHT 0x1c44 788#define RADEON_RE_STIPPLE_ADDR 0x1cc8 789#define RADEON_RE_STIPPLE_DATA 0x1ccc 790 791#define RADEON_SCISSOR_TL_0 0x1cd8 792#define RADEON_SCISSOR_BR_0 0x1cdc 793#define RADEON_SCISSOR_TL_1 0x1ce0 794#define RADEON_SCISSOR_BR_1 0x1ce4 795#define RADEON_SCISSOR_TL_2 0x1ce8 796#define RADEON_SCISSOR_BR_2 0x1cec 797#define RADEON_SE_COORD_FMT 0x1c50 798#define RADEON_SE_CNTL 0x1c4c 799# define RADEON_FFACE_CULL_CW (0 << 0) 800# define RADEON_BFACE_SOLID (3 << 1) 801# define RADEON_FFACE_SOLID (3 << 3) 802# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 803# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 804# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 805# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 806# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 807# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 808# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 809# define RADEON_FOG_SHADE_FLAT (1 << 14) 810# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 811# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 812# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 813# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 814# define RADEON_ROUND_MODE_TRUNC (0 << 28) 815# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 816#define RADEON_SE_CNTL_STATUS 0x2140 817#define RADEON_SE_LINE_WIDTH 0x1db8 818#define RADEON_SE_VPORT_XSCALE 0x1d98 819#define RADEON_SE_ZBIAS_FACTOR 0x1db0 820#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 821#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 822#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 823# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 824# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 825#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 826#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 827# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 828#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 829#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 830#define RADEON_SURFACE_ACCESS_CLR 0x0bfc 831#define RADEON_SURFACE_CNTL 0x0b00 832# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 833# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 834# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 835# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 836# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 837# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 838# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 839# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 840# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 841#define RADEON_SURFACE0_INFO 0x0b0c 842# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 843# define RADEON_SURF_TILE_MODE_MASK (3 << 16) 844# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 845# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 846# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 847# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 848#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 849#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 850# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 851#define RADEON_SURFACE1_INFO 0x0b1c 852#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 853#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 854#define RADEON_SURFACE2_INFO 0x0b2c 855#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 856#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 857#define RADEON_SURFACE3_INFO 0x0b3c 858#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 859#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 860#define RADEON_SURFACE4_INFO 0x0b4c 861#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 862#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 863#define RADEON_SURFACE5_INFO 0x0b5c 864#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 865#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 866#define RADEON_SURFACE6_INFO 0x0b6c 867#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 868#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 869#define RADEON_SURFACE7_INFO 0x0b7c 870#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 871#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 872#define RADEON_SW_SEMAPHORE 0x013c 873 874#define RADEON_WAIT_UNTIL 0x1720 875# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 876# define RADEON_WAIT_2D_IDLE (1 << 14) 877# define RADEON_WAIT_3D_IDLE (1 << 15) 878# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 879# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 880# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 881 882#define RADEON_RB3D_ZMASKOFFSET 0x3234 883#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 884# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 885# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 886 887/* CP registers */ 888#define RADEON_CP_ME_RAM_ADDR 0x07d4 889#define RADEON_CP_ME_RAM_RADDR 0x07d8 890#define RADEON_CP_ME_RAM_DATAH 0x07dc 891#define RADEON_CP_ME_RAM_DATAL 0x07e0 892 893#define RADEON_CP_RB_BASE 0x0700 894#define RADEON_CP_RB_CNTL 0x0704 895# define RADEON_BUF_SWAP_32BIT (2 << 16) 896# define RADEON_RB_NO_UPDATE (1 << 27) 897#define RADEON_CP_RB_RPTR_ADDR 0x070c 898#define RADEON_CP_RB_RPTR 0x0710 899#define RADEON_CP_RB_WPTR 0x0714 900 901#define RADEON_CP_RB_WPTR_DELAY 0x0718 902# define RADEON_PRE_WRITE_TIMER_SHIFT 0 903# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 904 905#define RADEON_CP_IB_BASE 0x0738 906 907#define RADEON_CP_CSQ_CNTL 0x0740 908# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 909# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 910# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 911# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 912# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 913# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 914# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 915 916#define RADEON_AIC_CNTL 0x01d0 917# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 918#define RADEON_AIC_STAT 0x01d4 919#define RADEON_AIC_PT_BASE 0x01d8 920#define RADEON_AIC_LO_ADDR 0x01dc 921#define RADEON_AIC_HI_ADDR 0x01e0 922#define RADEON_AIC_TLB_ADDR 0x01e4 923#define RADEON_AIC_TLB_DATA 0x01e8 924 925/* CP command packets */ 926#define RADEON_CP_PACKET0 0x00000000 927# define RADEON_ONE_REG_WR (1 << 15) 928#define RADEON_CP_PACKET1 0x40000000 929#define RADEON_CP_PACKET2 0x80000000 930#define RADEON_CP_PACKET3 0xC0000000 931# define RADEON_CP_NOP 0x00001000 932# define RADEON_CP_NEXT_CHAR 0x00001900 933# define RADEON_CP_PLY_NEXTSCAN 0x00001D00 934# define RADEON_CP_SET_SCISSORS 0x00001E00 935 /* GEN_INDX_PRIM is unsupported starting with R300 */ 936# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 937# define RADEON_WAIT_FOR_IDLE 0x00002600 938# define RADEON_3D_DRAW_VBUF 0x00002800 939# define RADEON_3D_DRAW_IMMD 0x00002900 940# define RADEON_3D_DRAW_INDX 0x00002A00 941# define RADEON_CP_LOAD_PALETTE 0x00002C00 942# define RADEON_3D_LOAD_VBPNTR 0x00002F00 943# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 944# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 945# define RADEON_3D_CLEAR_ZMASK 0x00003200 946# define RADEON_CP_INDX_BUFFER 0x00003300 947# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 948# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 949# define RADEON_CP_3D_DRAW_INDX_2 0x00003600 950# define RADEON_3D_CLEAR_HIZ 0x00003700 951# define RADEON_CP_3D_CLEAR_CMASK 0x00003802 952# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 953# define RADEON_CNTL_PAINT_MULTI 0x00009A00 954# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 955# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 956 957#define RADEON_CP_PACKET_MASK 0xC0000000 958#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 959#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 960#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 961#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 962 963#define RADEON_VTX_Z_PRESENT (1 << 31) 964#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 965 966#define RADEON_PRIM_TYPE_NONE (0 << 0) 967#define RADEON_PRIM_TYPE_POINT (1 << 0) 968#define RADEON_PRIM_TYPE_LINE (2 << 0) 969#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 970#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 971#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 972#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 973#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 974#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 975#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 976#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 977#define RADEON_PRIM_TYPE_MASK 0xf 978#define RADEON_PRIM_WALK_IND (1 << 4) 979#define RADEON_PRIM_WALK_LIST (2 << 4) 980#define RADEON_PRIM_WALK_RING (3 << 4) 981#define RADEON_COLOR_ORDER_BGRA (0 << 6) 982#define RADEON_COLOR_ORDER_RGBA (1 << 6) 983#define RADEON_MAOS_ENABLE (1 << 7) 984#define RADEON_VTX_FMT_R128_MODE (0 << 8) 985#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 986#define RADEON_NUM_VERTICES_SHIFT 16 987 988#define RADEON_COLOR_FORMAT_CI8 2 989#define RADEON_COLOR_FORMAT_ARGB1555 3 990#define RADEON_COLOR_FORMAT_RGB565 4 991#define RADEON_COLOR_FORMAT_ARGB8888 6 992#define RADEON_COLOR_FORMAT_RGB332 7 993#define RADEON_COLOR_FORMAT_RGB8 9 994#define RADEON_COLOR_FORMAT_ARGB4444 15 995 996#define RADEON_TXFORMAT_I8 0 997#define RADEON_TXFORMAT_AI88 1 998#define RADEON_TXFORMAT_RGB332 2 999#define RADEON_TXFORMAT_ARGB1555 3 1000#define RADEON_TXFORMAT_RGB565 4 1001#define RADEON_TXFORMAT_ARGB4444 5 1002#define RADEON_TXFORMAT_ARGB8888 6 1003#define RADEON_TXFORMAT_RGBA8888 7 1004#define RADEON_TXFORMAT_Y8 8 1005#define RADEON_TXFORMAT_VYUY422 10 1006#define RADEON_TXFORMAT_YVYU422 11 1007#define RADEON_TXFORMAT_DXT1 12 1008#define RADEON_TXFORMAT_DXT23 14 1009#define RADEON_TXFORMAT_DXT45 15 1010 1011#define R200_PP_TXCBLEND_0 0x2f00 1012#define R200_PP_TXCBLEND_1 0x2f10 1013#define R200_PP_TXCBLEND_2 0x2f20 1014#define R200_PP_TXCBLEND_3 0x2f30 1015#define R200_PP_TXCBLEND_4 0x2f40 1016#define R200_PP_TXCBLEND_5 0x2f50 1017#define R200_PP_TXCBLEND_6 0x2f60 1018#define R200_PP_TXCBLEND_7 0x2f70 1019#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 1020#define R200_PP_TFACTOR_0 0x2ee0 1021#define R200_SE_VTX_FMT_0 0x2088 1022#define R200_SE_VAP_CNTL 0x2080 1023#define R200_SE_TCL_MATRIX_SEL_0 0x2230 1024#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 1025#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 1026#define R200_PP_TXFILTER_5 0x2ca0 1027#define R200_PP_TXFILTER_4 0x2c80 1028#define R200_PP_TXFILTER_3 0x2c60 1029#define R200_PP_TXFILTER_2 0x2c40 1030#define R200_PP_TXFILTER_1 0x2c20 1031#define R200_PP_TXFILTER_0 0x2c00 1032#define R200_PP_TXOFFSET_5 0x2d78 1033#define R200_PP_TXOFFSET_4 0x2d60 1034#define R200_PP_TXOFFSET_3 0x2d48 1035#define R200_PP_TXOFFSET_2 0x2d30 1036#define R200_PP_TXOFFSET_1 0x2d18 1037#define R200_PP_TXOFFSET_0 0x2d00 1038 1039#define R200_PP_CUBIC_FACES_0 0x2c18 1040#define R200_PP_CUBIC_FACES_1 0x2c38 1041#define R200_PP_CUBIC_FACES_2 0x2c58 1042#define R200_PP_CUBIC_FACES_3 0x2c78 1043#define R200_PP_CUBIC_FACES_4 0x2c98 1044#define R200_PP_CUBIC_FACES_5 0x2cb8 1045#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 1046#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 1047#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 1048#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 1049#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 1050#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 1051#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 1052#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 1053#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 1054#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 1055#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 1056#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 1057#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 1058#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 1059#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 1060#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 1061#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 1062#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 1063#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 1064#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 1065#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 1066#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 1067#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 1068#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 1069#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 1070#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 1071#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 1072#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 1073#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 1074#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 1075 1076#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1077#define R200_SE_VTE_CNTL 0x20b0 1078#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 1079#define R200_PP_TAM_DEBUG3 0x2d9c 1080#define R200_PP_CNTL_X 0x2cc4 1081#define R200_SE_VAP_CNTL_STATUS 0x2140 1082#define R200_RE_SCISSOR_TL_0 0x1cd8 1083#define R200_RE_SCISSOR_TL_1 0x1ce0 1084#define R200_RE_SCISSOR_TL_2 0x1ce8 1085#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 1086#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1087#define R200_SE_VTX_STATE_CNTL 0x2180 1088#define R200_RE_POINTSIZE 0x2648 1089#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 1090 1091#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1092#define RADEON_PP_TEX_SIZE_1 0x1d0c 1093#define RADEON_PP_TEX_SIZE_2 0x1d14 1094 1095#define RADEON_PP_CUBIC_FACES_0 0x1d24 1096#define RADEON_PP_CUBIC_FACES_1 0x1d28 1097#define RADEON_PP_CUBIC_FACES_2 0x1d2c 1098#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1099#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 1100#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 1101 1102#define RADEON_SE_TCL_STATE_FLUSH 0x2284 1103 1104#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 1105#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 1106#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 1107#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 1108#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 1109#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 1110#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 1111#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 1112#define R200_3D_DRAW_IMMD_2 0xC0003500 1113#define R200_SE_VTX_FMT_1 0x208c 1114#define R200_RE_CNTL 0x1c50 1115 1116#define R200_RB3D_BLENDCOLOR 0x3218 1117 1118#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 1119 1120#define R200_PP_TRI_PERF 0x2cf8 1121 1122#define R200_PP_AFS_0 0x2f80 1123#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 1124 1125#define R200_VAP_PVS_CNTL_1 0x22D0 1126 1127/* MPEG settings from VHA code */ 1128#define RADEON_VHA_SETTO16_1 0x2694 1129#define RADEON_VHA_SETTO16_2 0x2680 1130#define RADEON_VHA_SETTO0_1 0x1840 1131#define RADEON_VHA_FB_OFFSET 0x19e4 1132#define RADEON_VHA_SETTO1AND70S 0x19d8 1133#define RADEON_VHA_DST_PITCH 0x1408 1134 1135// set as reference header 1136#define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840 1137#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844 1138#define RADEON_VHA_BACKFRAME0_OFF_U 0x1848 1139#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c 1140#define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850 1141#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854 1142#define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858 1143#define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c 1144#define RADEON_VHA_FORWFRAME0_OFF_U 0x1860 1145#define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864 1146#define RADEON_VHA_FORWFRAME0_OFF_V 0x1868 1147#define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880 1148#define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884 1149#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888 1150#define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c 1151#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890 1152#define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894 1153#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898 1154 1155#define R500_D1CRTC_STATUS 0x609c 1156#define R500_D2CRTC_STATUS 0x689c 1157#define R500_CRTC_V_BLANK (1<<0) 1158 1159#define R500_D1CRTC_FRAME_COUNT 0x60a4 1160#define R500_D2CRTC_FRAME_COUNT 0x68a4 1161 1162#define R500_D1MODE_V_COUNTER 0x6530 1163#define R500_D2MODE_V_COUNTER 0x6d30 1164 1165#define R500_D1MODE_VBLANK_STATUS 0x6534 1166#define R500_D2MODE_VBLANK_STATUS 0x6d34 1167#define R500_VBLANK_OCCURED (1<<0) 1168#define R500_VBLANK_ACK (1<<4) 1169#define R500_VBLANK_STAT (1<<12) 1170#define R500_VBLANK_INT (1<<16) 1171 1172#define R500_DxMODE_INT_MASK 0x6540 1173#define R500_D1MODE_INT_MASK (1<<0) 1174#define R500_D2MODE_INT_MASK (1<<8) 1175 1176#define R500_DISP_INTERRUPT_STATUS 0x7edc 1177#define R500_D1_VBLANK_INTERRUPT (1 << 4) 1178#define R500_D2_VBLANK_INTERRUPT (1 << 5) 1179 1180/* Constants */ 1181#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1182 1183#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 1184#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 1185#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 1186#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 1187#define RADEON_LAST_DISPATCH 1 1188 1189#define RADEON_MAX_VB_AGE 0x7fffffff 1190#define RADEON_MAX_VB_VERTS (0xffff) 1191 1192#define RADEON_RING_HIGH_MARK 128 1193 1194#define RADEON_PCIGART_TABLE_SIZE (32*1024) 1195 1196#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 1197#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) 1198#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1199#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1200 1201#define RADEON_WRITE_PLL( addr, val ) \ 1202do { \ 1203 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 1204 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1205 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 1206} while (0) 1207 1208#define RADEON_WRITE_PCIE( addr, val ) \ 1209do { \ 1210 RADEON_WRITE8( RADEON_PCIE_INDEX, \ 1211 ((addr) & 0xff)); \ 1212 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ 1213} while (0) 1214 1215#define R500_WRITE_MCIND( addr, val ) \ 1216do { \ 1217 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1218 RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1219 RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1220} while (0) 1221 1222#define RS480_WRITE_MCIND( addr, val ) \ 1223do { \ 1224 RADEON_WRITE( RS480_NB_MC_INDEX, \ 1225 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ 1226 RADEON_WRITE( RS480_NB_MC_DATA, (val) ); \ 1227 RADEON_WRITE( RS480_NB_MC_INDEX, 0xff ); \ 1228} while (0) 1229 1230#define RS690_WRITE_MCIND( addr, val ) \ 1231do { \ 1232 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1233 RADEON_WRITE(RS690_MC_DATA, val); \ 1234 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1235} while (0) 1236 1237#define IGP_WRITE_MCIND( addr, val ) \ 1238do { \ 1239 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ 1240 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ 1241 RS690_WRITE_MCIND( addr, val ); \ 1242 else \ 1243 RS480_WRITE_MCIND( addr, val ); \ 1244} while (0) 1245 1246#define CP_PACKET0( reg, n ) \ 1247 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1248#define CP_PACKET0_TABLE( reg, n ) \ 1249 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 1250#define CP_PACKET1( reg0, reg1 ) \ 1251 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 1252#define CP_PACKET2() \ 1253 (RADEON_CP_PACKET2) 1254#define CP_PACKET3( pkt, n ) \ 1255 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1256 1257/* ================================================================ 1258 * Engine control helper macros 1259 */ 1260 1261#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 1262 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1263 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1264 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1265} while (0) 1266 1267#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 1268 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1269 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1270 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1271} while (0) 1272 1273#define RADEON_WAIT_UNTIL_IDLE() do { \ 1274 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1275 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1276 RADEON_WAIT_3D_IDLECLEAN | \ 1277 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1278} while (0) 1279 1280#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 1281 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1282 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1283} while (0) 1284 1285#define RADEON_FLUSH_CACHE() do { \ 1286 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1287 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1288 OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1289 } else { \ 1290 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1291 OUT_RING(R300_RB3D_DC_FLUSH); \ 1292 } \ 1293} while (0) 1294 1295#define RADEON_PURGE_CACHE() do { \ 1296 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1297 OUT_RING(CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1298 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ 1299 } else { \ 1300 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1301 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE ); \ 1302 } \ 1303} while (0) 1304 1305#define RADEON_FLUSH_ZCACHE() do { \ 1306 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1307 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1308 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 1309 } else { \ 1310 OUT_RING( CP_PACKET0( R300_ZB_ZCACHE_CTLSTAT, 0 ) ); \ 1311 OUT_RING( R300_ZC_FLUSH ); \ 1312 } \ 1313} while (0) 1314 1315#define RADEON_PURGE_ZCACHE() do { \ 1316 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1317 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1318 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ 1319 } else { \ 1320 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1321 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ 1322 } \ 1323} while (0) 1324 1325/* ================================================================ 1326 * Misc helper macros 1327 */ 1328 1329/* Perfbox functionality only. 1330 */ 1331#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 1332do { \ 1333 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 1334 u32 head = GET_RING_HEAD( dev_priv ); \ 1335 if (head == dev_priv->ring.tail) \ 1336 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 1337 } \ 1338} while (0) 1339 1340#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 1341do { \ 1342 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 1343 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 1344 int __ret = radeon_do_cp_idle( dev_priv ); \ 1345 if ( __ret ) return __ret; \ 1346 sarea_priv->last_dispatch = 0; \ 1347 radeon_freelist_reset( dev ); \ 1348 } \ 1349} while (0) 1350 1351#define RADEON_DISPATCH_AGE( age ) do { \ 1352 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 1353 OUT_RING( age ); \ 1354} while (0) 1355 1356#define RADEON_FRAME_AGE( age ) do { \ 1357 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 1358 OUT_RING( age ); \ 1359} while (0) 1360 1361#define RADEON_CLEAR_AGE( age ) do { \ 1362 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 1363 OUT_RING( age ); \ 1364} while (0) 1365 1366/* ================================================================ 1367 * Ring control 1368 */ 1369 1370#define RADEON_VERBOSE 0 1371 1372#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; 1373 1374#define BEGIN_RING( n ) do { \ 1375 if ( RADEON_VERBOSE ) { \ 1376 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 1377 } \ 1378 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 1379 COMMIT_RING(); \ 1380 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 1381 } \ 1382 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 1383 ring = dev_priv->ring.start; \ 1384 write = dev_priv->ring.tail; \ 1385 mask = dev_priv->ring.tail_mask; \ 1386} while (0) 1387 1388#define ADVANCE_RING() do { \ 1389 if ( RADEON_VERBOSE ) { \ 1390 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 1391 write, dev_priv->ring.tail ); \ 1392 } \ 1393 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 1394 DRM_ERROR( \ 1395 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 1396 ((dev_priv->ring.tail + _nr) & mask), \ 1397 write, __LINE__); \ 1398 } else \ 1399 dev_priv->ring.tail = write; \ 1400} while (0) 1401 1402#define COMMIT_RING() do { \ 1403 /* Flush writes to ring */ \ 1404 DRM_MEMORYBARRIER(); \ 1405 GET_RING_HEAD( dev_priv ); \ 1406 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ 1407 /* read from PCI bus to ensure correct posting */ \ 1408 RADEON_READ( RADEON_CP_RB_RPTR ); \ 1409} while (0) 1410 1411#define OUT_RING( x ) do { \ 1412 if ( RADEON_VERBOSE ) { \ 1413 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 1414 (unsigned int)(x), write ); \ 1415 } \ 1416 ring[write++] = (x); \ 1417 write &= mask; \ 1418} while (0) 1419 1420#define OUT_RING_REG( reg, val ) do { \ 1421 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 1422 OUT_RING( val ); \ 1423} while (0) 1424 1425#define OUT_RING_TABLE( tab, sz ) do { \ 1426 int _size = (sz); \ 1427 int *_tab = (int *)(tab); \ 1428 \ 1429 if (write + _size > mask) { \ 1430 int _i = (mask+1) - write; \ 1431 _size -= _i; \ 1432 while (_i > 0) { \ 1433 *(int *)(ring + write) = *_tab++; \ 1434 write++; \ 1435 _i--; \ 1436 } \ 1437 write = 0; \ 1438 _tab += _i; \ 1439 } \ 1440 while (_size > 0) { \ 1441 *(ring + write) = *_tab++; \ 1442 write++; \ 1443 _size--; \ 1444 } \ 1445 write &= mask; \ 1446} while (0) 1447 1448#endif /* __RADEON_DRV_H__ */ 1449