radeon_drv.h revision 182080
1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drv.h 182080 2008-08-23 20:59:12Z rnoland $"); 33 34#ifndef __RADEON_DRV_H__ 35#define __RADEON_DRV_H__ 36 37/* General customization: 38 */ 39 40#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 41 42#define DRIVER_NAME "radeon" 43#define DRIVER_DESC "ATI Radeon" 44#define DRIVER_DATE "20080613" 45 46/* Interface history: 47 * 48 * 1.1 - ?? 49 * 1.2 - Add vertex2 ioctl (keith) 50 * - Add stencil capability to clear ioctl (gareth, keith) 51 * - Increase MAX_TEXTURE_LEVELS (brian) 52 * 1.3 - Add cmdbuf ioctl (keith) 53 * - Add support for new radeon packets (keith) 54 * - Add getparam ioctl (keith) 55 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 56 * 1.4 - Add scratch registers to get_param ioctl. 57 * 1.5 - Add r200 packets to cmdbuf ioctl 58 * - Add r200 function to init ioctl 59 * - Add 'scalar2' instruction to cmdbuf 60 * 1.6 - Add static GART memory manager 61 * Add irq handler (won't be turned on unless X server knows to) 62 * Add irq ioctls and irq_active getparam. 63 * Add wait command for cmdbuf ioctl 64 * Add GART offset query for getparam 65 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 66 * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 67 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 68 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 69 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 70 * Add 'GET' queries for starting additional clients on different VT's. 71 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 72 * Add texture rectangle support for r100. 73 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 74 * clients use to tell the DRM where they think the framebuffer is 75 * located in the card's address space 76 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 77 * and GL_EXT_blend_[func|equation]_separate on r200 78 * 1.12- Add R300 CP microcode support - this just loads the CP on r300 79 * (No 3D support yet - just microcode loading). 80 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 81 * - Add hyperz support, add hyperz flags to clear ioctl. 82 * 1.14- Add support for color tiling 83 * - Add R100/R200 surface allocation/free support 84 * 1.15- Add support for texture micro tiling 85 * - Add support for r100 cube maps 86 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 87 * texture filtering on r200 88 * 1.17- Add initial support for R300 (3D). 89 * 1.18- Add support for GL_ATI_fragment_shader, new packets 90 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 91 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 92 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 93 * 1.19- Add support for gart table in FB memory and PCIE r300 94 * 1.20- Add support for r300 texrect 95 * 1.21- Add support for card type getparam 96 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 97 * 1.23- Add new radeon memory map work from benh 98 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 99 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, 100 * new packet type) 101 * 1.26- Add support for variable size PCI(E) gart aperture 102 * 1.27- Add support for IGP GART 103 * 1.28- Add support for VBL on CRTC2 104 * 1.29- R500 3D cmd buffer support 105 */ 106 107#define DRIVER_MAJOR 1 108#define DRIVER_MINOR 29 109#define DRIVER_PATCHLEVEL 0 110 111/* 112 * Radeon chip families 113 */ 114enum radeon_family { 115 CHIP_R100, 116 CHIP_RV100, 117 CHIP_RS100, 118 CHIP_RV200, 119 CHIP_RS200, 120 CHIP_R200, 121 CHIP_RV250, 122 CHIP_RS300, 123 CHIP_RV280, 124 CHIP_R300, 125 CHIP_R350, 126 CHIP_RV350, 127 CHIP_RV380, 128 CHIP_R420, 129 CHIP_RV410, 130 CHIP_RS400, 131 CHIP_RS480, 132 CHIP_RS690, 133 CHIP_RV515, 134 CHIP_R520, 135 CHIP_RV530, 136 CHIP_RV560, 137 CHIP_RV570, 138 CHIP_R580, 139 CHIP_LAST, 140}; 141 142/* 143 * Chip flags 144 */ 145enum radeon_chip_flags { 146 RADEON_FAMILY_MASK = 0x0000ffffUL, 147 RADEON_FLAGS_MASK = 0xffff0000UL, 148 RADEON_IS_MOBILITY = 0x00010000UL, 149 RADEON_IS_IGP = 0x00020000UL, 150 RADEON_SINGLE_CRTC = 0x00040000UL, 151 RADEON_IS_AGP = 0x00080000UL, 152 RADEON_HAS_HIERZ = 0x00100000UL, 153 RADEON_IS_PCIE = 0x00200000UL, 154 RADEON_NEW_MEMMAP = 0x00400000UL, 155 RADEON_IS_PCI = 0x00800000UL, 156 RADEON_IS_IGPGART = 0x01000000UL, 157}; 158 159#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ 160 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR)) 161#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) 162 163typedef struct drm_radeon_freelist { 164 unsigned int age; 165 struct drm_buf *buf; 166 struct drm_radeon_freelist *next; 167 struct drm_radeon_freelist *prev; 168} drm_radeon_freelist_t; 169 170typedef struct drm_radeon_ring_buffer { 171 u32 *start; 172 u32 *end; 173 int size; /* Double Words */ 174 int size_l2qw; /* log2 Quad Words */ 175 176 int rptr_update; /* Double Words */ 177 int rptr_update_l2qw; /* log2 Quad Words */ 178 179 int fetch_size; /* Double Words */ 180 int fetch_size_l2ow; /* log2 Oct Words */ 181 182 u32 tail; 183 u32 tail_mask; 184 int space; 185 186 int high_mark; 187} drm_radeon_ring_buffer_t; 188 189typedef struct drm_radeon_depth_clear_t { 190 u32 rb3d_cntl; 191 u32 rb3d_zstencilcntl; 192 u32 se_cntl; 193} drm_radeon_depth_clear_t; 194 195struct drm_radeon_driver_file_fields { 196 int64_t radeon_fb_delta; 197}; 198 199struct mem_block { 200 struct mem_block *next; 201 struct mem_block *prev; 202 int start; 203 int size; 204 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 205}; 206 207struct radeon_surface { 208 int refcount; 209 u32 lower; 210 u32 upper; 211 u32 flags; 212}; 213 214struct radeon_virt_surface { 215 int surface_index; 216 u32 lower; 217 u32 upper; 218 u32 flags; 219 struct drm_file *file_priv; 220}; 221 222#define RADEON_FLUSH_EMITED (1 < 0) 223#define RADEON_PURGE_EMITED (1 < 1) 224 225typedef struct drm_radeon_private { 226 227 drm_radeon_ring_buffer_t ring; 228 drm_radeon_sarea_t *sarea_priv; 229 230 u32 fb_location; 231 u32 fb_size; 232 int new_memmap; 233 234 int gart_size; 235 u32 gart_vm_start; 236 unsigned long gart_buffers_offset; 237 238 int cp_mode; 239 int cp_running; 240 241 drm_radeon_freelist_t *head; 242 drm_radeon_freelist_t *tail; 243 int last_buf; 244 volatile u32 *scratch; 245 int writeback_works; 246 247 int usec_timeout; 248 249 struct { 250 u32 boxes; 251 int freelist_timeouts; 252 int freelist_loops; 253 int requested_bufs; 254 int last_frame_reads; 255 int last_clear_reads; 256 int clears; 257 int texture_uploads; 258 } stats; 259 260 int do_boxes; 261 int page_flipping; 262 263 u32 color_fmt; 264 unsigned int front_offset; 265 unsigned int front_pitch; 266 unsigned int back_offset; 267 unsigned int back_pitch; 268 269 u32 depth_fmt; 270 unsigned int depth_offset; 271 unsigned int depth_pitch; 272 273 u32 front_pitch_offset; 274 u32 back_pitch_offset; 275 u32 depth_pitch_offset; 276 277 drm_radeon_depth_clear_t depth_clear; 278 279 unsigned long ring_offset; 280 unsigned long ring_rptr_offset; 281 unsigned long buffers_offset; 282 unsigned long gart_textures_offset; 283 284 drm_local_map_t *sarea; 285 drm_local_map_t *mmio; 286 drm_local_map_t *cp_ring; 287 drm_local_map_t *ring_rptr; 288 drm_local_map_t *gart_textures; 289 290 struct mem_block *gart_heap; 291 struct mem_block *fb_heap; 292 293 /* SW interrupt */ 294 wait_queue_head_t swi_queue; 295 atomic_t swi_emitted; 296 int vblank_crtc; 297 uint32_t irq_enable_reg; 298 int irq_enabled; 299 uint32_t r500_disp_irq_reg; 300 301 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 302 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 303 304 unsigned long pcigart_offset; 305 unsigned int pcigart_offset_set; 306 struct drm_ati_pcigart_info gart_info; 307 308 u32 scratch_ages[5]; 309 310 unsigned int crtc_last_cnt; 311 unsigned int crtc2_last_cnt; 312 313 /* starting from here on, data is preserved accross an open */ 314 uint32_t flags; /* see radeon_chip_flags */ 315 unsigned long fb_aper_offset; 316 317 int num_gb_pipes; 318 int track_flush; 319 uint32_t chip_family; /* extract from flags */ 320} drm_radeon_private_t; 321 322typedef struct drm_radeon_buf_priv { 323 u32 age; 324} drm_radeon_buf_priv_t; 325 326typedef struct drm_radeon_kcmd_buffer { 327 int bufsz; 328 char *buf; 329 int nbox; 330 struct drm_clip_rect __user *boxes; 331} drm_radeon_kcmd_buffer_t; 332 333extern int radeon_no_wb; 334extern struct drm_ioctl_desc radeon_ioctls[]; 335extern int radeon_max_ioctl; 336 337/* Check whether the given hardware address is inside the framebuffer or the 338 * GART area. 339 */ 340static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, 341 u64 off) 342{ 343 u32 fb_start = dev_priv->fb_location; 344 u32 fb_end = fb_start + dev_priv->fb_size - 1; 345 u32 gart_start = dev_priv->gart_vm_start; 346 u32 gart_end = gart_start + dev_priv->gart_size - 1; 347 348 return ((off >= fb_start && off <= fb_end) || 349 (off >= gart_start && off <= gart_end)); 350} 351 352 /* radeon_cp.c */ 353extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 354extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 355extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 356extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 357extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 358extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); 359extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 360extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 361extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 362extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); 363 364extern void radeon_freelist_reset(struct drm_device * dev); 365extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); 366 367extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 368 369extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 370 371extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); 372extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); 373extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); 374extern void radeon_mem_takedown(struct mem_block **heap); 375extern void radeon_mem_release(struct drm_file *file_priv, 376 struct mem_block *heap); 377 378 /* radeon_irq.c */ 379extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); 380extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); 381extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); 382 383extern void radeon_do_release(struct drm_device * dev); 384extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); 385extern int radeon_enable_vblank(struct drm_device *dev, int crtc); 386extern void radeon_disable_vblank(struct drm_device *dev, int crtc); 387extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 388extern void radeon_driver_irq_preinstall(struct drm_device * dev); 389extern int radeon_driver_irq_postinstall(struct drm_device * dev); 390extern void radeon_driver_irq_uninstall(struct drm_device * dev); 391extern int radeon_vblank_crtc_get(struct drm_device *dev); 392extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 393 394extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 395extern int radeon_driver_unload(struct drm_device *dev); 396extern int radeon_driver_firstopen(struct drm_device *dev); 397extern void radeon_driver_preclose(struct drm_device * dev, 398 struct drm_file *file_priv); 399extern void radeon_driver_postclose(struct drm_device * dev, 400 struct drm_file *file_priv); 401extern void radeon_driver_lastclose(struct drm_device * dev); 402extern int radeon_driver_open(struct drm_device * dev, 403 struct drm_file * file_priv); 404extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 405 unsigned long arg); 406 407/* r300_cmdbuf.c */ 408extern void r300_init_reg_flags(struct drm_device *dev); 409 410extern int r300_do_cp_cmdbuf(struct drm_device *dev, 411 struct drm_file *file_priv, 412 drm_radeon_kcmd_buffer_t *cmdbuf); 413 414/* Flags for stats.boxes 415 */ 416#define RADEON_BOX_DMA_IDLE 0x1 417#define RADEON_BOX_RING_FULL 0x2 418#define RADEON_BOX_FLIP 0x4 419#define RADEON_BOX_WAIT_IDLE 0x8 420#define RADEON_BOX_TEXTURE_LOAD 0x10 421 422/* Register definitions, register access macros and drmAddMap constants 423 * for Radeon kernel driver. 424 */ 425#define RADEON_AGP_COMMAND 0x0f60 426#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 427# define RADEON_AGP_ENABLE (1<<8) 428#define RADEON_AUX_SCISSOR_CNTL 0x26f0 429# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 430# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 431# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 432# define RADEON_SCISSOR_0_ENABLE (1 << 28) 433# define RADEON_SCISSOR_1_ENABLE (1 << 29) 434# define RADEON_SCISSOR_2_ENABLE (1 << 30) 435 436#define RADEON_BUS_CNTL 0x0030 437# define RADEON_BUS_MASTER_DIS (1 << 6) 438 439#define RADEON_CLOCK_CNTL_DATA 0x000c 440# define RADEON_PLL_WR_EN (1 << 7) 441#define RADEON_CLOCK_CNTL_INDEX 0x0008 442#define RADEON_CONFIG_APER_SIZE 0x0108 443#define RADEON_CONFIG_MEMSIZE 0x00f8 444#define RADEON_CRTC_OFFSET 0x0224 445#define RADEON_CRTC_OFFSET_CNTL 0x0228 446# define RADEON_CRTC_TILE_EN (1 << 15) 447# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 448#define RADEON_CRTC2_OFFSET 0x0324 449#define RADEON_CRTC2_OFFSET_CNTL 0x0328 450 451#define RADEON_PCIE_INDEX 0x0030 452#define RADEON_PCIE_DATA 0x0034 453#define RADEON_PCIE_TX_GART_CNTL 0x10 454# define RADEON_PCIE_TX_GART_EN (1 << 0) 455# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) 456# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) 457# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) 458# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) 459# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) 460# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) 461# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) 462#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 463#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 464#define RADEON_PCIE_TX_GART_BASE 0x13 465#define RADEON_PCIE_TX_GART_START_LO 0x14 466#define RADEON_PCIE_TX_GART_START_HI 0x15 467#define RADEON_PCIE_TX_GART_END_LO 0x16 468#define RADEON_PCIE_TX_GART_END_HI 0x17 469 470#define RS480_NB_MC_INDEX 0x168 471# define RS480_NB_MC_IND_WR_EN (1 << 8) 472#define RS480_NB_MC_DATA 0x16c 473 474#define RS690_MC_INDEX 0x78 475# define RS690_MC_INDEX_MASK 0x1ff 476# define RS690_MC_INDEX_WR_EN (1 << 9) 477# define RS690_MC_INDEX_WR_ACK 0x7f 478#define RS690_MC_DATA 0x7c 479 480/* MC indirect registers */ 481#define RS480_MC_MISC_CNTL 0x18 482# define RS480_DISABLE_GTW (1 << 1) 483/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ 484# define RS480_GART_INDEX_REG_EN (1 << 12) 485# define RS690_BLOCK_GFX_D3_EN (1 << 14) 486#define RS480_K8_FB_LOCATION 0x1e 487#define RS480_GART_FEATURE_ID 0x2b 488# define RS480_HANG_EN (1 << 11) 489# define RS480_TLB_ENABLE (1 << 18) 490# define RS480_P2P_ENABLE (1 << 19) 491# define RS480_GTW_LAC_EN (1 << 25) 492# define RS480_2LEVEL_GART (0 << 30) 493# define RS480_1LEVEL_GART (1 << 30) 494# define RS480_PDC_EN (1 << 31) 495#define RS480_GART_BASE 0x2c 496#define RS480_GART_CACHE_CNTRL 0x2e 497# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 498#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 499# define RS480_GART_EN (1 << 0) 500# define RS480_VA_SIZE_32MB (0 << 1) 501# define RS480_VA_SIZE_64MB (1 << 1) 502# define RS480_VA_SIZE_128MB (2 << 1) 503# define RS480_VA_SIZE_256MB (3 << 1) 504# define RS480_VA_SIZE_512MB (4 << 1) 505# define RS480_VA_SIZE_1GB (5 << 1) 506# define RS480_VA_SIZE_2GB (6 << 1) 507#define RS480_AGP_MODE_CNTL 0x39 508# define RS480_POST_GART_Q_SIZE (1 << 18) 509# define RS480_NONGART_SNOOP (1 << 19) 510# define RS480_AGP_RD_BUF_SIZE (1 << 20) 511# define RS480_REQ_TYPE_SNOOP_SHIFT 22 512# define RS480_REQ_TYPE_SNOOP_MASK 0x3 513# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 514#define RS480_MC_MISC_UMA_CNTL 0x5f 515#define RS480_MC_MCLK_CNTL 0x7a 516#define RS480_MC_UMA_DUALCH_CNTL 0x86 517 518#define RS690_MC_FB_LOCATION 0x100 519#define RS690_MC_AGP_LOCATION 0x101 520#define RS690_MC_AGP_BASE 0x102 521#define RS690_MC_AGP_BASE_2 0x103 522 523#define R520_MC_IND_INDEX 0x70 524#define R520_MC_IND_WR_EN (1 << 24) 525#define R520_MC_IND_DATA 0x74 526 527#define RV515_MC_FB_LOCATION 0x01 528#define RV515_MC_AGP_LOCATION 0x02 529#define RV515_MC_AGP_BASE 0x03 530#define RV515_MC_AGP_BASE_2 0x04 531 532#define R520_MC_FB_LOCATION 0x04 533#define R520_MC_AGP_LOCATION 0x05 534#define R520_MC_AGP_BASE 0x06 535#define R520_MC_AGP_BASE_2 0x07 536 537#define RADEON_MPP_TB_CONFIG 0x01c0 538#define RADEON_MEM_CNTL 0x0140 539#define RADEON_MEM_SDRAM_MODE_REG 0x0158 540#define RADEON_AGP_BASE_2 0x015c /* r200+ only */ 541#define RS480_AGP_BASE_2 0x0164 542#define RADEON_AGP_BASE 0x0170 543 544/* pipe config regs */ 545#define R400_GB_PIPE_SELECT 0x402c 546#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 547#define R500_SU_REG_DEST 0x42c8 548#define R300_GB_TILE_CONFIG 0x4018 549# define R300_ENABLE_TILING (1 << 0) 550# define R300_PIPE_COUNT_RV350 (0 << 1) 551# define R300_PIPE_COUNT_R300 (3 << 1) 552# define R300_PIPE_COUNT_R420_3P (6 << 1) 553# define R300_PIPE_COUNT_R420 (7 << 1) 554# define R300_TILE_SIZE_8 (0 << 4) 555# define R300_TILE_SIZE_16 (1 << 4) 556# define R300_TILE_SIZE_32 (2 << 4) 557# define R300_SUBPIXEL_1_12 (0 << 16) 558# define R300_SUBPIXEL_1_16 (1 << 16) 559#define R300_DST_PIPE_CONFIG 0x170c 560# define R300_PIPE_AUTO_CONFIG (1 << 31) 561#define R300_RB2D_DSTCACHE_MODE 0x3428 562# define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 563# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 564 565#define RADEON_RB3D_COLOROFFSET 0x1c40 566#define RADEON_RB3D_COLORPITCH 0x1c48 567 568#define RADEON_SRC_X_Y 0x1590 569 570#define RADEON_DP_GUI_MASTER_CNTL 0x146c 571# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 572# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 573# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 574# define RADEON_GMC_BRUSH_NONE (15 << 4) 575# define RADEON_GMC_DST_16BPP (4 << 8) 576# define RADEON_GMC_DST_24BPP (5 << 8) 577# define RADEON_GMC_DST_32BPP (6 << 8) 578# define RADEON_GMC_DST_DATATYPE_SHIFT 8 579# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 580# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 581# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 582# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 583# define RADEON_GMC_WR_MSK_DIS (1 << 30) 584# define RADEON_ROP3_S 0x00cc0000 585# define RADEON_ROP3_P 0x00f00000 586#define RADEON_DP_WRITE_MASK 0x16cc 587#define RADEON_SRC_PITCH_OFFSET 0x1428 588#define RADEON_DST_PITCH_OFFSET 0x142c 589#define RADEON_DST_PITCH_OFFSET_C 0x1c80 590# define RADEON_DST_TILE_LINEAR (0 << 30) 591# define RADEON_DST_TILE_MACRO (1 << 30) 592# define RADEON_DST_TILE_MICRO (2 << 30) 593# define RADEON_DST_TILE_BOTH (3 << 30) 594 595#define RADEON_SCRATCH_REG0 0x15e0 596#define RADEON_SCRATCH_REG1 0x15e4 597#define RADEON_SCRATCH_REG2 0x15e8 598#define RADEON_SCRATCH_REG3 0x15ec 599#define RADEON_SCRATCH_REG4 0x15f0 600#define RADEON_SCRATCH_REG5 0x15f4 601#define RADEON_SCRATCH_UMSK 0x0770 602#define RADEON_SCRATCH_ADDR 0x0774 603 604#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 605 606#define GET_SCRATCH( x ) (dev_priv->writeback_works \ 607 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ 608 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) 609 610#define RADEON_CRTC_CRNT_FRAME 0x0214 611#define RADEON_CRTC2_CRNT_FRAME 0x0314 612 613#define RADEON_CRTC_STATUS 0x005c 614#define RADEON_CRTC2_STATUS 0x03fc 615 616#define RADEON_GEN_INT_CNTL 0x0040 617# define RADEON_CRTC_VBLANK_MASK (1 << 0) 618# define RADEON_CRTC2_VBLANK_MASK (1 << 9) 619# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 620# define RADEON_SW_INT_ENABLE (1 << 25) 621 622#define RADEON_GEN_INT_STATUS 0x0044 623# define RADEON_CRTC_VBLANK_STAT (1 << 0) 624# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 625# define RADEON_CRTC2_VBLANK_STAT (1 << 9) 626# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 627# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 628# define RADEON_SW_INT_TEST (1 << 25) 629# define RADEON_SW_INT_TEST_ACK (1 << 25) 630# define RADEON_SW_INT_FIRE (1 << 26) 631# define R500_DISPLAY_INT_STATUS (1 << 0) 632 633 634#define RADEON_HOST_PATH_CNTL 0x0130 635# define RADEON_HDP_SOFT_RESET (1 << 26) 636# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 637# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 638 639#define RADEON_ISYNC_CNTL 0x1724 640# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 641# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 642# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 643# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 644# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 645# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 646 647#define RADEON_RBBM_GUICNTL 0x172c 648# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 649# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 650# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 651# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 652 653#define RADEON_MC_AGP_LOCATION 0x014c 654#define RADEON_MC_FB_LOCATION 0x0148 655#define RADEON_MCLK_CNTL 0x0012 656# define RADEON_FORCEON_MCLKA (1 << 16) 657# define RADEON_FORCEON_MCLKB (1 << 17) 658# define RADEON_FORCEON_YCLKA (1 << 18) 659# define RADEON_FORCEON_YCLKB (1 << 19) 660# define RADEON_FORCEON_MC (1 << 20) 661# define RADEON_FORCEON_AIC (1 << 21) 662 663#define RADEON_PP_BORDER_COLOR_0 0x1d40 664#define RADEON_PP_BORDER_COLOR_1 0x1d44 665#define RADEON_PP_BORDER_COLOR_2 0x1d48 666#define RADEON_PP_CNTL 0x1c38 667# define RADEON_SCISSOR_ENABLE (1 << 1) 668#define RADEON_PP_LUM_MATRIX 0x1d00 669#define RADEON_PP_MISC 0x1c14 670#define RADEON_PP_ROT_MATRIX_0 0x1d58 671#define RADEON_PP_TXFILTER_0 0x1c54 672#define RADEON_PP_TXOFFSET_0 0x1c5c 673#define RADEON_PP_TXFILTER_1 0x1c6c 674#define RADEON_PP_TXFILTER_2 0x1c84 675 676#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ 677#define R300_DSTCACHE_CTLSTAT 0x1714 678# define R300_RB2D_DC_FLUSH (3 << 0) 679# define R300_RB2D_DC_FREE (3 << 2) 680# define R300_RB2D_DC_FLUSH_ALL 0xf 681# define R300_RB2D_DC_BUSY (1 << 31) 682#define RADEON_RB3D_CNTL 0x1c3c 683# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 684# define RADEON_PLANE_MASK_ENABLE (1 << 1) 685# define RADEON_DITHER_ENABLE (1 << 2) 686# define RADEON_ROUND_ENABLE (1 << 3) 687# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 688# define RADEON_DITHER_INIT (1 << 5) 689# define RADEON_ROP_ENABLE (1 << 6) 690# define RADEON_STENCIL_ENABLE (1 << 7) 691# define RADEON_Z_ENABLE (1 << 8) 692# define RADEON_ZBLOCK16 (1 << 15) 693#define RADEON_RB3D_DEPTHOFFSET 0x1c24 694#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 695#define RADEON_RB3D_DEPTHPITCH 0x1c28 696#define RADEON_RB3D_PLANEMASK 0x1d84 697#define RADEON_RB3D_STENCILREFMASK 0x1d7c 698#define RADEON_RB3D_ZCACHE_MODE 0x3250 699#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 700# define RADEON_RB3D_ZC_FLUSH (1 << 0) 701# define RADEON_RB3D_ZC_FREE (1 << 2) 702# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 703# define RADEON_RB3D_ZC_BUSY (1 << 31) 704#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 705# define R300_ZC_FLUSH (1 << 0) 706# define R300_ZC_FREE (1 << 1) 707# define R300_ZC_BUSY (1 << 31) 708#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 709# define RADEON_RB3D_DC_FLUSH (3 << 0) 710# define RADEON_RB3D_DC_FREE (3 << 2) 711# define RADEON_RB3D_DC_FLUSH_ALL 0xf 712# define RADEON_RB3D_DC_BUSY (1 << 31) 713#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 714# define R300_RB3D_DC_FLUSH (2 << 0) 715# define R300_RB3D_DC_FREE (2 << 2) 716# define R300_RB3D_DC_FINISH (1 << 4) 717#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 718# define RADEON_Z_TEST_MASK (7 << 4) 719# define RADEON_Z_TEST_ALWAYS (7 << 4) 720# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 721# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 722# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 723# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 724# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 725# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 726# define RADEON_FORCE_Z_DIRTY (1 << 29) 727# define RADEON_Z_WRITE_ENABLE (1 << 30) 728# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 729#define RADEON_RBBM_SOFT_RESET 0x00f0 730# define RADEON_SOFT_RESET_CP (1 << 0) 731# define RADEON_SOFT_RESET_HI (1 << 1) 732# define RADEON_SOFT_RESET_SE (1 << 2) 733# define RADEON_SOFT_RESET_RE (1 << 3) 734# define RADEON_SOFT_RESET_PP (1 << 4) 735# define RADEON_SOFT_RESET_E2 (1 << 5) 736# define RADEON_SOFT_RESET_RB (1 << 6) 737# define RADEON_SOFT_RESET_HDP (1 << 7) 738/* 739 * 6:0 Available slots in the FIFO 740 * 8 Host Interface active 741 * 9 CP request active 742 * 10 FIFO request active 743 * 11 Host Interface retry active 744 * 12 CP retry active 745 * 13 FIFO retry active 746 * 14 FIFO pipeline busy 747 * 15 Event engine busy 748 * 16 CP command stream busy 749 * 17 2D engine busy 750 * 18 2D portion of render backend busy 751 * 20 3D setup engine busy 752 * 26 GA engine busy 753 * 27 CBA 2D engine busy 754 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or 755 * command stream queue not empty or Ring Buffer not empty 756 */ 757#define RADEON_RBBM_STATUS 0x0e40 758/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ 759/* #define RADEON_RBBM_STATUS 0x1740 */ 760/* bits 6:0 are dword slots available in the cmd fifo */ 761# define RADEON_RBBM_FIFOCNT_MASK 0x007f 762# define RADEON_HIRQ_ON_RBB (1 << 8) 763# define RADEON_CPRQ_ON_RBB (1 << 9) 764# define RADEON_CFRQ_ON_RBB (1 << 10) 765# define RADEON_HIRQ_IN_RTBUF (1 << 11) 766# define RADEON_CPRQ_IN_RTBUF (1 << 12) 767# define RADEON_CFRQ_IN_RTBUF (1 << 13) 768# define RADEON_PIPE_BUSY (1 << 14) 769# define RADEON_ENG_EV_BUSY (1 << 15) 770# define RADEON_CP_CMDSTRM_BUSY (1 << 16) 771# define RADEON_E2_BUSY (1 << 17) 772# define RADEON_RB2D_BUSY (1 << 18) 773# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ 774# define RADEON_VAP_BUSY (1 << 20) 775# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ 776# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ 777# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ 778# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ 779# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ 780# define RADEON_GA_BUSY (1 << 26) 781# define RADEON_CBA2D_BUSY (1 << 27) 782# define RADEON_RBBM_ACTIVE (1 << 31) 783#define RADEON_RE_LINE_PATTERN 0x1cd0 784#define RADEON_RE_MISC 0x26c4 785#define RADEON_RE_TOP_LEFT 0x26c0 786#define RADEON_RE_WIDTH_HEIGHT 0x1c44 787#define RADEON_RE_STIPPLE_ADDR 0x1cc8 788#define RADEON_RE_STIPPLE_DATA 0x1ccc 789 790#define RADEON_SCISSOR_TL_0 0x1cd8 791#define RADEON_SCISSOR_BR_0 0x1cdc 792#define RADEON_SCISSOR_TL_1 0x1ce0 793#define RADEON_SCISSOR_BR_1 0x1ce4 794#define RADEON_SCISSOR_TL_2 0x1ce8 795#define RADEON_SCISSOR_BR_2 0x1cec 796#define RADEON_SE_COORD_FMT 0x1c50 797#define RADEON_SE_CNTL 0x1c4c 798# define RADEON_FFACE_CULL_CW (0 << 0) 799# define RADEON_BFACE_SOLID (3 << 1) 800# define RADEON_FFACE_SOLID (3 << 3) 801# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 802# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 803# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 804# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 805# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 806# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 807# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 808# define RADEON_FOG_SHADE_FLAT (1 << 14) 809# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 810# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 811# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 812# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 813# define RADEON_ROUND_MODE_TRUNC (0 << 28) 814# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 815#define RADEON_SE_CNTL_STATUS 0x2140 816#define RADEON_SE_LINE_WIDTH 0x1db8 817#define RADEON_SE_VPORT_XSCALE 0x1d98 818#define RADEON_SE_ZBIAS_FACTOR 0x1db0 819#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 820#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 821#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 822# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 823# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 824#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 825#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 826# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 827#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 828#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 829#define RADEON_SURFACE_ACCESS_CLR 0x0bfc 830#define RADEON_SURFACE_CNTL 0x0b00 831# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 832# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 833# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 834# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 835# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 836# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 837# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 838# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 839# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 840#define RADEON_SURFACE0_INFO 0x0b0c 841# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 842# define RADEON_SURF_TILE_MODE_MASK (3 << 16) 843# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 844# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 845# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 846# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 847#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 848#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 849# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 850#define RADEON_SURFACE1_INFO 0x0b1c 851#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 852#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 853#define RADEON_SURFACE2_INFO 0x0b2c 854#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 855#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 856#define RADEON_SURFACE3_INFO 0x0b3c 857#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 858#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 859#define RADEON_SURFACE4_INFO 0x0b4c 860#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 861#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 862#define RADEON_SURFACE5_INFO 0x0b5c 863#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 864#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 865#define RADEON_SURFACE6_INFO 0x0b6c 866#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 867#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 868#define RADEON_SURFACE7_INFO 0x0b7c 869#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 870#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 871#define RADEON_SW_SEMAPHORE 0x013c 872 873#define RADEON_WAIT_UNTIL 0x1720 874# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 875# define RADEON_WAIT_2D_IDLE (1 << 14) 876# define RADEON_WAIT_3D_IDLE (1 << 15) 877# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 878# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 879# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 880 881#define RADEON_RB3D_ZMASKOFFSET 0x3234 882#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 883# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 884# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 885 886/* CP registers */ 887#define RADEON_CP_ME_RAM_ADDR 0x07d4 888#define RADEON_CP_ME_RAM_RADDR 0x07d8 889#define RADEON_CP_ME_RAM_DATAH 0x07dc 890#define RADEON_CP_ME_RAM_DATAL 0x07e0 891 892#define RADEON_CP_RB_BASE 0x0700 893#define RADEON_CP_RB_CNTL 0x0704 894# define RADEON_BUF_SWAP_32BIT (2 << 16) 895# define RADEON_RB_NO_UPDATE (1 << 27) 896#define RADEON_CP_RB_RPTR_ADDR 0x070c 897#define RADEON_CP_RB_RPTR 0x0710 898#define RADEON_CP_RB_WPTR 0x0714 899 900#define RADEON_CP_RB_WPTR_DELAY 0x0718 901# define RADEON_PRE_WRITE_TIMER_SHIFT 0 902# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 903 904#define RADEON_CP_IB_BASE 0x0738 905 906#define RADEON_CP_CSQ_CNTL 0x0740 907# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 908# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 909# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 910# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 911# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 912# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 913# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 914 915#define RADEON_AIC_CNTL 0x01d0 916# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 917#define RADEON_AIC_STAT 0x01d4 918#define RADEON_AIC_PT_BASE 0x01d8 919#define RADEON_AIC_LO_ADDR 0x01dc 920#define RADEON_AIC_HI_ADDR 0x01e0 921#define RADEON_AIC_TLB_ADDR 0x01e4 922#define RADEON_AIC_TLB_DATA 0x01e8 923 924/* CP command packets */ 925#define RADEON_CP_PACKET0 0x00000000 926# define RADEON_ONE_REG_WR (1 << 15) 927#define RADEON_CP_PACKET1 0x40000000 928#define RADEON_CP_PACKET2 0x80000000 929#define RADEON_CP_PACKET3 0xC0000000 930# define RADEON_CP_NOP 0x00001000 931# define RADEON_CP_NEXT_CHAR 0x00001900 932# define RADEON_CP_PLY_NEXTSCAN 0x00001D00 933# define RADEON_CP_SET_SCISSORS 0x00001E00 934 /* GEN_INDX_PRIM is unsupported starting with R300 */ 935# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 936# define RADEON_WAIT_FOR_IDLE 0x00002600 937# define RADEON_3D_DRAW_VBUF 0x00002800 938# define RADEON_3D_DRAW_IMMD 0x00002900 939# define RADEON_3D_DRAW_INDX 0x00002A00 940# define RADEON_CP_LOAD_PALETTE 0x00002C00 941# define RADEON_3D_LOAD_VBPNTR 0x00002F00 942# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 943# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 944# define RADEON_3D_CLEAR_ZMASK 0x00003200 945# define RADEON_CP_INDX_BUFFER 0x00003300 946# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 947# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 948# define RADEON_CP_3D_DRAW_INDX_2 0x00003600 949# define RADEON_3D_CLEAR_HIZ 0x00003700 950# define RADEON_CP_3D_CLEAR_CMASK 0x00003802 951# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 952# define RADEON_CNTL_PAINT_MULTI 0x00009A00 953# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 954# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 955 956#define RADEON_CP_PACKET_MASK 0xC0000000 957#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 958#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 959#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 960#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 961 962#define RADEON_VTX_Z_PRESENT (1 << 31) 963#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 964 965#define RADEON_PRIM_TYPE_NONE (0 << 0) 966#define RADEON_PRIM_TYPE_POINT (1 << 0) 967#define RADEON_PRIM_TYPE_LINE (2 << 0) 968#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 969#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 970#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 971#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 972#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 973#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 974#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 975#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 976#define RADEON_PRIM_TYPE_MASK 0xf 977#define RADEON_PRIM_WALK_IND (1 << 4) 978#define RADEON_PRIM_WALK_LIST (2 << 4) 979#define RADEON_PRIM_WALK_RING (3 << 4) 980#define RADEON_COLOR_ORDER_BGRA (0 << 6) 981#define RADEON_COLOR_ORDER_RGBA (1 << 6) 982#define RADEON_MAOS_ENABLE (1 << 7) 983#define RADEON_VTX_FMT_R128_MODE (0 << 8) 984#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 985#define RADEON_NUM_VERTICES_SHIFT 16 986 987#define RADEON_COLOR_FORMAT_CI8 2 988#define RADEON_COLOR_FORMAT_ARGB1555 3 989#define RADEON_COLOR_FORMAT_RGB565 4 990#define RADEON_COLOR_FORMAT_ARGB8888 6 991#define RADEON_COLOR_FORMAT_RGB332 7 992#define RADEON_COLOR_FORMAT_RGB8 9 993#define RADEON_COLOR_FORMAT_ARGB4444 15 994 995#define RADEON_TXFORMAT_I8 0 996#define RADEON_TXFORMAT_AI88 1 997#define RADEON_TXFORMAT_RGB332 2 998#define RADEON_TXFORMAT_ARGB1555 3 999#define RADEON_TXFORMAT_RGB565 4 1000#define RADEON_TXFORMAT_ARGB4444 5 1001#define RADEON_TXFORMAT_ARGB8888 6 1002#define RADEON_TXFORMAT_RGBA8888 7 1003#define RADEON_TXFORMAT_Y8 8 1004#define RADEON_TXFORMAT_VYUY422 10 1005#define RADEON_TXFORMAT_YVYU422 11 1006#define RADEON_TXFORMAT_DXT1 12 1007#define RADEON_TXFORMAT_DXT23 14 1008#define RADEON_TXFORMAT_DXT45 15 1009 1010#define R200_PP_TXCBLEND_0 0x2f00 1011#define R200_PP_TXCBLEND_1 0x2f10 1012#define R200_PP_TXCBLEND_2 0x2f20 1013#define R200_PP_TXCBLEND_3 0x2f30 1014#define R200_PP_TXCBLEND_4 0x2f40 1015#define R200_PP_TXCBLEND_5 0x2f50 1016#define R200_PP_TXCBLEND_6 0x2f60 1017#define R200_PP_TXCBLEND_7 0x2f70 1018#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 1019#define R200_PP_TFACTOR_0 0x2ee0 1020#define R200_SE_VTX_FMT_0 0x2088 1021#define R200_SE_VAP_CNTL 0x2080 1022#define R200_SE_TCL_MATRIX_SEL_0 0x2230 1023#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 1024#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 1025#define R200_PP_TXFILTER_5 0x2ca0 1026#define R200_PP_TXFILTER_4 0x2c80 1027#define R200_PP_TXFILTER_3 0x2c60 1028#define R200_PP_TXFILTER_2 0x2c40 1029#define R200_PP_TXFILTER_1 0x2c20 1030#define R200_PP_TXFILTER_0 0x2c00 1031#define R200_PP_TXOFFSET_5 0x2d78 1032#define R200_PP_TXOFFSET_4 0x2d60 1033#define R200_PP_TXOFFSET_3 0x2d48 1034#define R200_PP_TXOFFSET_2 0x2d30 1035#define R200_PP_TXOFFSET_1 0x2d18 1036#define R200_PP_TXOFFSET_0 0x2d00 1037 1038#define R200_PP_CUBIC_FACES_0 0x2c18 1039#define R200_PP_CUBIC_FACES_1 0x2c38 1040#define R200_PP_CUBIC_FACES_2 0x2c58 1041#define R200_PP_CUBIC_FACES_3 0x2c78 1042#define R200_PP_CUBIC_FACES_4 0x2c98 1043#define R200_PP_CUBIC_FACES_5 0x2cb8 1044#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 1045#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 1046#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 1047#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 1048#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 1049#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 1050#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 1051#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 1052#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 1053#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 1054#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 1055#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 1056#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 1057#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 1058#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 1059#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 1060#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 1061#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 1062#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 1063#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 1064#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 1065#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 1066#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 1067#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 1068#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 1069#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 1070#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 1071#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 1072#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 1073#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 1074 1075#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1076#define R200_SE_VTE_CNTL 0x20b0 1077#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 1078#define R200_PP_TAM_DEBUG3 0x2d9c 1079#define R200_PP_CNTL_X 0x2cc4 1080#define R200_SE_VAP_CNTL_STATUS 0x2140 1081#define R200_RE_SCISSOR_TL_0 0x1cd8 1082#define R200_RE_SCISSOR_TL_1 0x1ce0 1083#define R200_RE_SCISSOR_TL_2 0x1ce8 1084#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 1085#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1086#define R200_SE_VTX_STATE_CNTL 0x2180 1087#define R200_RE_POINTSIZE 0x2648 1088#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 1089 1090#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1091#define RADEON_PP_TEX_SIZE_1 0x1d0c 1092#define RADEON_PP_TEX_SIZE_2 0x1d14 1093 1094#define RADEON_PP_CUBIC_FACES_0 0x1d24 1095#define RADEON_PP_CUBIC_FACES_1 0x1d28 1096#define RADEON_PP_CUBIC_FACES_2 0x1d2c 1097#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1098#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 1099#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 1100 1101#define RADEON_SE_TCL_STATE_FLUSH 0x2284 1102 1103#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 1104#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 1105#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 1106#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 1107#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 1108#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 1109#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 1110#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 1111#define R200_3D_DRAW_IMMD_2 0xC0003500 1112#define R200_SE_VTX_FMT_1 0x208c 1113#define R200_RE_CNTL 0x1c50 1114 1115#define R200_RB3D_BLENDCOLOR 0x3218 1116 1117#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 1118 1119#define R200_PP_TRI_PERF 0x2cf8 1120 1121#define R200_PP_AFS_0 0x2f80 1122#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 1123 1124#define R200_VAP_PVS_CNTL_1 0x22D0 1125 1126/* MPEG settings from VHA code */ 1127#define RADEON_VHA_SETTO16_1 0x2694 1128#define RADEON_VHA_SETTO16_2 0x2680 1129#define RADEON_VHA_SETTO0_1 0x1840 1130#define RADEON_VHA_FB_OFFSET 0x19e4 1131#define RADEON_VHA_SETTO1AND70S 0x19d8 1132#define RADEON_VHA_DST_PITCH 0x1408 1133 1134// set as reference header 1135#define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840 1136#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844 1137#define RADEON_VHA_BACKFRAME0_OFF_U 0x1848 1138#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c 1139#define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850 1140#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854 1141#define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858 1142#define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c 1143#define RADEON_VHA_FORWFRAME0_OFF_U 0x1860 1144#define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864 1145#define RADEON_VHA_FORWFRAME0_OFF_V 0x1868 1146#define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880 1147#define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884 1148#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888 1149#define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c 1150#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890 1151#define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894 1152#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898 1153 1154#define R500_D1CRTC_STATUS 0x609c 1155#define R500_D2CRTC_STATUS 0x689c 1156#define R500_CRTC_V_BLANK (1<<0) 1157 1158#define R500_D1CRTC_FRAME_COUNT 0x60a4 1159#define R500_D2CRTC_FRAME_COUNT 0x68a4 1160 1161#define R500_D1MODE_V_COUNTER 0x6530 1162#define R500_D2MODE_V_COUNTER 0x6d30 1163 1164#define R500_D1MODE_VBLANK_STATUS 0x6534 1165#define R500_D2MODE_VBLANK_STATUS 0x6d34 1166#define R500_VBLANK_OCCURED (1<<0) 1167#define R500_VBLANK_ACK (1<<4) 1168#define R500_VBLANK_STAT (1<<12) 1169#define R500_VBLANK_INT (1<<16) 1170 1171#define R500_DxMODE_INT_MASK 0x6540 1172#define R500_D1MODE_INT_MASK (1<<0) 1173#define R500_D2MODE_INT_MASK (1<<8) 1174 1175#define R500_DISP_INTERRUPT_STATUS 0x7edc 1176#define R500_D1_VBLANK_INTERRUPT (1 << 4) 1177#define R500_D2_VBLANK_INTERRUPT (1 << 5) 1178 1179/* Constants */ 1180#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1181 1182#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 1183#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 1184#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 1185#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 1186#define RADEON_LAST_DISPATCH 1 1187 1188#define RADEON_MAX_VB_AGE 0x7fffffff 1189#define RADEON_MAX_VB_VERTS (0xffff) 1190 1191#define RADEON_RING_HIGH_MARK 128 1192 1193#define RADEON_PCIGART_TABLE_SIZE (32*1024) 1194 1195#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 1196#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) 1197#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1198#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1199 1200#define RADEON_WRITE_PLL( addr, val ) \ 1201do { \ 1202 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 1203 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1204 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 1205} while (0) 1206 1207#define RADEON_WRITE_PCIE( addr, val ) \ 1208do { \ 1209 RADEON_WRITE8( RADEON_PCIE_INDEX, \ 1210 ((addr) & 0xff)); \ 1211 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ 1212} while (0) 1213 1214#define R500_WRITE_MCIND( addr, val ) \ 1215do { \ 1216 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1217 RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1218 RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1219} while (0) 1220 1221#define RS480_WRITE_MCIND( addr, val ) \ 1222do { \ 1223 RADEON_WRITE( RS480_NB_MC_INDEX, \ 1224 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ 1225 RADEON_WRITE( RS480_NB_MC_DATA, (val) ); \ 1226 RADEON_WRITE( RS480_NB_MC_INDEX, 0xff ); \ 1227} while (0) 1228 1229#define RS690_WRITE_MCIND( addr, val ) \ 1230do { \ 1231 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1232 RADEON_WRITE(RS690_MC_DATA, val); \ 1233 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1234} while (0) 1235 1236#define IGP_WRITE_MCIND( addr, val ) \ 1237do { \ 1238 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \ 1239 RS690_WRITE_MCIND( addr, val ); \ 1240 else \ 1241 RS480_WRITE_MCIND( addr, val ); \ 1242} while (0) 1243 1244#define CP_PACKET0( reg, n ) \ 1245 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1246#define CP_PACKET0_TABLE( reg, n ) \ 1247 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 1248#define CP_PACKET1( reg0, reg1 ) \ 1249 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 1250#define CP_PACKET2() \ 1251 (RADEON_CP_PACKET2) 1252#define CP_PACKET3( pkt, n ) \ 1253 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1254 1255/* ================================================================ 1256 * Engine control helper macros 1257 */ 1258 1259#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 1260 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1261 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1262 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1263} while (0) 1264 1265#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 1266 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1267 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1268 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1269} while (0) 1270 1271#define RADEON_WAIT_UNTIL_IDLE() do { \ 1272 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1273 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1274 RADEON_WAIT_3D_IDLECLEAN | \ 1275 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1276} while (0) 1277 1278#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 1279 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1280 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1281} while (0) 1282 1283#define RADEON_FLUSH_CACHE() do { \ 1284 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1285 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1286 OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1287 } else { \ 1288 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1289 OUT_RING(R300_RB3D_DC_FLUSH); \ 1290 } \ 1291} while (0) 1292 1293#define RADEON_PURGE_CACHE() do { \ 1294 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1295 OUT_RING(CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1296 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ 1297 } else { \ 1298 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1299 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE ); \ 1300 } \ 1301} while (0) 1302 1303#define RADEON_FLUSH_ZCACHE() do { \ 1304 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1305 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1306 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 1307 } else { \ 1308 OUT_RING( CP_PACKET0( R300_ZB_ZCACHE_CTLSTAT, 0 ) ); \ 1309 OUT_RING( R300_ZC_FLUSH ); \ 1310 } \ 1311} while (0) 1312 1313#define RADEON_PURGE_ZCACHE() do { \ 1314 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1315 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1316 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ 1317 } else { \ 1318 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1319 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ 1320 } \ 1321} while (0) 1322 1323/* ================================================================ 1324 * Misc helper macros 1325 */ 1326 1327/* Perfbox functionality only. 1328 */ 1329#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 1330do { \ 1331 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 1332 u32 head = GET_RING_HEAD( dev_priv ); \ 1333 if (head == dev_priv->ring.tail) \ 1334 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 1335 } \ 1336} while (0) 1337 1338#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 1339do { \ 1340 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 1341 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 1342 int __ret = radeon_do_cp_idle( dev_priv ); \ 1343 if ( __ret ) return __ret; \ 1344 sarea_priv->last_dispatch = 0; \ 1345 radeon_freelist_reset( dev ); \ 1346 } \ 1347} while (0) 1348 1349#define RADEON_DISPATCH_AGE( age ) do { \ 1350 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 1351 OUT_RING( age ); \ 1352} while (0) 1353 1354#define RADEON_FRAME_AGE( age ) do { \ 1355 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 1356 OUT_RING( age ); \ 1357} while (0) 1358 1359#define RADEON_CLEAR_AGE( age ) do { \ 1360 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 1361 OUT_RING( age ); \ 1362} while (0) 1363 1364/* ================================================================ 1365 * Ring control 1366 */ 1367 1368#define RADEON_VERBOSE 0 1369 1370#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; 1371 1372#define BEGIN_RING( n ) do { \ 1373 if ( RADEON_VERBOSE ) { \ 1374 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 1375 } \ 1376 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 1377 COMMIT_RING(); \ 1378 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 1379 } \ 1380 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 1381 ring = dev_priv->ring.start; \ 1382 write = dev_priv->ring.tail; \ 1383 mask = dev_priv->ring.tail_mask; \ 1384} while (0) 1385 1386#define ADVANCE_RING() do { \ 1387 if ( RADEON_VERBOSE ) { \ 1388 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 1389 write, dev_priv->ring.tail ); \ 1390 } \ 1391 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 1392 DRM_ERROR( \ 1393 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 1394 ((dev_priv->ring.tail + _nr) & mask), \ 1395 write, __LINE__); \ 1396 } else \ 1397 dev_priv->ring.tail = write; \ 1398} while (0) 1399 1400#define COMMIT_RING() do { \ 1401 /* Flush writes to ring */ \ 1402 DRM_MEMORYBARRIER(); \ 1403 GET_RING_HEAD( dev_priv ); \ 1404 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ 1405 /* read from PCI bus to ensure correct posting */ \ 1406 RADEON_READ( RADEON_CP_RB_RPTR ); \ 1407} while (0) 1408 1409#define OUT_RING( x ) do { \ 1410 if ( RADEON_VERBOSE ) { \ 1411 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 1412 (unsigned int)(x), write ); \ 1413 } \ 1414 ring[write++] = (x); \ 1415 write &= mask; \ 1416} while (0) 1417 1418#define OUT_RING_REG( reg, val ) do { \ 1419 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 1420 OUT_RING( val ); \ 1421} while (0) 1422 1423#define OUT_RING_TABLE( tab, sz ) do { \ 1424 int _size = (sz); \ 1425 int *_tab = (int *)(tab); \ 1426 \ 1427 if (write + _size > mask) { \ 1428 int _i = (mask+1) - write; \ 1429 _size -= _i; \ 1430 while (_i > 0) { \ 1431 *(int *)(ring + write) = *_tab++; \ 1432 write++; \ 1433 _i--; \ 1434 } \ 1435 write = 0; \ 1436 _tab += _i; \ 1437 } \ 1438 while (_size > 0) { \ 1439 *(ring + write) = *_tab++; \ 1440 write++; \ 1441 _size--; \ 1442 } \ 1443 write &= mask; \ 1444} while (0) 1445 1446#endif /* __RADEON_DRV_H__ */ 1447