radeon_drv.h revision 157617
1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_drv.h 157617 2006-04-09 20:45:45Z anholt $"); 33 34#ifndef __RADEON_DRV_H__ 35#define __RADEON_DRV_H__ 36 37/* General customization: 38 */ 39 40#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 41 42#define DRIVER_NAME "radeon" 43#define DRIVER_DESC "ATI Radeon" 44#define DRIVER_DATE "20060225" 45 46/* Interface history: 47 * 48 * 1.1 - ?? 49 * 1.2 - Add vertex2 ioctl (keith) 50 * - Add stencil capability to clear ioctl (gareth, keith) 51 * - Increase MAX_TEXTURE_LEVELS (brian) 52 * 1.3 - Add cmdbuf ioctl (keith) 53 * - Add support for new radeon packets (keith) 54 * - Add getparam ioctl (keith) 55 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 56 * 1.4 - Add scratch registers to get_param ioctl. 57 * 1.5 - Add r200 packets to cmdbuf ioctl 58 * - Add r200 function to init ioctl 59 * - Add 'scalar2' instruction to cmdbuf 60 * 1.6 - Add static GART memory manager 61 * Add irq handler (won't be turned on unless X server knows to) 62 * Add irq ioctls and irq_active getparam. 63 * Add wait command for cmdbuf ioctl 64 * Add GART offset query for getparam 65 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 66 * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 67 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 68 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 69 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 70 * Add 'GET' queries for starting additional clients on different VT's. 71 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 72 * Add texture rectangle support for r100. 73 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 74 * clients use to tell the DRM where they think the framebuffer is 75 * located in the card's address space 76 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 77 * and GL_EXT_blend_[func|equation]_separate on r200 78 * 1.12- Add R300 CP microcode support - this just loads the CP on r300 79 * (No 3D support yet - just microcode loading). 80 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 81 * - Add hyperz support, add hyperz flags to clear ioctl. 82 * 1.14- Add support for color tiling 83 * - Add R100/R200 surface allocation/free support 84 * 1.15- Add support for texture micro tiling 85 * - Add support for r100 cube maps 86 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 87 * texture filtering on r200 88 * 1.17- Add initial support for R300 (3D). 89 * 1.18- Add support for GL_ATI_fragment_shader, new packets 90 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 91 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 92 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 93 * 1.19- Add support for gart table in FB memory and PCIE r300 94 * 1.20- Add support for r300 texrect 95 * 1.21- Add support for card type getparam 96 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 97 * 1.23- Add new radeon memory map work from benh 98 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 99 */ 100 101#define DRIVER_MAJOR 1 102#define DRIVER_MINOR 24 103#define DRIVER_PATCHLEVEL 0 104 105/* 106 * Radeon chip families 107 */ 108enum radeon_family { 109 CHIP_R100, 110 CHIP_RV100, 111 CHIP_RS100, 112 CHIP_RV200, 113 CHIP_RS200, 114 CHIP_R200, 115 CHIP_RV250, 116 CHIP_RS300, 117 CHIP_RV280, 118 CHIP_R300, 119 CHIP_R350, 120 CHIP_RV350, 121 CHIP_RV380, 122 CHIP_R420, 123 CHIP_RV410, 124 CHIP_RS400, 125 CHIP_LAST, 126}; 127 128enum radeon_cp_microcode_version { 129 UCODE_R100, 130 UCODE_R200, 131 UCODE_R300, 132}; 133 134/* 135 * Chip flags 136 */ 137enum radeon_chip_flags { 138 CHIP_FAMILY_MASK = 0x0000ffffUL, 139 CHIP_FLAGS_MASK = 0xffff0000UL, 140 CHIP_IS_MOBILITY = 0x00010000UL, 141 CHIP_IS_IGP = 0x00020000UL, 142 CHIP_SINGLE_CRTC = 0x00040000UL, 143 CHIP_IS_AGP = 0x00080000UL, 144 CHIP_HAS_HIERZ = 0x00100000UL, 145 CHIP_IS_PCIE = 0x00200000UL, 146 CHIP_NEW_MEMMAP = 0x00400000UL, 147}; 148 149#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ 150 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR)) 151#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) 152 153typedef struct drm_radeon_freelist { 154 unsigned int age; 155 drm_buf_t *buf; 156 struct drm_radeon_freelist *next; 157 struct drm_radeon_freelist *prev; 158} drm_radeon_freelist_t; 159 160typedef struct drm_radeon_ring_buffer { 161 u32 *start; 162 u32 *end; 163 int size; 164 int size_l2qw; 165 166 u32 tail; 167 u32 tail_mask; 168 int space; 169 170 int high_mark; 171} drm_radeon_ring_buffer_t; 172 173typedef struct drm_radeon_depth_clear_t { 174 u32 rb3d_cntl; 175 u32 rb3d_zstencilcntl; 176 u32 se_cntl; 177} drm_radeon_depth_clear_t; 178 179struct drm_radeon_driver_file_fields { 180 int64_t radeon_fb_delta; 181}; 182 183struct mem_block { 184 struct mem_block *next; 185 struct mem_block *prev; 186 int start; 187 int size; 188 DRMFILE filp; /* 0: free, -1: heap, other: real files */ 189}; 190 191struct radeon_surface { 192 int refcount; 193 u32 lower; 194 u32 upper; 195 u32 flags; 196}; 197 198struct radeon_virt_surface { 199 int surface_index; 200 u32 lower; 201 u32 upper; 202 u32 flags; 203 DRMFILE filp; 204}; 205 206typedef struct drm_radeon_private { 207 208 drm_radeon_ring_buffer_t ring; 209 drm_radeon_sarea_t *sarea_priv; 210 211 u32 fb_location; 212 u32 fb_size; 213 int new_memmap; 214 215 int gart_size; 216 u32 gart_vm_start; 217 unsigned long gart_buffers_offset; 218 219 int cp_mode; 220 int cp_running; 221 222 drm_radeon_freelist_t *head; 223 drm_radeon_freelist_t *tail; 224 int last_buf; 225 volatile u32 *scratch; 226 int writeback_works; 227 228 int usec_timeout; 229 230 int microcode_version; 231 232 struct { 233 u32 boxes; 234 int freelist_timeouts; 235 int freelist_loops; 236 int requested_bufs; 237 int last_frame_reads; 238 int last_clear_reads; 239 int clears; 240 int texture_uploads; 241 } stats; 242 243 int do_boxes; 244 int page_flipping; 245 int current_page; 246 247 u32 color_fmt; 248 unsigned int front_offset; 249 unsigned int front_pitch; 250 unsigned int back_offset; 251 unsigned int back_pitch; 252 253 u32 depth_fmt; 254 unsigned int depth_offset; 255 unsigned int depth_pitch; 256 257 u32 front_pitch_offset; 258 u32 back_pitch_offset; 259 u32 depth_pitch_offset; 260 261 drm_radeon_depth_clear_t depth_clear; 262 263 unsigned long ring_offset; 264 unsigned long ring_rptr_offset; 265 unsigned long buffers_offset; 266 unsigned long gart_textures_offset; 267 268 drm_local_map_t *sarea; 269 drm_local_map_t *mmio; 270 drm_local_map_t *cp_ring; 271 drm_local_map_t *ring_rptr; 272 drm_local_map_t *gart_textures; 273 274 struct mem_block *gart_heap; 275 struct mem_block *fb_heap; 276 277 /* SW interrupt */ 278 wait_queue_head_t swi_queue; 279 atomic_t swi_emitted; 280 281 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 282 struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; 283 284 unsigned long pcigart_offset; 285 drm_ati_pcigart_info gart_info; 286 287 u32 scratch_ages[5]; 288 289 /* starting from here on, data is preserved accross an open */ 290 uint32_t flags; /* see radeon_chip_flags */ 291 292} drm_radeon_private_t; 293 294typedef struct drm_radeon_buf_priv { 295 u32 age; 296} drm_radeon_buf_priv_t; 297 298typedef struct drm_radeon_kcmd_buffer { 299 int bufsz; 300 char *buf; 301 int nbox; 302 drm_clip_rect_t __user *boxes; 303} drm_radeon_kcmd_buffer_t; 304 305extern int radeon_no_wb; 306extern drm_ioctl_desc_t radeon_ioctls[]; 307extern int radeon_max_ioctl; 308 309 /* radeon_cp.c */ 310extern int radeon_cp_init(DRM_IOCTL_ARGS); 311extern int radeon_cp_start(DRM_IOCTL_ARGS); 312extern int radeon_cp_stop(DRM_IOCTL_ARGS); 313extern int radeon_cp_reset(DRM_IOCTL_ARGS); 314extern int radeon_cp_idle(DRM_IOCTL_ARGS); 315extern int radeon_cp_resume(DRM_IOCTL_ARGS); 316extern int radeon_engine_reset(DRM_IOCTL_ARGS); 317extern int radeon_fullscreen(DRM_IOCTL_ARGS); 318extern int radeon_cp_buffers(DRM_IOCTL_ARGS); 319 320extern void radeon_freelist_reset(drm_device_t * dev); 321extern drm_buf_t *radeon_freelist_get(drm_device_t * dev); 322 323extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 324 325extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 326 327extern int radeon_mem_alloc(DRM_IOCTL_ARGS); 328extern int radeon_mem_free(DRM_IOCTL_ARGS); 329extern int radeon_mem_init_heap(DRM_IOCTL_ARGS); 330extern void radeon_mem_takedown(struct mem_block **heap); 331extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap); 332 333 /* radeon_irq.c */ 334extern int radeon_irq_emit(DRM_IOCTL_ARGS); 335extern int radeon_irq_wait(DRM_IOCTL_ARGS); 336 337extern void radeon_do_release(drm_device_t * dev); 338extern int radeon_driver_vblank_wait(drm_device_t * dev, 339 unsigned int *sequence); 340extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 341extern void radeon_driver_irq_preinstall(drm_device_t * dev); 342extern void radeon_driver_irq_postinstall(drm_device_t * dev); 343extern void radeon_driver_irq_uninstall(drm_device_t * dev); 344 345extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 346extern int radeon_driver_unload(struct drm_device *dev); 347extern int radeon_driver_firstopen(struct drm_device *dev); 348extern void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp); 349extern void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp); 350extern void radeon_driver_lastclose(drm_device_t * dev); 351extern int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv); 352extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 353 unsigned long arg); 354 355/* r300_cmdbuf.c */ 356extern void r300_init_reg_flags(void); 357 358extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp, 359 drm_file_t* filp_priv, 360 drm_radeon_kcmd_buffer_t* cmdbuf); 361 362/* Flags for stats.boxes 363 */ 364#define RADEON_BOX_DMA_IDLE 0x1 365#define RADEON_BOX_RING_FULL 0x2 366#define RADEON_BOX_FLIP 0x4 367#define RADEON_BOX_WAIT_IDLE 0x8 368#define RADEON_BOX_TEXTURE_LOAD 0x10 369 370/* Register definitions, register access macros and drmAddMap constants 371 * for Radeon kernel driver. 372 */ 373#define RADEON_AGP_COMMAND 0x0f60 374#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 375# define RADEON_AGP_ENABLE (1<<8) 376#define RADEON_AUX_SCISSOR_CNTL 0x26f0 377# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 378# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 379# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 380# define RADEON_SCISSOR_0_ENABLE (1 << 28) 381# define RADEON_SCISSOR_1_ENABLE (1 << 29) 382# define RADEON_SCISSOR_2_ENABLE (1 << 30) 383 384#define RADEON_BUS_CNTL 0x0030 385# define RADEON_BUS_MASTER_DIS (1 << 6) 386 387#define RADEON_CLOCK_CNTL_DATA 0x000c 388# define RADEON_PLL_WR_EN (1 << 7) 389#define RADEON_CLOCK_CNTL_INDEX 0x0008 390#define RADEON_CONFIG_APER_SIZE 0x0108 391#define RADEON_CONFIG_MEMSIZE 0x00f8 392#define RADEON_CRTC_OFFSET 0x0224 393#define RADEON_CRTC_OFFSET_CNTL 0x0228 394# define RADEON_CRTC_TILE_EN (1 << 15) 395# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 396#define RADEON_CRTC2_OFFSET 0x0324 397#define RADEON_CRTC2_OFFSET_CNTL 0x0328 398 399#define RADEON_PCIE_INDEX 0x0030 400#define RADEON_PCIE_DATA 0x0034 401#define RADEON_PCIE_TX_GART_CNTL 0x10 402# define RADEON_PCIE_TX_GART_EN (1 << 0) 403# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1) 404# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1) 405# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1) 406# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3) 407# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3) 408# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5) 409# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8) 410#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 411#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 412#define RADEON_PCIE_TX_GART_BASE 0x13 413#define RADEON_PCIE_TX_GART_START_LO 0x14 414#define RADEON_PCIE_TX_GART_START_HI 0x15 415#define RADEON_PCIE_TX_GART_END_LO 0x16 416#define RADEON_PCIE_TX_GART_END_HI 0x17 417 418#define RADEON_MPP_TB_CONFIG 0x01c0 419#define RADEON_MEM_CNTL 0x0140 420#define RADEON_MEM_SDRAM_MODE_REG 0x0158 421#define RADEON_AGP_BASE 0x0170 422 423#define RADEON_RB3D_COLOROFFSET 0x1c40 424#define RADEON_RB3D_COLORPITCH 0x1c48 425 426#define RADEON_DP_GUI_MASTER_CNTL 0x146c 427# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 428# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 429# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 430# define RADEON_GMC_BRUSH_NONE (15 << 4) 431# define RADEON_GMC_DST_16BPP (4 << 8) 432# define RADEON_GMC_DST_24BPP (5 << 8) 433# define RADEON_GMC_DST_32BPP (6 << 8) 434# define RADEON_GMC_DST_DATATYPE_SHIFT 8 435# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 436# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 437# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 438# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 439# define RADEON_GMC_WR_MSK_DIS (1 << 30) 440# define RADEON_ROP3_S 0x00cc0000 441# define RADEON_ROP3_P 0x00f00000 442#define RADEON_DP_WRITE_MASK 0x16cc 443#define RADEON_DST_PITCH_OFFSET 0x142c 444#define RADEON_DST_PITCH_OFFSET_C 0x1c80 445# define RADEON_DST_TILE_LINEAR (0 << 30) 446# define RADEON_DST_TILE_MACRO (1 << 30) 447# define RADEON_DST_TILE_MICRO (2 << 30) 448# define RADEON_DST_TILE_BOTH (3 << 30) 449 450#define RADEON_SCRATCH_REG0 0x15e0 451#define RADEON_SCRATCH_REG1 0x15e4 452#define RADEON_SCRATCH_REG2 0x15e8 453#define RADEON_SCRATCH_REG3 0x15ec 454#define RADEON_SCRATCH_REG4 0x15f0 455#define RADEON_SCRATCH_REG5 0x15f4 456#define RADEON_SCRATCH_UMSK 0x0770 457#define RADEON_SCRATCH_ADDR 0x0774 458 459#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 460 461#define GET_SCRATCH( x ) (dev_priv->writeback_works \ 462 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ 463 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) 464 465#define RADEON_GEN_INT_CNTL 0x0040 466# define RADEON_CRTC_VBLANK_MASK (1 << 0) 467# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 468# define RADEON_SW_INT_ENABLE (1 << 25) 469 470#define RADEON_GEN_INT_STATUS 0x0044 471# define RADEON_CRTC_VBLANK_STAT (1 << 0) 472# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 473# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 474# define RADEON_SW_INT_TEST (1 << 25) 475# define RADEON_SW_INT_TEST_ACK (1 << 25) 476# define RADEON_SW_INT_FIRE (1 << 26) 477 478#define RADEON_HOST_PATH_CNTL 0x0130 479# define RADEON_HDP_SOFT_RESET (1 << 26) 480# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 481# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 482 483#define RADEON_ISYNC_CNTL 0x1724 484# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 485# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 486# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 487# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 488# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 489# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 490 491#define RADEON_RBBM_GUICNTL 0x172c 492# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 493# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 494# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 495# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 496 497#define RADEON_MC_AGP_LOCATION 0x014c 498#define RADEON_MC_FB_LOCATION 0x0148 499#define RADEON_MCLK_CNTL 0x0012 500# define RADEON_FORCEON_MCLKA (1 << 16) 501# define RADEON_FORCEON_MCLKB (1 << 17) 502# define RADEON_FORCEON_YCLKA (1 << 18) 503# define RADEON_FORCEON_YCLKB (1 << 19) 504# define RADEON_FORCEON_MC (1 << 20) 505# define RADEON_FORCEON_AIC (1 << 21) 506 507#define RADEON_PP_BORDER_COLOR_0 0x1d40 508#define RADEON_PP_BORDER_COLOR_1 0x1d44 509#define RADEON_PP_BORDER_COLOR_2 0x1d48 510#define RADEON_PP_CNTL 0x1c38 511# define RADEON_SCISSOR_ENABLE (1 << 1) 512#define RADEON_PP_LUM_MATRIX 0x1d00 513#define RADEON_PP_MISC 0x1c14 514#define RADEON_PP_ROT_MATRIX_0 0x1d58 515#define RADEON_PP_TXFILTER_0 0x1c54 516#define RADEON_PP_TXOFFSET_0 0x1c5c 517#define RADEON_PP_TXFILTER_1 0x1c6c 518#define RADEON_PP_TXFILTER_2 0x1c84 519 520#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 521# define RADEON_RB2D_DC_FLUSH (3 << 0) 522# define RADEON_RB2D_DC_FREE (3 << 2) 523# define RADEON_RB2D_DC_FLUSH_ALL 0xf 524# define RADEON_RB2D_DC_BUSY (1 << 31) 525#define RADEON_RB3D_CNTL 0x1c3c 526# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 527# define RADEON_PLANE_MASK_ENABLE (1 << 1) 528# define RADEON_DITHER_ENABLE (1 << 2) 529# define RADEON_ROUND_ENABLE (1 << 3) 530# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 531# define RADEON_DITHER_INIT (1 << 5) 532# define RADEON_ROP_ENABLE (1 << 6) 533# define RADEON_STENCIL_ENABLE (1 << 7) 534# define RADEON_Z_ENABLE (1 << 8) 535# define RADEON_ZBLOCK16 (1 << 15) 536#define RADEON_RB3D_DEPTHOFFSET 0x1c24 537#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 538#define RADEON_RB3D_DEPTHPITCH 0x1c28 539#define RADEON_RB3D_PLANEMASK 0x1d84 540#define RADEON_RB3D_STENCILREFMASK 0x1d7c 541#define RADEON_RB3D_ZCACHE_MODE 0x3250 542#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 543# define RADEON_RB3D_ZC_FLUSH (1 << 0) 544# define RADEON_RB3D_ZC_FREE (1 << 2) 545# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 546# define RADEON_RB3D_ZC_BUSY (1 << 31) 547#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 548# define RADEON_Z_TEST_MASK (7 << 4) 549# define RADEON_Z_TEST_ALWAYS (7 << 4) 550# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 551# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 552# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 553# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 554# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 555# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 556# define RADEON_FORCE_Z_DIRTY (1 << 29) 557# define RADEON_Z_WRITE_ENABLE (1 << 30) 558# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 559#define RADEON_RBBM_SOFT_RESET 0x00f0 560# define RADEON_SOFT_RESET_CP (1 << 0) 561# define RADEON_SOFT_RESET_HI (1 << 1) 562# define RADEON_SOFT_RESET_SE (1 << 2) 563# define RADEON_SOFT_RESET_RE (1 << 3) 564# define RADEON_SOFT_RESET_PP (1 << 4) 565# define RADEON_SOFT_RESET_E2 (1 << 5) 566# define RADEON_SOFT_RESET_RB (1 << 6) 567# define RADEON_SOFT_RESET_HDP (1 << 7) 568#define RADEON_RBBM_STATUS 0x0e40 569# define RADEON_RBBM_FIFOCNT_MASK 0x007f 570# define RADEON_RBBM_ACTIVE (1 << 31) 571#define RADEON_RE_LINE_PATTERN 0x1cd0 572#define RADEON_RE_MISC 0x26c4 573#define RADEON_RE_TOP_LEFT 0x26c0 574#define RADEON_RE_WIDTH_HEIGHT 0x1c44 575#define RADEON_RE_STIPPLE_ADDR 0x1cc8 576#define RADEON_RE_STIPPLE_DATA 0x1ccc 577 578#define RADEON_SCISSOR_TL_0 0x1cd8 579#define RADEON_SCISSOR_BR_0 0x1cdc 580#define RADEON_SCISSOR_TL_1 0x1ce0 581#define RADEON_SCISSOR_BR_1 0x1ce4 582#define RADEON_SCISSOR_TL_2 0x1ce8 583#define RADEON_SCISSOR_BR_2 0x1cec 584#define RADEON_SE_COORD_FMT 0x1c50 585#define RADEON_SE_CNTL 0x1c4c 586# define RADEON_FFACE_CULL_CW (0 << 0) 587# define RADEON_BFACE_SOLID (3 << 1) 588# define RADEON_FFACE_SOLID (3 << 3) 589# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 590# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 591# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 592# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 593# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 594# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 595# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 596# define RADEON_FOG_SHADE_FLAT (1 << 14) 597# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 598# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 599# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 600# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 601# define RADEON_ROUND_MODE_TRUNC (0 << 28) 602# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 603#define RADEON_SE_CNTL_STATUS 0x2140 604#define RADEON_SE_LINE_WIDTH 0x1db8 605#define RADEON_SE_VPORT_XSCALE 0x1d98 606#define RADEON_SE_ZBIAS_FACTOR 0x1db0 607#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 608#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 609#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 610# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 611# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 612#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 613#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 614# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 615#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 616#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 617#define RADEON_SURFACE_ACCESS_CLR 0x0bfc 618#define RADEON_SURFACE_CNTL 0x0b00 619# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 620# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 621# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 622# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 623# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 624# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 625# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 626# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 627# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 628#define RADEON_SURFACE0_INFO 0x0b0c 629# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 630# define RADEON_SURF_TILE_MODE_MASK (3 << 16) 631# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 632# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 633# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 634# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 635#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 636#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 637# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 638#define RADEON_SURFACE1_INFO 0x0b1c 639#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 640#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 641#define RADEON_SURFACE2_INFO 0x0b2c 642#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 643#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 644#define RADEON_SURFACE3_INFO 0x0b3c 645#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 646#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 647#define RADEON_SURFACE4_INFO 0x0b4c 648#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 649#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 650#define RADEON_SURFACE5_INFO 0x0b5c 651#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 652#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 653#define RADEON_SURFACE6_INFO 0x0b6c 654#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 655#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 656#define RADEON_SURFACE7_INFO 0x0b7c 657#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 658#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 659#define RADEON_SW_SEMAPHORE 0x013c 660 661#define RADEON_WAIT_UNTIL 0x1720 662# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 663# define RADEON_WAIT_2D_IDLE (1 << 14) 664# define RADEON_WAIT_3D_IDLE (1 << 15) 665# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 666# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 667# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 668 669#define RADEON_RB3D_ZMASKOFFSET 0x3234 670#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 671# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 672# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 673 674/* CP registers */ 675#define RADEON_CP_ME_RAM_ADDR 0x07d4 676#define RADEON_CP_ME_RAM_RADDR 0x07d8 677#define RADEON_CP_ME_RAM_DATAH 0x07dc 678#define RADEON_CP_ME_RAM_DATAL 0x07e0 679 680#define RADEON_CP_RB_BASE 0x0700 681#define RADEON_CP_RB_CNTL 0x0704 682# define RADEON_BUF_SWAP_32BIT (2 << 16) 683#define RADEON_CP_RB_RPTR_ADDR 0x070c 684#define RADEON_CP_RB_RPTR 0x0710 685#define RADEON_CP_RB_WPTR 0x0714 686 687#define RADEON_CP_RB_WPTR_DELAY 0x0718 688# define RADEON_PRE_WRITE_TIMER_SHIFT 0 689# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 690 691#define RADEON_CP_IB_BASE 0x0738 692 693#define RADEON_CP_CSQ_CNTL 0x0740 694# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 695# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 696# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 697# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 698# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 699# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 700# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 701 702#define RADEON_AIC_CNTL 0x01d0 703# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 704#define RADEON_AIC_STAT 0x01d4 705#define RADEON_AIC_PT_BASE 0x01d8 706#define RADEON_AIC_LO_ADDR 0x01dc 707#define RADEON_AIC_HI_ADDR 0x01e0 708#define RADEON_AIC_TLB_ADDR 0x01e4 709#define RADEON_AIC_TLB_DATA 0x01e8 710 711/* CP command packets */ 712#define RADEON_CP_PACKET0 0x00000000 713# define RADEON_ONE_REG_WR (1 << 15) 714#define RADEON_CP_PACKET1 0x40000000 715#define RADEON_CP_PACKET2 0x80000000 716#define RADEON_CP_PACKET3 0xC0000000 717# define RADEON_CP_NOP 0x00001000 718# define RADEON_CP_NEXT_CHAR 0x00001900 719# define RADEON_CP_PLY_NEXTSCAN 0x00001D00 720# define RADEON_CP_SET_SCISSORS 0x00001E00 721 /* GEN_INDX_PRIM is unsupported starting with R300 */ 722# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 723# define RADEON_WAIT_FOR_IDLE 0x00002600 724# define RADEON_3D_DRAW_VBUF 0x00002800 725# define RADEON_3D_DRAW_IMMD 0x00002900 726# define RADEON_3D_DRAW_INDX 0x00002A00 727# define RADEON_CP_LOAD_PALETTE 0x00002C00 728# define RADEON_3D_LOAD_VBPNTR 0x00002F00 729# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 730# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 731# define RADEON_3D_CLEAR_ZMASK 0x00003200 732# define RADEON_CP_INDX_BUFFER 0x00003300 733# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 734# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 735# define RADEON_CP_3D_DRAW_INDX_2 0x00003600 736# define RADEON_3D_CLEAR_HIZ 0x00003700 737# define RADEON_CP_3D_CLEAR_CMASK 0x00003802 738# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 739# define RADEON_CNTL_PAINT_MULTI 0x00009A00 740# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 741# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 742 743#define RADEON_CP_PACKET_MASK 0xC0000000 744#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 745#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 746#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 747#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 748 749#define RADEON_VTX_Z_PRESENT (1 << 31) 750#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 751 752#define RADEON_PRIM_TYPE_NONE (0 << 0) 753#define RADEON_PRIM_TYPE_POINT (1 << 0) 754#define RADEON_PRIM_TYPE_LINE (2 << 0) 755#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 756#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 757#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 758#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 759#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 760#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 761#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 762#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 763#define RADEON_PRIM_TYPE_MASK 0xf 764#define RADEON_PRIM_WALK_IND (1 << 4) 765#define RADEON_PRIM_WALK_LIST (2 << 4) 766#define RADEON_PRIM_WALK_RING (3 << 4) 767#define RADEON_COLOR_ORDER_BGRA (0 << 6) 768#define RADEON_COLOR_ORDER_RGBA (1 << 6) 769#define RADEON_MAOS_ENABLE (1 << 7) 770#define RADEON_VTX_FMT_R128_MODE (0 << 8) 771#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 772#define RADEON_NUM_VERTICES_SHIFT 16 773 774#define RADEON_COLOR_FORMAT_CI8 2 775#define RADEON_COLOR_FORMAT_ARGB1555 3 776#define RADEON_COLOR_FORMAT_RGB565 4 777#define RADEON_COLOR_FORMAT_ARGB8888 6 778#define RADEON_COLOR_FORMAT_RGB332 7 779#define RADEON_COLOR_FORMAT_RGB8 9 780#define RADEON_COLOR_FORMAT_ARGB4444 15 781 782#define RADEON_TXFORMAT_I8 0 783#define RADEON_TXFORMAT_AI88 1 784#define RADEON_TXFORMAT_RGB332 2 785#define RADEON_TXFORMAT_ARGB1555 3 786#define RADEON_TXFORMAT_RGB565 4 787#define RADEON_TXFORMAT_ARGB4444 5 788#define RADEON_TXFORMAT_ARGB8888 6 789#define RADEON_TXFORMAT_RGBA8888 7 790#define RADEON_TXFORMAT_Y8 8 791#define RADEON_TXFORMAT_VYUY422 10 792#define RADEON_TXFORMAT_YVYU422 11 793#define RADEON_TXFORMAT_DXT1 12 794#define RADEON_TXFORMAT_DXT23 14 795#define RADEON_TXFORMAT_DXT45 15 796 797#define R200_PP_TXCBLEND_0 0x2f00 798#define R200_PP_TXCBLEND_1 0x2f10 799#define R200_PP_TXCBLEND_2 0x2f20 800#define R200_PP_TXCBLEND_3 0x2f30 801#define R200_PP_TXCBLEND_4 0x2f40 802#define R200_PP_TXCBLEND_5 0x2f50 803#define R200_PP_TXCBLEND_6 0x2f60 804#define R200_PP_TXCBLEND_7 0x2f70 805#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 806#define R200_PP_TFACTOR_0 0x2ee0 807#define R200_SE_VTX_FMT_0 0x2088 808#define R200_SE_VAP_CNTL 0x2080 809#define R200_SE_TCL_MATRIX_SEL_0 0x2230 810#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 811#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 812#define R200_PP_TXFILTER_5 0x2ca0 813#define R200_PP_TXFILTER_4 0x2c80 814#define R200_PP_TXFILTER_3 0x2c60 815#define R200_PP_TXFILTER_2 0x2c40 816#define R200_PP_TXFILTER_1 0x2c20 817#define R200_PP_TXFILTER_0 0x2c00 818#define R200_PP_TXOFFSET_5 0x2d78 819#define R200_PP_TXOFFSET_4 0x2d60 820#define R200_PP_TXOFFSET_3 0x2d48 821#define R200_PP_TXOFFSET_2 0x2d30 822#define R200_PP_TXOFFSET_1 0x2d18 823#define R200_PP_TXOFFSET_0 0x2d00 824 825#define R200_PP_CUBIC_FACES_0 0x2c18 826#define R200_PP_CUBIC_FACES_1 0x2c38 827#define R200_PP_CUBIC_FACES_2 0x2c58 828#define R200_PP_CUBIC_FACES_3 0x2c78 829#define R200_PP_CUBIC_FACES_4 0x2c98 830#define R200_PP_CUBIC_FACES_5 0x2cb8 831#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 832#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 833#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 834#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 835#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 836#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 837#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 838#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 839#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 840#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 841#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 842#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 843#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 844#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 845#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 846#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 847#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 848#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 849#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 850#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 851#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 852#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 853#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 854#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 855#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 856#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 857#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 858#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 859#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 860#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 861 862#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 863#define R200_SE_VTE_CNTL 0x20b0 864#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 865#define R200_PP_TAM_DEBUG3 0x2d9c 866#define R200_PP_CNTL_X 0x2cc4 867#define R200_SE_VAP_CNTL_STATUS 0x2140 868#define R200_RE_SCISSOR_TL_0 0x1cd8 869#define R200_RE_SCISSOR_TL_1 0x1ce0 870#define R200_RE_SCISSOR_TL_2 0x1ce8 871#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 872#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 873#define R200_SE_VTX_STATE_CNTL 0x2180 874#define R200_RE_POINTSIZE 0x2648 875#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 876 877#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 878#define RADEON_PP_TEX_SIZE_1 0x1d0c 879#define RADEON_PP_TEX_SIZE_2 0x1d14 880 881#define RADEON_PP_CUBIC_FACES_0 0x1d24 882#define RADEON_PP_CUBIC_FACES_1 0x1d28 883#define RADEON_PP_CUBIC_FACES_2 0x1d2c 884#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 885#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 886#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 887 888#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 889#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 890#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 891#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 892#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 893#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 894#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 895#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 896#define R200_3D_DRAW_IMMD_2 0xC0003500 897#define R200_SE_VTX_FMT_1 0x208c 898#define R200_RE_CNTL 0x1c50 899 900#define R200_RB3D_BLENDCOLOR 0x3218 901 902#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 903 904#define R200_PP_TRI_PERF 0x2cf8 905 906#define R200_PP_AFS_0 0x2f80 907#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 908 909/* MPEG settings from VHA code */ 910#define RADEON_VHA_SETTO16_1 0x2694 911#define RADEON_VHA_SETTO16_2 0x2680 912#define RADEON_VHA_SETTO0_1 0x1840 913#define RADEON_VHA_FB_OFFSET 0x19e4 914#define RADEON_VHA_SETTO1AND70S 0x19d8 915#define RADEON_VHA_DST_PITCH 0x1408 916 917// set as reference header 918#define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840 919#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844 920#define RADEON_VHA_BACKFRAME0_OFF_U 0x1848 921#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c 922#define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850 923#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854 924#define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858 925#define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c 926#define RADEON_VHA_FORWFRAME0_OFF_U 0x1860 927#define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864 928#define RADEON_VHA_FORWFRAME0_OFF_V 0x1868 929#define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880 930#define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884 931#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888 932#define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c 933#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890 934#define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894 935#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898 936 937 938 939/* Constants */ 940#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 941 942#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 943#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 944#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 945#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 946#define RADEON_LAST_DISPATCH 1 947 948#define RADEON_MAX_VB_AGE 0x7fffffff 949#define RADEON_MAX_VB_VERTS (0xffff) 950 951#define RADEON_RING_HIGH_MARK 128 952 953#define RADEON_PCIGART_TABLE_SIZE (32*1024) 954 955#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 956#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) 957#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 958#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 959 960#define RADEON_WRITE_PLL( addr, val ) \ 961do { \ 962 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 963 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 964 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 965} while (0) 966 967#define RADEON_WRITE_PCIE( addr, val ) \ 968do { \ 969 RADEON_WRITE8( RADEON_PCIE_INDEX, \ 970 ((addr) & 0xff)); \ 971 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ 972} while (0) 973 974#define CP_PACKET0( reg, n ) \ 975 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 976#define CP_PACKET0_TABLE( reg, n ) \ 977 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 978#define CP_PACKET1( reg0, reg1 ) \ 979 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 980#define CP_PACKET2() \ 981 (RADEON_CP_PACKET2) 982#define CP_PACKET3( pkt, n ) \ 983 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 984 985/* ================================================================ 986 * Engine control helper macros 987 */ 988 989#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 990 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 991 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 992 RADEON_WAIT_HOST_IDLECLEAN) ); \ 993} while (0) 994 995#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 996 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 997 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 998 RADEON_WAIT_HOST_IDLECLEAN) ); \ 999} while (0) 1000 1001#define RADEON_WAIT_UNTIL_IDLE() do { \ 1002 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1003 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1004 RADEON_WAIT_3D_IDLECLEAN | \ 1005 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1006} while (0) 1007 1008#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 1009 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1010 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1011} while (0) 1012 1013#define RADEON_FLUSH_CACHE() do { \ 1014 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ 1015 OUT_RING( RADEON_RB2D_DC_FLUSH ); \ 1016} while (0) 1017 1018#define RADEON_PURGE_CACHE() do { \ 1019 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ 1020 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \ 1021} while (0) 1022 1023#define RADEON_FLUSH_ZCACHE() do { \ 1024 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1025 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 1026} while (0) 1027 1028#define RADEON_PURGE_ZCACHE() do { \ 1029 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1030 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ 1031} while (0) 1032 1033/* ================================================================ 1034 * Misc helper macros 1035 */ 1036 1037/* Perfbox functionality only. 1038 */ 1039#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 1040do { \ 1041 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 1042 u32 head = GET_RING_HEAD( dev_priv ); \ 1043 if (head == dev_priv->ring.tail) \ 1044 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 1045 } \ 1046} while (0) 1047 1048#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 1049do { \ 1050 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 1051 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 1052 int __ret = radeon_do_cp_idle( dev_priv ); \ 1053 if ( __ret ) return __ret; \ 1054 sarea_priv->last_dispatch = 0; \ 1055 radeon_freelist_reset( dev ); \ 1056 } \ 1057} while (0) 1058 1059#define RADEON_DISPATCH_AGE( age ) do { \ 1060 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 1061 OUT_RING( age ); \ 1062} while (0) 1063 1064#define RADEON_FRAME_AGE( age ) do { \ 1065 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 1066 OUT_RING( age ); \ 1067} while (0) 1068 1069#define RADEON_CLEAR_AGE( age ) do { \ 1070 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 1071 OUT_RING( age ); \ 1072} while (0) 1073 1074/* ================================================================ 1075 * Ring control 1076 */ 1077 1078#define RADEON_VERBOSE 0 1079 1080#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; 1081 1082#define BEGIN_RING( n ) do { \ 1083 if ( RADEON_VERBOSE ) { \ 1084 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ 1085 n, __FUNCTION__ ); \ 1086 } \ 1087 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 1088 COMMIT_RING(); \ 1089 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 1090 } \ 1091 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 1092 ring = dev_priv->ring.start; \ 1093 write = dev_priv->ring.tail; \ 1094 mask = dev_priv->ring.tail_mask; \ 1095} while (0) 1096 1097#define ADVANCE_RING() do { \ 1098 if ( RADEON_VERBOSE ) { \ 1099 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 1100 write, dev_priv->ring.tail ); \ 1101 } \ 1102 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 1103 DRM_ERROR( \ 1104 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 1105 ((dev_priv->ring.tail + _nr) & mask), \ 1106 write, __LINE__); \ 1107 } else \ 1108 dev_priv->ring.tail = write; \ 1109} while (0) 1110 1111#define COMMIT_RING() do { \ 1112 /* Flush writes to ring */ \ 1113 DRM_MEMORYBARRIER(); \ 1114 GET_RING_HEAD( dev_priv ); \ 1115 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ 1116 /* read from PCI bus to ensure correct posting */ \ 1117 RADEON_READ( RADEON_CP_RB_RPTR ); \ 1118} while (0) 1119 1120#define OUT_RING( x ) do { \ 1121 if ( RADEON_VERBOSE ) { \ 1122 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 1123 (unsigned int)(x), write ); \ 1124 } \ 1125 ring[write++] = (x); \ 1126 write &= mask; \ 1127} while (0) 1128 1129#define OUT_RING_REG( reg, val ) do { \ 1130 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 1131 OUT_RING( val ); \ 1132} while (0) 1133 1134#define OUT_RING_TABLE( tab, sz ) do { \ 1135 int _size = (sz); \ 1136 int *_tab = (int *)(tab); \ 1137 \ 1138 if (write + _size > mask) { \ 1139 int _i = (mask+1) - write; \ 1140 _size -= _i; \ 1141 while (_i > 0) { \ 1142 *(int *)(ring + write) = *_tab++; \ 1143 write++; \ 1144 _i--; \ 1145 } \ 1146 write = 0; \ 1147 _tab += _i; \ 1148 } \ 1149 while (_size > 0) { \ 1150 *(ring + write) = *_tab++; \ 1151 write++; \ 1152 _size--; \ 1153 } \ 1154 write &= mask; \ 1155} while (0) 1156 1157#endif /* __RADEON_DRV_H__ */ 1158