radeon_drv.h revision 145132
1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- */ 2/*- 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * 30 * $FreeBSD: head/sys/dev/drm/radeon_drv.h 145132 2005-04-16 03:44:47Z anholt $ 31 */ 32 33#ifndef __RADEON_DRV_H__ 34#define __RADEON_DRV_H__ 35 36#ifdef __linux__ 37#include "radeon_i2c.h" 38#endif /* __linux__ */ 39 40/* General customization: 41 */ 42 43#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 44 45#define DRIVER_NAME "radeon" 46#define DRIVER_DESC "ATI Radeon" 47#define DRIVER_DATE "20050311" 48 49/* Interface history: 50 * 51 * 1.1 - ?? 52 * 1.2 - Add vertex2 ioctl (keith) 53 * - Add stencil capability to clear ioctl (gareth, keith) 54 * - Increase MAX_TEXTURE_LEVELS (brian) 55 * 1.3 - Add cmdbuf ioctl (keith) 56 * - Add support for new radeon packets (keith) 57 * - Add getparam ioctl (keith) 58 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 59 * 1.4 - Add scratch registers to get_param ioctl. 60 * 1.5 - Add r200 packets to cmdbuf ioctl 61 * - Add r200 function to init ioctl 62 * - Add 'scalar2' instruction to cmdbuf 63 * 1.6 - Add static GART memory manager 64 * Add irq handler (won't be turned on unless X server knows to) 65 * Add irq ioctls and irq_active getparam. 66 * Add wait command for cmdbuf ioctl 67 * Add GART offset query for getparam 68 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 69 * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 70 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 71 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 72 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 73 * Add 'GET' queries for starting additional clients on different VT's. 74 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 75 * Add texture rectangle support for r100. 76 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 77 * clients use to tell the DRM where they think the framebuffer is 78 * located in the card's address space 79 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 80 * and GL_EXT_blend_[func|equation]_separate on r200 81 * 1.12- Add R300 CP microcode support - this just loads the CP on r300 82 * (No 3D support yet - just microcode loading). 83 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 84 * - Add hyperz support, add hyperz flags to clear ioctl. 85 * 1.14- Add support for color tiling 86 * - Add R100/R200 surface allocation/free support 87 * 1.15- Add support for texture micro tiling 88 * - Add support for r100 cube maps 89 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 90 * texture filtering on r200 91 */ 92 93#define DRIVER_MAJOR 1 94#define DRIVER_MINOR 16 95#define DRIVER_PATCHLEVEL 0 96 97enum radeon_family { 98 CHIP_R100, 99 CHIP_RS100, 100 CHIP_RV100, 101 CHIP_R200, 102 CHIP_RV200, 103 CHIP_RS200, 104 CHIP_R250, 105 CHIP_RS250, 106 CHIP_RV250, 107 CHIP_RV280, 108 CHIP_R300, 109 CHIP_RS300, 110 CHIP_RV350, 111 CHIP_LAST, 112}; 113 114enum radeon_cp_microcode_version { 115 UCODE_R100, 116 UCODE_R200, 117 UCODE_R300, 118}; 119 120/* 121 * Chip flags 122 */ 123enum radeon_chip_flags { 124 CHIP_FAMILY_MASK = 0x0000ffffUL, 125 CHIP_FLAGS_MASK = 0xffff0000UL, 126 CHIP_IS_MOBILITY = 0x00010000UL, 127 CHIP_IS_IGP = 0x00020000UL, 128 CHIP_SINGLE_CRTC = 0x00040000UL, 129 CHIP_IS_AGP = 0x00080000UL, 130 CHIP_HAS_HIERZ = 0x00100000UL, 131}; 132 133#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) 134#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) 135 136typedef struct drm_radeon_freelist { 137 unsigned int age; 138 drm_buf_t *buf; 139 struct drm_radeon_freelist *next; 140 struct drm_radeon_freelist *prev; 141} drm_radeon_freelist_t; 142 143typedef struct drm_radeon_ring_buffer { 144 u32 *start; 145 u32 *end; 146 int size; 147 int size_l2qw; 148 149 u32 tail; 150 u32 tail_mask; 151 int space; 152 153 int high_mark; 154} drm_radeon_ring_buffer_t; 155 156typedef struct drm_radeon_depth_clear_t { 157 u32 rb3d_cntl; 158 u32 rb3d_zstencilcntl; 159 u32 se_cntl; 160} drm_radeon_depth_clear_t; 161 162struct drm_radeon_driver_file_fields { 163 int64_t radeon_fb_delta; 164}; 165 166struct mem_block { 167 struct mem_block *next; 168 struct mem_block *prev; 169 int start; 170 int size; 171 DRMFILE filp; /* 0: free, -1: heap, other: real files */ 172}; 173 174struct radeon_surface { 175 int refcount; 176 u32 lower; 177 u32 upper; 178 u32 flags; 179}; 180 181struct radeon_virt_surface { 182 int surface_index; 183 u32 lower; 184 u32 upper; 185 u32 flags; 186 DRMFILE filp; 187}; 188 189typedef struct drm_radeon_private { 190 191 drm_radeon_ring_buffer_t ring; 192 drm_radeon_sarea_t *sarea_priv; 193 194 u32 fb_location; 195 196 int gart_size; 197 u32 gart_vm_start; 198 unsigned long gart_buffers_offset; 199 200 int cp_mode; 201 int cp_running; 202 203 drm_radeon_freelist_t *head; 204 drm_radeon_freelist_t *tail; 205 int last_buf; 206 volatile u32 *scratch; 207 int writeback_works; 208 209 int usec_timeout; 210 211 int microcode_version; 212 213 unsigned long phys_pci_gart; 214 dma_addr_t bus_pci_gart; 215 216 struct { 217 u32 boxes; 218 int freelist_timeouts; 219 int freelist_loops; 220 int requested_bufs; 221 int last_frame_reads; 222 int last_clear_reads; 223 int clears; 224 int texture_uploads; 225 } stats; 226 227 int do_boxes; 228 int page_flipping; 229 int current_page; 230 231 u32 color_fmt; 232 unsigned int front_offset; 233 unsigned int front_pitch; 234 unsigned int back_offset; 235 unsigned int back_pitch; 236 237 u32 depth_fmt; 238 unsigned int depth_offset; 239 unsigned int depth_pitch; 240 241 u32 front_pitch_offset; 242 u32 back_pitch_offset; 243 u32 depth_pitch_offset; 244 245 drm_radeon_depth_clear_t depth_clear; 246 247 unsigned long fb_offset; 248 unsigned long mmio_offset; 249 unsigned long ring_offset; 250 unsigned long ring_rptr_offset; 251 unsigned long buffers_offset; 252 unsigned long gart_textures_offset; 253 254 drm_local_map_t *sarea; 255 drm_local_map_t *mmio; 256 drm_local_map_t *cp_ring; 257 drm_local_map_t *ring_rptr; 258 drm_local_map_t *gart_textures; 259 260 struct mem_block *gart_heap; 261 struct mem_block *fb_heap; 262 263 /* SW interrupt */ 264 wait_queue_head_t swi_queue; 265 atomic_t swi_emitted; 266 267 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 268 struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; 269 270 /* starting from here on, data is preserved accross an open */ 271 uint32_t flags; /* see radeon_chip_flags */ 272 273#ifdef __linux__ 274 struct radeon_i2c_chan i2c[4]; 275#endif /* __linux__ */ 276} drm_radeon_private_t; 277 278typedef struct drm_radeon_buf_priv { 279 u32 age; 280} drm_radeon_buf_priv_t; 281 282 /* radeon_cp.c */ 283extern int radeon_cp_init(DRM_IOCTL_ARGS); 284extern int radeon_cp_start(DRM_IOCTL_ARGS); 285extern int radeon_cp_stop(DRM_IOCTL_ARGS); 286extern int radeon_cp_reset(DRM_IOCTL_ARGS); 287extern int radeon_cp_idle(DRM_IOCTL_ARGS); 288extern int radeon_cp_resume(DRM_IOCTL_ARGS); 289extern int radeon_engine_reset(DRM_IOCTL_ARGS); 290extern int radeon_fullscreen(DRM_IOCTL_ARGS); 291extern int radeon_cp_buffers(DRM_IOCTL_ARGS); 292 293extern void radeon_freelist_reset(drm_device_t * dev); 294extern drm_buf_t *radeon_freelist_get(drm_device_t * dev); 295 296extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 297 298extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 299 300extern int radeon_mem_alloc(DRM_IOCTL_ARGS); 301extern int radeon_mem_free(DRM_IOCTL_ARGS); 302extern int radeon_mem_init_heap(DRM_IOCTL_ARGS); 303extern void radeon_mem_takedown(struct mem_block **heap); 304extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap); 305 306 /* radeon_irq.c */ 307extern int radeon_irq_emit(DRM_IOCTL_ARGS); 308extern int radeon_irq_wait(DRM_IOCTL_ARGS); 309 310extern void radeon_do_release(drm_device_t * dev); 311extern int radeon_driver_vblank_wait(drm_device_t * dev, 312 unsigned int *sequence); 313extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 314extern void radeon_driver_irq_preinstall(drm_device_t * dev); 315extern void radeon_driver_irq_postinstall(drm_device_t * dev); 316extern void radeon_driver_irq_uninstall(drm_device_t * dev); 317extern void radeon_driver_prerelease(drm_device_t * dev, DRMFILE filp); 318extern void radeon_driver_pretakedown(drm_device_t * dev); 319extern int radeon_driver_open_helper(drm_device_t * dev, 320 drm_file_t * filp_priv); 321extern void radeon_driver_free_filp_priv(drm_device_t * dev, 322 drm_file_t * filp_priv); 323 324/* Flags for stats.boxes 325 */ 326#define RADEON_BOX_DMA_IDLE 0x1 327#define RADEON_BOX_RING_FULL 0x2 328#define RADEON_BOX_FLIP 0x4 329#define RADEON_BOX_WAIT_IDLE 0x8 330#define RADEON_BOX_TEXTURE_LOAD 0x10 331 332/* Register definitions, register access macros and drmAddMap constants 333 * for Radeon kernel driver. 334 */ 335#define RADEON_AGP_COMMAND 0x0f60 336#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 337# define RADEON_AGP_ENABLE (1<<8) 338 339#define RADEON_AUX_SCISSOR_CNTL 0x26f0 340# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 341# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 342# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 343# define RADEON_SCISSOR_0_ENABLE (1 << 28) 344# define RADEON_SCISSOR_1_ENABLE (1 << 29) 345# define RADEON_SCISSOR_2_ENABLE (1 << 30) 346 347#define RADEON_BUS_CNTL 0x0030 348# define RADEON_BUS_MASTER_DIS (1 << 6) 349 350#define RADEON_CLOCK_CNTL_DATA 0x000c 351# define RADEON_PLL_WR_EN (1 << 7) 352#define RADEON_CLOCK_CNTL_INDEX 0x0008 353#define RADEON_CONFIG_APER_SIZE 0x0108 354#define RADEON_CRTC_OFFSET 0x0224 355#define RADEON_CRTC_OFFSET_CNTL 0x0228 356# define RADEON_CRTC_TILE_EN (1 << 15) 357# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 358#define RADEON_CRTC2_OFFSET 0x0324 359#define RADEON_CRTC2_OFFSET_CNTL 0x0328 360 361#define RADEON_MPP_TB_CONFIG 0x01c0 362#define RADEON_MEM_CNTL 0x0140 363#define RADEON_MEM_SDRAM_MODE_REG 0x0158 364#define RADEON_AGP_BASE 0x0170 365 366#define RADEON_RB3D_COLOROFFSET 0x1c40 367#define RADEON_RB3D_COLORPITCH 0x1c48 368 369#define RADEON_DP_GUI_MASTER_CNTL 0x146c 370# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 371# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 372# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 373# define RADEON_GMC_BRUSH_NONE (15 << 4) 374# define RADEON_GMC_DST_16BPP (4 << 8) 375# define RADEON_GMC_DST_24BPP (5 << 8) 376# define RADEON_GMC_DST_32BPP (6 << 8) 377# define RADEON_GMC_DST_DATATYPE_SHIFT 8 378# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 379# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 380# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 381# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 382# define RADEON_GMC_WR_MSK_DIS (1 << 30) 383# define RADEON_ROP3_S 0x00cc0000 384# define RADEON_ROP3_P 0x00f00000 385#define RADEON_DP_WRITE_MASK 0x16cc 386#define RADEON_DST_PITCH_OFFSET 0x142c 387#define RADEON_DST_PITCH_OFFSET_C 0x1c80 388# define RADEON_DST_TILE_LINEAR (0 << 30) 389# define RADEON_DST_TILE_MACRO (1 << 30) 390# define RADEON_DST_TILE_MICRO (2 << 30) 391# define RADEON_DST_TILE_BOTH (3 << 30) 392 393#define RADEON_SCRATCH_REG0 0x15e0 394#define RADEON_SCRATCH_REG1 0x15e4 395#define RADEON_SCRATCH_REG2 0x15e8 396#define RADEON_SCRATCH_REG3 0x15ec 397#define RADEON_SCRATCH_REG4 0x15f0 398#define RADEON_SCRATCH_REG5 0x15f4 399#define RADEON_SCRATCH_UMSK 0x0770 400#define RADEON_SCRATCH_ADDR 0x0774 401 402#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 403 404#define GET_SCRATCH( x ) (dev_priv->writeback_works \ 405 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ 406 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) 407 408#define RADEON_GEN_INT_CNTL 0x0040 409# define RADEON_CRTC_VBLANK_MASK (1 << 0) 410# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 411# define RADEON_SW_INT_ENABLE (1 << 25) 412 413#define RADEON_GEN_INT_STATUS 0x0044 414# define RADEON_CRTC_VBLANK_STAT (1 << 0) 415# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 416# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 417# define RADEON_SW_INT_TEST (1 << 25) 418# define RADEON_SW_INT_TEST_ACK (1 << 25) 419# define RADEON_SW_INT_FIRE (1 << 26) 420 421#define RADEON_HOST_PATH_CNTL 0x0130 422# define RADEON_HDP_SOFT_RESET (1 << 26) 423# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 424# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 425 426#define RADEON_ISYNC_CNTL 0x1724 427# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 428# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 429# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 430# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 431# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 432# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 433 434#define RADEON_RBBM_GUICNTL 0x172c 435# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 436# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 437# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 438# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 439 440#define RADEON_MC_AGP_LOCATION 0x014c 441#define RADEON_MC_FB_LOCATION 0x0148 442#define RADEON_MCLK_CNTL 0x0012 443# define RADEON_FORCEON_MCLKA (1 << 16) 444# define RADEON_FORCEON_MCLKB (1 << 17) 445# define RADEON_FORCEON_YCLKA (1 << 18) 446# define RADEON_FORCEON_YCLKB (1 << 19) 447# define RADEON_FORCEON_MC (1 << 20) 448# define RADEON_FORCEON_AIC (1 << 21) 449 450#define RADEON_PP_BORDER_COLOR_0 0x1d40 451#define RADEON_PP_BORDER_COLOR_1 0x1d44 452#define RADEON_PP_BORDER_COLOR_2 0x1d48 453#define RADEON_PP_CNTL 0x1c38 454# define RADEON_SCISSOR_ENABLE (1 << 1) 455#define RADEON_PP_LUM_MATRIX 0x1d00 456#define RADEON_PP_MISC 0x1c14 457#define RADEON_PP_ROT_MATRIX_0 0x1d58 458#define RADEON_PP_TXFILTER_0 0x1c54 459#define RADEON_PP_TXOFFSET_0 0x1c5c 460#define RADEON_PP_TXFILTER_1 0x1c6c 461#define RADEON_PP_TXFILTER_2 0x1c84 462 463#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 464# define RADEON_RB2D_DC_FLUSH (3 << 0) 465# define RADEON_RB2D_DC_FREE (3 << 2) 466# define RADEON_RB2D_DC_FLUSH_ALL 0xf 467# define RADEON_RB2D_DC_BUSY (1 << 31) 468#define RADEON_RB3D_CNTL 0x1c3c 469# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 470# define RADEON_PLANE_MASK_ENABLE (1 << 1) 471# define RADEON_DITHER_ENABLE (1 << 2) 472# define RADEON_ROUND_ENABLE (1 << 3) 473# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 474# define RADEON_DITHER_INIT (1 << 5) 475# define RADEON_ROP_ENABLE (1 << 6) 476# define RADEON_STENCIL_ENABLE (1 << 7) 477# define RADEON_Z_ENABLE (1 << 8) 478# define RADEON_ZBLOCK16 (1 << 15) 479#define RADEON_RB3D_DEPTHOFFSET 0x1c24 480#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 481#define RADEON_RB3D_DEPTHPITCH 0x1c28 482#define RADEON_RB3D_PLANEMASK 0x1d84 483#define RADEON_RB3D_STENCILREFMASK 0x1d7c 484#define RADEON_RB3D_ZCACHE_MODE 0x3250 485#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 486# define RADEON_RB3D_ZC_FLUSH (1 << 0) 487# define RADEON_RB3D_ZC_FREE (1 << 2) 488# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 489# define RADEON_RB3D_ZC_BUSY (1 << 31) 490#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 491# define RADEON_Z_TEST_MASK (7 << 4) 492# define RADEON_Z_TEST_ALWAYS (7 << 4) 493# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 494# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 495# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 496# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 497# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 498# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 499# define RADEON_FORCE_Z_DIRTY (1 << 29) 500# define RADEON_Z_WRITE_ENABLE (1 << 30) 501# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 502#define RADEON_RBBM_SOFT_RESET 0x00f0 503# define RADEON_SOFT_RESET_CP (1 << 0) 504# define RADEON_SOFT_RESET_HI (1 << 1) 505# define RADEON_SOFT_RESET_SE (1 << 2) 506# define RADEON_SOFT_RESET_RE (1 << 3) 507# define RADEON_SOFT_RESET_PP (1 << 4) 508# define RADEON_SOFT_RESET_E2 (1 << 5) 509# define RADEON_SOFT_RESET_RB (1 << 6) 510# define RADEON_SOFT_RESET_HDP (1 << 7) 511#define RADEON_RBBM_STATUS 0x0e40 512# define RADEON_RBBM_FIFOCNT_MASK 0x007f 513# define RADEON_RBBM_ACTIVE (1 << 31) 514#define RADEON_RE_LINE_PATTERN 0x1cd0 515#define RADEON_RE_MISC 0x26c4 516#define RADEON_RE_TOP_LEFT 0x26c0 517#define RADEON_RE_WIDTH_HEIGHT 0x1c44 518#define RADEON_RE_STIPPLE_ADDR 0x1cc8 519#define RADEON_RE_STIPPLE_DATA 0x1ccc 520 521#define RADEON_SCISSOR_TL_0 0x1cd8 522#define RADEON_SCISSOR_BR_0 0x1cdc 523#define RADEON_SCISSOR_TL_1 0x1ce0 524#define RADEON_SCISSOR_BR_1 0x1ce4 525#define RADEON_SCISSOR_TL_2 0x1ce8 526#define RADEON_SCISSOR_BR_2 0x1cec 527#define RADEON_SE_COORD_FMT 0x1c50 528#define RADEON_SE_CNTL 0x1c4c 529# define RADEON_FFACE_CULL_CW (0 << 0) 530# define RADEON_BFACE_SOLID (3 << 1) 531# define RADEON_FFACE_SOLID (3 << 3) 532# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 533# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 534# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 535# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 536# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 537# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 538# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 539# define RADEON_FOG_SHADE_FLAT (1 << 14) 540# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 541# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 542# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 543# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 544# define RADEON_ROUND_MODE_TRUNC (0 << 28) 545# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 546#define RADEON_SE_CNTL_STATUS 0x2140 547#define RADEON_SE_LINE_WIDTH 0x1db8 548#define RADEON_SE_VPORT_XSCALE 0x1d98 549#define RADEON_SE_ZBIAS_FACTOR 0x1db0 550#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 551#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 552#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 553# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 554# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 555#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 556#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 557# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 558#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 559#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 560#define RADEON_SURFACE_ACCESS_CLR 0x0bfc 561#define RADEON_SURFACE_CNTL 0x0b00 562# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 563# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 564# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 565# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 566# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 567# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 568# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 569# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 570# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 571#define RADEON_SURFACE0_INFO 0x0b0c 572# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 573# define RADEON_SURF_TILE_MODE_MASK (3 << 16) 574# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 575# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 576# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 577# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 578#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 579#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 580# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 581#define RADEON_SURFACE1_INFO 0x0b1c 582#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 583#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 584#define RADEON_SURFACE2_INFO 0x0b2c 585#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 586#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 587#define RADEON_SURFACE3_INFO 0x0b3c 588#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 589#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 590#define RADEON_SURFACE4_INFO 0x0b4c 591#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 592#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 593#define RADEON_SURFACE5_INFO 0x0b5c 594#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 595#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 596#define RADEON_SURFACE6_INFO 0x0b6c 597#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 598#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 599#define RADEON_SURFACE7_INFO 0x0b7c 600#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 601#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 602#define RADEON_SW_SEMAPHORE 0x013c 603 604#define RADEON_WAIT_UNTIL 0x1720 605# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 606# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 607# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 608# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 609 610#define RADEON_RB3D_ZMASKOFFSET 0x3234 611#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 612# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 613# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 614 615/* CP registers */ 616#define RADEON_CP_ME_RAM_ADDR 0x07d4 617#define RADEON_CP_ME_RAM_RADDR 0x07d8 618#define RADEON_CP_ME_RAM_DATAH 0x07dc 619#define RADEON_CP_ME_RAM_DATAL 0x07e0 620 621#define RADEON_CP_RB_BASE 0x0700 622#define RADEON_CP_RB_CNTL 0x0704 623# define RADEON_BUF_SWAP_32BIT (2 << 16) 624#define RADEON_CP_RB_RPTR_ADDR 0x070c 625#define RADEON_CP_RB_RPTR 0x0710 626#define RADEON_CP_RB_WPTR 0x0714 627 628#define RADEON_CP_RB_WPTR_DELAY 0x0718 629# define RADEON_PRE_WRITE_TIMER_SHIFT 0 630# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 631 632#define RADEON_CP_IB_BASE 0x0738 633 634#define RADEON_CP_CSQ_CNTL 0x0740 635# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 636# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 637# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 638# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 639# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 640# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 641# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 642 643#define RADEON_AIC_CNTL 0x01d0 644# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 645#define RADEON_AIC_STAT 0x01d4 646#define RADEON_AIC_PT_BASE 0x01d8 647#define RADEON_AIC_LO_ADDR 0x01dc 648#define RADEON_AIC_HI_ADDR 0x01e0 649#define RADEON_AIC_TLB_ADDR 0x01e4 650#define RADEON_AIC_TLB_DATA 0x01e8 651 652/* CP command packets */ 653#define RADEON_CP_PACKET0 0x00000000 654# define RADEON_ONE_REG_WR (1 << 15) 655#define RADEON_CP_PACKET1 0x40000000 656#define RADEON_CP_PACKET2 0x80000000 657#define RADEON_CP_PACKET3 0xC0000000 658# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 659# define RADEON_WAIT_FOR_IDLE 0x00002600 660# define RADEON_3D_DRAW_VBUF 0x00002800 661# define RADEON_3D_DRAW_IMMD 0x00002900 662# define RADEON_3D_DRAW_INDX 0x00002A00 663# define RADEON_3D_LOAD_VBPNTR 0x00002F00 664# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 665# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 666# define RADEON_3D_CLEAR_ZMASK 0x00003200 667# define RADEON_3D_CLEAR_HIZ 0x00003700 668# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 669# define RADEON_CNTL_PAINT_MULTI 0x00009A00 670# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 671# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 672 673#define RADEON_CP_PACKET_MASK 0xC0000000 674#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 675#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 676#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 677#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 678 679#define RADEON_VTX_Z_PRESENT (1 << 31) 680#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 681 682#define RADEON_PRIM_TYPE_NONE (0 << 0) 683#define RADEON_PRIM_TYPE_POINT (1 << 0) 684#define RADEON_PRIM_TYPE_LINE (2 << 0) 685#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 686#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 687#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 688#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 689#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 690#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 691#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 692#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 693#define RADEON_PRIM_TYPE_MASK 0xf 694#define RADEON_PRIM_WALK_IND (1 << 4) 695#define RADEON_PRIM_WALK_LIST (2 << 4) 696#define RADEON_PRIM_WALK_RING (3 << 4) 697#define RADEON_COLOR_ORDER_BGRA (0 << 6) 698#define RADEON_COLOR_ORDER_RGBA (1 << 6) 699#define RADEON_MAOS_ENABLE (1 << 7) 700#define RADEON_VTX_FMT_R128_MODE (0 << 8) 701#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 702#define RADEON_NUM_VERTICES_SHIFT 16 703 704#define RADEON_COLOR_FORMAT_CI8 2 705#define RADEON_COLOR_FORMAT_ARGB1555 3 706#define RADEON_COLOR_FORMAT_RGB565 4 707#define RADEON_COLOR_FORMAT_ARGB8888 6 708#define RADEON_COLOR_FORMAT_RGB332 7 709#define RADEON_COLOR_FORMAT_RGB8 9 710#define RADEON_COLOR_FORMAT_ARGB4444 15 711 712#define RADEON_TXFORMAT_I8 0 713#define RADEON_TXFORMAT_AI88 1 714#define RADEON_TXFORMAT_RGB332 2 715#define RADEON_TXFORMAT_ARGB1555 3 716#define RADEON_TXFORMAT_RGB565 4 717#define RADEON_TXFORMAT_ARGB4444 5 718#define RADEON_TXFORMAT_ARGB8888 6 719#define RADEON_TXFORMAT_RGBA8888 7 720#define RADEON_TXFORMAT_Y8 8 721#define RADEON_TXFORMAT_VYUY422 10 722#define RADEON_TXFORMAT_YVYU422 11 723#define RADEON_TXFORMAT_DXT1 12 724#define RADEON_TXFORMAT_DXT23 14 725#define RADEON_TXFORMAT_DXT45 15 726 727#define R200_PP_TXCBLEND_0 0x2f00 728#define R200_PP_TXCBLEND_1 0x2f10 729#define R200_PP_TXCBLEND_2 0x2f20 730#define R200_PP_TXCBLEND_3 0x2f30 731#define R200_PP_TXCBLEND_4 0x2f40 732#define R200_PP_TXCBLEND_5 0x2f50 733#define R200_PP_TXCBLEND_6 0x2f60 734#define R200_PP_TXCBLEND_7 0x2f70 735#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 736#define R200_PP_TFACTOR_0 0x2ee0 737#define R200_SE_VTX_FMT_0 0x2088 738#define R200_SE_VAP_CNTL 0x2080 739#define R200_SE_TCL_MATRIX_SEL_0 0x2230 740#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 741#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 742#define R200_PP_TXFILTER_5 0x2ca0 743#define R200_PP_TXFILTER_4 0x2c80 744#define R200_PP_TXFILTER_3 0x2c60 745#define R200_PP_TXFILTER_2 0x2c40 746#define R200_PP_TXFILTER_1 0x2c20 747#define R200_PP_TXFILTER_0 0x2c00 748#define R200_PP_TXOFFSET_5 0x2d78 749#define R200_PP_TXOFFSET_4 0x2d60 750#define R200_PP_TXOFFSET_3 0x2d48 751#define R200_PP_TXOFFSET_2 0x2d30 752#define R200_PP_TXOFFSET_1 0x2d18 753#define R200_PP_TXOFFSET_0 0x2d00 754 755#define R200_PP_CUBIC_FACES_0 0x2c18 756#define R200_PP_CUBIC_FACES_1 0x2c38 757#define R200_PP_CUBIC_FACES_2 0x2c58 758#define R200_PP_CUBIC_FACES_3 0x2c78 759#define R200_PP_CUBIC_FACES_4 0x2c98 760#define R200_PP_CUBIC_FACES_5 0x2cb8 761#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 762#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 763#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 764#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 765#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 766#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 767#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 768#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 769#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 770#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 771#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 772#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 773#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 774#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 775#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 776#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 777#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 778#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 779#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 780#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 781#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 782#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 783#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 784#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 785#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 786#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 787#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 788#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 789#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 790#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 791 792#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 793#define R200_SE_VTE_CNTL 0x20b0 794#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 795#define R200_PP_TAM_DEBUG3 0x2d9c 796#define R200_PP_CNTL_X 0x2cc4 797#define R200_SE_VAP_CNTL_STATUS 0x2140 798#define R200_RE_SCISSOR_TL_0 0x1cd8 799#define R200_RE_SCISSOR_TL_1 0x1ce0 800#define R200_RE_SCISSOR_TL_2 0x1ce8 801#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 802#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 803#define R200_SE_VTX_STATE_CNTL 0x2180 804#define R200_RE_POINTSIZE 0x2648 805#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 806 807#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 808#define RADEON_PP_TEX_SIZE_1 0x1d0c 809#define RADEON_PP_TEX_SIZE_2 0x1d14 810 811#define RADEON_PP_CUBIC_FACES_0 0x1d24 812#define RADEON_PP_CUBIC_FACES_1 0x1d28 813#define RADEON_PP_CUBIC_FACES_2 0x1d2c 814#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 815#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 816#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 817 818#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 819#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 820#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 821#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 822#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 823#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 824#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 825#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 826#define R200_3D_DRAW_IMMD_2 0xC0003500 827#define R200_SE_VTX_FMT_1 0x208c 828#define R200_RE_CNTL 0x1c50 829 830#define R200_RB3D_BLENDCOLOR 0x3218 831 832#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 833 834#define R200_PP_TRI_PERF 0x2cf8 835 836/* Constants */ 837#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 838 839#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 840#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 841#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 842#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 843#define RADEON_LAST_DISPATCH 1 844 845#define RADEON_MAX_VB_AGE 0x7fffffff 846#define RADEON_MAX_VB_VERTS (0xffff) 847 848#define RADEON_RING_HIGH_MARK 128 849 850#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 851#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) 852#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 853#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 854 855#define RADEON_WRITE_PLL( addr, val ) \ 856do { \ 857 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 858 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 859 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 860} while (0) 861 862extern int radeon_preinit(struct drm_device *dev, unsigned long flags); 863extern int radeon_postcleanup(struct drm_device *dev); 864 865#define CP_PACKET0( reg, n ) \ 866 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 867#define CP_PACKET0_TABLE( reg, n ) \ 868 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 869#define CP_PACKET1( reg0, reg1 ) \ 870 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 871#define CP_PACKET2() \ 872 (RADEON_CP_PACKET2) 873#define CP_PACKET3( pkt, n ) \ 874 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 875 876/* ================================================================ 877 * Engine control helper macros 878 */ 879 880#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 881 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 882 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 883 RADEON_WAIT_HOST_IDLECLEAN) ); \ 884} while (0) 885 886#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 887 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 888 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 889 RADEON_WAIT_HOST_IDLECLEAN) ); \ 890} while (0) 891 892#define RADEON_WAIT_UNTIL_IDLE() do { \ 893 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 894 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 895 RADEON_WAIT_3D_IDLECLEAN | \ 896 RADEON_WAIT_HOST_IDLECLEAN) ); \ 897} while (0) 898 899#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 900 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 901 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 902} while (0) 903 904#define RADEON_FLUSH_CACHE() do { \ 905 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ 906 OUT_RING( RADEON_RB2D_DC_FLUSH ); \ 907} while (0) 908 909#define RADEON_PURGE_CACHE() do { \ 910 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ 911 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \ 912} while (0) 913 914#define RADEON_FLUSH_ZCACHE() do { \ 915 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 916 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 917} while (0) 918 919#define RADEON_PURGE_ZCACHE() do { \ 920 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 921 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ 922} while (0) 923 924/* ================================================================ 925 * Misc helper macros 926 */ 927 928/* Perfbox functionality only. 929 */ 930#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 931do { \ 932 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 933 u32 head = GET_RING_HEAD( dev_priv ); \ 934 if (head == dev_priv->ring.tail) \ 935 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 936 } \ 937} while (0) 938 939#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 940do { \ 941 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 942 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 943 int __ret = radeon_do_cp_idle( dev_priv ); \ 944 if ( __ret ) return __ret; \ 945 sarea_priv->last_dispatch = 0; \ 946 radeon_freelist_reset( dev ); \ 947 } \ 948} while (0) 949 950#define RADEON_DISPATCH_AGE( age ) do { \ 951 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 952 OUT_RING( age ); \ 953} while (0) 954 955#define RADEON_FRAME_AGE( age ) do { \ 956 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 957 OUT_RING( age ); \ 958} while (0) 959 960#define RADEON_CLEAR_AGE( age ) do { \ 961 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 962 OUT_RING( age ); \ 963} while (0) 964 965/* ================================================================ 966 * Ring control 967 */ 968 969#define RADEON_VERBOSE 0 970 971#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; 972 973#define BEGIN_RING( n ) do { \ 974 if ( RADEON_VERBOSE ) { \ 975 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ 976 n, __FUNCTION__ ); \ 977 } \ 978 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 979 COMMIT_RING(); \ 980 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 981 } \ 982 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 983 ring = dev_priv->ring.start; \ 984 write = dev_priv->ring.tail; \ 985 mask = dev_priv->ring.tail_mask; \ 986} while (0) 987 988#define ADVANCE_RING() do { \ 989 if ( RADEON_VERBOSE ) { \ 990 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 991 write, dev_priv->ring.tail ); \ 992 } \ 993 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 994 DRM_ERROR( \ 995 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 996 ((dev_priv->ring.tail + _nr) & mask), \ 997 write, __LINE__); \ 998 } else \ 999 dev_priv->ring.tail = write; \ 1000} while (0) 1001 1002#define COMMIT_RING() do { \ 1003 /* Flush writes to ring */ \ 1004 DRM_MEMORYBARRIER(); \ 1005 GET_RING_HEAD( dev_priv ); \ 1006 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ 1007 /* read from PCI bus to ensure correct posting */ \ 1008 RADEON_READ( RADEON_CP_RB_RPTR ); \ 1009} while (0) 1010 1011#define OUT_RING( x ) do { \ 1012 if ( RADEON_VERBOSE ) { \ 1013 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 1014 (unsigned int)(x), write ); \ 1015 } \ 1016 ring[write++] = (x); \ 1017 write &= mask; \ 1018} while (0) 1019 1020#define OUT_RING_REG( reg, val ) do { \ 1021 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 1022 OUT_RING( val ); \ 1023} while (0) 1024 1025#define OUT_RING_TABLE( tab, sz ) do { \ 1026 int _size = (sz); \ 1027 int *_tab = (int *)(tab); \ 1028 \ 1029 if (write + _size > mask) { \ 1030 int _i = (mask+1) - write; \ 1031 _size -= _i; \ 1032 while (_i > 0) { \ 1033 *(int *)(ring + write) = *_tab++; \ 1034 write++; \ 1035 _i--; \ 1036 } \ 1037 write = 0; \ 1038 _tab += _i; \ 1039 } \ 1040 while (_size > 0) { \ 1041 *(ring + write) = *_tab++; \ 1042 write++; \ 1043 _size--; \ 1044 } \ 1045 write &= mask; \ 1046} while (0) 1047 1048#endif /* __RADEON_DRV_H__ */ 1049