radeon_drv.h revision 122580
1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * 30 * $FreeBSD: head/sys/dev/drm/radeon_drv.h 122580 2003-11-12 20:56:30Z anholt $ 31 */ 32 33#ifndef __RADEON_DRV_H__ 34#define __RADEON_DRV_H__ 35 36#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) 37#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) 38 39typedef struct drm_radeon_freelist { 40 unsigned int age; 41 drm_buf_t *buf; 42 struct drm_radeon_freelist *next; 43 struct drm_radeon_freelist *prev; 44} drm_radeon_freelist_t; 45 46typedef struct drm_radeon_ring_buffer { 47 u32 *start; 48 u32 *end; 49 int size; 50 int size_l2qw; 51 52 u32 tail; 53 u32 tail_mask; 54 int space; 55 56 int high_mark; 57} drm_radeon_ring_buffer_t; 58 59typedef struct drm_radeon_depth_clear_t { 60 u32 rb3d_cntl; 61 u32 rb3d_zstencilcntl; 62 u32 se_cntl; 63} drm_radeon_depth_clear_t; 64 65 66struct mem_block { 67 struct mem_block *next; 68 struct mem_block *prev; 69 int start; 70 int size; 71 DRMFILE filp; /* 0: free, -1: heap, other: real files */ 72}; 73 74typedef struct drm_radeon_private { 75 drm_radeon_ring_buffer_t ring; 76 drm_radeon_sarea_t *sarea_priv; 77 78 u32 fb_location; 79 80 int gart_size; 81 u32 gart_vm_start; 82 unsigned long gart_buffers_offset; 83 84 int cp_mode; 85 int cp_running; 86 87 drm_radeon_freelist_t *head; 88 drm_radeon_freelist_t *tail; 89 int last_buf; 90 volatile u32 *scratch; 91 int writeback_works; 92 93 int usec_timeout; 94 95 int is_r200; 96 97 int is_pci; 98 unsigned long phys_pci_gart; 99 dma_addr_t bus_pci_gart; 100 101 struct { 102 u32 boxes; 103 int freelist_timeouts; 104 int freelist_loops; 105 int requested_bufs; 106 int last_frame_reads; 107 int last_clear_reads; 108 int clears; 109 int texture_uploads; 110 } stats; 111 112 int do_boxes; 113 int page_flipping; 114 int current_page; 115 116 u32 color_fmt; 117 unsigned int front_offset; 118 unsigned int front_pitch; 119 unsigned int back_offset; 120 unsigned int back_pitch; 121 122 u32 depth_fmt; 123 unsigned int depth_offset; 124 unsigned int depth_pitch; 125 126 u32 front_pitch_offset; 127 u32 back_pitch_offset; 128 u32 depth_pitch_offset; 129 130 drm_radeon_depth_clear_t depth_clear; 131 132 unsigned long fb_offset; 133 unsigned long mmio_offset; 134 unsigned long ring_offset; 135 unsigned long ring_rptr_offset; 136 unsigned long buffers_offset; 137 unsigned long gart_textures_offset; 138 139 drm_local_map_t *sarea; 140 drm_local_map_t *fb; 141 drm_local_map_t *mmio; 142 drm_local_map_t *cp_ring; 143 drm_local_map_t *ring_rptr; 144 drm_local_map_t *buffers; 145 drm_local_map_t *gart_textures; 146 147 struct mem_block *gart_heap; 148 struct mem_block *fb_heap; 149 150 /* SW interrupt */ 151 wait_queue_head_t swi_queue; 152 atomic_t swi_emitted; 153 154} drm_radeon_private_t; 155 156typedef struct drm_radeon_buf_priv { 157 u32 age; 158} drm_radeon_buf_priv_t; 159 160 /* radeon_cp.c */ 161extern int radeon_cp_init( DRM_IOCTL_ARGS ); 162extern int radeon_cp_start( DRM_IOCTL_ARGS ); 163extern int radeon_cp_stop( DRM_IOCTL_ARGS ); 164extern int radeon_cp_reset( DRM_IOCTL_ARGS ); 165extern int radeon_cp_idle( DRM_IOCTL_ARGS ); 166extern int radeon_cp_resume( DRM_IOCTL_ARGS ); 167extern int radeon_engine_reset( DRM_IOCTL_ARGS ); 168extern int radeon_fullscreen( DRM_IOCTL_ARGS ); 169extern int radeon_cp_buffers( DRM_IOCTL_ARGS ); 170 171extern void radeon_freelist_reset( drm_device_t *dev ); 172extern drm_buf_t *radeon_freelist_get( drm_device_t *dev ); 173 174extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ); 175 176extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ); 177extern int radeon_do_cleanup_cp( drm_device_t *dev ); 178extern int radeon_do_cleanup_pageflip( drm_device_t *dev ); 179 180 /* radeon_state.c */ 181extern int radeon_cp_clear( DRM_IOCTL_ARGS ); 182extern int radeon_cp_swap( DRM_IOCTL_ARGS ); 183extern int radeon_cp_vertex( DRM_IOCTL_ARGS ); 184extern int radeon_cp_indices( DRM_IOCTL_ARGS ); 185extern int radeon_cp_texture( DRM_IOCTL_ARGS ); 186extern int radeon_cp_stipple( DRM_IOCTL_ARGS ); 187extern int radeon_cp_indirect( DRM_IOCTL_ARGS ); 188extern int radeon_cp_vertex2( DRM_IOCTL_ARGS ); 189extern int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ); 190extern int radeon_cp_getparam( DRM_IOCTL_ARGS ); 191extern int radeon_cp_setparam( DRM_IOCTL_ARGS ); 192extern int radeon_cp_flip( DRM_IOCTL_ARGS ); 193 194extern int radeon_mem_alloc( DRM_IOCTL_ARGS ); 195extern int radeon_mem_free( DRM_IOCTL_ARGS ); 196extern int radeon_mem_init_heap( DRM_IOCTL_ARGS ); 197extern void radeon_mem_takedown( struct mem_block **heap ); 198extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap ); 199 200 /* radeon_irq.c */ 201extern int radeon_irq_emit( DRM_IOCTL_ARGS ); 202extern int radeon_irq_wait( DRM_IOCTL_ARGS ); 203 204extern int radeon_emit_and_wait_irq(drm_device_t *dev); 205extern int radeon_wait_irq(drm_device_t *dev, int swi_nr); 206extern int radeon_emit_irq(drm_device_t *dev); 207 208extern void radeon_do_release(drm_device_t *dev); 209 210/* Flags for stats.boxes 211 */ 212#define RADEON_BOX_DMA_IDLE 0x1 213#define RADEON_BOX_RING_FULL 0x2 214#define RADEON_BOX_FLIP 0x4 215#define RADEON_BOX_WAIT_IDLE 0x8 216#define RADEON_BOX_TEXTURE_LOAD 0x10 217 218 219 220/* Register definitions, register access macros and drmAddMap constants 221 * for Radeon kernel driver. 222 */ 223 224#define RADEON_AGP_COMMAND 0x0f60 225#define RADEON_AUX_SCISSOR_CNTL 0x26f0 226# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 227# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 228# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 229# define RADEON_SCISSOR_0_ENABLE (1 << 28) 230# define RADEON_SCISSOR_1_ENABLE (1 << 29) 231# define RADEON_SCISSOR_2_ENABLE (1 << 30) 232 233#define RADEON_BUS_CNTL 0x0030 234# define RADEON_BUS_MASTER_DIS (1 << 6) 235 236#define RADEON_CLOCK_CNTL_DATA 0x000c 237# define RADEON_PLL_WR_EN (1 << 7) 238#define RADEON_CLOCK_CNTL_INDEX 0x0008 239#define RADEON_CONFIG_APER_SIZE 0x0108 240#define RADEON_CRTC_OFFSET 0x0224 241#define RADEON_CRTC_OFFSET_CNTL 0x0228 242# define RADEON_CRTC_TILE_EN (1 << 15) 243# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 244#define RADEON_CRTC2_OFFSET 0x0324 245#define RADEON_CRTC2_OFFSET_CNTL 0x0328 246 247#define RADEON_RB3D_COLOROFFSET 0x1c40 248#define RADEON_RB3D_COLORPITCH 0x1c48 249 250#define RADEON_DP_GUI_MASTER_CNTL 0x146c 251# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 252# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 253# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 254# define RADEON_GMC_BRUSH_NONE (15 << 4) 255# define RADEON_GMC_DST_16BPP (4 << 8) 256# define RADEON_GMC_DST_24BPP (5 << 8) 257# define RADEON_GMC_DST_32BPP (6 << 8) 258# define RADEON_GMC_DST_DATATYPE_SHIFT 8 259# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 260# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 261# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 262# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 263# define RADEON_GMC_WR_MSK_DIS (1 << 30) 264# define RADEON_ROP3_S 0x00cc0000 265# define RADEON_ROP3_P 0x00f00000 266#define RADEON_DP_WRITE_MASK 0x16cc 267#define RADEON_DST_PITCH_OFFSET 0x142c 268#define RADEON_DST_PITCH_OFFSET_C 0x1c80 269# define RADEON_DST_TILE_LINEAR (0 << 30) 270# define RADEON_DST_TILE_MACRO (1 << 30) 271# define RADEON_DST_TILE_MICRO (2 << 30) 272# define RADEON_DST_TILE_BOTH (3 << 30) 273 274#define RADEON_SCRATCH_REG0 0x15e0 275#define RADEON_SCRATCH_REG1 0x15e4 276#define RADEON_SCRATCH_REG2 0x15e8 277#define RADEON_SCRATCH_REG3 0x15ec 278#define RADEON_SCRATCH_REG4 0x15f0 279#define RADEON_SCRATCH_REG5 0x15f4 280#define RADEON_SCRATCH_UMSK 0x0770 281#define RADEON_SCRATCH_ADDR 0x0774 282 283#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 284 285#define GET_SCRATCH( x ) (dev_priv->writeback_works \ 286 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ 287 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) 288 289 290#define RADEON_GEN_INT_CNTL 0x0040 291# define RADEON_CRTC_VBLANK_MASK (1 << 0) 292# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 293# define RADEON_SW_INT_ENABLE (1 << 25) 294 295#define RADEON_GEN_INT_STATUS 0x0044 296# define RADEON_CRTC_VBLANK_STAT (1 << 0) 297# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 298# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 299# define RADEON_SW_INT_TEST (1 << 25) 300# define RADEON_SW_INT_TEST_ACK (1 << 25) 301# define RADEON_SW_INT_FIRE (1 << 26) 302 303#define RADEON_HOST_PATH_CNTL 0x0130 304# define RADEON_HDP_SOFT_RESET (1 << 26) 305# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 306# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 307 308#define RADEON_ISYNC_CNTL 0x1724 309# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 310# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 311# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 312# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 313# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 314# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 315 316#define RADEON_RBBM_GUICNTL 0x172c 317# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 318# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 319# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 320# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 321 322#define RADEON_MC_AGP_LOCATION 0x014c 323#define RADEON_MC_FB_LOCATION 0x0148 324#define RADEON_MCLK_CNTL 0x0012 325# define RADEON_FORCEON_MCLKA (1 << 16) 326# define RADEON_FORCEON_MCLKB (1 << 17) 327# define RADEON_FORCEON_YCLKA (1 << 18) 328# define RADEON_FORCEON_YCLKB (1 << 19) 329# define RADEON_FORCEON_MC (1 << 20) 330# define RADEON_FORCEON_AIC (1 << 21) 331 332#define RADEON_PP_BORDER_COLOR_0 0x1d40 333#define RADEON_PP_BORDER_COLOR_1 0x1d44 334#define RADEON_PP_BORDER_COLOR_2 0x1d48 335#define RADEON_PP_CNTL 0x1c38 336# define RADEON_SCISSOR_ENABLE (1 << 1) 337#define RADEON_PP_LUM_MATRIX 0x1d00 338#define RADEON_PP_MISC 0x1c14 339#define RADEON_PP_ROT_MATRIX_0 0x1d58 340#define RADEON_PP_TXFILTER_0 0x1c54 341#define RADEON_PP_TXOFFSET_0 0x1c5c 342#define RADEON_PP_TXFILTER_1 0x1c6c 343#define RADEON_PP_TXFILTER_2 0x1c84 344 345#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 346# define RADEON_RB2D_DC_FLUSH (3 << 0) 347# define RADEON_RB2D_DC_FREE (3 << 2) 348# define RADEON_RB2D_DC_FLUSH_ALL 0xf 349# define RADEON_RB2D_DC_BUSY (1 << 31) 350#define RADEON_RB3D_CNTL 0x1c3c 351# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 352# define RADEON_PLANE_MASK_ENABLE (1 << 1) 353# define RADEON_DITHER_ENABLE (1 << 2) 354# define RADEON_ROUND_ENABLE (1 << 3) 355# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 356# define RADEON_DITHER_INIT (1 << 5) 357# define RADEON_ROP_ENABLE (1 << 6) 358# define RADEON_STENCIL_ENABLE (1 << 7) 359# define RADEON_Z_ENABLE (1 << 8) 360#define RADEON_RB3D_DEPTHOFFSET 0x1c24 361#define RADEON_RB3D_DEPTHPITCH 0x1c28 362#define RADEON_RB3D_PLANEMASK 0x1d84 363#define RADEON_RB3D_STENCILREFMASK 0x1d7c 364#define RADEON_RB3D_ZCACHE_MODE 0x3250 365#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 366# define RADEON_RB3D_ZC_FLUSH (1 << 0) 367# define RADEON_RB3D_ZC_FREE (1 << 2) 368# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 369# define RADEON_RB3D_ZC_BUSY (1 << 31) 370#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 371# define RADEON_Z_TEST_MASK (7 << 4) 372# define RADEON_Z_TEST_ALWAYS (7 << 4) 373# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 374# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 375# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 376# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 377# define RADEON_Z_WRITE_ENABLE (1 << 30) 378#define RADEON_RBBM_SOFT_RESET 0x00f0 379# define RADEON_SOFT_RESET_CP (1 << 0) 380# define RADEON_SOFT_RESET_HI (1 << 1) 381# define RADEON_SOFT_RESET_SE (1 << 2) 382# define RADEON_SOFT_RESET_RE (1 << 3) 383# define RADEON_SOFT_RESET_PP (1 << 4) 384# define RADEON_SOFT_RESET_E2 (1 << 5) 385# define RADEON_SOFT_RESET_RB (1 << 6) 386# define RADEON_SOFT_RESET_HDP (1 << 7) 387#define RADEON_RBBM_STATUS 0x0e40 388# define RADEON_RBBM_FIFOCNT_MASK 0x007f 389# define RADEON_RBBM_ACTIVE (1 << 31) 390#define RADEON_RE_LINE_PATTERN 0x1cd0 391#define RADEON_RE_MISC 0x26c4 392#define RADEON_RE_TOP_LEFT 0x26c0 393#define RADEON_RE_WIDTH_HEIGHT 0x1c44 394#define RADEON_RE_STIPPLE_ADDR 0x1cc8 395#define RADEON_RE_STIPPLE_DATA 0x1ccc 396 397#define RADEON_SCISSOR_TL_0 0x1cd8 398#define RADEON_SCISSOR_BR_0 0x1cdc 399#define RADEON_SCISSOR_TL_1 0x1ce0 400#define RADEON_SCISSOR_BR_1 0x1ce4 401#define RADEON_SCISSOR_TL_2 0x1ce8 402#define RADEON_SCISSOR_BR_2 0x1cec 403#define RADEON_SE_COORD_FMT 0x1c50 404#define RADEON_SE_CNTL 0x1c4c 405# define RADEON_FFACE_CULL_CW (0 << 0) 406# define RADEON_BFACE_SOLID (3 << 1) 407# define RADEON_FFACE_SOLID (3 << 3) 408# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 409# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 410# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 411# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 412# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 413# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 414# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 415# define RADEON_FOG_SHADE_FLAT (1 << 14) 416# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 417# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 418# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 419# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 420# define RADEON_ROUND_MODE_TRUNC (0 << 28) 421# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 422#define RADEON_SE_CNTL_STATUS 0x2140 423#define RADEON_SE_LINE_WIDTH 0x1db8 424#define RADEON_SE_VPORT_XSCALE 0x1d98 425#define RADEON_SE_ZBIAS_FACTOR 0x1db0 426#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 427#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 428#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 429# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 430# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 431#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 432#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 433# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 434#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 435#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 436#define RADEON_SURFACE_ACCESS_CLR 0x0bfc 437#define RADEON_SURFACE_CNTL 0x0b00 438# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 439# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 440# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 441# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 442# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 443# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 444# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 445# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 446# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 447#define RADEON_SURFACE0_INFO 0x0b0c 448# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 449# define RADEON_SURF_TILE_MODE_MASK (3 << 16) 450# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 451# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 452# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 453# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 454#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 455#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 456#define RADEON_SURFACE1_INFO 0x0b1c 457#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 458#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 459#define RADEON_SURFACE2_INFO 0x0b2c 460#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 461#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 462#define RADEON_SURFACE3_INFO 0x0b3c 463#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 464#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 465#define RADEON_SURFACE4_INFO 0x0b4c 466#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 467#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 468#define RADEON_SURFACE5_INFO 0x0b5c 469#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 470#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 471#define RADEON_SURFACE6_INFO 0x0b6c 472#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 473#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 474#define RADEON_SURFACE7_INFO 0x0b7c 475#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 476#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 477#define RADEON_SW_SEMAPHORE 0x013c 478 479#define RADEON_WAIT_UNTIL 0x1720 480# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 481# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 482# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 483# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 484 485#define RADEON_RB3D_ZMASKOFFSET 0x1c34 486#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 487# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 488# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 489 490 491/* CP registers */ 492#define RADEON_CP_ME_RAM_ADDR 0x07d4 493#define RADEON_CP_ME_RAM_RADDR 0x07d8 494#define RADEON_CP_ME_RAM_DATAH 0x07dc 495#define RADEON_CP_ME_RAM_DATAL 0x07e0 496 497#define RADEON_CP_RB_BASE 0x0700 498#define RADEON_CP_RB_CNTL 0x0704 499# define RADEON_BUF_SWAP_32BIT (2 << 16) 500#define RADEON_CP_RB_RPTR_ADDR 0x070c 501#define RADEON_CP_RB_RPTR 0x0710 502#define RADEON_CP_RB_WPTR 0x0714 503 504#define RADEON_CP_RB_WPTR_DELAY 0x0718 505# define RADEON_PRE_WRITE_TIMER_SHIFT 0 506# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 507 508#define RADEON_CP_IB_BASE 0x0738 509 510#define RADEON_CP_CSQ_CNTL 0x0740 511# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 512# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 513# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 514# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 515# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 516# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 517# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 518 519#define RADEON_AIC_CNTL 0x01d0 520# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 521#define RADEON_AIC_STAT 0x01d4 522#define RADEON_AIC_PT_BASE 0x01d8 523#define RADEON_AIC_LO_ADDR 0x01dc 524#define RADEON_AIC_HI_ADDR 0x01e0 525#define RADEON_AIC_TLB_ADDR 0x01e4 526#define RADEON_AIC_TLB_DATA 0x01e8 527 528/* CP command packets */ 529#define RADEON_CP_PACKET0 0x00000000 530# define RADEON_ONE_REG_WR (1 << 15) 531#define RADEON_CP_PACKET1 0x40000000 532#define RADEON_CP_PACKET2 0x80000000 533#define RADEON_CP_PACKET3 0xC0000000 534# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 535# define RADEON_WAIT_FOR_IDLE 0x00002600 536# define RADEON_3D_DRAW_VBUF 0x00002800 537# define RADEON_3D_DRAW_IMMD 0x00002900 538# define RADEON_3D_DRAW_INDX 0x00002A00 539# define RADEON_3D_LOAD_VBPNTR 0x00002F00 540# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 541# define RADEON_CNTL_PAINT_MULTI 0x00009A00 542# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 543# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 544 545#define RADEON_CP_PACKET_MASK 0xC0000000 546#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 547#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 548#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 549#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 550 551#define RADEON_VTX_Z_PRESENT (1 << 31) 552#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 553 554#define RADEON_PRIM_TYPE_NONE (0 << 0) 555#define RADEON_PRIM_TYPE_POINT (1 << 0) 556#define RADEON_PRIM_TYPE_LINE (2 << 0) 557#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 558#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 559#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 560#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 561#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 562#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 563#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 564#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 565#define RADEON_PRIM_TYPE_MASK 0xf 566#define RADEON_PRIM_WALK_IND (1 << 4) 567#define RADEON_PRIM_WALK_LIST (2 << 4) 568#define RADEON_PRIM_WALK_RING (3 << 4) 569#define RADEON_COLOR_ORDER_BGRA (0 << 6) 570#define RADEON_COLOR_ORDER_RGBA (1 << 6) 571#define RADEON_MAOS_ENABLE (1 << 7) 572#define RADEON_VTX_FMT_R128_MODE (0 << 8) 573#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 574#define RADEON_NUM_VERTICES_SHIFT 16 575 576#define RADEON_COLOR_FORMAT_CI8 2 577#define RADEON_COLOR_FORMAT_ARGB1555 3 578#define RADEON_COLOR_FORMAT_RGB565 4 579#define RADEON_COLOR_FORMAT_ARGB8888 6 580#define RADEON_COLOR_FORMAT_RGB332 7 581#define RADEON_COLOR_FORMAT_RGB8 9 582#define RADEON_COLOR_FORMAT_ARGB4444 15 583 584#define RADEON_TXFORMAT_I8 0 585#define RADEON_TXFORMAT_AI88 1 586#define RADEON_TXFORMAT_RGB332 2 587#define RADEON_TXFORMAT_ARGB1555 3 588#define RADEON_TXFORMAT_RGB565 4 589#define RADEON_TXFORMAT_ARGB4444 5 590#define RADEON_TXFORMAT_ARGB8888 6 591#define RADEON_TXFORMAT_RGBA8888 7 592#define RADEON_TXFORMAT_Y8 8 593#define RADEON_TXFORMAT_VYUY422 10 594#define RADEON_TXFORMAT_YVYU422 11 595#define RADEON_TXFORMAT_DXT1 12 596#define RADEON_TXFORMAT_DXT23 14 597#define RADEON_TXFORMAT_DXT45 15 598 599#define R200_PP_TXCBLEND_0 0x2f00 600#define R200_PP_TXCBLEND_1 0x2f10 601#define R200_PP_TXCBLEND_2 0x2f20 602#define R200_PP_TXCBLEND_3 0x2f30 603#define R200_PP_TXCBLEND_4 0x2f40 604#define R200_PP_TXCBLEND_5 0x2f50 605#define R200_PP_TXCBLEND_6 0x2f60 606#define R200_PP_TXCBLEND_7 0x2f70 607#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 608#define R200_PP_TFACTOR_0 0x2ee0 609#define R200_SE_VTX_FMT_0 0x2088 610#define R200_SE_VAP_CNTL 0x2080 611#define R200_SE_TCL_MATRIX_SEL_0 0x2230 612#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 613#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 614#define R200_PP_TXFILTER_5 0x2ca0 615#define R200_PP_TXFILTER_4 0x2c80 616#define R200_PP_TXFILTER_3 0x2c60 617#define R200_PP_TXFILTER_2 0x2c40 618#define R200_PP_TXFILTER_1 0x2c20 619#define R200_PP_TXFILTER_0 0x2c00 620#define R200_PP_TXOFFSET_5 0x2d78 621#define R200_PP_TXOFFSET_4 0x2d60 622#define R200_PP_TXOFFSET_3 0x2d48 623#define R200_PP_TXOFFSET_2 0x2d30 624#define R200_PP_TXOFFSET_1 0x2d18 625#define R200_PP_TXOFFSET_0 0x2d00 626 627#define R200_PP_CUBIC_FACES_0 0x2c18 628#define R200_PP_CUBIC_FACES_1 0x2c38 629#define R200_PP_CUBIC_FACES_2 0x2c58 630#define R200_PP_CUBIC_FACES_3 0x2c78 631#define R200_PP_CUBIC_FACES_4 0x2c98 632#define R200_PP_CUBIC_FACES_5 0x2cb8 633#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 634#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 635#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 636#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 637#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 638#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 639#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 640#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 641#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 642#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 643#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 644#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 645#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 646#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 647#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 648#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 649#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 650#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 651#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 652#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 653#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 654#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 655#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 656#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 657#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 658#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 659#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 660#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 661#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 662#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 663 664#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 665#define R200_SE_VTE_CNTL 0x20b0 666#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 667#define R200_PP_TAM_DEBUG3 0x2d9c 668#define R200_PP_CNTL_X 0x2cc4 669#define R200_SE_VAP_CNTL_STATUS 0x2140 670#define R200_RE_SCISSOR_TL_0 0x1cd8 671#define R200_RE_SCISSOR_TL_1 0x1ce0 672#define R200_RE_SCISSOR_TL_2 0x1ce8 673#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 674#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 675#define R200_SE_VTX_STATE_CNTL 0x2180 676#define R200_RE_POINTSIZE 0x2648 677#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 678 679#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 680#define RADEON_PP_TEX_SIZE_1 0x1d0c 681#define RADEON_PP_TEX_SIZE_2 0x1d14 682 683 684#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 685#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 686#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 687#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 688#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 689#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 690#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 691#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 692#define R200_3D_DRAW_IMMD_2 0xC0003500 693#define R200_SE_VTX_FMT_1 0x208c 694#define R200_RE_CNTL 0x1c50 695 696 697/* Constants */ 698#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 699 700#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 701#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 702#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 703#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 704#define RADEON_LAST_DISPATCH 1 705 706#define RADEON_MAX_VB_AGE 0x7fffffff 707#define RADEON_MAX_VB_VERTS (0xffff) 708 709#define RADEON_RING_HIGH_MARK 128 710 711#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 712#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) 713#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 714#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 715 716#define RADEON_WRITE_PLL( addr, val ) \ 717do { \ 718 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 719 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 720 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 721} while (0) 722 723extern int RADEON_READ_PLL( drm_device_t *dev, int addr ); 724 725 726#define CP_PACKET0( reg, n ) \ 727 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 728#define CP_PACKET0_TABLE( reg, n ) \ 729 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 730#define CP_PACKET1( reg0, reg1 ) \ 731 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 732#define CP_PACKET2() \ 733 (RADEON_CP_PACKET2) 734#define CP_PACKET3( pkt, n ) \ 735 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 736 737 738/* ================================================================ 739 * Engine control helper macros 740 */ 741 742#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 743 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 744 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 745 RADEON_WAIT_HOST_IDLECLEAN) ); \ 746} while (0) 747 748#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 749 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 750 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 751 RADEON_WAIT_HOST_IDLECLEAN) ); \ 752} while (0) 753 754#define RADEON_WAIT_UNTIL_IDLE() do { \ 755 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 756 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 757 RADEON_WAIT_3D_IDLECLEAN | \ 758 RADEON_WAIT_HOST_IDLECLEAN) ); \ 759} while (0) 760 761#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 762 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 763 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 764} while (0) 765 766#define RADEON_FLUSH_CACHE() do { \ 767 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ 768 OUT_RING( RADEON_RB2D_DC_FLUSH ); \ 769} while (0) 770 771#define RADEON_PURGE_CACHE() do { \ 772 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \ 773 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \ 774} while (0) 775 776#define RADEON_FLUSH_ZCACHE() do { \ 777 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 778 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 779} while (0) 780 781#define RADEON_PURGE_ZCACHE() do { \ 782 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 783 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ 784} while (0) 785 786 787/* ================================================================ 788 * Misc helper macros 789 */ 790 791/* Perfbox functionality only. 792 */ 793#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 794do { \ 795 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 796 u32 head = GET_RING_HEAD( dev_priv ); \ 797 if (head == dev_priv->ring.tail) \ 798 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 799 } \ 800} while (0) 801 802#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 803do { \ 804 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 805 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 806 int __ret = radeon_do_cp_idle( dev_priv ); \ 807 if ( __ret ) return __ret; \ 808 sarea_priv->last_dispatch = 0; \ 809 radeon_freelist_reset( dev ); \ 810 } \ 811} while (0) 812 813#define RADEON_DISPATCH_AGE( age ) do { \ 814 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 815 OUT_RING( age ); \ 816} while (0) 817 818#define RADEON_FRAME_AGE( age ) do { \ 819 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 820 OUT_RING( age ); \ 821} while (0) 822 823#define RADEON_CLEAR_AGE( age ) do { \ 824 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 825 OUT_RING( age ); \ 826} while (0) 827 828 829/* ================================================================ 830 * Ring control 831 */ 832 833#define RADEON_VERBOSE 0 834 835#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; 836 837#define BEGIN_RING( n ) do { \ 838 if ( RADEON_VERBOSE ) { \ 839 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ 840 n, __FUNCTION__ ); \ 841 } \ 842 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 843 COMMIT_RING(); \ 844 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 845 } \ 846 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 847 ring = dev_priv->ring.start; \ 848 write = dev_priv->ring.tail; \ 849 mask = dev_priv->ring.tail_mask; \ 850} while (0) 851 852#define ADVANCE_RING() do { \ 853 if ( RADEON_VERBOSE ) { \ 854 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 855 write, dev_priv->ring.tail ); \ 856 } \ 857 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 858 DRM_ERROR( \ 859 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 860 ((dev_priv->ring.tail + _nr) & mask), \ 861 write, __LINE__); \ 862 } else \ 863 dev_priv->ring.tail = write; \ 864} while (0) 865 866#define COMMIT_RING() do { \ 867 /* Flush writes to ring */ \ 868 DRM_MEMORYBARRIER(); \ 869 GET_RING_HEAD( dev_priv ); \ 870 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ 871 /* read from PCI bus to ensure correct posting */ \ 872 RADEON_READ( RADEON_CP_RB_RPTR ); \ 873} while (0) 874 875#define OUT_RING( x ) do { \ 876 if ( RADEON_VERBOSE ) { \ 877 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 878 (unsigned int)(x), write ); \ 879 } \ 880 ring[write++] = (x); \ 881 write &= mask; \ 882} while (0) 883 884#define OUT_RING_REG( reg, val ) do { \ 885 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 886 OUT_RING( val ); \ 887} while (0) 888 889 890#define OUT_RING_USER_TABLE( tab, sz ) do { \ 891 int _size = (sz); \ 892 int *_tab = (tab); \ 893 \ 894 if (write + _size > mask) { \ 895 int i = (mask+1) - write; \ 896 if (DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \ 897 _tab, i*4 )) \ 898 return DRM_ERR(EFAULT); \ 899 write = 0; \ 900 _size -= i; \ 901 _tab += i; \ 902 } \ 903 \ 904 if (_size && DRM_COPY_FROM_USER_UNCHECKED( (int *)(ring+write), \ 905 _tab, _size*4 )) \ 906 return DRM_ERR(EFAULT); \ 907 \ 908 write += _size; \ 909 write &= mask; \ 910} while (0) 911 912 913#endif /* __RADEON_DRV_H__ */ 914