radeon_cp.c revision 190595
1139749Simp/*- 295584Sanholt * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 395584Sanholt * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 4182080Srnoland * Copyright 2007 Advanced Micro Devices, Inc. 595584Sanholt * All Rights Reserved. 695584Sanholt * 795584Sanholt * Permission is hereby granted, free of charge, to any person obtaining a 895584Sanholt * copy of this software and associated documentation files (the "Software"), 995584Sanholt * to deal in the Software without restriction, including without limitation 1095584Sanholt * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1195584Sanholt * and/or sell copies of the Software, and to permit persons to whom the 1295584Sanholt * Software is furnished to do so, subject to the following conditions: 1395584Sanholt * 1495584Sanholt * The above copyright notice and this permission notice (including the next 1595584Sanholt * paragraph) shall be included in all copies or substantial portions of the 1695584Sanholt * Software. 1795584Sanholt * 1895584Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1995584Sanholt * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2095584Sanholt * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2195584Sanholt * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 2295584Sanholt * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2395584Sanholt * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 2495584Sanholt * DEALINGS IN THE SOFTWARE. 2595584Sanholt * 2695584Sanholt * Authors: 2795584Sanholt * Kevin E. Martin <martin@valinux.com> 2895584Sanholt * Gareth Hughes <gareth@valinux.com> 2995584Sanholt */ 3095584Sanholt 31152909Sanholt#include <sys/cdefs.h> 32152909Sanholt__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_cp.c 190595 2009-03-31 17:52:05Z rnoland $"); 33152909Sanholt 3495584Sanholt#include "dev/drm/drmP.h" 35112015Sanholt#include "dev/drm/drm.h" 36189499Srnoland#include "dev/drm/drm_sarea.h" 3795746Sanholt#include "dev/drm/radeon_drm.h" 3895584Sanholt#include "dev/drm/radeon_drv.h" 39148211Sanholt#include "dev/drm/r300_reg.h" 4095584Sanholt 41182080Srnoland#include "dev/drm/radeon_microcode.h" 42189499Srnoland 4395584Sanholt#define RADEON_FIFO_DEBUG 0 4495584Sanholt 45182080Srnolandstatic int radeon_do_cleanup_cp(struct drm_device * dev); 46182080Srnolandstatic void radeon_do_cp_start(drm_radeon_private_t * dev_priv); 4795584Sanholt 48189499Srnolandu32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off) 49189499Srnoland{ 50189499Srnoland u32 val; 51189499Srnoland 52189499Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 53189499Srnoland val = DRM_READ32(dev_priv->ring_rptr, off); 54189499Srnoland } else { 55189499Srnoland val = *(((volatile u32 *) 56189499Srnoland dev_priv->ring_rptr->handle) + 57189499Srnoland (off / sizeof(u32))); 58189499Srnoland val = le32_to_cpu(val); 59189499Srnoland } 60189499Srnoland return val; 61189499Srnoland} 62189499Srnoland 63189499Srnolandu32 radeon_get_ring_head(drm_radeon_private_t *dev_priv) 64189499Srnoland{ 65189499Srnoland if (dev_priv->writeback_works) 66189499Srnoland return radeon_read_ring_rptr(dev_priv, 0); 67189499Srnoland else { 68189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 69189499Srnoland return RADEON_READ(R600_CP_RB_RPTR); 70189499Srnoland else 71189499Srnoland return RADEON_READ(RADEON_CP_RB_RPTR); 72189499Srnoland } 73189499Srnoland} 74189499Srnoland 75189499Srnolandvoid radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val) 76189499Srnoland{ 77189499Srnoland if (dev_priv->flags & RADEON_IS_AGP) 78189499Srnoland DRM_WRITE32(dev_priv->ring_rptr, off, val); 79189499Srnoland else 80189499Srnoland *(((volatile u32 *) dev_priv->ring_rptr->handle) + 81189499Srnoland (off / sizeof(u32))) = cpu_to_le32(val); 82189499Srnoland} 83189499Srnoland 84189499Srnolandvoid radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val) 85189499Srnoland{ 86189499Srnoland radeon_write_ring_rptr(dev_priv, 0, val); 87189499Srnoland} 88189499Srnoland 89189499Srnolandu32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index) 90189499Srnoland{ 91189499Srnoland if (dev_priv->writeback_works) { 92189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 93189499Srnoland return radeon_read_ring_rptr(dev_priv, 94189499Srnoland R600_SCRATCHOFF(index)); 95189499Srnoland else 96189499Srnoland return radeon_read_ring_rptr(dev_priv, 97189499Srnoland RADEON_SCRATCHOFF(index)); 98189499Srnoland } else { 99189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 100189499Srnoland return RADEON_READ(R600_SCRATCH_REG0 + 4*index); 101189499Srnoland else 102189499Srnoland return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index); 103189499Srnoland } 104189499Srnoland} 105189499Srnoland 106189499Srnolandu32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr) 107189499Srnoland{ 108189499Srnoland u32 ret; 109189499Srnoland 110189499Srnoland if (addr < 0x10000) 111189499Srnoland ret = DRM_READ32(dev_priv->mmio, addr); 112189499Srnoland else { 113189499Srnoland DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr); 114189499Srnoland ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA); 115189499Srnoland } 116189499Srnoland 117189499Srnoland return ret; 118189499Srnoland} 119189499Srnoland 120182080Srnolandstatic u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 121182080Srnoland{ 122182080Srnoland u32 ret; 123182080Srnoland RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); 124182080Srnoland ret = RADEON_READ(R520_MC_IND_DATA); 125182080Srnoland RADEON_WRITE(R520_MC_IND_INDEX, 0); 126182080Srnoland return ret; 127182080Srnoland} 128112015Sanholt 129182080Srnolandstatic u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 130182080Srnoland{ 131182080Srnoland u32 ret; 132182080Srnoland RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); 133182080Srnoland ret = RADEON_READ(RS480_NB_MC_DATA); 134182080Srnoland RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); 135182080Srnoland return ret; 136182080Srnoland} 137112015Sanholt 138182080Srnolandstatic u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 139182080Srnoland{ 140182080Srnoland u32 ret; 141182080Srnoland RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); 142182080Srnoland ret = RADEON_READ(RS690_MC_DATA); 143182080Srnoland RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK); 144182080Srnoland return ret; 145182080Srnoland} 14695584Sanholt 147189499Srnolandstatic u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 148189499Srnoland{ 149189499Srnoland u32 ret; 150189499Srnoland RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | 151189499Srnoland RS600_MC_IND_CITF_ARB0)); 152189499Srnoland ret = RADEON_READ(RS600_MC_DATA); 153189499Srnoland return ret; 154189499Srnoland} 155189499Srnoland 156182080Srnolandstatic u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 15795584Sanholt{ 158183828Srnoland if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 159183828Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 160189499Srnoland return RS690_READ_MCIND(dev_priv, addr); 161189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 162189499Srnoland return RS600_READ_MCIND(dev_priv, addr); 163182080Srnoland else 164189499Srnoland return RS480_READ_MCIND(dev_priv, addr); 165182080Srnoland} 166182080Srnoland 167182080Srnolandu32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) 168182080Srnoland{ 169182080Srnoland 170189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 171189499Srnoland return RADEON_READ(R700_MC_VM_FB_LOCATION); 172189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 173189499Srnoland return RADEON_READ(R600_MC_VM_FB_LOCATION); 174189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 175182080Srnoland return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); 176183828Srnoland else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 177183828Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 178182080Srnoland return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); 179189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 180189499Srnoland return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION); 181182080Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 182182080Srnoland return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); 183182080Srnoland else 184182080Srnoland return RADEON_READ(RADEON_MC_FB_LOCATION); 185182080Srnoland} 186182080Srnoland 187182080Srnolandstatic void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) 188182080Srnoland{ 189189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 190189499Srnoland RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc); 191189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 192189499Srnoland RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc); 193189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 194182080Srnoland R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); 195183828Srnoland else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 196183828Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 197182080Srnoland RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); 198189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 199189499Srnoland RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc); 200182080Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 201182080Srnoland R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); 202182080Srnoland else 203182080Srnoland RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); 204182080Srnoland} 205182080Srnoland 206189499Srnolandvoid radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) 207182080Srnoland{ 208189499Srnoland /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */ 209189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { 210189499Srnoland RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */ 211189499Srnoland RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff); 212189499Srnoland } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { 213189499Srnoland RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */ 214189499Srnoland RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff); 215189499Srnoland } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 216182080Srnoland R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); 217183828Srnoland else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 218183828Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 219182080Srnoland RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); 220189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 221189499Srnoland RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc); 222182080Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 223182080Srnoland R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); 224182080Srnoland else 225182080Srnoland RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); 226182080Srnoland} 227182080Srnoland 228189499Srnolandvoid radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) 229182080Srnoland{ 230182080Srnoland u32 agp_base_hi = upper_32_bits(agp_base); 231182080Srnoland u32 agp_base_lo = agp_base & 0xffffffff; 232189499Srnoland u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff; 233182080Srnoland 234189499Srnoland /* R6xx/R7xx must be aligned to a 4MB boundry */ 235189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 236189499Srnoland RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base); 237189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 238189499Srnoland RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base); 239189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) { 240182080Srnoland R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo); 241182080Srnoland R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi); 242183828Srnoland } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 243189499Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 244182080Srnoland RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo); 245182080Srnoland RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi); 246189499Srnoland } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { 247189499Srnoland RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo); 248189499Srnoland RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi); 249182080Srnoland } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { 250182080Srnoland R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); 251182080Srnoland R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); 252182080Srnoland } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || 253182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { 254182080Srnoland RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); 255182080Srnoland RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi); 256182080Srnoland } else { 257182080Srnoland RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); 258182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) 259182080Srnoland RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi); 260182080Srnoland } 261182080Srnoland} 262182080Srnoland 263189499Srnolandvoid radeon_enable_bm(struct drm_radeon_private *dev_priv) 264189499Srnoland{ 265189499Srnoland u32 tmp; 266189499Srnoland /* Turn on bus mastering */ 267189499Srnoland if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 268189499Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 269189499Srnoland /* rs600/rs690/rs740 */ 270189499Srnoland tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 271189499Srnoland RADEON_WRITE(RADEON_BUS_CNTL, tmp); 272189499Srnoland } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) || 273189499Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || 274189499Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || 275189499Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { 276189499Srnoland /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 277189499Srnoland tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 278189499Srnoland RADEON_WRITE(RADEON_BUS_CNTL, tmp); 279189499Srnoland } /* PCIE cards appears to not need this */ 280189499Srnoland} 281189499Srnoland 282182080Srnolandstatic int RADEON_READ_PLL(struct drm_device * dev, int addr) 283182080Srnoland{ 28495584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 28595584Sanholt 28695584Sanholt RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); 28795584Sanholt return RADEON_READ(RADEON_CLOCK_CNTL_DATA); 28895584Sanholt} 28995584Sanholt 290182080Srnolandstatic u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) 291148211Sanholt{ 292148211Sanholt RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); 293148211Sanholt return RADEON_READ(RADEON_PCIE_DATA); 294148211Sanholt} 295148211Sanholt 29695584Sanholt#if RADEON_FIFO_DEBUG 297145132Sanholtstatic void radeon_status(drm_radeon_private_t * dev_priv) 29895584Sanholt{ 299189499Srnoland printk("%s:\n", __func__); 300145132Sanholt printk("RBBM_STATUS = 0x%08x\n", 301145132Sanholt (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); 302145132Sanholt printk("CP_RB_RTPR = 0x%08x\n", 303145132Sanholt (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); 304145132Sanholt printk("CP_RB_WTPR = 0x%08x\n", 305145132Sanholt (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); 306145132Sanholt printk("AIC_CNTL = 0x%08x\n", 307145132Sanholt (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); 308145132Sanholt printk("AIC_STAT = 0x%08x\n", 309145132Sanholt (unsigned int)RADEON_READ(RADEON_AIC_STAT)); 310145132Sanholt printk("AIC_PT_BASE = 0x%08x\n", 311145132Sanholt (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); 312145132Sanholt printk("TLB_ADDR = 0x%08x\n", 313145132Sanholt (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); 314145132Sanholt printk("TLB_DATA = 0x%08x\n", 315145132Sanholt (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); 31695584Sanholt} 31795584Sanholt#endif 31895584Sanholt 31995584Sanholt/* ================================================================ 32095584Sanholt * Engine, FIFO control 32195584Sanholt */ 32295584Sanholt 323145132Sanholtstatic int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) 32495584Sanholt{ 32595584Sanholt u32 tmp; 32695584Sanholt int i; 32795584Sanholt 328112015Sanholt dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 329112015Sanholt 330182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { 331182080Srnoland tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); 332182080Srnoland tmp |= RADEON_RB3D_DC_FLUSH_ALL; 333182080Srnoland RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); 33495584Sanholt 335182080Srnoland for (i = 0; i < dev_priv->usec_timeout; i++) { 336182080Srnoland if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) 337182080Srnoland & RADEON_RB3D_DC_BUSY)) { 338182080Srnoland return 0; 339182080Srnoland } 340182080Srnoland DRM_UDELAY(1); 34195584Sanholt } 342182080Srnoland } else { 343182080Srnoland /* don't flush or purge cache here or lockup */ 344182080Srnoland return 0; 34595584Sanholt } 34695584Sanholt 34795584Sanholt#if RADEON_FIFO_DEBUG 348145132Sanholt DRM_ERROR("failed!\n"); 349145132Sanholt radeon_status(dev_priv); 35095584Sanholt#endif 351182080Srnoland return -EBUSY; 35295584Sanholt} 35395584Sanholt 354145132Sanholtstatic int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) 35595584Sanholt{ 35695584Sanholt int i; 35795584Sanholt 358112015Sanholt dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 359112015Sanholt 360145132Sanholt for (i = 0; i < dev_priv->usec_timeout; i++) { 361145132Sanholt int slots = (RADEON_READ(RADEON_RBBM_STATUS) 362145132Sanholt & RADEON_RBBM_FIFOCNT_MASK); 363145132Sanholt if (slots >= entries) 364145132Sanholt return 0; 365145132Sanholt DRM_UDELAY(1); 36695584Sanholt } 367189499Srnoland DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n", 368182080Srnoland RADEON_READ(RADEON_RBBM_STATUS), 369182080Srnoland RADEON_READ(R300_VAP_CNTL_STATUS)); 37095584Sanholt 37195584Sanholt#if RADEON_FIFO_DEBUG 372145132Sanholt DRM_ERROR("failed!\n"); 373145132Sanholt radeon_status(dev_priv); 37495584Sanholt#endif 375182080Srnoland return -EBUSY; 37695584Sanholt} 37795584Sanholt 378145132Sanholtstatic int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) 37995584Sanholt{ 38095584Sanholt int i, ret; 38195584Sanholt 382112015Sanholt dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 383112015Sanholt 384145132Sanholt ret = radeon_do_wait_for_fifo(dev_priv, 64); 385145132Sanholt if (ret) 386145132Sanholt return ret; 387112015Sanholt 388145132Sanholt for (i = 0; i < dev_priv->usec_timeout; i++) { 389145132Sanholt if (!(RADEON_READ(RADEON_RBBM_STATUS) 390145132Sanholt & RADEON_RBBM_ACTIVE)) { 391145132Sanholt radeon_do_pixcache_flush(dev_priv); 39295584Sanholt return 0; 39395584Sanholt } 394145132Sanholt DRM_UDELAY(1); 39595584Sanholt } 396189499Srnoland DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n", 397182080Srnoland RADEON_READ(RADEON_RBBM_STATUS), 398182080Srnoland RADEON_READ(R300_VAP_CNTL_STATUS)); 39995584Sanholt 40095584Sanholt#if RADEON_FIFO_DEBUG 401145132Sanholt DRM_ERROR("failed!\n"); 402145132Sanholt radeon_status(dev_priv); 40395584Sanholt#endif 404182080Srnoland return -EBUSY; 40595584Sanholt} 40695584Sanholt 407189499Srnolandstatic void radeon_init_pipes(drm_radeon_private_t *dev_priv) 408182080Srnoland{ 409182080Srnoland uint32_t gb_tile_config, gb_pipe_sel = 0; 410182080Srnoland 411182080Srnoland /* RS4xx/RS6xx/R4xx/R5xx */ 412182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { 413182080Srnoland gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); 414182080Srnoland dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; 415182080Srnoland } else { 416182080Srnoland /* R3xx */ 417182080Srnoland if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || 418182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { 419182080Srnoland dev_priv->num_gb_pipes = 2; 420182080Srnoland } else { 421182080Srnoland /* R3Vxx */ 422182080Srnoland dev_priv->num_gb_pipes = 1; 423182080Srnoland } 424182080Srnoland } 425182080Srnoland DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes); 426182080Srnoland 427182080Srnoland gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/); 428182080Srnoland 429189499Srnoland switch (dev_priv->num_gb_pipes) { 430182080Srnoland case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; 431182080Srnoland case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; 432182080Srnoland case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; 433182080Srnoland default: 434182080Srnoland case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; 435182080Srnoland } 436182080Srnoland 437182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { 438182080Srnoland RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); 439182080Srnoland RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); 440182080Srnoland } 441182080Srnoland RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); 442182080Srnoland radeon_do_wait_for_idle(dev_priv); 443182080Srnoland RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); 444182080Srnoland RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) | 445182080Srnoland R300_DC_AUTOFLUSH_ENABLE | 446182080Srnoland R300_DC_DC_DISABLE_IGNORE_PE)); 447182080Srnoland 448182080Srnoland 449182080Srnoland} 450182080Srnoland 45195584Sanholt/* ================================================================ 45295584Sanholt * CP control, initialization 45395584Sanholt */ 45495584Sanholt 45595584Sanholt/* Load the microcode for the CP */ 456145132Sanholtstatic void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) 45795584Sanholt{ 458190595Srnoland const u32 (*cp)[2]; 45995584Sanholt int i; 460190595Srnoland 461145132Sanholt DRM_DEBUG("\n"); 46295584Sanholt 463145132Sanholt radeon_do_wait_for_idle(dev_priv); 46495584Sanholt 465145132Sanholt RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); 466190595Srnoland switch (dev_priv->flags & RADEON_FAMILY_MASK) { 467190595Srnoland case CHIP_R100: 468190595Srnoland case CHIP_RV100: 469190595Srnoland case CHIP_RV200: 470190595Srnoland case CHIP_RS100: 471190595Srnoland case CHIP_RS200: 472182080Srnoland DRM_INFO("Loading R100 Microcode\n"); 473190595Srnoland cp = R100_cp_microcode; 474190595Srnoland break; 475190595Srnoland case CHIP_R200: 476190595Srnoland case CHIP_RV250: 477190595Srnoland case CHIP_RV280: 478190595Srnoland case CHIP_RS300: 479112015Sanholt DRM_INFO("Loading R200 Microcode\n"); 480190595Srnoland cp = R200_cp_microcode; 481190595Srnoland break; 482190595Srnoland case CHIP_R300: 483190595Srnoland case CHIP_R350: 484190595Srnoland case CHIP_RV350: 485190595Srnoland case CHIP_RV380: 486190595Srnoland case CHIP_RS400: 487190595Srnoland case CHIP_RS480: 488145132Sanholt DRM_INFO("Loading R300 Microcode\n"); 489190595Srnoland cp = R300_cp_microcode; 490190595Srnoland break; 491190595Srnoland case CHIP_R420: 492190595Srnoland case CHIP_R423: 493190595Srnoland case CHIP_RV410: 494182080Srnoland DRM_INFO("Loading R400 Microcode\n"); 495190595Srnoland cp = R420_cp_microcode; 496190595Srnoland break; 497190595Srnoland case CHIP_RS690: 498190595Srnoland case CHIP_RS740: 499183828Srnoland DRM_INFO("Loading RS690/RS740 Microcode\n"); 500190595Srnoland cp = RS690_cp_microcode; 501190595Srnoland break; 502190595Srnoland case CHIP_RS600: 503189499Srnoland DRM_INFO("Loading RS600 Microcode\n"); 504190595Srnoland cp = RS600_cp_microcode; 505190595Srnoland break; 506190595Srnoland case CHIP_RV515: 507190595Srnoland case CHIP_R520: 508190595Srnoland case CHIP_RV530: 509190595Srnoland case CHIP_R580: 510190595Srnoland case CHIP_RV560: 511190595Srnoland case CHIP_RV570: 512182080Srnoland DRM_INFO("Loading R500 Microcode\n"); 513190595Srnoland cp = R520_cp_microcode; 514190595Srnoland break; 515190595Srnoland default: 516190595Srnoland return; 517112015Sanholt } 518190595Srnoland 519190595Srnoland for (i = 0; i != 256; i++) { 520190595Srnoland RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, cp[i][1]); 521190595Srnoland RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, cp[i][0]); 522190595Srnoland } 52395584Sanholt} 52495584Sanholt 52595584Sanholt/* Flush any pending commands to the CP. This should only be used just 52695584Sanholt * prior to a wait for idle, as it informs the engine that the command 52795584Sanholt * stream is ending. 52895584Sanholt */ 529145132Sanholtstatic void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) 53095584Sanholt{ 531145132Sanholt DRM_DEBUG("\n"); 53295584Sanholt#if 0 53395584Sanholt u32 tmp; 53495584Sanholt 535145132Sanholt tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); 536145132Sanholt RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); 53795584Sanholt#endif 53895584Sanholt} 53995584Sanholt 54095584Sanholt/* Wait for the CP to go idle. 54195584Sanholt */ 542145132Sanholtint radeon_do_cp_idle(drm_radeon_private_t * dev_priv) 54395584Sanholt{ 54495584Sanholt RING_LOCALS; 545145132Sanholt DRM_DEBUG("\n"); 54695584Sanholt 547145132Sanholt BEGIN_RING(6); 54895584Sanholt 54995584Sanholt RADEON_PURGE_CACHE(); 55095584Sanholt RADEON_PURGE_ZCACHE(); 55195584Sanholt RADEON_WAIT_UNTIL_IDLE(); 55295584Sanholt 55395584Sanholt ADVANCE_RING(); 554112015Sanholt COMMIT_RING(); 55595584Sanholt 556145132Sanholt return radeon_do_wait_for_idle(dev_priv); 55795584Sanholt} 55895584Sanholt 55995584Sanholt/* Start the Command Processor. 56095584Sanholt */ 561145132Sanholtstatic void radeon_do_cp_start(drm_radeon_private_t * dev_priv) 56295584Sanholt{ 56395584Sanholt RING_LOCALS; 564145132Sanholt DRM_DEBUG("\n"); 56595584Sanholt 566145132Sanholt radeon_do_wait_for_idle(dev_priv); 56795584Sanholt 568145132Sanholt RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); 56995584Sanholt 57095584Sanholt dev_priv->cp_running = 1; 57195584Sanholt 572182080Srnoland BEGIN_RING(8); 573182080Srnoland /* isync can only be written through cp on r5xx write it here */ 574182080Srnoland OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); 575182080Srnoland OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | 576182080Srnoland RADEON_ISYNC_ANY3D_IDLE2D | 577182080Srnoland RADEON_ISYNC_WAIT_IDLEGUI | 578182080Srnoland RADEON_ISYNC_CPSCRATCH_IDLEGUI); 57995584Sanholt RADEON_PURGE_CACHE(); 58095584Sanholt RADEON_PURGE_ZCACHE(); 58195584Sanholt RADEON_WAIT_UNTIL_IDLE(); 58295584Sanholt ADVANCE_RING(); 583112015Sanholt COMMIT_RING(); 584182080Srnoland 585182080Srnoland dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED; 58695584Sanholt} 58795584Sanholt 58895584Sanholt/* Reset the Command Processor. This will not flush any pending 58995584Sanholt * commands, so you must wait for the CP command stream to complete 59095584Sanholt * before calling this routine. 59195584Sanholt */ 592145132Sanholtstatic void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) 59395584Sanholt{ 59495584Sanholt u32 cur_read_ptr; 595145132Sanholt DRM_DEBUG("\n"); 59695584Sanholt 597145132Sanholt cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); 598145132Sanholt RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); 599145132Sanholt SET_RING_HEAD(dev_priv, cur_read_ptr); 60095584Sanholt dev_priv->ring.tail = cur_read_ptr; 60195584Sanholt} 60295584Sanholt 60395584Sanholt/* Stop the Command Processor. This will not flush any pending 60495584Sanholt * commands, so you must flush the command stream and wait for the CP 60595584Sanholt * to go idle before calling this routine. 60695584Sanholt */ 607145132Sanholtstatic void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) 60895584Sanholt{ 609145132Sanholt DRM_DEBUG("\n"); 61095584Sanholt 611145132Sanholt RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); 61295584Sanholt 61395584Sanholt dev_priv->cp_running = 0; 61495584Sanholt} 61595584Sanholt 61695584Sanholt/* Reset the engine. This will stop the CP if it is running. 61795584Sanholt */ 618182080Srnolandstatic int radeon_do_engine_reset(struct drm_device * dev) 61995584Sanholt{ 62095584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 621182080Srnoland u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset; 622145132Sanholt DRM_DEBUG("\n"); 62395584Sanholt 624145132Sanholt radeon_do_pixcache_flush(dev_priv); 62595584Sanholt 626182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { 627189499Srnoland /* may need something similar for newer chips */ 628182080Srnoland clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); 629182080Srnoland mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); 63095584Sanholt 631182080Srnoland RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | 632182080Srnoland RADEON_FORCEON_MCLKA | 633182080Srnoland RADEON_FORCEON_MCLKB | 634182080Srnoland RADEON_FORCEON_YCLKA | 635182080Srnoland RADEON_FORCEON_YCLKB | 636182080Srnoland RADEON_FORCEON_MC | 637182080Srnoland RADEON_FORCEON_AIC)); 638182080Srnoland } 63995584Sanholt 640145132Sanholt rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); 64195584Sanholt 642145132Sanholt RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | 643145132Sanholt RADEON_SOFT_RESET_CP | 644145132Sanholt RADEON_SOFT_RESET_HI | 645145132Sanholt RADEON_SOFT_RESET_SE | 646145132Sanholt RADEON_SOFT_RESET_RE | 647145132Sanholt RADEON_SOFT_RESET_PP | 648145132Sanholt RADEON_SOFT_RESET_E2 | 649145132Sanholt RADEON_SOFT_RESET_RB)); 650145132Sanholt RADEON_READ(RADEON_RBBM_SOFT_RESET); 651145132Sanholt RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & 652145132Sanholt ~(RADEON_SOFT_RESET_CP | 65395584Sanholt RADEON_SOFT_RESET_HI | 65495584Sanholt RADEON_SOFT_RESET_SE | 65595584Sanholt RADEON_SOFT_RESET_RE | 65695584Sanholt RADEON_SOFT_RESET_PP | 65795584Sanholt RADEON_SOFT_RESET_E2 | 658145132Sanholt RADEON_SOFT_RESET_RB))); 659145132Sanholt RADEON_READ(RADEON_RBBM_SOFT_RESET); 66095584Sanholt 661182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { 662182080Srnoland RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); 663182080Srnoland RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); 664182080Srnoland RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); 665182080Srnoland } 66695584Sanholt 667182080Srnoland /* setup the raster pipes */ 668182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) 669182080Srnoland radeon_init_pipes(dev_priv); 670182080Srnoland 67195584Sanholt /* Reset the CP ring */ 672145132Sanholt radeon_do_cp_reset(dev_priv); 67395584Sanholt 67495584Sanholt /* The CP is no longer running after an engine reset */ 67595584Sanholt dev_priv->cp_running = 0; 67695584Sanholt 67795584Sanholt /* Reset any pending vertex, indirect buffers */ 678145132Sanholt radeon_freelist_reset(dev); 67995584Sanholt 68095584Sanholt return 0; 68195584Sanholt} 68295584Sanholt 683182080Srnolandstatic void radeon_cp_init_ring_buffer(struct drm_device * dev, 684189499Srnoland drm_radeon_private_t *dev_priv, 685189499Srnoland struct drm_file *file_priv) 68695584Sanholt{ 68795584Sanholt u32 ring_start, cur_read_ptr; 688182080Srnoland 689157617Sanholt /* Initialize the memory controller. With new memory map, the fb location 690157617Sanholt * is not changed, it should have been properly initialized already. Part 691157617Sanholt * of the problem is that the code below is bogus, assuming the GART is 692157617Sanholt * always appended to the fb which is not necessarily the case 693157617Sanholt */ 694157617Sanholt if (!dev_priv->new_memmap) 695182080Srnoland radeon_write_fb_location(dev_priv, 696157617Sanholt ((dev_priv->gart_vm_start - 1) & 0xffff0000) 697157617Sanholt | (dev_priv->fb_location >> 16)); 69895584Sanholt 699145132Sanholt#if __OS_HAS_AGP 700182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 701182080Srnoland radeon_write_agp_base(dev_priv, dev->agp->base); 702182080Srnoland 703182080Srnoland radeon_write_agp_location(dev_priv, 704145132Sanholt (((dev_priv->gart_vm_start - 1 + 705145132Sanholt dev_priv->gart_size) & 0xffff0000) | 706145132Sanholt (dev_priv->gart_vm_start >> 16))); 70795584Sanholt 70895584Sanholt ring_start = (dev_priv->cp_ring->offset 709157617Sanholt - dev->agp->base 710157617Sanholt + dev_priv->gart_vm_start); 711145132Sanholt } else 71295584Sanholt#endif 71395584Sanholt ring_start = (dev_priv->cp_ring->offset 714157617Sanholt - (unsigned long)dev->sg->virtual 715157617Sanholt + dev_priv->gart_vm_start); 71695584Sanholt 717145132Sanholt RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); 71895584Sanholt 71995584Sanholt /* Set the write pointer delay */ 720145132Sanholt RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); 72195584Sanholt 72295584Sanholt /* Initialize the ring buffer's read and write pointers */ 723145132Sanholt cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); 724145132Sanholt RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); 725145132Sanholt SET_RING_HEAD(dev_priv, cur_read_ptr); 72695584Sanholt dev_priv->ring.tail = cur_read_ptr; 72795584Sanholt 728145132Sanholt#if __OS_HAS_AGP 729182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 730145132Sanholt RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, 731145132Sanholt dev_priv->ring_rptr->offset 732145132Sanholt - dev->agp->base + dev_priv->gart_vm_start); 733113995Sanholt } else 734113995Sanholt#endif 735113995Sanholt { 736189499Srnoland RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, 737189499Srnoland dev_priv->ring_rptr->offset 738189499Srnoland - ((unsigned long) dev->sg->virtual) 739189499Srnoland + dev_priv->gart_vm_start); 74095584Sanholt } 74195584Sanholt 742157617Sanholt /* Set ring buffer size */ 743157617Sanholt#ifdef __BIG_ENDIAN 744157617Sanholt RADEON_WRITE(RADEON_CP_RB_CNTL, 745182080Srnoland RADEON_BUF_SWAP_32BIT | 746182080Srnoland (dev_priv->ring.fetch_size_l2ow << 18) | 747182080Srnoland (dev_priv->ring.rptr_update_l2qw << 8) | 748182080Srnoland dev_priv->ring.size_l2qw); 749157617Sanholt#else 750182080Srnoland RADEON_WRITE(RADEON_CP_RB_CNTL, 751182080Srnoland (dev_priv->ring.fetch_size_l2ow << 18) | 752182080Srnoland (dev_priv->ring.rptr_update_l2qw << 8) | 753182080Srnoland dev_priv->ring.size_l2qw); 754157617Sanholt#endif 755157617Sanholt 756189499Srnoland 757112015Sanholt /* Initialize the scratch register pointer. This will cause 758112015Sanholt * the scratch register values to be written out to memory 759112015Sanholt * whenever they are updated. 760112015Sanholt * 761112015Sanholt * We simply put this behind the ring read pointer, this works 762112015Sanholt * with PCI GART as well as (whatever kind of) AGP GART 763112015Sanholt */ 764145132Sanholt RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) 765145132Sanholt + RADEON_SCRATCH_REG_OFFSET); 766112015Sanholt 767145132Sanholt RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); 768112015Sanholt 769189499Srnoland radeon_enable_bm(dev_priv); 770112015Sanholt 771189499Srnoland radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0); 772189499Srnoland RADEON_WRITE(RADEON_LAST_FRAME_REG, 0); 773112015Sanholt 774189499Srnoland radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0); 775189499Srnoland RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0); 776112015Sanholt 777189499Srnoland radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0); 778189499Srnoland RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0); 779112015Sanholt 780189499Srnoland /* reset sarea copies of these */ 781189499Srnoland if (dev_priv->sarea_priv) { 782189499Srnoland dev_priv->sarea_priv->last_frame = 0; 783189499Srnoland dev_priv->sarea_priv->last_dispatch = 0; 784189499Srnoland dev_priv->sarea_priv->last_clear = 0; 785189499Srnoland } 786189499Srnoland 787145132Sanholt radeon_do_wait_for_idle(dev_priv); 78895584Sanholt 78995584Sanholt /* Sync everything up */ 790145132Sanholt RADEON_WRITE(RADEON_ISYNC_CNTL, 791145132Sanholt (RADEON_ISYNC_ANY2D_IDLE3D | 792145132Sanholt RADEON_ISYNC_ANY3D_IDLE2D | 793145132Sanholt RADEON_ISYNC_WAIT_IDLEGUI | 794145132Sanholt RADEON_ISYNC_CPSCRATCH_IDLEGUI)); 795157617Sanholt 79695584Sanholt} 79795584Sanholt 798157617Sanholtstatic void radeon_test_writeback(drm_radeon_private_t * dev_priv) 799157617Sanholt{ 800157617Sanholt u32 tmp; 801157617Sanholt 802189499Srnoland /* Start with assuming that writeback doesn't work */ 803189499Srnoland dev_priv->writeback_works = 0; 804189499Srnoland 805157617Sanholt /* Writeback doesn't seem to work everywhere, test it here and possibly 806157617Sanholt * enable it if it appears to work 807157617Sanholt */ 808189499Srnoland radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0); 809189499Srnoland 810157617Sanholt RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); 811157617Sanholt 812157617Sanholt for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 813189499Srnoland u32 val; 814189499Srnoland 815189499Srnoland val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1)); 816189499Srnoland if (val == 0xdeadbeef) 817157617Sanholt break; 818157617Sanholt DRM_UDELAY(1); 819157617Sanholt } 820157617Sanholt 821157617Sanholt if (tmp < dev_priv->usec_timeout) { 822157617Sanholt dev_priv->writeback_works = 1; 823157617Sanholt DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 824157617Sanholt } else { 825157617Sanholt dev_priv->writeback_works = 0; 826157617Sanholt DRM_INFO("writeback test failed\n"); 827157617Sanholt } 828157617Sanholt if (radeon_no_wb == 1) { 829157617Sanholt dev_priv->writeback_works = 0; 830157617Sanholt DRM_INFO("writeback forced off\n"); 831157617Sanholt } 832162132Sanholt 833162132Sanholt if (!dev_priv->writeback_works) { 834189499Srnoland /* Disable writeback to avoid unnecessary bus master transfer */ 835189499Srnoland RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | 836189499Srnoland RADEON_RB_NO_UPDATE); 837162132Sanholt RADEON_WRITE(RADEON_SCRATCH_UMSK, 0); 838162132Sanholt } 839157617Sanholt} 840157617Sanholt 841182080Srnoland/* Enable or disable IGP GART on the chip */ 842182080Srnolandstatic void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) 843182080Srnoland{ 844182080Srnoland u32 temp; 845182080Srnoland 846182080Srnoland if (on) { 847182080Srnoland DRM_DEBUG("programming igp gart %08X %08lX %08X\n", 848189499Srnoland dev_priv->gart_vm_start, 849189499Srnoland (long)dev_priv->gart_info.bus_addr, 850189499Srnoland dev_priv->gart_size); 851182080Srnoland 852182080Srnoland temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); 853183828Srnoland if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 854183828Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 855182080Srnoland IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | 856182080Srnoland RS690_BLOCK_GFX_D3_EN)); 857182080Srnoland else 858182080Srnoland IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); 859182080Srnoland 860182080Srnoland IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | 861182080Srnoland RS480_VA_SIZE_32MB)); 862182080Srnoland 863182080Srnoland temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); 864182080Srnoland IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN | 865182080Srnoland RS480_TLB_ENABLE | 866182080Srnoland RS480_GTW_LAC_EN | 867182080Srnoland RS480_1LEVEL_GART)); 868182080Srnoland 869182080Srnoland temp = dev_priv->gart_info.bus_addr & 0xfffff000; 870182080Srnoland temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; 871182080Srnoland IGP_WRITE_MCIND(RS480_GART_BASE, temp); 872182080Srnoland 873182080Srnoland temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); 874182080Srnoland IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | 875182080Srnoland RS480_REQ_TYPE_SNOOP_DIS)); 876182080Srnoland 877182080Srnoland radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start); 878182080Srnoland 879182080Srnoland dev_priv->gart_size = 32*1024*1024; 880189499Srnoland temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & 881189499Srnoland 0xffff0000) | (dev_priv->gart_vm_start >> 16)); 882182080Srnoland 883182080Srnoland radeon_write_agp_location(dev_priv, temp); 884182080Srnoland 885182080Srnoland temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); 886182080Srnoland IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | 887182080Srnoland RS480_VA_SIZE_32MB)); 888182080Srnoland 889182080Srnoland do { 890182080Srnoland temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 891182080Srnoland if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) 892182080Srnoland break; 893182080Srnoland DRM_UDELAY(1); 894189499Srnoland } while (1); 895182080Srnoland 896182080Srnoland IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 897182080Srnoland RS480_GART_CACHE_INVALIDATE); 898182080Srnoland 899182080Srnoland do { 900182080Srnoland temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 901182080Srnoland if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) 902182080Srnoland break; 903182080Srnoland DRM_UDELAY(1); 904189499Srnoland } while (1); 905182080Srnoland 906182080Srnoland IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); 907182080Srnoland } else { 908182080Srnoland IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 909182080Srnoland } 910182080Srnoland} 911182080Srnoland 912189499Srnoland/* Enable or disable IGP GART on the chip */ 913189499Srnolandstatic void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on) 914189499Srnoland{ 915189499Srnoland u32 temp; 916189499Srnoland int i; 917189499Srnoland 918189499Srnoland if (on) { 919189499Srnoland DRM_DEBUG("programming igp gart %08X %08lX %08X\n", 920189499Srnoland dev_priv->gart_vm_start, 921189499Srnoland (long)dev_priv->gart_info.bus_addr, 922189499Srnoland dev_priv->gart_size); 923189499Srnoland 924189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) | 925189499Srnoland RS600_EFFECTIVE_L2_QUEUE_SIZE(6))); 926189499Srnoland 927189499Srnoland for (i = 0; i < 19; i++) 928189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i, 929189499Srnoland (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE | 930189499Srnoland RS600_SYSTEM_ACCESS_MODE_IN_SYS | 931189499Srnoland RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH | 932189499Srnoland RS600_EFFECTIVE_L1_CACHE_SIZE(3) | 933189499Srnoland RS600_ENABLE_FRAGMENT_PROCESSING | 934189499Srnoland RS600_EFFECTIVE_L1_QUEUE_SIZE(3))); 935189499Srnoland 936189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE | 937189499Srnoland RS600_PAGE_TABLE_TYPE_FLAT)); 938189499Srnoland 939189499Srnoland /* disable all other contexts */ 940189499Srnoland for (i = 1; i < 8; i++) 941189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0); 942189499Srnoland 943189499Srnoland /* setup the page table aperture */ 944189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 945189499Srnoland dev_priv->gart_info.bus_addr); 946189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR, 947189499Srnoland dev_priv->gart_vm_start); 948189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR, 949189499Srnoland (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); 950189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 951189499Srnoland 952189499Srnoland /* setup the system aperture */ 953189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, 954189499Srnoland dev_priv->gart_vm_start); 955189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, 956189499Srnoland (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); 957189499Srnoland 958189499Srnoland /* enable page tables */ 959189499Srnoland temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 960189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT)); 961189499Srnoland 962189499Srnoland temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1); 963189499Srnoland IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES)); 964189499Srnoland 965189499Srnoland /* invalidate the cache */ 966189499Srnoland temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 967189499Srnoland 968189499Srnoland temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); 969189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp); 970189499Srnoland temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 971189499Srnoland 972189499Srnoland temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE; 973189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp); 974189499Srnoland temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 975189499Srnoland 976189499Srnoland temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); 977189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp); 978189499Srnoland temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 979189499Srnoland 980189499Srnoland } else { 981189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0); 982189499Srnoland temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1); 983189499Srnoland temp &= ~RS600_ENABLE_PAGE_TABLES; 984189499Srnoland IGP_WRITE_MCIND(RS600_MC_CNTL1, temp); 985189499Srnoland } 986189499Srnoland} 987189499Srnoland 988148211Sanholtstatic void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) 989148211Sanholt{ 990148211Sanholt u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); 991148211Sanholt if (on) { 992148211Sanholt 993152909Sanholt DRM_DEBUG("programming pcie %08X %08lX %08X\n", 994157617Sanholt dev_priv->gart_vm_start, 995157617Sanholt (long)dev_priv->gart_info.bus_addr, 996152909Sanholt dev_priv->gart_size); 997157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, 998157617Sanholt dev_priv->gart_vm_start); 999157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, 1000157617Sanholt dev_priv->gart_info.bus_addr); 1001157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, 1002157617Sanholt dev_priv->gart_vm_start); 1003157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, 1004157617Sanholt dev_priv->gart_vm_start + 1005157617Sanholt dev_priv->gart_size - 1); 1006148211Sanholt 1007182080Srnoland radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ 1008148211Sanholt 1009157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, 1010157617Sanholt RADEON_PCIE_TX_GART_EN); 1011148211Sanholt } else { 1012157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, 1013157617Sanholt tmp & ~RADEON_PCIE_TX_GART_EN); 1014148211Sanholt } 1015148211Sanholt} 1016148211Sanholt 1017119098Sanholt/* Enable or disable PCI GART on the chip */ 1018145132Sanholtstatic void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) 1019119098Sanholt{ 1020152909Sanholt u32 tmp; 1021119098Sanholt 1022182080Srnoland if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 1023183828Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) || 1024182080Srnoland (dev_priv->flags & RADEON_IS_IGPGART)) { 1025182080Srnoland radeon_set_igpgart(dev_priv, on); 1026182080Srnoland return; 1027182080Srnoland } 1028182080Srnoland 1029189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { 1030189499Srnoland rs600_set_igpgart(dev_priv, on); 1031189499Srnoland return; 1032189499Srnoland } 1033189499Srnoland 1034182080Srnoland if (dev_priv->flags & RADEON_IS_PCIE) { 1035148211Sanholt radeon_set_pciegart(dev_priv, on); 1036148211Sanholt return; 1037148211Sanholt } 1038148211Sanholt 1039182080Srnoland tmp = RADEON_READ(RADEON_AIC_CNTL); 1040152909Sanholt 1041145132Sanholt if (on) { 1042145132Sanholt RADEON_WRITE(RADEON_AIC_CNTL, 1043145132Sanholt tmp | RADEON_PCIGART_TRANSLATE_EN); 1044119098Sanholt 1045119098Sanholt /* set PCI GART page-table base address 1046119098Sanholt */ 1047152909Sanholt RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); 1048119098Sanholt 1049119098Sanholt /* set address range for PCI address translate 1050119098Sanholt */ 1051145132Sanholt RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); 1052145132Sanholt RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start 1053145132Sanholt + dev_priv->gart_size - 1); 1054119098Sanholt 1055119895Sanholt /* Turn off AGP aperture -- is this required for PCI GART? 1056119098Sanholt */ 1057182080Srnoland radeon_write_agp_location(dev_priv, 0xffffffc0); 1058145132Sanholt RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ 1059119098Sanholt } else { 1060145132Sanholt RADEON_WRITE(RADEON_AIC_CNTL, 1061145132Sanholt tmp & ~RADEON_PCIGART_TRANSLATE_EN); 1062119098Sanholt } 1063119098Sanholt} 1064119098Sanholt 1065189499Srnolandstatic int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv) 106695584Sanholt{ 1067189499Srnoland struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; 1068189499Srnoland struct radeon_virt_surface *vp; 1069189499Srnoland int i; 1070189499Srnoland 1071189499Srnoland for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) { 1072189499Srnoland if (!dev_priv->virt_surfaces[i].file_priv || 1073189499Srnoland dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV) 1074189499Srnoland break; 1075189499Srnoland } 1076189499Srnoland if (i >= 2 * RADEON_MAX_SURFACES) 1077189499Srnoland return -ENOMEM; 1078189499Srnoland vp = &dev_priv->virt_surfaces[i]; 1079189499Srnoland 1080189499Srnoland for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1081189499Srnoland struct radeon_surface *sp = &dev_priv->surfaces[i]; 1082189499Srnoland if (sp->refcount) 1083189499Srnoland continue; 1084189499Srnoland 1085189499Srnoland vp->surface_index = i; 1086189499Srnoland vp->lower = gart_info->bus_addr; 1087189499Srnoland vp->upper = vp->lower + gart_info->table_size; 1088189499Srnoland vp->flags = 0; 1089189499Srnoland vp->file_priv = PCIGART_FILE_PRIV; 1090189499Srnoland 1091189499Srnoland sp->refcount = 1; 1092189499Srnoland sp->lower = vp->lower; 1093189499Srnoland sp->upper = vp->upper; 1094189499Srnoland sp->flags = 0; 1095189499Srnoland 1096189499Srnoland RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags); 1097189499Srnoland RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower); 1098189499Srnoland RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper); 1099189499Srnoland return 0; 1100189499Srnoland } 1101189499Srnoland 1102189499Srnoland return -ENOMEM; 1103189499Srnoland} 1104189499Srnoland 1105189499Srnolandstatic int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 1106189499Srnoland struct drm_file *file_priv) 1107189499Srnoland{ 1108145132Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1109157617Sanholt 1110145132Sanholt DRM_DEBUG("\n"); 111195584Sanholt 1112157617Sanholt /* if we require new memory map but we don't have it fail */ 1113182080Srnoland if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 1114157617Sanholt DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 1115157617Sanholt radeon_do_cleanup_cp(dev); 1116182080Srnoland return -EINVAL; 1117157617Sanholt } 1118157617Sanholt 1119189499Srnoland if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { 1120152909Sanholt DRM_DEBUG("Forcing AGP card to PCI mode\n"); 1121182080Srnoland dev_priv->flags &= ~RADEON_IS_AGP; 1122189499Srnoland } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) 1123189499Srnoland && !init->is_pci) { 1124162132Sanholt DRM_DEBUG("Restoring AGP flag\n"); 1125182080Srnoland dev_priv->flags |= RADEON_IS_AGP; 1126162132Sanholt } 1127152909Sanholt 1128182080Srnoland if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { 1129145132Sanholt DRM_ERROR("PCI GART memory not allocated!\n"); 113095584Sanholt radeon_do_cleanup_cp(dev); 1131182080Srnoland return -EINVAL; 113295584Sanholt } 113395584Sanholt 113495584Sanholt dev_priv->usec_timeout = init->usec_timeout; 1135145132Sanholt if (dev_priv->usec_timeout < 1 || 1136145132Sanholt dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 1137145132Sanholt DRM_DEBUG("TIMEOUT problem!\n"); 113895584Sanholt radeon_do_cleanup_cp(dev); 1139182080Srnoland return -EINVAL; 114095584Sanholt } 114195584Sanholt 1142182080Srnoland /* Enable vblank on CRTC1 for older X servers 1143182080Srnoland */ 1144182080Srnoland dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 1145145132Sanholt 1146189499Srnoland switch(init->func) { 1147189499Srnoland case RADEON_INIT_R200_CP: 1148189499Srnoland dev_priv->microcode_version = UCODE_R200; 1149189499Srnoland break; 1150189499Srnoland case RADEON_INIT_R300_CP: 1151189499Srnoland dev_priv->microcode_version = UCODE_R300; 1152189499Srnoland break; 1153189499Srnoland default: 1154189499Srnoland dev_priv->microcode_version = UCODE_R100; 1155189499Srnoland } 1156189499Srnoland 1157112015Sanholt dev_priv->do_boxes = 0; 115895584Sanholt dev_priv->cp_mode = init->cp_mode; 115995584Sanholt 116095584Sanholt /* We don't support anything other than bus-mastering ring mode, 116195584Sanholt * but the ring can be in either AGP or PCI space for the ring 116295584Sanholt * read pointer. 116395584Sanholt */ 1164145132Sanholt if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 1165145132Sanholt (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 1166145132Sanholt DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 116795584Sanholt radeon_do_cleanup_cp(dev); 1168182080Srnoland return -EINVAL; 116995584Sanholt } 117095584Sanholt 1171145132Sanholt switch (init->fb_bpp) { 117295584Sanholt case 16: 117395584Sanholt dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 117495584Sanholt break; 117595584Sanholt case 32: 117695584Sanholt default: 117795584Sanholt dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 117895584Sanholt break; 117995584Sanholt } 1180145132Sanholt dev_priv->front_offset = init->front_offset; 1181145132Sanholt dev_priv->front_pitch = init->front_pitch; 1182145132Sanholt dev_priv->back_offset = init->back_offset; 1183145132Sanholt dev_priv->back_pitch = init->back_pitch; 118495584Sanholt 1185145132Sanholt switch (init->depth_bpp) { 118695584Sanholt case 16: 118795584Sanholt dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 118895584Sanholt break; 118995584Sanholt case 32: 119095584Sanholt default: 119195584Sanholt dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 119295584Sanholt break; 119395584Sanholt } 1194145132Sanholt dev_priv->depth_offset = init->depth_offset; 1195145132Sanholt dev_priv->depth_pitch = init->depth_pitch; 119695584Sanholt 119795584Sanholt /* Hardware state for depth clears. Remove this if/when we no 119895584Sanholt * longer clear the depth buffer with a 3D rectangle. Hard-code 119995584Sanholt * all values to prevent unwanted 3D state from slipping through 120095584Sanholt * and screwing with the clear operation. 120195584Sanholt */ 120295584Sanholt dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | 120395584Sanholt (dev_priv->color_fmt << 10) | 1204189499Srnoland (dev_priv->microcode_version == 1205189499Srnoland UCODE_R100 ? RADEON_ZBLOCK16 : 0)); 120695584Sanholt 1207145132Sanholt dev_priv->depth_clear.rb3d_zstencilcntl = 1208145132Sanholt (dev_priv->depth_fmt | 1209145132Sanholt RADEON_Z_TEST_ALWAYS | 1210145132Sanholt RADEON_STENCIL_TEST_ALWAYS | 1211145132Sanholt RADEON_STENCIL_S_FAIL_REPLACE | 1212145132Sanholt RADEON_STENCIL_ZPASS_REPLACE | 1213145132Sanholt RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); 121495584Sanholt 121595584Sanholt dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | 121695584Sanholt RADEON_BFACE_SOLID | 121795584Sanholt RADEON_FFACE_SOLID | 121895584Sanholt RADEON_FLAT_SHADE_VTX_LAST | 121995584Sanholt RADEON_DIFFUSE_SHADE_FLAT | 122095584Sanholt RADEON_ALPHA_SHADE_FLAT | 122195584Sanholt RADEON_SPECULAR_SHADE_FLAT | 122295584Sanholt RADEON_FOG_SHADE_FLAT | 122395584Sanholt RADEON_VTX_PIX_CENTER_OGL | 122495584Sanholt RADEON_ROUND_MODE_TRUNC | 122595584Sanholt RADEON_ROUND_PREC_8TH_PIX); 122695584Sanholt 1227113995Sanholt 1228113995Sanholt dev_priv->ring_offset = init->ring_offset; 1229113995Sanholt dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1230113995Sanholt dev_priv->buffers_offset = init->buffers_offset; 1231119895Sanholt dev_priv->gart_textures_offset = init->gart_textures_offset; 1232145132Sanholt 1233182080Srnoland dev_priv->sarea = drm_getsarea(dev); 1234145132Sanholt if (!dev_priv->sarea) { 123595584Sanholt DRM_ERROR("could not find sarea!\n"); 123695584Sanholt radeon_do_cleanup_cp(dev); 1237182080Srnoland return -EINVAL; 123895584Sanholt } 123995584Sanholt 1240145132Sanholt dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 1241145132Sanholt if (!dev_priv->cp_ring) { 124295584Sanholt DRM_ERROR("could not find cp ring region!\n"); 124395584Sanholt radeon_do_cleanup_cp(dev); 1244182080Srnoland return -EINVAL; 124595584Sanholt } 1246145132Sanholt dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1247145132Sanholt if (!dev_priv->ring_rptr) { 124895584Sanholt DRM_ERROR("could not find ring read pointer!\n"); 124995584Sanholt radeon_do_cleanup_cp(dev); 1250182080Srnoland return -EINVAL; 125195584Sanholt } 1252152909Sanholt dev->agp_buffer_token = init->buffers_offset; 1253145132Sanholt dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1254145132Sanholt if (!dev->agp_buffer_map) { 125595584Sanholt DRM_ERROR("could not find dma buffer region!\n"); 125695584Sanholt radeon_do_cleanup_cp(dev); 1257182080Srnoland return -EINVAL; 125895584Sanholt } 125995584Sanholt 1260145132Sanholt if (init->gart_textures_offset) { 1261145132Sanholt dev_priv->gart_textures = 1262145132Sanholt drm_core_findmap(dev, init->gart_textures_offset); 1263145132Sanholt if (!dev_priv->gart_textures) { 1264119895Sanholt DRM_ERROR("could not find GART texture region!\n"); 126595584Sanholt radeon_do_cleanup_cp(dev); 1266182080Srnoland return -EINVAL; 126795584Sanholt } 126895584Sanholt } 126995584Sanholt 127095584Sanholt dev_priv->sarea_priv = 1271145132Sanholt (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + 1272145132Sanholt init->sarea_priv_offset); 127395584Sanholt 1274145132Sanholt#if __OS_HAS_AGP 1275182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 1276189499Srnoland drm_core_ioremap_wc(dev_priv->cp_ring, dev); 1277189499Srnoland drm_core_ioremap_wc(dev_priv->ring_rptr, dev); 1278189499Srnoland drm_core_ioremap_wc(dev->agp_buffer_map, dev); 1279145132Sanholt if (!dev_priv->cp_ring->handle || 1280145132Sanholt !dev_priv->ring_rptr->handle || 1281145132Sanholt !dev->agp_buffer_map->handle) { 128295584Sanholt DRM_ERROR("could not find ioremap agp regions!\n"); 128395584Sanholt radeon_do_cleanup_cp(dev); 1284182080Srnoland return -EINVAL; 128595584Sanholt } 1286119098Sanholt } else 1287119098Sanholt#endif 1288119098Sanholt { 1289189499Srnoland dev_priv->cp_ring->handle = 1290189499Srnoland (void *)(unsigned long)dev_priv->cp_ring->offset; 129195584Sanholt dev_priv->ring_rptr->handle = 1292189499Srnoland (void *)(unsigned long)dev_priv->ring_rptr->offset; 1293145132Sanholt dev->agp_buffer_map->handle = 1294189499Srnoland (void *)(unsigned long)dev->agp_buffer_map->offset; 129595584Sanholt 1296145132Sanholt DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 1297145132Sanholt dev_priv->cp_ring->handle); 1298145132Sanholt DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 1299145132Sanholt dev_priv->ring_rptr->handle); 1300145132Sanholt DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 1301145132Sanholt dev->agp_buffer_map->handle); 130295584Sanholt } 130395584Sanholt 1304182080Srnoland dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16; 1305182080Srnoland dev_priv->fb_size = 1306182080Srnoland ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000) 1307157617Sanholt - dev_priv->fb_location; 130895584Sanholt 1309145132Sanholt dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 1310145132Sanholt ((dev_priv->front_offset 1311145132Sanholt + dev_priv->fb_location) >> 10)); 1312122580Sanholt 1313145132Sanholt dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 1314145132Sanholt ((dev_priv->back_offset 1315145132Sanholt + dev_priv->fb_location) >> 10)); 1316122580Sanholt 1317145132Sanholt dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 1318145132Sanholt ((dev_priv->depth_offset 1319145132Sanholt + dev_priv->fb_location) >> 10)); 1320122580Sanholt 1321119895Sanholt dev_priv->gart_size = init->gart_size; 1322122580Sanholt 1323157617Sanholt /* New let's set the memory map ... */ 1324157617Sanholt if (dev_priv->new_memmap) { 1325157617Sanholt u32 base = 0; 1326157617Sanholt 1327157617Sanholt DRM_INFO("Setting GART location based on new memory map\n"); 1328157617Sanholt 1329157617Sanholt /* If using AGP, try to locate the AGP aperture at the same 1330157617Sanholt * location in the card and on the bus, though we have to 1331157617Sanholt * align it down. 1332157617Sanholt */ 1333145132Sanholt#if __OS_HAS_AGP 1334182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 1335157617Sanholt base = dev->agp->base; 1336157617Sanholt /* Check if valid */ 1337182080Srnoland if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && 1338182080Srnoland base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { 1339157617Sanholt DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 1340157617Sanholt dev->agp->base); 1341157617Sanholt base = 0; 1342157617Sanholt } 1343157617Sanholt } 1344157617Sanholt#endif 1345157617Sanholt /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 1346157617Sanholt if (base == 0) { 1347157617Sanholt base = dev_priv->fb_location + dev_priv->fb_size; 1348182080Srnoland if (base < dev_priv->fb_location || 1349182080Srnoland ((base + dev_priv->gart_size) & 0xfffffffful) < base) 1350157617Sanholt base = dev_priv->fb_location 1351157617Sanholt - dev_priv->gart_size; 1352182080Srnoland } 1353157617Sanholt dev_priv->gart_vm_start = base & 0xffc00000u; 1354157617Sanholt if (dev_priv->gart_vm_start != base) 1355157617Sanholt DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 1356157617Sanholt base, dev_priv->gart_vm_start); 1357157617Sanholt } else { 1358157617Sanholt DRM_INFO("Setting GART location based on old memory map\n"); 1359157617Sanholt dev_priv->gart_vm_start = dev_priv->fb_location + 1360157617Sanholt RADEON_READ(RADEON_CONFIG_APER_SIZE); 1361157617Sanholt } 1362157617Sanholt 1363157617Sanholt#if __OS_HAS_AGP 1364182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) 1365145132Sanholt dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1366145132Sanholt - dev->agp->base 1367145132Sanholt + dev_priv->gart_vm_start); 136895584Sanholt else 136995584Sanholt#endif 1370145132Sanholt dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1371157617Sanholt - (unsigned long)dev->sg->virtual 1372157617Sanholt + dev_priv->gart_vm_start); 137395584Sanholt 1374145132Sanholt DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 1375145132Sanholt DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); 1376145132Sanholt DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", 1377145132Sanholt dev_priv->gart_buffers_offset); 137895584Sanholt 1379145132Sanholt dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 1380145132Sanholt dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 138195584Sanholt + init->ring_size / sizeof(u32)); 138295584Sanholt dev_priv->ring.size = init->ring_size; 1383145132Sanholt dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 138495584Sanholt 1385182080Srnoland dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; 1386182080Srnoland dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8); 1387182080Srnoland 1388182080Srnoland dev_priv->ring.fetch_size = /* init->fetch_size */ 32; 1389182080Srnoland dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16); 1390145132Sanholt dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 139195584Sanholt 139295584Sanholt dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 139395584Sanholt 1394145132Sanholt#if __OS_HAS_AGP 1395182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 1396119098Sanholt /* Turn off PCI GART */ 1397145132Sanholt radeon_set_pcigart(dev_priv, 0); 1398119098Sanholt } else 1399119098Sanholt#endif 1400119098Sanholt { 1401189499Srnoland u32 sctrl; 1402189499Srnoland int ret; 1403189499Srnoland 1404182080Srnoland dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); 1405152909Sanholt /* if we have an offset set from userspace */ 1406182080Srnoland if (dev_priv->pcigart_offset_set) { 1407157617Sanholt dev_priv->gart_info.bus_addr = 1408157617Sanholt dev_priv->pcigart_offset + dev_priv->fb_location; 1409157617Sanholt dev_priv->gart_info.mapping.offset = 1410182080Srnoland dev_priv->pcigart_offset + dev_priv->fb_aper_offset; 1411157617Sanholt dev_priv->gart_info.mapping.size = 1412182080Srnoland dev_priv->gart_info.table_size; 1413157617Sanholt 1414182080Srnoland drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); 1415157617Sanholt dev_priv->gart_info.addr = 1416157617Sanholt dev_priv->gart_info.mapping.handle; 1417152909Sanholt 1418182080Srnoland if (dev_priv->flags & RADEON_IS_PCIE) 1419182080Srnoland dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE; 1420182080Srnoland else 1421182080Srnoland dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; 1422157617Sanholt dev_priv->gart_info.gart_table_location = 1423157617Sanholt DRM_ATI_GART_FB; 1424157617Sanholt 1425157617Sanholt DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 1426157617Sanholt dev_priv->gart_info.addr, 1427157617Sanholt dev_priv->pcigart_offset); 1428157617Sanholt } else { 1429182080Srnoland if (dev_priv->flags & RADEON_IS_IGPGART) 1430182080Srnoland dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP; 1431182080Srnoland else 1432182080Srnoland dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; 1433157617Sanholt dev_priv->gart_info.gart_table_location = 1434157617Sanholt DRM_ATI_GART_MAIN; 1435152909Sanholt dev_priv->gart_info.addr = NULL; 1436152909Sanholt dev_priv->gart_info.bus_addr = 0; 1437182080Srnoland if (dev_priv->flags & RADEON_IS_PCIE) { 1438157617Sanholt DRM_ERROR 1439157617Sanholt ("Cannot use PCI Express without GART in FB memory\n"); 1440152909Sanholt radeon_do_cleanup_cp(dev); 1441182080Srnoland return -EINVAL; 1442152909Sanholt } 1443152909Sanholt } 1444152909Sanholt 1445189499Srnoland sctrl = RADEON_READ(RADEON_SURFACE_CNTL); 1446189499Srnoland RADEON_WRITE(RADEON_SURFACE_CNTL, 0); 1447189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 1448189499Srnoland ret = r600_page_table_init(dev); 1449189499Srnoland else 1450189499Srnoland ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info); 1451189499Srnoland RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl); 1452189499Srnoland 1453189499Srnoland if (!ret) { 1454145132Sanholt DRM_ERROR("failed to init PCI GART!\n"); 145595584Sanholt radeon_do_cleanup_cp(dev); 1456182080Srnoland return -ENOMEM; 145795584Sanholt } 145895584Sanholt 1459189499Srnoland ret = radeon_setup_pcigart_surface(dev_priv); 1460189499Srnoland if (ret) { 1461189499Srnoland DRM_ERROR("failed to setup GART surface!\n"); 1462189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 1463189499Srnoland r600_page_table_cleanup(dev, &dev_priv->gart_info); 1464189499Srnoland else 1465189499Srnoland drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info); 1466189499Srnoland radeon_do_cleanup_cp(dev); 1467189499Srnoland return ret; 1468189499Srnoland } 1469189499Srnoland 1470119098Sanholt /* Turn on PCI GART */ 1471145132Sanholt radeon_set_pcigart(dev_priv, 1); 147295584Sanholt } 147395584Sanholt 1474145132Sanholt radeon_cp_load_microcode(dev_priv); 1475189499Srnoland radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); 147695584Sanholt 147795584Sanholt dev_priv->last_buf = 0; 147895584Sanholt 1479145132Sanholt radeon_do_engine_reset(dev); 1480157617Sanholt radeon_test_writeback(dev_priv); 148195584Sanholt 148295584Sanholt return 0; 148395584Sanholt} 148495584Sanholt 1485182080Srnolandstatic int radeon_do_cleanup_cp(struct drm_device * dev) 148695584Sanholt{ 1487145132Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1488145132Sanholt DRM_DEBUG("\n"); 148995584Sanholt 1490119098Sanholt /* Make sure interrupts are disabled here because the uninstall ioctl 1491119098Sanholt * may not have been called from userspace and after dev_private 1492119098Sanholt * is freed, it's too late. 1493119098Sanholt */ 1494145132Sanholt if (dev->irq_enabled) 1495145132Sanholt drm_irq_uninstall(dev); 1496119098Sanholt 1497145132Sanholt#if __OS_HAS_AGP 1498182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 1499145132Sanholt if (dev_priv->cp_ring != NULL) { 1500145132Sanholt drm_core_ioremapfree(dev_priv->cp_ring, dev); 1501145132Sanholt dev_priv->cp_ring = NULL; 1502145132Sanholt } 1503145132Sanholt if (dev_priv->ring_rptr != NULL) { 1504145132Sanholt drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1505145132Sanholt dev_priv->ring_rptr = NULL; 1506145132Sanholt } 1507145132Sanholt if (dev->agp_buffer_map != NULL) { 1508145132Sanholt drm_core_ioremapfree(dev->agp_buffer_map, dev); 1509145132Sanholt dev->agp_buffer_map = NULL; 1510145132Sanholt } 1511145132Sanholt } else 1512119098Sanholt#endif 1513145132Sanholt { 1514152909Sanholt 1515152909Sanholt if (dev_priv->gart_info.bus_addr) { 1516152909Sanholt /* Turn off PCI GART */ 1517152909Sanholt radeon_set_pcigart(dev_priv, 0); 1518189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 1519189499Srnoland r600_page_table_cleanup(dev, &dev_priv->gart_info); 1520189499Srnoland else { 1521189499Srnoland if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) 1522189499Srnoland DRM_ERROR("failed to cleanup PCI GART!\n"); 1523189499Srnoland } 1524152909Sanholt } 1525152909Sanholt 1526152909Sanholt if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) 1527152909Sanholt { 1528152909Sanholt drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 1529152909Sanholt dev_priv->gart_info.addr = 0; 1530152909Sanholt } 153195584Sanholt } 1532145132Sanholt /* only clear to the start of flags */ 1533145132Sanholt memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 153495584Sanholt 153595584Sanholt return 0; 153695584Sanholt} 153795584Sanholt 1538145132Sanholt/* This code will reinit the Radeon CP hardware after a resume from disc. 1539145132Sanholt * AFAIK, it would be very difficult to pickle the state at suspend time, so 1540119098Sanholt * here we make sure that all Radeon hardware initialisation is re-done without 1541119098Sanholt * affecting running applications. 1542119098Sanholt * 1543119098Sanholt * Charl P. Botha <http://cpbotha.net> 1544119098Sanholt */ 1545189499Srnolandstatic int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) 1546119098Sanholt{ 1547119098Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1548119098Sanholt 1549145132Sanholt if (!dev_priv) { 1550145132Sanholt DRM_ERROR("Called with no initialization\n"); 1551182080Srnoland return -EINVAL; 1552119098Sanholt } 1553119098Sanholt 1554119098Sanholt DRM_DEBUG("Starting radeon_do_resume_cp()\n"); 1555119098Sanholt 1556145132Sanholt#if __OS_HAS_AGP 1557182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 1558119098Sanholt /* Turn off PCI GART */ 1559145132Sanholt radeon_set_pcigart(dev_priv, 0); 1560119098Sanholt } else 1561119098Sanholt#endif 1562119098Sanholt { 1563119098Sanholt /* Turn on PCI GART */ 1564145132Sanholt radeon_set_pcigart(dev_priv, 1); 1565119098Sanholt } 1566119098Sanholt 1567145132Sanholt radeon_cp_load_microcode(dev_priv); 1568189499Srnoland radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); 1569119098Sanholt 1570145132Sanholt radeon_do_engine_reset(dev); 1571182080Srnoland radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); 1572119098Sanholt 1573119098Sanholt DRM_DEBUG("radeon_do_resume_cp() complete\n"); 1574119098Sanholt 1575119098Sanholt return 0; 1576119098Sanholt} 1577119098Sanholt 1578182080Srnolandint radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) 157995584Sanholt{ 1580189499Srnoland drm_radeon_private_t *dev_priv = dev->dev_private; 1581182080Srnoland drm_radeon_init_t *init = data; 158295584Sanholt 1583182080Srnoland LOCK_TEST_WITH_RETURN(dev, file_priv); 1584119098Sanholt 1585182080Srnoland if (init->func == RADEON_INIT_R300_CP) 1586182080Srnoland r300_init_reg_flags(dev); 158795584Sanholt 1588182080Srnoland switch (init->func) { 158995584Sanholt case RADEON_INIT_CP: 1590112015Sanholt case RADEON_INIT_R200_CP: 1591145132Sanholt case RADEON_INIT_R300_CP: 1592189499Srnoland return radeon_do_init_cp(dev, init, file_priv); 1593189499Srnoland case RADEON_INIT_R600_CP: 1594189499Srnoland return r600_do_init_cp(dev, init, file_priv); 159595584Sanholt case RADEON_CLEANUP_CP: 1596189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1597189499Srnoland return r600_do_cleanup_cp(dev); 1598189499Srnoland else 1599189499Srnoland return radeon_do_cleanup_cp(dev); 160095584Sanholt } 160195584Sanholt 1602182080Srnoland return -EINVAL; 160395584Sanholt} 160495584Sanholt 1605182080Srnolandint radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv) 160695584Sanholt{ 160795584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1608145132Sanholt DRM_DEBUG("\n"); 160995584Sanholt 1610182080Srnoland LOCK_TEST_WITH_RETURN(dev, file_priv); 161195584Sanholt 1612145132Sanholt if (dev_priv->cp_running) { 1613182080Srnoland DRM_DEBUG("while CP running\n"); 161495584Sanholt return 0; 161595584Sanholt } 1616145132Sanholt if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { 1617182080Srnoland DRM_DEBUG("called with bogus CP mode (%d)\n", 1618182080Srnoland dev_priv->cp_mode); 161995584Sanholt return 0; 162095584Sanholt } 162195584Sanholt 1622189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1623189499Srnoland r600_do_cp_start(dev_priv); 1624189499Srnoland else 1625189499Srnoland radeon_do_cp_start(dev_priv); 162695584Sanholt 162795584Sanholt return 0; 162895584Sanholt} 162995584Sanholt 163095584Sanholt/* Stop the CP. The engine must have been idled before calling this 163195584Sanholt * routine. 163295584Sanholt */ 1633182080Srnolandint radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv) 163495584Sanholt{ 163595584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1636182080Srnoland drm_radeon_cp_stop_t *stop = data; 163795584Sanholt int ret; 1638145132Sanholt DRM_DEBUG("\n"); 163995584Sanholt 1640182080Srnoland LOCK_TEST_WITH_RETURN(dev, file_priv); 164195584Sanholt 1642112015Sanholt if (!dev_priv->cp_running) 1643112015Sanholt return 0; 1644112015Sanholt 164595584Sanholt /* Flush any pending CP commands. This ensures any outstanding 164695584Sanholt * commands are exectuted by the engine before we turn it off. 164795584Sanholt */ 1648182080Srnoland if (stop->flush) { 1649145132Sanholt radeon_do_cp_flush(dev_priv); 165095584Sanholt } 165195584Sanholt 165295584Sanholt /* If we fail to make the engine go idle, we return an error 165395584Sanholt * code so that the DRM ioctl wrapper can try again. 165495584Sanholt */ 1655182080Srnoland if (stop->idle) { 1656189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1657189499Srnoland ret = r600_do_cp_idle(dev_priv); 1658189499Srnoland else 1659189499Srnoland ret = radeon_do_cp_idle(dev_priv); 1660145132Sanholt if (ret) 1661145132Sanholt return ret; 166295584Sanholt } 166395584Sanholt 166495584Sanholt /* Finally, we can turn off the CP. If the engine isn't idle, 166595584Sanholt * we will get some dropped triangles as they won't be fully 166695584Sanholt * rendered before the CP is shut down. 166795584Sanholt */ 1668189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1669189499Srnoland r600_do_cp_stop(dev_priv); 1670189499Srnoland else 1671189499Srnoland radeon_do_cp_stop(dev_priv); 167295584Sanholt 167395584Sanholt /* Reset the engine */ 1674189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1675189499Srnoland r600_do_engine_reset(dev); 1676189499Srnoland else 1677189499Srnoland radeon_do_engine_reset(dev); 167895584Sanholt 167995584Sanholt return 0; 168095584Sanholt} 168195584Sanholt 1682182080Srnolandvoid radeon_do_release(struct drm_device * dev) 1683112015Sanholt{ 1684112015Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1685145132Sanholt int i, ret; 1686112015Sanholt 1687112015Sanholt if (dev_priv) { 1688112015Sanholt if (dev_priv->cp_running) { 1689112015Sanholt /* Stop the cp */ 1690189557Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { 1691189499Srnoland while ((ret = r600_do_cp_idle(dev_priv)) != 0) { 1692189499Srnoland DRM_DEBUG("radeon_do_cp_idle %d\n", ret); 1693189499Srnoland mtx_sleep(&ret, &dev->dev_lock, 0, 1694189499Srnoland "rdnrel", 1); 1695189499Srnoland } 1696189499Srnoland } else { 1697189499Srnoland while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { 1698189499Srnoland DRM_DEBUG("radeon_do_cp_idle %d\n", ret); 1699189499Srnoland mtx_sleep(&ret, &dev->dev_lock, 0, 1700189499Srnoland "rdnrel", 1); 1701189499Srnoland } 1702112015Sanholt } 1703189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { 1704189499Srnoland r600_do_cp_stop(dev_priv); 1705189499Srnoland r600_do_engine_reset(dev); 1706189499Srnoland } else { 1707189499Srnoland radeon_do_cp_stop(dev_priv); 1708189499Srnoland radeon_do_engine_reset(dev); 1709189499Srnoland } 1710112015Sanholt } 1711112015Sanholt 1712189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) { 1713189499Srnoland /* Disable *all* interrupts */ 1714189499Srnoland if (dev_priv->mmio) /* remove this after permanent addmaps */ 1715189499Srnoland RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 1716112015Sanholt 1717189499Srnoland if (dev_priv->mmio) { /* remove all surfaces */ 1718189499Srnoland for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1719189499Srnoland RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0); 1720189499Srnoland RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 1721189499Srnoland 16 * i, 0); 1722189499Srnoland RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 1723189499Srnoland 16 * i, 0); 1724189499Srnoland } 1725145132Sanholt } 1726145132Sanholt } 1727145132Sanholt 1728112015Sanholt /* Free memory heap structures */ 1729145132Sanholt radeon_mem_takedown(&(dev_priv->gart_heap)); 1730145132Sanholt radeon_mem_takedown(&(dev_priv->fb_heap)); 1731112015Sanholt 1732112015Sanholt /* deallocate kernel resources */ 1733189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1734189499Srnoland r600_do_cleanup_cp(dev); 1735189499Srnoland else 1736189499Srnoland radeon_do_cleanup_cp(dev); 1737112015Sanholt } 1738112015Sanholt} 1739112015Sanholt 174095584Sanholt/* Just reset the CP ring. Called as part of an X Server engine reset. 174195584Sanholt */ 1742182080Srnolandint radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) 174395584Sanholt{ 174495584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1745145132Sanholt DRM_DEBUG("\n"); 174695584Sanholt 1747182080Srnoland LOCK_TEST_WITH_RETURN(dev, file_priv); 174895584Sanholt 1749145132Sanholt if (!dev_priv) { 1750182080Srnoland DRM_DEBUG("called before init done\n"); 1751182080Srnoland return -EINVAL; 175295584Sanholt } 175395584Sanholt 1754189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1755189499Srnoland r600_do_cp_reset(dev_priv); 1756189499Srnoland else 1757189499Srnoland radeon_do_cp_reset(dev_priv); 175895584Sanholt 175995584Sanholt /* The CP is no longer running after an engine reset */ 176095584Sanholt dev_priv->cp_running = 0; 176195584Sanholt 176295584Sanholt return 0; 176395584Sanholt} 176495584Sanholt 1765182080Srnolandint radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv) 176695584Sanholt{ 176795584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1768145132Sanholt DRM_DEBUG("\n"); 176995584Sanholt 1770182080Srnoland LOCK_TEST_WITH_RETURN(dev, file_priv); 177195584Sanholt 1772189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1773189499Srnoland return r600_do_cp_idle(dev_priv); 1774189499Srnoland else 1775189499Srnoland return radeon_do_cp_idle(dev_priv); 177695584Sanholt} 177795584Sanholt 1778119098Sanholt/* Added by Charl P. Botha to call radeon_do_resume_cp(). 1779119098Sanholt */ 1780182080Srnolandint radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv) 1781119098Sanholt{ 1782189499Srnoland drm_radeon_private_t *dev_priv = dev->dev_private; 1783189499Srnoland DRM_DEBUG("\n"); 1784119098Sanholt 1785189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1786189499Srnoland return r600_do_resume_cp(dev, file_priv); 1787189499Srnoland else 1788189499Srnoland return radeon_do_resume_cp(dev, file_priv); 1789119098Sanholt} 1790119098Sanholt 1791182080Srnolandint radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) 179295584Sanholt{ 1793189499Srnoland drm_radeon_private_t *dev_priv = dev->dev_private; 1794145132Sanholt DRM_DEBUG("\n"); 179595584Sanholt 1796182080Srnoland LOCK_TEST_WITH_RETURN(dev, file_priv); 179795584Sanholt 1798189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1799189499Srnoland return r600_do_engine_reset(dev); 1800189499Srnoland else 1801189499Srnoland return radeon_do_engine_reset(dev); 180295584Sanholt} 180395584Sanholt 180495584Sanholt/* ================================================================ 180595584Sanholt * Fullscreen mode 180695584Sanholt */ 180795584Sanholt 1808112015Sanholt/* KW: Deprecated to say the least: 1809112015Sanholt */ 1810182080Srnolandint radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv) 181195584Sanholt{ 181295584Sanholt return 0; 181395584Sanholt} 181495584Sanholt 181595584Sanholt/* ================================================================ 181695584Sanholt * Freelist management 181795584Sanholt */ 181895584Sanholt 1819112015Sanholt/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through 1820112015Sanholt * bufs until freelist code is used. Note this hides a problem with 1821112015Sanholt * the scratch register * (used to keep track of last buffer 1822112015Sanholt * completed) being written to before * the last buffer has actually 1823145132Sanholt * completed rendering. 1824112015Sanholt * 1825112015Sanholt * KW: It's also a good way to find free buffers quickly. 1826112015Sanholt * 1827112015Sanholt * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't 1828112015Sanholt * sleep. However, bugs in older versions of radeon_accel.c mean that 1829112015Sanholt * we essentially have to do this, else old clients will break. 1830145132Sanholt * 1831112015Sanholt * However, it does leave open a potential deadlock where all the 1832112015Sanholt * buffers are held by other clients, which can't release them because 1833145132Sanholt * they can't get the lock. 1834112015Sanholt */ 1835112015Sanholt 1836182080Srnolandstruct drm_buf *radeon_freelist_get(struct drm_device * dev) 183795584Sanholt{ 1838182080Srnoland struct drm_device_dma *dma = dev->dma; 183995584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1840112015Sanholt drm_radeon_buf_priv_t *buf_priv; 1841182080Srnoland struct drm_buf *buf; 1842112015Sanholt int i, t; 1843112015Sanholt int start; 184495584Sanholt 1845145132Sanholt if (++dev_priv->last_buf >= dma->buf_count) 1846112015Sanholt dev_priv->last_buf = 0; 184795584Sanholt 1848112015Sanholt start = dev_priv->last_buf; 184995584Sanholt 1850145132Sanholt for (t = 0; t < dev_priv->usec_timeout; t++) { 1851189499Srnoland u32 done_age = GET_SCRATCH(dev_priv, 1); 1852145132Sanholt DRM_DEBUG("done_age = %d\n", done_age); 1853145132Sanholt for (i = start; i < dma->buf_count; i++) { 1854112015Sanholt buf = dma->buflist[i]; 1855112015Sanholt buf_priv = buf->dev_private; 1856182080Srnoland if (buf->file_priv == NULL || (buf->pending && 1857182080Srnoland buf_priv->age <= 1858182080Srnoland done_age)) { 1859112015Sanholt dev_priv->stats.requested_bufs++; 1860112015Sanholt buf->pending = 0; 1861112015Sanholt return buf; 1862112015Sanholt } 1863112015Sanholt start = 0; 1864112015Sanholt } 186595584Sanholt 1866112015Sanholt if (t) { 1867145132Sanholt DRM_UDELAY(1); 1868112015Sanholt dev_priv->stats.freelist_loops++; 1869112015Sanholt } 187095584Sanholt } 187195584Sanholt 1872145132Sanholt DRM_DEBUG("returning NULL!\n"); 1873112015Sanholt return NULL; 187495584Sanholt} 1875145132Sanholt 1876112015Sanholt#if 0 1877182080Srnolandstruct drm_buf *radeon_freelist_get(struct drm_device * dev) 187895584Sanholt{ 1879182080Srnoland struct drm_device_dma *dma = dev->dma; 188095584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 188195584Sanholt drm_radeon_buf_priv_t *buf_priv; 1882182080Srnoland struct drm_buf *buf; 188395584Sanholt int i, t; 188495584Sanholt int start; 1885189499Srnoland u32 done_age; 188695584Sanholt 1887189499Srnoland done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1)); 1888145132Sanholt if (++dev_priv->last_buf >= dma->buf_count) 188995584Sanholt dev_priv->last_buf = 0; 1890112015Sanholt 189195584Sanholt start = dev_priv->last_buf; 1892112015Sanholt dev_priv->stats.freelist_loops++; 1893145132Sanholt 1894145132Sanholt for (t = 0; t < 2; t++) { 1895145132Sanholt for (i = start; i < dma->buf_count; i++) { 189695584Sanholt buf = dma->buflist[i]; 189795584Sanholt buf_priv = buf->dev_private; 1898182080Srnoland if (buf->file_priv == 0 || (buf->pending && 1899182080Srnoland buf_priv->age <= 1900182080Srnoland done_age)) { 1901112015Sanholt dev_priv->stats.requested_bufs++; 190295584Sanholt buf->pending = 0; 190395584Sanholt return buf; 190495584Sanholt } 190595584Sanholt } 1906112015Sanholt start = 0; 190795584Sanholt } 190895584Sanholt 190995584Sanholt return NULL; 191095584Sanholt} 1911112015Sanholt#endif 191295584Sanholt 1913182080Srnolandvoid radeon_freelist_reset(struct drm_device * dev) 191495584Sanholt{ 1915182080Srnoland struct drm_device_dma *dma = dev->dma; 191695584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 191795584Sanholt int i; 191895584Sanholt 191995584Sanholt dev_priv->last_buf = 0; 1920145132Sanholt for (i = 0; i < dma->buf_count; i++) { 1921182080Srnoland struct drm_buf *buf = dma->buflist[i]; 192295584Sanholt drm_radeon_buf_priv_t *buf_priv = buf->dev_private; 192395584Sanholt buf_priv->age = 0; 192495584Sanholt } 192595584Sanholt} 192695584Sanholt 192795584Sanholt/* ================================================================ 192895584Sanholt * CP command submission 192995584Sanholt */ 193095584Sanholt 1931145132Sanholtint radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) 193295584Sanholt{ 193395584Sanholt drm_radeon_ring_buffer_t *ring = &dev_priv->ring; 193495584Sanholt int i; 1935145132Sanholt u32 last_head = GET_RING_HEAD(dev_priv); 193695584Sanholt 1937145132Sanholt for (i = 0; i < dev_priv->usec_timeout; i++) { 1938145132Sanholt u32 head = GET_RING_HEAD(dev_priv); 1939112015Sanholt 1940112015Sanholt ring->space = (head - ring->tail) * sizeof(u32); 1941145132Sanholt if (ring->space <= 0) 1942112015Sanholt ring->space += ring->size; 1943145132Sanholt if (ring->space > n) 194495584Sanholt return 0; 1945145132Sanholt 1946112015Sanholt dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 1947112015Sanholt 1948112015Sanholt if (head != last_head) 1949112015Sanholt i = 0; 1950112015Sanholt last_head = head; 1951112015Sanholt 1952145132Sanholt DRM_UDELAY(1); 195395584Sanholt } 195495584Sanholt 195595584Sanholt /* FIXME: This return value is ignored in the BEGIN_RING macro! */ 195695584Sanholt#if RADEON_FIFO_DEBUG 1957145132Sanholt radeon_status(dev_priv); 1958145132Sanholt DRM_ERROR("failed!\n"); 195995584Sanholt#endif 1960182080Srnoland return -EBUSY; 196195584Sanholt} 196295584Sanholt 1963182080Srnolandstatic int radeon_cp_get_buffers(struct drm_device *dev, 1964182080Srnoland struct drm_file *file_priv, 1965182080Srnoland struct drm_dma * d) 196695584Sanholt{ 196795584Sanholt int i; 1968182080Srnoland struct drm_buf *buf; 196995584Sanholt 1970145132Sanholt for (i = d->granted_count; i < d->request_count; i++) { 1971145132Sanholt buf = radeon_freelist_get(dev); 1972145132Sanholt if (!buf) 1973182080Srnoland return -EBUSY; /* NOTE: broken client */ 197495584Sanholt 1975182080Srnoland buf->file_priv = file_priv; 197695584Sanholt 1977145132Sanholt if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, 1978145132Sanholt sizeof(buf->idx))) 1979182080Srnoland return -EFAULT; 1980145132Sanholt if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, 1981145132Sanholt sizeof(buf->total))) 1982182080Srnoland return -EFAULT; 198395584Sanholt 198495584Sanholt d->granted_count++; 198595584Sanholt } 198695584Sanholt return 0; 198795584Sanholt} 198895584Sanholt 1989182080Srnolandint radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) 199095584Sanholt{ 1991182080Srnoland struct drm_device_dma *dma = dev->dma; 199295584Sanholt int ret = 0; 1993182080Srnoland struct drm_dma *d = data; 199495584Sanholt 1995182080Srnoland LOCK_TEST_WITH_RETURN(dev, file_priv); 199695584Sanholt 199795584Sanholt /* Please don't send us buffers. 199895584Sanholt */ 1999182080Srnoland if (d->send_count != 0) { 2000145132Sanholt DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", 2001182080Srnoland DRM_CURRENTPID, d->send_count); 2002182080Srnoland return -EINVAL; 200395584Sanholt } 200495584Sanholt 200595584Sanholt /* We'll send you buffers. 200695584Sanholt */ 2007182080Srnoland if (d->request_count < 0 || d->request_count > dma->buf_count) { 2008145132Sanholt DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", 2009182080Srnoland DRM_CURRENTPID, d->request_count, dma->buf_count); 2010182080Srnoland return -EINVAL; 201195584Sanholt } 201295584Sanholt 2013182080Srnoland d->granted_count = 0; 201495584Sanholt 2015182080Srnoland if (d->request_count) { 2016182080Srnoland ret = radeon_cp_get_buffers(dev, file_priv, d); 201795584Sanholt } 201895584Sanholt 201995584Sanholt return ret; 202095584Sanholt} 2021145132Sanholt 2022152909Sanholtint radeon_driver_load(struct drm_device *dev, unsigned long flags) 2023145132Sanholt{ 2024145132Sanholt drm_radeon_private_t *dev_priv; 2025145132Sanholt int ret = 0; 2026145132Sanholt 2027145132Sanholt dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); 2028145132Sanholt if (dev_priv == NULL) 2029182080Srnoland return -ENOMEM; 2030145132Sanholt 2031145132Sanholt memset(dev_priv, 0, sizeof(drm_radeon_private_t)); 2032145132Sanholt dev->dev_private = (void *)dev_priv; 2033145132Sanholt dev_priv->flags = flags; 2034145132Sanholt 2035182080Srnoland switch (flags & RADEON_FAMILY_MASK) { 2036145132Sanholt case CHIP_R100: 2037145132Sanholt case CHIP_RV200: 2038145132Sanholt case CHIP_R200: 2039145132Sanholt case CHIP_R300: 2040157617Sanholt case CHIP_R350: 2041148211Sanholt case CHIP_R420: 2042183830Srnoland case CHIP_R423: 2043157617Sanholt case CHIP_RV410: 2044182080Srnoland case CHIP_RV515: 2045182080Srnoland case CHIP_R520: 2046182080Srnoland case CHIP_RV570: 2047182080Srnoland case CHIP_R580: 2048182080Srnoland dev_priv->flags |= RADEON_HAS_HIERZ; 2049145132Sanholt break; 2050145132Sanholt default: 2051157617Sanholt /* all other chips have no hierarchical z buffer */ 2052145132Sanholt break; 2053145132Sanholt } 2054145132Sanholt 2055145132Sanholt if (drm_device_is_agp(dev)) 2056182080Srnoland dev_priv->flags |= RADEON_IS_AGP; 2057162132Sanholt else if (drm_device_is_pcie(dev)) 2058182080Srnoland dev_priv->flags |= RADEON_IS_PCIE; 2059162132Sanholt else 2060182080Srnoland dev_priv->flags |= RADEON_IS_PCI; 2061148211Sanholt 2062189499Srnoland ret = drm_addmap(dev, drm_get_resource_start(dev, 2), 2063189499Srnoland drm_get_resource_len(dev, 2), _DRM_REGISTERS, 2064189499Srnoland _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio); 2065189499Srnoland if (ret != 0) 2066189499Srnoland return ret; 2067189499Srnoland 2068189130Srnoland ret = drm_vblank_init(dev, 2); 2069189130Srnoland if (ret) { 2070189130Srnoland radeon_driver_unload(dev); 2071189130Srnoland return ret; 2072189130Srnoland } 2073189130Srnoland 2074145132Sanholt DRM_DEBUG("%s card detected\n", 2075182080Srnoland ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); 2076145132Sanholt return ret; 2077145132Sanholt} 2078145132Sanholt 2079152909Sanholt/* Create mappings for registers and framebuffer so userland doesn't necessarily 2080152909Sanholt * have to find them. 2081152909Sanholt */ 2082152909Sanholtint radeon_driver_firstopen(struct drm_device *dev) 2083145132Sanholt{ 2084152909Sanholt int ret; 2085152909Sanholt drm_local_map_t *map; 2086145132Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 2087145132Sanholt 2088182080Srnoland dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; 2089182080Srnoland 2090182080Srnoland dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); 2091182080Srnoland ret = drm_addmap(dev, dev_priv->fb_aper_offset, 2092152909Sanholt drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, 2093152909Sanholt _DRM_WRITE_COMBINING, &map); 2094152909Sanholt if (ret != 0) 2095152909Sanholt return ret; 2096152909Sanholt 2097152909Sanholt return 0; 2098152909Sanholt} 2099152909Sanholt 2100152909Sanholtint radeon_driver_unload(struct drm_device *dev) 2101152909Sanholt{ 2102152909Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 2103152909Sanholt 2104145132Sanholt DRM_DEBUG("\n"); 2105189499Srnoland 2106189499Srnoland drm_rmmap(dev, dev_priv->mmio); 2107189499Srnoland 2108145132Sanholt drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); 2109145132Sanholt 2110145132Sanholt dev->dev_private = NULL; 2111145132Sanholt return 0; 2112145132Sanholt} 2113189499Srnoland 2114189499Srnolandvoid radeon_commit_ring(drm_radeon_private_t *dev_priv) 2115189499Srnoland{ 2116189499Srnoland int i; 2117189499Srnoland u32 *ring; 2118189499Srnoland int tail_aligned; 2119189499Srnoland 2120189499Srnoland /* check if the ring is padded out to 16-dword alignment */ 2121189499Srnoland 2122189499Srnoland tail_aligned = dev_priv->ring.tail & 0xf; 2123189499Srnoland if (tail_aligned) { 2124189499Srnoland int num_p2 = 16 - tail_aligned; 2125189499Srnoland 2126189499Srnoland ring = dev_priv->ring.start; 2127189499Srnoland /* pad with some CP_PACKET2 */ 2128189499Srnoland for (i = 0; i < num_p2; i++) 2129189499Srnoland ring[dev_priv->ring.tail + i] = CP_PACKET2(); 2130189499Srnoland 2131189499Srnoland dev_priv->ring.tail += i; 2132189499Srnoland 2133189499Srnoland dev_priv->ring.space -= num_p2 * sizeof(u32); 2134189499Srnoland } 2135189499Srnoland 2136189499Srnoland dev_priv->ring.tail &= dev_priv->ring.tail_mask; 2137189499Srnoland 2138189499Srnoland DRM_MEMORYBARRIER(); 2139189499Srnoland GET_RING_HEAD( dev_priv ); 2140189499Srnoland 2141189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { 2142189499Srnoland RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail); 2143189499Srnoland /* read from PCI bus to ensure correct posting */ 2144189499Srnoland RADEON_READ(R600_CP_RB_RPTR); 2145189499Srnoland } else { 2146189499Srnoland RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail); 2147189499Srnoland /* read from PCI bus to ensure correct posting */ 2148189499Srnoland RADEON_READ(RADEON_CP_RB_RPTR); 2149189499Srnoland } 2150189499Srnoland} 2151