radeon_cp.c revision 189499
1139749Simp/*- 295584Sanholt * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 395584Sanholt * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 4182080Srnoland * Copyright 2007 Advanced Micro Devices, Inc. 595584Sanholt * All Rights Reserved. 695584Sanholt * 795584Sanholt * Permission is hereby granted, free of charge, to any person obtaining a 895584Sanholt * copy of this software and associated documentation files (the "Software"), 995584Sanholt * to deal in the Software without restriction, including without limitation 1095584Sanholt * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1195584Sanholt * and/or sell copies of the Software, and to permit persons to whom the 1295584Sanholt * Software is furnished to do so, subject to the following conditions: 1395584Sanholt * 1495584Sanholt * The above copyright notice and this permission notice (including the next 1595584Sanholt * paragraph) shall be included in all copies or substantial portions of the 1695584Sanholt * Software. 1795584Sanholt * 1895584Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1995584Sanholt * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2095584Sanholt * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2195584Sanholt * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 2295584Sanholt * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2395584Sanholt * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 2495584Sanholt * DEALINGS IN THE SOFTWARE. 2595584Sanholt * 2695584Sanholt * Authors: 2795584Sanholt * Kevin E. Martin <martin@valinux.com> 2895584Sanholt * Gareth Hughes <gareth@valinux.com> 2995584Sanholt */ 3095584Sanholt 31152909Sanholt#include <sys/cdefs.h> 32152909Sanholt__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_cp.c 189499 2009-03-07 21:36:57Z rnoland $"); 33152909Sanholt 3495584Sanholt#include "dev/drm/drmP.h" 35112015Sanholt#include "dev/drm/drm.h" 36189499Srnoland#include "dev/drm/drm_sarea.h" 3795746Sanholt#include "dev/drm/radeon_drm.h" 3895584Sanholt#include "dev/drm/radeon_drv.h" 39148211Sanholt#include "dev/drm/r300_reg.h" 4095584Sanholt 41182080Srnoland#include "dev/drm/radeon_microcode.h" 42189499Srnoland 4395584Sanholt#define RADEON_FIFO_DEBUG 0 4495584Sanholt 45182080Srnolandstatic int radeon_do_cleanup_cp(struct drm_device * dev); 46182080Srnolandstatic void radeon_do_cp_start(drm_radeon_private_t * dev_priv); 4795584Sanholt 48189499Srnolandu32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off) 49189499Srnoland{ 50189499Srnoland u32 val; 51189499Srnoland 52189499Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 53189499Srnoland val = DRM_READ32(dev_priv->ring_rptr, off); 54189499Srnoland } else { 55189499Srnoland val = *(((volatile u32 *) 56189499Srnoland dev_priv->ring_rptr->handle) + 57189499Srnoland (off / sizeof(u32))); 58189499Srnoland val = le32_to_cpu(val); 59189499Srnoland } 60189499Srnoland return val; 61189499Srnoland} 62189499Srnoland 63189499Srnolandu32 radeon_get_ring_head(drm_radeon_private_t *dev_priv) 64189499Srnoland{ 65189499Srnoland if (dev_priv->writeback_works) 66189499Srnoland return radeon_read_ring_rptr(dev_priv, 0); 67189499Srnoland else { 68189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 69189499Srnoland return RADEON_READ(R600_CP_RB_RPTR); 70189499Srnoland else 71189499Srnoland return RADEON_READ(RADEON_CP_RB_RPTR); 72189499Srnoland } 73189499Srnoland} 74189499Srnoland 75189499Srnolandvoid radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val) 76189499Srnoland{ 77189499Srnoland if (dev_priv->flags & RADEON_IS_AGP) 78189499Srnoland DRM_WRITE32(dev_priv->ring_rptr, off, val); 79189499Srnoland else 80189499Srnoland *(((volatile u32 *) dev_priv->ring_rptr->handle) + 81189499Srnoland (off / sizeof(u32))) = cpu_to_le32(val); 82189499Srnoland} 83189499Srnoland 84189499Srnolandvoid radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val) 85189499Srnoland{ 86189499Srnoland radeon_write_ring_rptr(dev_priv, 0, val); 87189499Srnoland} 88189499Srnoland 89189499Srnolandu32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index) 90189499Srnoland{ 91189499Srnoland if (dev_priv->writeback_works) { 92189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 93189499Srnoland return radeon_read_ring_rptr(dev_priv, 94189499Srnoland R600_SCRATCHOFF(index)); 95189499Srnoland else 96189499Srnoland return radeon_read_ring_rptr(dev_priv, 97189499Srnoland RADEON_SCRATCHOFF(index)); 98189499Srnoland } else { 99189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 100189499Srnoland return RADEON_READ(R600_SCRATCH_REG0 + 4*index); 101189499Srnoland else 102189499Srnoland return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index); 103189499Srnoland } 104189499Srnoland} 105189499Srnoland 106189499Srnolandu32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr) 107189499Srnoland{ 108189499Srnoland u32 ret; 109189499Srnoland 110189499Srnoland if (addr < 0x10000) 111189499Srnoland ret = DRM_READ32(dev_priv->mmio, addr); 112189499Srnoland else { 113189499Srnoland DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr); 114189499Srnoland ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA); 115189499Srnoland } 116189499Srnoland 117189499Srnoland return ret; 118189499Srnoland} 119189499Srnoland 120182080Srnolandstatic u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 121182080Srnoland{ 122182080Srnoland u32 ret; 123182080Srnoland RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); 124182080Srnoland ret = RADEON_READ(R520_MC_IND_DATA); 125182080Srnoland RADEON_WRITE(R520_MC_IND_INDEX, 0); 126182080Srnoland return ret; 127182080Srnoland} 128112015Sanholt 129182080Srnolandstatic u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 130182080Srnoland{ 131182080Srnoland u32 ret; 132182080Srnoland RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); 133182080Srnoland ret = RADEON_READ(RS480_NB_MC_DATA); 134182080Srnoland RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); 135182080Srnoland return ret; 136182080Srnoland} 137112015Sanholt 138182080Srnolandstatic u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 139182080Srnoland{ 140182080Srnoland u32 ret; 141182080Srnoland RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); 142182080Srnoland ret = RADEON_READ(RS690_MC_DATA); 143182080Srnoland RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK); 144182080Srnoland return ret; 145182080Srnoland} 14695584Sanholt 147189499Srnolandstatic u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 148189499Srnoland{ 149189499Srnoland u32 ret; 150189499Srnoland RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | 151189499Srnoland RS600_MC_IND_CITF_ARB0)); 152189499Srnoland ret = RADEON_READ(RS600_MC_DATA); 153189499Srnoland return ret; 154189499Srnoland} 155189499Srnoland 156182080Srnolandstatic u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 15795584Sanholt{ 158183828Srnoland if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 159183828Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 160189499Srnoland return RS690_READ_MCIND(dev_priv, addr); 161189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 162189499Srnoland return RS600_READ_MCIND(dev_priv, addr); 163182080Srnoland else 164189499Srnoland return RS480_READ_MCIND(dev_priv, addr); 165182080Srnoland} 166182080Srnoland 167182080Srnolandu32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) 168182080Srnoland{ 169182080Srnoland 170189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 171189499Srnoland return RADEON_READ(R700_MC_VM_FB_LOCATION); 172189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 173189499Srnoland return RADEON_READ(R600_MC_VM_FB_LOCATION); 174189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 175182080Srnoland return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); 176183828Srnoland else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 177183828Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 178182080Srnoland return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); 179189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 180189499Srnoland return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION); 181182080Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 182182080Srnoland return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); 183182080Srnoland else 184182080Srnoland return RADEON_READ(RADEON_MC_FB_LOCATION); 185182080Srnoland} 186182080Srnoland 187182080Srnolandstatic void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) 188182080Srnoland{ 189189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 190189499Srnoland RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc); 191189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 192189499Srnoland RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc); 193189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 194182080Srnoland R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); 195183828Srnoland else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 196183828Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 197182080Srnoland RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); 198189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 199189499Srnoland RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc); 200182080Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 201182080Srnoland R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); 202182080Srnoland else 203182080Srnoland RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); 204182080Srnoland} 205182080Srnoland 206189499Srnolandvoid radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) 207182080Srnoland{ 208189499Srnoland /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */ 209189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { 210189499Srnoland RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */ 211189499Srnoland RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff); 212189499Srnoland } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { 213189499Srnoland RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */ 214189499Srnoland RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff); 215189499Srnoland } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 216182080Srnoland R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); 217183828Srnoland else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 218183828Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 219182080Srnoland RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); 220189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 221189499Srnoland RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc); 222182080Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 223182080Srnoland R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); 224182080Srnoland else 225182080Srnoland RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); 226182080Srnoland} 227182080Srnoland 228189499Srnolandvoid radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) 229182080Srnoland{ 230182080Srnoland u32 agp_base_hi = upper_32_bits(agp_base); 231182080Srnoland u32 agp_base_lo = agp_base & 0xffffffff; 232189499Srnoland u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff; 233182080Srnoland 234189499Srnoland /* R6xx/R7xx must be aligned to a 4MB boundry */ 235189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 236189499Srnoland RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base); 237189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 238189499Srnoland RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base); 239189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) { 240182080Srnoland R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo); 241182080Srnoland R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi); 242183828Srnoland } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 243189499Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 244182080Srnoland RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo); 245182080Srnoland RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi); 246189499Srnoland } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { 247189499Srnoland RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo); 248189499Srnoland RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi); 249182080Srnoland } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { 250182080Srnoland R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); 251182080Srnoland R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); 252182080Srnoland } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || 253182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { 254182080Srnoland RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); 255182080Srnoland RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi); 256182080Srnoland } else { 257182080Srnoland RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); 258182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) 259182080Srnoland RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi); 260182080Srnoland } 261182080Srnoland} 262182080Srnoland 263189499Srnolandvoid radeon_enable_bm(struct drm_radeon_private *dev_priv) 264189499Srnoland{ 265189499Srnoland u32 tmp; 266189499Srnoland /* Turn on bus mastering */ 267189499Srnoland if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 268189499Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 269189499Srnoland /* rs600/rs690/rs740 */ 270189499Srnoland tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 271189499Srnoland RADEON_WRITE(RADEON_BUS_CNTL, tmp); 272189499Srnoland } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) || 273189499Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || 274189499Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || 275189499Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { 276189499Srnoland /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 277189499Srnoland tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 278189499Srnoland RADEON_WRITE(RADEON_BUS_CNTL, tmp); 279189499Srnoland } /* PCIE cards appears to not need this */ 280189499Srnoland} 281189499Srnoland 282182080Srnolandstatic int RADEON_READ_PLL(struct drm_device * dev, int addr) 283182080Srnoland{ 28495584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 28595584Sanholt 28695584Sanholt RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); 28795584Sanholt return RADEON_READ(RADEON_CLOCK_CNTL_DATA); 28895584Sanholt} 28995584Sanholt 290182080Srnolandstatic u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) 291148211Sanholt{ 292148211Sanholt RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); 293148211Sanholt return RADEON_READ(RADEON_PCIE_DATA); 294148211Sanholt} 295148211Sanholt 29695584Sanholt#if RADEON_FIFO_DEBUG 297145132Sanholtstatic void radeon_status(drm_radeon_private_t * dev_priv) 29895584Sanholt{ 299189499Srnoland printk("%s:\n", __func__); 300145132Sanholt printk("RBBM_STATUS = 0x%08x\n", 301145132Sanholt (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); 302145132Sanholt printk("CP_RB_RTPR = 0x%08x\n", 303145132Sanholt (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); 304145132Sanholt printk("CP_RB_WTPR = 0x%08x\n", 305145132Sanholt (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); 306145132Sanholt printk("AIC_CNTL = 0x%08x\n", 307145132Sanholt (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); 308145132Sanholt printk("AIC_STAT = 0x%08x\n", 309145132Sanholt (unsigned int)RADEON_READ(RADEON_AIC_STAT)); 310145132Sanholt printk("AIC_PT_BASE = 0x%08x\n", 311145132Sanholt (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); 312145132Sanholt printk("TLB_ADDR = 0x%08x\n", 313145132Sanholt (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); 314145132Sanholt printk("TLB_DATA = 0x%08x\n", 315145132Sanholt (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); 31695584Sanholt} 31795584Sanholt#endif 31895584Sanholt 31995584Sanholt/* ================================================================ 32095584Sanholt * Engine, FIFO control 32195584Sanholt */ 32295584Sanholt 323145132Sanholtstatic int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) 32495584Sanholt{ 32595584Sanholt u32 tmp; 32695584Sanholt int i; 32795584Sanholt 328112015Sanholt dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 329112015Sanholt 330182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { 331182080Srnoland tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); 332182080Srnoland tmp |= RADEON_RB3D_DC_FLUSH_ALL; 333182080Srnoland RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); 33495584Sanholt 335182080Srnoland for (i = 0; i < dev_priv->usec_timeout; i++) { 336182080Srnoland if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) 337182080Srnoland & RADEON_RB3D_DC_BUSY)) { 338182080Srnoland return 0; 339182080Srnoland } 340182080Srnoland DRM_UDELAY(1); 34195584Sanholt } 342182080Srnoland } else { 343182080Srnoland /* don't flush or purge cache here or lockup */ 344182080Srnoland return 0; 34595584Sanholt } 34695584Sanholt 34795584Sanholt#if RADEON_FIFO_DEBUG 348145132Sanholt DRM_ERROR("failed!\n"); 349145132Sanholt radeon_status(dev_priv); 35095584Sanholt#endif 351182080Srnoland return -EBUSY; 35295584Sanholt} 35395584Sanholt 354145132Sanholtstatic int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) 35595584Sanholt{ 35695584Sanholt int i; 35795584Sanholt 358112015Sanholt dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 359112015Sanholt 360145132Sanholt for (i = 0; i < dev_priv->usec_timeout; i++) { 361145132Sanholt int slots = (RADEON_READ(RADEON_RBBM_STATUS) 362145132Sanholt & RADEON_RBBM_FIFOCNT_MASK); 363145132Sanholt if (slots >= entries) 364145132Sanholt return 0; 365145132Sanholt DRM_UDELAY(1); 36695584Sanholt } 367189499Srnoland DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n", 368182080Srnoland RADEON_READ(RADEON_RBBM_STATUS), 369182080Srnoland RADEON_READ(R300_VAP_CNTL_STATUS)); 37095584Sanholt 37195584Sanholt#if RADEON_FIFO_DEBUG 372145132Sanholt DRM_ERROR("failed!\n"); 373145132Sanholt radeon_status(dev_priv); 37495584Sanholt#endif 375182080Srnoland return -EBUSY; 37695584Sanholt} 37795584Sanholt 378145132Sanholtstatic int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) 37995584Sanholt{ 38095584Sanholt int i, ret; 38195584Sanholt 382112015Sanholt dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 383112015Sanholt 384145132Sanholt ret = radeon_do_wait_for_fifo(dev_priv, 64); 385145132Sanholt if (ret) 386145132Sanholt return ret; 387112015Sanholt 388145132Sanholt for (i = 0; i < dev_priv->usec_timeout; i++) { 389145132Sanholt if (!(RADEON_READ(RADEON_RBBM_STATUS) 390145132Sanholt & RADEON_RBBM_ACTIVE)) { 391145132Sanholt radeon_do_pixcache_flush(dev_priv); 39295584Sanholt return 0; 39395584Sanholt } 394145132Sanholt DRM_UDELAY(1); 39595584Sanholt } 396189499Srnoland DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n", 397182080Srnoland RADEON_READ(RADEON_RBBM_STATUS), 398182080Srnoland RADEON_READ(R300_VAP_CNTL_STATUS)); 39995584Sanholt 40095584Sanholt#if RADEON_FIFO_DEBUG 401145132Sanholt DRM_ERROR("failed!\n"); 402145132Sanholt radeon_status(dev_priv); 40395584Sanholt#endif 404182080Srnoland return -EBUSY; 40595584Sanholt} 40695584Sanholt 407189499Srnolandstatic void radeon_init_pipes(drm_radeon_private_t *dev_priv) 408182080Srnoland{ 409182080Srnoland uint32_t gb_tile_config, gb_pipe_sel = 0; 410182080Srnoland 411182080Srnoland /* RS4xx/RS6xx/R4xx/R5xx */ 412182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { 413182080Srnoland gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); 414182080Srnoland dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; 415182080Srnoland } else { 416182080Srnoland /* R3xx */ 417182080Srnoland if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || 418182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { 419182080Srnoland dev_priv->num_gb_pipes = 2; 420182080Srnoland } else { 421182080Srnoland /* R3Vxx */ 422182080Srnoland dev_priv->num_gb_pipes = 1; 423182080Srnoland } 424182080Srnoland } 425182080Srnoland DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes); 426182080Srnoland 427182080Srnoland gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/); 428182080Srnoland 429189499Srnoland switch (dev_priv->num_gb_pipes) { 430182080Srnoland case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; 431182080Srnoland case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; 432182080Srnoland case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; 433182080Srnoland default: 434182080Srnoland case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; 435182080Srnoland } 436182080Srnoland 437182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { 438182080Srnoland RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); 439182080Srnoland RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); 440182080Srnoland } 441182080Srnoland RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); 442182080Srnoland radeon_do_wait_for_idle(dev_priv); 443182080Srnoland RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); 444182080Srnoland RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) | 445182080Srnoland R300_DC_AUTOFLUSH_ENABLE | 446182080Srnoland R300_DC_DC_DISABLE_IGNORE_PE)); 447182080Srnoland 448182080Srnoland 449182080Srnoland} 450182080Srnoland 45195584Sanholt/* ================================================================ 45295584Sanholt * CP control, initialization 45395584Sanholt */ 45495584Sanholt 45595584Sanholt/* Load the microcode for the CP */ 456145132Sanholtstatic void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) 45795584Sanholt{ 45895584Sanholt int i; 459145132Sanholt DRM_DEBUG("\n"); 46095584Sanholt 461145132Sanholt radeon_do_wait_for_idle(dev_priv); 46295584Sanholt 463145132Sanholt RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); 464182080Srnoland if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || 465182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || 466182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || 467182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || 468182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { 469182080Srnoland DRM_INFO("Loading R100 Microcode\n"); 470182080Srnoland for (i = 0; i < 256; i++) { 471182080Srnoland RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 472182080Srnoland R100_cp_microcode[i][1]); 473182080Srnoland RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 474182080Srnoland R100_cp_microcode[i][0]); 475182080Srnoland } 476182080Srnoland } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || 477182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || 478182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || 479182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { 480112015Sanholt DRM_INFO("Loading R200 Microcode\n"); 481145132Sanholt for (i = 0; i < 256; i++) { 482145132Sanholt RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 483145132Sanholt R200_cp_microcode[i][1]); 484145132Sanholt RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 485145132Sanholt R200_cp_microcode[i][0]); 486112015Sanholt } 487182080Srnoland } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || 488182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || 489182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || 490182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || 491182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || 492182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { 493145132Sanholt DRM_INFO("Loading R300 Microcode\n"); 494157617Sanholt for (i = 0; i < 256; i++) { 495157617Sanholt RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 496157617Sanholt R300_cp_microcode[i][1]); 497157617Sanholt RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 498157617Sanholt R300_cp_microcode[i][0]); 499112015Sanholt } 500182080Srnoland } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || 501183830Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) || 502182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { 503182080Srnoland DRM_INFO("Loading R400 Microcode\n"); 504145132Sanholt for (i = 0; i < 256; i++) { 505145132Sanholt RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 506182080Srnoland R420_cp_microcode[i][1]); 507145132Sanholt RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 508182080Srnoland R420_cp_microcode[i][0]); 509145132Sanholt } 510183828Srnoland } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 511183828Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 512183828Srnoland DRM_INFO("Loading RS690/RS740 Microcode\n"); 513182080Srnoland for (i = 0; i < 256; i++) { 514182080Srnoland RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 515182080Srnoland RS690_cp_microcode[i][1]); 516182080Srnoland RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 517182080Srnoland RS690_cp_microcode[i][0]); 518182080Srnoland } 519189499Srnoland } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { 520189499Srnoland DRM_INFO("Loading RS600 Microcode\n"); 521189499Srnoland for (i = 0; i < 256; i++) { 522189499Srnoland RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 523189499Srnoland RS600_cp_microcode[i][1]); 524189499Srnoland RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 525189499Srnoland RS600_cp_microcode[i][0]); 526189499Srnoland } 527182080Srnoland } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || 528182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || 529182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || 530182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) || 531182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || 532182080Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { 533182080Srnoland DRM_INFO("Loading R500 Microcode\n"); 534182080Srnoland for (i = 0; i < 256; i++) { 535182080Srnoland RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 536182080Srnoland R520_cp_microcode[i][1]); 537182080Srnoland RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 538182080Srnoland R520_cp_microcode[i][0]); 539182080Srnoland } 540112015Sanholt } 54195584Sanholt} 54295584Sanholt 54395584Sanholt/* Flush any pending commands to the CP. This should only be used just 54495584Sanholt * prior to a wait for idle, as it informs the engine that the command 54595584Sanholt * stream is ending. 54695584Sanholt */ 547145132Sanholtstatic void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) 54895584Sanholt{ 549145132Sanholt DRM_DEBUG("\n"); 55095584Sanholt#if 0 55195584Sanholt u32 tmp; 55295584Sanholt 553145132Sanholt tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); 554145132Sanholt RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); 55595584Sanholt#endif 55695584Sanholt} 55795584Sanholt 55895584Sanholt/* Wait for the CP to go idle. 55995584Sanholt */ 560145132Sanholtint radeon_do_cp_idle(drm_radeon_private_t * dev_priv) 56195584Sanholt{ 56295584Sanholt RING_LOCALS; 563145132Sanholt DRM_DEBUG("\n"); 56495584Sanholt 565145132Sanholt BEGIN_RING(6); 56695584Sanholt 56795584Sanholt RADEON_PURGE_CACHE(); 56895584Sanholt RADEON_PURGE_ZCACHE(); 56995584Sanholt RADEON_WAIT_UNTIL_IDLE(); 57095584Sanholt 57195584Sanholt ADVANCE_RING(); 572112015Sanholt COMMIT_RING(); 57395584Sanholt 574145132Sanholt return radeon_do_wait_for_idle(dev_priv); 57595584Sanholt} 57695584Sanholt 57795584Sanholt/* Start the Command Processor. 57895584Sanholt */ 579145132Sanholtstatic void radeon_do_cp_start(drm_radeon_private_t * dev_priv) 58095584Sanholt{ 58195584Sanholt RING_LOCALS; 582145132Sanholt DRM_DEBUG("\n"); 58395584Sanholt 584145132Sanholt radeon_do_wait_for_idle(dev_priv); 58595584Sanholt 586145132Sanholt RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); 58795584Sanholt 58895584Sanholt dev_priv->cp_running = 1; 58995584Sanholt 590182080Srnoland BEGIN_RING(8); 591182080Srnoland /* isync can only be written through cp on r5xx write it here */ 592182080Srnoland OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); 593182080Srnoland OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | 594182080Srnoland RADEON_ISYNC_ANY3D_IDLE2D | 595182080Srnoland RADEON_ISYNC_WAIT_IDLEGUI | 596182080Srnoland RADEON_ISYNC_CPSCRATCH_IDLEGUI); 59795584Sanholt RADEON_PURGE_CACHE(); 59895584Sanholt RADEON_PURGE_ZCACHE(); 59995584Sanholt RADEON_WAIT_UNTIL_IDLE(); 60095584Sanholt ADVANCE_RING(); 601112015Sanholt COMMIT_RING(); 602182080Srnoland 603182080Srnoland dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED; 60495584Sanholt} 60595584Sanholt 60695584Sanholt/* Reset the Command Processor. This will not flush any pending 60795584Sanholt * commands, so you must wait for the CP command stream to complete 60895584Sanholt * before calling this routine. 60995584Sanholt */ 610145132Sanholtstatic void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) 61195584Sanholt{ 61295584Sanholt u32 cur_read_ptr; 613145132Sanholt DRM_DEBUG("\n"); 61495584Sanholt 615145132Sanholt cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); 616145132Sanholt RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); 617145132Sanholt SET_RING_HEAD(dev_priv, cur_read_ptr); 61895584Sanholt dev_priv->ring.tail = cur_read_ptr; 61995584Sanholt} 62095584Sanholt 62195584Sanholt/* Stop the Command Processor. This will not flush any pending 62295584Sanholt * commands, so you must flush the command stream and wait for the CP 62395584Sanholt * to go idle before calling this routine. 62495584Sanholt */ 625145132Sanholtstatic void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) 62695584Sanholt{ 627145132Sanholt DRM_DEBUG("\n"); 62895584Sanholt 629145132Sanholt RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); 63095584Sanholt 63195584Sanholt dev_priv->cp_running = 0; 63295584Sanholt} 63395584Sanholt 63495584Sanholt/* Reset the engine. This will stop the CP if it is running. 63595584Sanholt */ 636182080Srnolandstatic int radeon_do_engine_reset(struct drm_device * dev) 63795584Sanholt{ 63895584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 639182080Srnoland u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset; 640145132Sanholt DRM_DEBUG("\n"); 64195584Sanholt 642145132Sanholt radeon_do_pixcache_flush(dev_priv); 64395584Sanholt 644182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { 645189499Srnoland /* may need something similar for newer chips */ 646182080Srnoland clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); 647182080Srnoland mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); 64895584Sanholt 649182080Srnoland RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | 650182080Srnoland RADEON_FORCEON_MCLKA | 651182080Srnoland RADEON_FORCEON_MCLKB | 652182080Srnoland RADEON_FORCEON_YCLKA | 653182080Srnoland RADEON_FORCEON_YCLKB | 654182080Srnoland RADEON_FORCEON_MC | 655182080Srnoland RADEON_FORCEON_AIC)); 656182080Srnoland } 65795584Sanholt 658145132Sanholt rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); 65995584Sanholt 660145132Sanholt RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | 661145132Sanholt RADEON_SOFT_RESET_CP | 662145132Sanholt RADEON_SOFT_RESET_HI | 663145132Sanholt RADEON_SOFT_RESET_SE | 664145132Sanholt RADEON_SOFT_RESET_RE | 665145132Sanholt RADEON_SOFT_RESET_PP | 666145132Sanholt RADEON_SOFT_RESET_E2 | 667145132Sanholt RADEON_SOFT_RESET_RB)); 668145132Sanholt RADEON_READ(RADEON_RBBM_SOFT_RESET); 669145132Sanholt RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & 670145132Sanholt ~(RADEON_SOFT_RESET_CP | 67195584Sanholt RADEON_SOFT_RESET_HI | 67295584Sanholt RADEON_SOFT_RESET_SE | 67395584Sanholt RADEON_SOFT_RESET_RE | 67495584Sanholt RADEON_SOFT_RESET_PP | 67595584Sanholt RADEON_SOFT_RESET_E2 | 676145132Sanholt RADEON_SOFT_RESET_RB))); 677145132Sanholt RADEON_READ(RADEON_RBBM_SOFT_RESET); 67895584Sanholt 679182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { 680182080Srnoland RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); 681182080Srnoland RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); 682182080Srnoland RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); 683182080Srnoland } 68495584Sanholt 685182080Srnoland /* setup the raster pipes */ 686182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) 687182080Srnoland radeon_init_pipes(dev_priv); 688182080Srnoland 68995584Sanholt /* Reset the CP ring */ 690145132Sanholt radeon_do_cp_reset(dev_priv); 69195584Sanholt 69295584Sanholt /* The CP is no longer running after an engine reset */ 69395584Sanholt dev_priv->cp_running = 0; 69495584Sanholt 69595584Sanholt /* Reset any pending vertex, indirect buffers */ 696145132Sanholt radeon_freelist_reset(dev); 69795584Sanholt 69895584Sanholt return 0; 69995584Sanholt} 70095584Sanholt 701182080Srnolandstatic void radeon_cp_init_ring_buffer(struct drm_device * dev, 702189499Srnoland drm_radeon_private_t *dev_priv, 703189499Srnoland struct drm_file *file_priv) 70495584Sanholt{ 70595584Sanholt u32 ring_start, cur_read_ptr; 706182080Srnoland 707157617Sanholt /* Initialize the memory controller. With new memory map, the fb location 708157617Sanholt * is not changed, it should have been properly initialized already. Part 709157617Sanholt * of the problem is that the code below is bogus, assuming the GART is 710157617Sanholt * always appended to the fb which is not necessarily the case 711157617Sanholt */ 712157617Sanholt if (!dev_priv->new_memmap) 713182080Srnoland radeon_write_fb_location(dev_priv, 714157617Sanholt ((dev_priv->gart_vm_start - 1) & 0xffff0000) 715157617Sanholt | (dev_priv->fb_location >> 16)); 71695584Sanholt 717145132Sanholt#if __OS_HAS_AGP 718182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 719182080Srnoland radeon_write_agp_base(dev_priv, dev->agp->base); 720182080Srnoland 721182080Srnoland radeon_write_agp_location(dev_priv, 722145132Sanholt (((dev_priv->gart_vm_start - 1 + 723145132Sanholt dev_priv->gart_size) & 0xffff0000) | 724145132Sanholt (dev_priv->gart_vm_start >> 16))); 72595584Sanholt 72695584Sanholt ring_start = (dev_priv->cp_ring->offset 727157617Sanholt - dev->agp->base 728157617Sanholt + dev_priv->gart_vm_start); 729145132Sanholt } else 73095584Sanholt#endif 73195584Sanholt ring_start = (dev_priv->cp_ring->offset 732157617Sanholt - (unsigned long)dev->sg->virtual 733157617Sanholt + dev_priv->gart_vm_start); 73495584Sanholt 735145132Sanholt RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); 73695584Sanholt 73795584Sanholt /* Set the write pointer delay */ 738145132Sanholt RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); 73995584Sanholt 74095584Sanholt /* Initialize the ring buffer's read and write pointers */ 741145132Sanholt cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); 742145132Sanholt RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); 743145132Sanholt SET_RING_HEAD(dev_priv, cur_read_ptr); 74495584Sanholt dev_priv->ring.tail = cur_read_ptr; 74595584Sanholt 746145132Sanholt#if __OS_HAS_AGP 747182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 748145132Sanholt RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, 749145132Sanholt dev_priv->ring_rptr->offset 750145132Sanholt - dev->agp->base + dev_priv->gart_vm_start); 751113995Sanholt } else 752113995Sanholt#endif 753113995Sanholt { 754189499Srnoland RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, 755189499Srnoland dev_priv->ring_rptr->offset 756189499Srnoland - ((unsigned long) dev->sg->virtual) 757189499Srnoland + dev_priv->gart_vm_start); 75895584Sanholt } 75995584Sanholt 760157617Sanholt /* Set ring buffer size */ 761157617Sanholt#ifdef __BIG_ENDIAN 762157617Sanholt RADEON_WRITE(RADEON_CP_RB_CNTL, 763182080Srnoland RADEON_BUF_SWAP_32BIT | 764182080Srnoland (dev_priv->ring.fetch_size_l2ow << 18) | 765182080Srnoland (dev_priv->ring.rptr_update_l2qw << 8) | 766182080Srnoland dev_priv->ring.size_l2qw); 767157617Sanholt#else 768182080Srnoland RADEON_WRITE(RADEON_CP_RB_CNTL, 769182080Srnoland (dev_priv->ring.fetch_size_l2ow << 18) | 770182080Srnoland (dev_priv->ring.rptr_update_l2qw << 8) | 771182080Srnoland dev_priv->ring.size_l2qw); 772157617Sanholt#endif 773157617Sanholt 774189499Srnoland 775112015Sanholt /* Initialize the scratch register pointer. This will cause 776112015Sanholt * the scratch register values to be written out to memory 777112015Sanholt * whenever they are updated. 778112015Sanholt * 779112015Sanholt * We simply put this behind the ring read pointer, this works 780112015Sanholt * with PCI GART as well as (whatever kind of) AGP GART 781112015Sanholt */ 782145132Sanholt RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) 783145132Sanholt + RADEON_SCRATCH_REG_OFFSET); 784112015Sanholt 785145132Sanholt RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); 786112015Sanholt 787189499Srnoland radeon_enable_bm(dev_priv); 788112015Sanholt 789189499Srnoland radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0); 790189499Srnoland RADEON_WRITE(RADEON_LAST_FRAME_REG, 0); 791112015Sanholt 792189499Srnoland radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0); 793189499Srnoland RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0); 794112015Sanholt 795189499Srnoland radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0); 796189499Srnoland RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0); 797112015Sanholt 798189499Srnoland /* reset sarea copies of these */ 799189499Srnoland if (dev_priv->sarea_priv) { 800189499Srnoland dev_priv->sarea_priv->last_frame = 0; 801189499Srnoland dev_priv->sarea_priv->last_dispatch = 0; 802189499Srnoland dev_priv->sarea_priv->last_clear = 0; 803189499Srnoland } 804189499Srnoland 805145132Sanholt radeon_do_wait_for_idle(dev_priv); 80695584Sanholt 80795584Sanholt /* Sync everything up */ 808145132Sanholt RADEON_WRITE(RADEON_ISYNC_CNTL, 809145132Sanholt (RADEON_ISYNC_ANY2D_IDLE3D | 810145132Sanholt RADEON_ISYNC_ANY3D_IDLE2D | 811145132Sanholt RADEON_ISYNC_WAIT_IDLEGUI | 812145132Sanholt RADEON_ISYNC_CPSCRATCH_IDLEGUI)); 813157617Sanholt 81495584Sanholt} 81595584Sanholt 816157617Sanholtstatic void radeon_test_writeback(drm_radeon_private_t * dev_priv) 817157617Sanholt{ 818157617Sanholt u32 tmp; 819157617Sanholt 820189499Srnoland /* Start with assuming that writeback doesn't work */ 821189499Srnoland dev_priv->writeback_works = 0; 822189499Srnoland 823157617Sanholt /* Writeback doesn't seem to work everywhere, test it here and possibly 824157617Sanholt * enable it if it appears to work 825157617Sanholt */ 826189499Srnoland radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0); 827189499Srnoland 828157617Sanholt RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); 829157617Sanholt 830157617Sanholt for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 831189499Srnoland u32 val; 832189499Srnoland 833189499Srnoland val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1)); 834189499Srnoland if (val == 0xdeadbeef) 835157617Sanholt break; 836157617Sanholt DRM_UDELAY(1); 837157617Sanholt } 838157617Sanholt 839157617Sanholt if (tmp < dev_priv->usec_timeout) { 840157617Sanholt dev_priv->writeback_works = 1; 841157617Sanholt DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 842157617Sanholt } else { 843157617Sanholt dev_priv->writeback_works = 0; 844157617Sanholt DRM_INFO("writeback test failed\n"); 845157617Sanholt } 846157617Sanholt if (radeon_no_wb == 1) { 847157617Sanholt dev_priv->writeback_works = 0; 848157617Sanholt DRM_INFO("writeback forced off\n"); 849157617Sanholt } 850162132Sanholt 851162132Sanholt if (!dev_priv->writeback_works) { 852189499Srnoland /* Disable writeback to avoid unnecessary bus master transfer */ 853189499Srnoland RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | 854189499Srnoland RADEON_RB_NO_UPDATE); 855162132Sanholt RADEON_WRITE(RADEON_SCRATCH_UMSK, 0); 856162132Sanholt } 857157617Sanholt} 858157617Sanholt 859182080Srnoland/* Enable or disable IGP GART on the chip */ 860182080Srnolandstatic void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) 861182080Srnoland{ 862182080Srnoland u32 temp; 863182080Srnoland 864182080Srnoland if (on) { 865182080Srnoland DRM_DEBUG("programming igp gart %08X %08lX %08X\n", 866189499Srnoland dev_priv->gart_vm_start, 867189499Srnoland (long)dev_priv->gart_info.bus_addr, 868189499Srnoland dev_priv->gart_size); 869182080Srnoland 870182080Srnoland temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); 871183828Srnoland if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 872183828Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 873182080Srnoland IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | 874182080Srnoland RS690_BLOCK_GFX_D3_EN)); 875182080Srnoland else 876182080Srnoland IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); 877182080Srnoland 878182080Srnoland IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | 879182080Srnoland RS480_VA_SIZE_32MB)); 880182080Srnoland 881182080Srnoland temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); 882182080Srnoland IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN | 883182080Srnoland RS480_TLB_ENABLE | 884182080Srnoland RS480_GTW_LAC_EN | 885182080Srnoland RS480_1LEVEL_GART)); 886182080Srnoland 887182080Srnoland temp = dev_priv->gart_info.bus_addr & 0xfffff000; 888182080Srnoland temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; 889182080Srnoland IGP_WRITE_MCIND(RS480_GART_BASE, temp); 890182080Srnoland 891182080Srnoland temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); 892182080Srnoland IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | 893182080Srnoland RS480_REQ_TYPE_SNOOP_DIS)); 894182080Srnoland 895182080Srnoland radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start); 896182080Srnoland 897182080Srnoland dev_priv->gart_size = 32*1024*1024; 898189499Srnoland temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & 899189499Srnoland 0xffff0000) | (dev_priv->gart_vm_start >> 16)); 900182080Srnoland 901182080Srnoland radeon_write_agp_location(dev_priv, temp); 902182080Srnoland 903182080Srnoland temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); 904182080Srnoland IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | 905182080Srnoland RS480_VA_SIZE_32MB)); 906182080Srnoland 907182080Srnoland do { 908182080Srnoland temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 909182080Srnoland if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) 910182080Srnoland break; 911182080Srnoland DRM_UDELAY(1); 912189499Srnoland } while (1); 913182080Srnoland 914182080Srnoland IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 915182080Srnoland RS480_GART_CACHE_INVALIDATE); 916182080Srnoland 917182080Srnoland do { 918182080Srnoland temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 919182080Srnoland if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) 920182080Srnoland break; 921182080Srnoland DRM_UDELAY(1); 922189499Srnoland } while (1); 923182080Srnoland 924182080Srnoland IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); 925182080Srnoland } else { 926182080Srnoland IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 927182080Srnoland } 928182080Srnoland} 929182080Srnoland 930189499Srnoland/* Enable or disable IGP GART on the chip */ 931189499Srnolandstatic void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on) 932189499Srnoland{ 933189499Srnoland u32 temp; 934189499Srnoland int i; 935189499Srnoland 936189499Srnoland if (on) { 937189499Srnoland DRM_DEBUG("programming igp gart %08X %08lX %08X\n", 938189499Srnoland dev_priv->gart_vm_start, 939189499Srnoland (long)dev_priv->gart_info.bus_addr, 940189499Srnoland dev_priv->gart_size); 941189499Srnoland 942189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) | 943189499Srnoland RS600_EFFECTIVE_L2_QUEUE_SIZE(6))); 944189499Srnoland 945189499Srnoland for (i = 0; i < 19; i++) 946189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i, 947189499Srnoland (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE | 948189499Srnoland RS600_SYSTEM_ACCESS_MODE_IN_SYS | 949189499Srnoland RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH | 950189499Srnoland RS600_EFFECTIVE_L1_CACHE_SIZE(3) | 951189499Srnoland RS600_ENABLE_FRAGMENT_PROCESSING | 952189499Srnoland RS600_EFFECTIVE_L1_QUEUE_SIZE(3))); 953189499Srnoland 954189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE | 955189499Srnoland RS600_PAGE_TABLE_TYPE_FLAT)); 956189499Srnoland 957189499Srnoland /* disable all other contexts */ 958189499Srnoland for (i = 1; i < 8; i++) 959189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0); 960189499Srnoland 961189499Srnoland /* setup the page table aperture */ 962189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 963189499Srnoland dev_priv->gart_info.bus_addr); 964189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR, 965189499Srnoland dev_priv->gart_vm_start); 966189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR, 967189499Srnoland (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); 968189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 969189499Srnoland 970189499Srnoland /* setup the system aperture */ 971189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, 972189499Srnoland dev_priv->gart_vm_start); 973189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, 974189499Srnoland (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); 975189499Srnoland 976189499Srnoland /* enable page tables */ 977189499Srnoland temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 978189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT)); 979189499Srnoland 980189499Srnoland temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1); 981189499Srnoland IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES)); 982189499Srnoland 983189499Srnoland /* invalidate the cache */ 984189499Srnoland temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 985189499Srnoland 986189499Srnoland temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); 987189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp); 988189499Srnoland temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 989189499Srnoland 990189499Srnoland temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE; 991189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp); 992189499Srnoland temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 993189499Srnoland 994189499Srnoland temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); 995189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp); 996189499Srnoland temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 997189499Srnoland 998189499Srnoland } else { 999189499Srnoland IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0); 1000189499Srnoland temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1); 1001189499Srnoland temp &= ~RS600_ENABLE_PAGE_TABLES; 1002189499Srnoland IGP_WRITE_MCIND(RS600_MC_CNTL1, temp); 1003189499Srnoland } 1004189499Srnoland} 1005189499Srnoland 1006148211Sanholtstatic void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) 1007148211Sanholt{ 1008148211Sanholt u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); 1009148211Sanholt if (on) { 1010148211Sanholt 1011152909Sanholt DRM_DEBUG("programming pcie %08X %08lX %08X\n", 1012157617Sanholt dev_priv->gart_vm_start, 1013157617Sanholt (long)dev_priv->gart_info.bus_addr, 1014152909Sanholt dev_priv->gart_size); 1015157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, 1016157617Sanholt dev_priv->gart_vm_start); 1017157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, 1018157617Sanholt dev_priv->gart_info.bus_addr); 1019157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, 1020157617Sanholt dev_priv->gart_vm_start); 1021157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, 1022157617Sanholt dev_priv->gart_vm_start + 1023157617Sanholt dev_priv->gart_size - 1); 1024148211Sanholt 1025182080Srnoland radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ 1026148211Sanholt 1027157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, 1028157617Sanholt RADEON_PCIE_TX_GART_EN); 1029148211Sanholt } else { 1030157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, 1031157617Sanholt tmp & ~RADEON_PCIE_TX_GART_EN); 1032148211Sanholt } 1033148211Sanholt} 1034148211Sanholt 1035119098Sanholt/* Enable or disable PCI GART on the chip */ 1036145132Sanholtstatic void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) 1037119098Sanholt{ 1038152909Sanholt u32 tmp; 1039119098Sanholt 1040182080Srnoland if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 1041183828Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) || 1042182080Srnoland (dev_priv->flags & RADEON_IS_IGPGART)) { 1043182080Srnoland radeon_set_igpgart(dev_priv, on); 1044182080Srnoland return; 1045182080Srnoland } 1046182080Srnoland 1047189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { 1048189499Srnoland rs600_set_igpgart(dev_priv, on); 1049189499Srnoland return; 1050189499Srnoland } 1051189499Srnoland 1052182080Srnoland if (dev_priv->flags & RADEON_IS_PCIE) { 1053148211Sanholt radeon_set_pciegart(dev_priv, on); 1054148211Sanholt return; 1055148211Sanholt } 1056148211Sanholt 1057182080Srnoland tmp = RADEON_READ(RADEON_AIC_CNTL); 1058152909Sanholt 1059145132Sanholt if (on) { 1060145132Sanholt RADEON_WRITE(RADEON_AIC_CNTL, 1061145132Sanholt tmp | RADEON_PCIGART_TRANSLATE_EN); 1062119098Sanholt 1063119098Sanholt /* set PCI GART page-table base address 1064119098Sanholt */ 1065152909Sanholt RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); 1066119098Sanholt 1067119098Sanholt /* set address range for PCI address translate 1068119098Sanholt */ 1069145132Sanholt RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); 1070145132Sanholt RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start 1071145132Sanholt + dev_priv->gart_size - 1); 1072119098Sanholt 1073119895Sanholt /* Turn off AGP aperture -- is this required for PCI GART? 1074119098Sanholt */ 1075182080Srnoland radeon_write_agp_location(dev_priv, 0xffffffc0); 1076145132Sanholt RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ 1077119098Sanholt } else { 1078145132Sanholt RADEON_WRITE(RADEON_AIC_CNTL, 1079145132Sanholt tmp & ~RADEON_PCIGART_TRANSLATE_EN); 1080119098Sanholt } 1081119098Sanholt} 1082119098Sanholt 1083189499Srnolandstatic int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv) 108495584Sanholt{ 1085189499Srnoland struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; 1086189499Srnoland struct radeon_virt_surface *vp; 1087189499Srnoland int i; 1088189499Srnoland 1089189499Srnoland for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) { 1090189499Srnoland if (!dev_priv->virt_surfaces[i].file_priv || 1091189499Srnoland dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV) 1092189499Srnoland break; 1093189499Srnoland } 1094189499Srnoland if (i >= 2 * RADEON_MAX_SURFACES) 1095189499Srnoland return -ENOMEM; 1096189499Srnoland vp = &dev_priv->virt_surfaces[i]; 1097189499Srnoland 1098189499Srnoland for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1099189499Srnoland struct radeon_surface *sp = &dev_priv->surfaces[i]; 1100189499Srnoland if (sp->refcount) 1101189499Srnoland continue; 1102189499Srnoland 1103189499Srnoland vp->surface_index = i; 1104189499Srnoland vp->lower = gart_info->bus_addr; 1105189499Srnoland vp->upper = vp->lower + gart_info->table_size; 1106189499Srnoland vp->flags = 0; 1107189499Srnoland vp->file_priv = PCIGART_FILE_PRIV; 1108189499Srnoland 1109189499Srnoland sp->refcount = 1; 1110189499Srnoland sp->lower = vp->lower; 1111189499Srnoland sp->upper = vp->upper; 1112189499Srnoland sp->flags = 0; 1113189499Srnoland 1114189499Srnoland RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags); 1115189499Srnoland RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower); 1116189499Srnoland RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper); 1117189499Srnoland return 0; 1118189499Srnoland } 1119189499Srnoland 1120189499Srnoland return -ENOMEM; 1121189499Srnoland} 1122189499Srnoland 1123189499Srnolandstatic int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 1124189499Srnoland struct drm_file *file_priv) 1125189499Srnoland{ 1126145132Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1127157617Sanholt 1128145132Sanholt DRM_DEBUG("\n"); 112995584Sanholt 1130157617Sanholt /* if we require new memory map but we don't have it fail */ 1131182080Srnoland if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 1132157617Sanholt DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 1133157617Sanholt radeon_do_cleanup_cp(dev); 1134182080Srnoland return -EINVAL; 1135157617Sanholt } 1136157617Sanholt 1137189499Srnoland if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { 1138152909Sanholt DRM_DEBUG("Forcing AGP card to PCI mode\n"); 1139182080Srnoland dev_priv->flags &= ~RADEON_IS_AGP; 1140189499Srnoland } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) 1141189499Srnoland && !init->is_pci) { 1142162132Sanholt DRM_DEBUG("Restoring AGP flag\n"); 1143182080Srnoland dev_priv->flags |= RADEON_IS_AGP; 1144162132Sanholt } 1145152909Sanholt 1146182080Srnoland if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { 1147145132Sanholt DRM_ERROR("PCI GART memory not allocated!\n"); 114895584Sanholt radeon_do_cleanup_cp(dev); 1149182080Srnoland return -EINVAL; 115095584Sanholt } 115195584Sanholt 115295584Sanholt dev_priv->usec_timeout = init->usec_timeout; 1153145132Sanholt if (dev_priv->usec_timeout < 1 || 1154145132Sanholt dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 1155145132Sanholt DRM_DEBUG("TIMEOUT problem!\n"); 115695584Sanholt radeon_do_cleanup_cp(dev); 1157182080Srnoland return -EINVAL; 115895584Sanholt } 115995584Sanholt 1160182080Srnoland /* Enable vblank on CRTC1 for older X servers 1161182080Srnoland */ 1162182080Srnoland dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 1163145132Sanholt 1164189499Srnoland switch(init->func) { 1165189499Srnoland case RADEON_INIT_R200_CP: 1166189499Srnoland dev_priv->microcode_version = UCODE_R200; 1167189499Srnoland break; 1168189499Srnoland case RADEON_INIT_R300_CP: 1169189499Srnoland dev_priv->microcode_version = UCODE_R300; 1170189499Srnoland break; 1171189499Srnoland default: 1172189499Srnoland dev_priv->microcode_version = UCODE_R100; 1173189499Srnoland } 1174189499Srnoland 1175112015Sanholt dev_priv->do_boxes = 0; 117695584Sanholt dev_priv->cp_mode = init->cp_mode; 117795584Sanholt 117895584Sanholt /* We don't support anything other than bus-mastering ring mode, 117995584Sanholt * but the ring can be in either AGP or PCI space for the ring 118095584Sanholt * read pointer. 118195584Sanholt */ 1182145132Sanholt if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 1183145132Sanholt (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 1184145132Sanholt DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 118595584Sanholt radeon_do_cleanup_cp(dev); 1186182080Srnoland return -EINVAL; 118795584Sanholt } 118895584Sanholt 1189145132Sanholt switch (init->fb_bpp) { 119095584Sanholt case 16: 119195584Sanholt dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 119295584Sanholt break; 119395584Sanholt case 32: 119495584Sanholt default: 119595584Sanholt dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 119695584Sanholt break; 119795584Sanholt } 1198145132Sanholt dev_priv->front_offset = init->front_offset; 1199145132Sanholt dev_priv->front_pitch = init->front_pitch; 1200145132Sanholt dev_priv->back_offset = init->back_offset; 1201145132Sanholt dev_priv->back_pitch = init->back_pitch; 120295584Sanholt 1203145132Sanholt switch (init->depth_bpp) { 120495584Sanholt case 16: 120595584Sanholt dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 120695584Sanholt break; 120795584Sanholt case 32: 120895584Sanholt default: 120995584Sanholt dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 121095584Sanholt break; 121195584Sanholt } 1212145132Sanholt dev_priv->depth_offset = init->depth_offset; 1213145132Sanholt dev_priv->depth_pitch = init->depth_pitch; 121495584Sanholt 121595584Sanholt /* Hardware state for depth clears. Remove this if/when we no 121695584Sanholt * longer clear the depth buffer with a 3D rectangle. Hard-code 121795584Sanholt * all values to prevent unwanted 3D state from slipping through 121895584Sanholt * and screwing with the clear operation. 121995584Sanholt */ 122095584Sanholt dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | 122195584Sanholt (dev_priv->color_fmt << 10) | 1222189499Srnoland (dev_priv->microcode_version == 1223189499Srnoland UCODE_R100 ? RADEON_ZBLOCK16 : 0)); 122495584Sanholt 1225145132Sanholt dev_priv->depth_clear.rb3d_zstencilcntl = 1226145132Sanholt (dev_priv->depth_fmt | 1227145132Sanholt RADEON_Z_TEST_ALWAYS | 1228145132Sanholt RADEON_STENCIL_TEST_ALWAYS | 1229145132Sanholt RADEON_STENCIL_S_FAIL_REPLACE | 1230145132Sanholt RADEON_STENCIL_ZPASS_REPLACE | 1231145132Sanholt RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); 123295584Sanholt 123395584Sanholt dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | 123495584Sanholt RADEON_BFACE_SOLID | 123595584Sanholt RADEON_FFACE_SOLID | 123695584Sanholt RADEON_FLAT_SHADE_VTX_LAST | 123795584Sanholt RADEON_DIFFUSE_SHADE_FLAT | 123895584Sanholt RADEON_ALPHA_SHADE_FLAT | 123995584Sanholt RADEON_SPECULAR_SHADE_FLAT | 124095584Sanholt RADEON_FOG_SHADE_FLAT | 124195584Sanholt RADEON_VTX_PIX_CENTER_OGL | 124295584Sanholt RADEON_ROUND_MODE_TRUNC | 124395584Sanholt RADEON_ROUND_PREC_8TH_PIX); 124495584Sanholt 1245113995Sanholt 1246113995Sanholt dev_priv->ring_offset = init->ring_offset; 1247113995Sanholt dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1248113995Sanholt dev_priv->buffers_offset = init->buffers_offset; 1249119895Sanholt dev_priv->gart_textures_offset = init->gart_textures_offset; 1250145132Sanholt 1251182080Srnoland dev_priv->sarea = drm_getsarea(dev); 1252145132Sanholt if (!dev_priv->sarea) { 125395584Sanholt DRM_ERROR("could not find sarea!\n"); 125495584Sanholt radeon_do_cleanup_cp(dev); 1255182080Srnoland return -EINVAL; 125695584Sanholt } 125795584Sanholt 1258145132Sanholt dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 1259145132Sanholt if (!dev_priv->cp_ring) { 126095584Sanholt DRM_ERROR("could not find cp ring region!\n"); 126195584Sanholt radeon_do_cleanup_cp(dev); 1262182080Srnoland return -EINVAL; 126395584Sanholt } 1264145132Sanholt dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1265145132Sanholt if (!dev_priv->ring_rptr) { 126695584Sanholt DRM_ERROR("could not find ring read pointer!\n"); 126795584Sanholt radeon_do_cleanup_cp(dev); 1268182080Srnoland return -EINVAL; 126995584Sanholt } 1270152909Sanholt dev->agp_buffer_token = init->buffers_offset; 1271145132Sanholt dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1272145132Sanholt if (!dev->agp_buffer_map) { 127395584Sanholt DRM_ERROR("could not find dma buffer region!\n"); 127495584Sanholt radeon_do_cleanup_cp(dev); 1275182080Srnoland return -EINVAL; 127695584Sanholt } 127795584Sanholt 1278145132Sanholt if (init->gart_textures_offset) { 1279145132Sanholt dev_priv->gart_textures = 1280145132Sanholt drm_core_findmap(dev, init->gart_textures_offset); 1281145132Sanholt if (!dev_priv->gart_textures) { 1282119895Sanholt DRM_ERROR("could not find GART texture region!\n"); 128395584Sanholt radeon_do_cleanup_cp(dev); 1284182080Srnoland return -EINVAL; 128595584Sanholt } 128695584Sanholt } 128795584Sanholt 128895584Sanholt dev_priv->sarea_priv = 1289145132Sanholt (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + 1290145132Sanholt init->sarea_priv_offset); 129195584Sanholt 1292145132Sanholt#if __OS_HAS_AGP 1293182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 1294189499Srnoland drm_core_ioremap_wc(dev_priv->cp_ring, dev); 1295189499Srnoland drm_core_ioremap_wc(dev_priv->ring_rptr, dev); 1296189499Srnoland drm_core_ioremap_wc(dev->agp_buffer_map, dev); 1297145132Sanholt if (!dev_priv->cp_ring->handle || 1298145132Sanholt !dev_priv->ring_rptr->handle || 1299145132Sanholt !dev->agp_buffer_map->handle) { 130095584Sanholt DRM_ERROR("could not find ioremap agp regions!\n"); 130195584Sanholt radeon_do_cleanup_cp(dev); 1302182080Srnoland return -EINVAL; 130395584Sanholt } 1304119098Sanholt } else 1305119098Sanholt#endif 1306119098Sanholt { 1307189499Srnoland dev_priv->cp_ring->handle = 1308189499Srnoland (void *)(unsigned long)dev_priv->cp_ring->offset; 130995584Sanholt dev_priv->ring_rptr->handle = 1310189499Srnoland (void *)(unsigned long)dev_priv->ring_rptr->offset; 1311145132Sanholt dev->agp_buffer_map->handle = 1312189499Srnoland (void *)(unsigned long)dev->agp_buffer_map->offset; 131395584Sanholt 1314145132Sanholt DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 1315145132Sanholt dev_priv->cp_ring->handle); 1316145132Sanholt DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 1317145132Sanholt dev_priv->ring_rptr->handle); 1318145132Sanholt DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 1319145132Sanholt dev->agp_buffer_map->handle); 132095584Sanholt } 132195584Sanholt 1322182080Srnoland dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16; 1323182080Srnoland dev_priv->fb_size = 1324182080Srnoland ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000) 1325157617Sanholt - dev_priv->fb_location; 132695584Sanholt 1327145132Sanholt dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 1328145132Sanholt ((dev_priv->front_offset 1329145132Sanholt + dev_priv->fb_location) >> 10)); 1330122580Sanholt 1331145132Sanholt dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 1332145132Sanholt ((dev_priv->back_offset 1333145132Sanholt + dev_priv->fb_location) >> 10)); 1334122580Sanholt 1335145132Sanholt dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 1336145132Sanholt ((dev_priv->depth_offset 1337145132Sanholt + dev_priv->fb_location) >> 10)); 1338122580Sanholt 1339119895Sanholt dev_priv->gart_size = init->gart_size; 1340122580Sanholt 1341157617Sanholt /* New let's set the memory map ... */ 1342157617Sanholt if (dev_priv->new_memmap) { 1343157617Sanholt u32 base = 0; 1344157617Sanholt 1345157617Sanholt DRM_INFO("Setting GART location based on new memory map\n"); 1346157617Sanholt 1347157617Sanholt /* If using AGP, try to locate the AGP aperture at the same 1348157617Sanholt * location in the card and on the bus, though we have to 1349157617Sanholt * align it down. 1350157617Sanholt */ 1351145132Sanholt#if __OS_HAS_AGP 1352182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 1353157617Sanholt base = dev->agp->base; 1354157617Sanholt /* Check if valid */ 1355182080Srnoland if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && 1356182080Srnoland base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { 1357157617Sanholt DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 1358157617Sanholt dev->agp->base); 1359157617Sanholt base = 0; 1360157617Sanholt } 1361157617Sanholt } 1362157617Sanholt#endif 1363157617Sanholt /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 1364157617Sanholt if (base == 0) { 1365157617Sanholt base = dev_priv->fb_location + dev_priv->fb_size; 1366182080Srnoland if (base < dev_priv->fb_location || 1367182080Srnoland ((base + dev_priv->gart_size) & 0xfffffffful) < base) 1368157617Sanholt base = dev_priv->fb_location 1369157617Sanholt - dev_priv->gart_size; 1370182080Srnoland } 1371157617Sanholt dev_priv->gart_vm_start = base & 0xffc00000u; 1372157617Sanholt if (dev_priv->gart_vm_start != base) 1373157617Sanholt DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 1374157617Sanholt base, dev_priv->gart_vm_start); 1375157617Sanholt } else { 1376157617Sanholt DRM_INFO("Setting GART location based on old memory map\n"); 1377157617Sanholt dev_priv->gart_vm_start = dev_priv->fb_location + 1378157617Sanholt RADEON_READ(RADEON_CONFIG_APER_SIZE); 1379157617Sanholt } 1380157617Sanholt 1381157617Sanholt#if __OS_HAS_AGP 1382182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) 1383145132Sanholt dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1384145132Sanholt - dev->agp->base 1385145132Sanholt + dev_priv->gart_vm_start); 138695584Sanholt else 138795584Sanholt#endif 1388145132Sanholt dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1389157617Sanholt - (unsigned long)dev->sg->virtual 1390157617Sanholt + dev_priv->gart_vm_start); 139195584Sanholt 1392145132Sanholt DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 1393145132Sanholt DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); 1394145132Sanholt DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", 1395145132Sanholt dev_priv->gart_buffers_offset); 139695584Sanholt 1397145132Sanholt dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 1398145132Sanholt dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 139995584Sanholt + init->ring_size / sizeof(u32)); 140095584Sanholt dev_priv->ring.size = init->ring_size; 1401145132Sanholt dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 140295584Sanholt 1403182080Srnoland dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; 1404182080Srnoland dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8); 1405182080Srnoland 1406182080Srnoland dev_priv->ring.fetch_size = /* init->fetch_size */ 32; 1407182080Srnoland dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16); 1408145132Sanholt dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 140995584Sanholt 141095584Sanholt dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 141195584Sanholt 1412145132Sanholt#if __OS_HAS_AGP 1413182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 1414119098Sanholt /* Turn off PCI GART */ 1415145132Sanholt radeon_set_pcigart(dev_priv, 0); 1416119098Sanholt } else 1417119098Sanholt#endif 1418119098Sanholt { 1419189499Srnoland u32 sctrl; 1420189499Srnoland int ret; 1421189499Srnoland 1422182080Srnoland dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); 1423152909Sanholt /* if we have an offset set from userspace */ 1424182080Srnoland if (dev_priv->pcigart_offset_set) { 1425157617Sanholt dev_priv->gart_info.bus_addr = 1426157617Sanholt dev_priv->pcigart_offset + dev_priv->fb_location; 1427157617Sanholt dev_priv->gart_info.mapping.offset = 1428182080Srnoland dev_priv->pcigart_offset + dev_priv->fb_aper_offset; 1429157617Sanholt dev_priv->gart_info.mapping.size = 1430182080Srnoland dev_priv->gart_info.table_size; 1431157617Sanholt 1432182080Srnoland drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); 1433157617Sanholt dev_priv->gart_info.addr = 1434157617Sanholt dev_priv->gart_info.mapping.handle; 1435152909Sanholt 1436182080Srnoland if (dev_priv->flags & RADEON_IS_PCIE) 1437182080Srnoland dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE; 1438182080Srnoland else 1439182080Srnoland dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; 1440157617Sanholt dev_priv->gart_info.gart_table_location = 1441157617Sanholt DRM_ATI_GART_FB; 1442157617Sanholt 1443157617Sanholt DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 1444157617Sanholt dev_priv->gart_info.addr, 1445157617Sanholt dev_priv->pcigart_offset); 1446157617Sanholt } else { 1447182080Srnoland if (dev_priv->flags & RADEON_IS_IGPGART) 1448182080Srnoland dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP; 1449182080Srnoland else 1450182080Srnoland dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; 1451157617Sanholt dev_priv->gart_info.gart_table_location = 1452157617Sanholt DRM_ATI_GART_MAIN; 1453152909Sanholt dev_priv->gart_info.addr = NULL; 1454152909Sanholt dev_priv->gart_info.bus_addr = 0; 1455182080Srnoland if (dev_priv->flags & RADEON_IS_PCIE) { 1456157617Sanholt DRM_ERROR 1457157617Sanholt ("Cannot use PCI Express without GART in FB memory\n"); 1458152909Sanholt radeon_do_cleanup_cp(dev); 1459182080Srnoland return -EINVAL; 1460152909Sanholt } 1461152909Sanholt } 1462152909Sanholt 1463189499Srnoland sctrl = RADEON_READ(RADEON_SURFACE_CNTL); 1464189499Srnoland RADEON_WRITE(RADEON_SURFACE_CNTL, 0); 1465189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 1466189499Srnoland ret = r600_page_table_init(dev); 1467189499Srnoland else 1468189499Srnoland ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info); 1469189499Srnoland RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl); 1470189499Srnoland 1471189499Srnoland if (!ret) { 1472145132Sanholt DRM_ERROR("failed to init PCI GART!\n"); 147395584Sanholt radeon_do_cleanup_cp(dev); 1474182080Srnoland return -ENOMEM; 147595584Sanholt } 147695584Sanholt 1477189499Srnoland ret = radeon_setup_pcigart_surface(dev_priv); 1478189499Srnoland if (ret) { 1479189499Srnoland DRM_ERROR("failed to setup GART surface!\n"); 1480189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 1481189499Srnoland r600_page_table_cleanup(dev, &dev_priv->gart_info); 1482189499Srnoland else 1483189499Srnoland drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info); 1484189499Srnoland radeon_do_cleanup_cp(dev); 1485189499Srnoland return ret; 1486189499Srnoland } 1487189499Srnoland 1488119098Sanholt /* Turn on PCI GART */ 1489145132Sanholt radeon_set_pcigart(dev_priv, 1); 149095584Sanholt } 149195584Sanholt 1492145132Sanholt radeon_cp_load_microcode(dev_priv); 1493189499Srnoland radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); 149495584Sanholt 149595584Sanholt dev_priv->last_buf = 0; 149695584Sanholt 1497145132Sanholt radeon_do_engine_reset(dev); 1498157617Sanholt radeon_test_writeback(dev_priv); 149995584Sanholt 150095584Sanholt return 0; 150195584Sanholt} 150295584Sanholt 1503182080Srnolandstatic int radeon_do_cleanup_cp(struct drm_device * dev) 150495584Sanholt{ 1505145132Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1506145132Sanholt DRM_DEBUG("\n"); 150795584Sanholt 1508119098Sanholt /* Make sure interrupts are disabled here because the uninstall ioctl 1509119098Sanholt * may not have been called from userspace and after dev_private 1510119098Sanholt * is freed, it's too late. 1511119098Sanholt */ 1512145132Sanholt if (dev->irq_enabled) 1513145132Sanholt drm_irq_uninstall(dev); 1514119098Sanholt 1515145132Sanholt#if __OS_HAS_AGP 1516182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 1517145132Sanholt if (dev_priv->cp_ring != NULL) { 1518145132Sanholt drm_core_ioremapfree(dev_priv->cp_ring, dev); 1519145132Sanholt dev_priv->cp_ring = NULL; 1520145132Sanholt } 1521145132Sanholt if (dev_priv->ring_rptr != NULL) { 1522145132Sanholt drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1523145132Sanholt dev_priv->ring_rptr = NULL; 1524145132Sanholt } 1525145132Sanholt if (dev->agp_buffer_map != NULL) { 1526145132Sanholt drm_core_ioremapfree(dev->agp_buffer_map, dev); 1527145132Sanholt dev->agp_buffer_map = NULL; 1528145132Sanholt } 1529145132Sanholt } else 1530119098Sanholt#endif 1531145132Sanholt { 1532152909Sanholt 1533152909Sanholt if (dev_priv->gart_info.bus_addr) { 1534152909Sanholt /* Turn off PCI GART */ 1535152909Sanholt radeon_set_pcigart(dev_priv, 0); 1536189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 1537189499Srnoland r600_page_table_cleanup(dev, &dev_priv->gart_info); 1538189499Srnoland else { 1539189499Srnoland if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) 1540189499Srnoland DRM_ERROR("failed to cleanup PCI GART!\n"); 1541189499Srnoland } 1542152909Sanholt } 1543152909Sanholt 1544152909Sanholt if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) 1545152909Sanholt { 1546152909Sanholt drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 1547152909Sanholt dev_priv->gart_info.addr = 0; 1548152909Sanholt } 154995584Sanholt } 1550145132Sanholt /* only clear to the start of flags */ 1551145132Sanholt memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 155295584Sanholt 155395584Sanholt return 0; 155495584Sanholt} 155595584Sanholt 1556145132Sanholt/* This code will reinit the Radeon CP hardware after a resume from disc. 1557145132Sanholt * AFAIK, it would be very difficult to pickle the state at suspend time, so 1558119098Sanholt * here we make sure that all Radeon hardware initialisation is re-done without 1559119098Sanholt * affecting running applications. 1560119098Sanholt * 1561119098Sanholt * Charl P. Botha <http://cpbotha.net> 1562119098Sanholt */ 1563189499Srnolandstatic int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) 1564119098Sanholt{ 1565119098Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1566119098Sanholt 1567145132Sanholt if (!dev_priv) { 1568145132Sanholt DRM_ERROR("Called with no initialization\n"); 1569182080Srnoland return -EINVAL; 1570119098Sanholt } 1571119098Sanholt 1572119098Sanholt DRM_DEBUG("Starting radeon_do_resume_cp()\n"); 1573119098Sanholt 1574145132Sanholt#if __OS_HAS_AGP 1575182080Srnoland if (dev_priv->flags & RADEON_IS_AGP) { 1576119098Sanholt /* Turn off PCI GART */ 1577145132Sanholt radeon_set_pcigart(dev_priv, 0); 1578119098Sanholt } else 1579119098Sanholt#endif 1580119098Sanholt { 1581119098Sanholt /* Turn on PCI GART */ 1582145132Sanholt radeon_set_pcigart(dev_priv, 1); 1583119098Sanholt } 1584119098Sanholt 1585145132Sanholt radeon_cp_load_microcode(dev_priv); 1586189499Srnoland radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); 1587119098Sanholt 1588145132Sanholt radeon_do_engine_reset(dev); 1589182080Srnoland radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); 1590119098Sanholt 1591119098Sanholt DRM_DEBUG("radeon_do_resume_cp() complete\n"); 1592119098Sanholt 1593119098Sanholt return 0; 1594119098Sanholt} 1595119098Sanholt 1596182080Srnolandint radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) 159795584Sanholt{ 1598189499Srnoland drm_radeon_private_t *dev_priv = dev->dev_private; 1599182080Srnoland drm_radeon_init_t *init = data; 160095584Sanholt 1601182080Srnoland LOCK_TEST_WITH_RETURN(dev, file_priv); 1602119098Sanholt 1603182080Srnoland if (init->func == RADEON_INIT_R300_CP) 1604182080Srnoland r300_init_reg_flags(dev); 160595584Sanholt 1606182080Srnoland switch (init->func) { 160795584Sanholt case RADEON_INIT_CP: 1608112015Sanholt case RADEON_INIT_R200_CP: 1609145132Sanholt case RADEON_INIT_R300_CP: 1610189499Srnoland return radeon_do_init_cp(dev, init, file_priv); 1611189499Srnoland case RADEON_INIT_R600_CP: 1612189499Srnoland return r600_do_init_cp(dev, init, file_priv); 161395584Sanholt case RADEON_CLEANUP_CP: 1614189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1615189499Srnoland return r600_do_cleanup_cp(dev); 1616189499Srnoland else 1617189499Srnoland return radeon_do_cleanup_cp(dev); 161895584Sanholt } 161995584Sanholt 1620182080Srnoland return -EINVAL; 162195584Sanholt} 162295584Sanholt 1623182080Srnolandint radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv) 162495584Sanholt{ 162595584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1626145132Sanholt DRM_DEBUG("\n"); 162795584Sanholt 1628182080Srnoland LOCK_TEST_WITH_RETURN(dev, file_priv); 162995584Sanholt 1630145132Sanholt if (dev_priv->cp_running) { 1631182080Srnoland DRM_DEBUG("while CP running\n"); 163295584Sanholt return 0; 163395584Sanholt } 1634145132Sanholt if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { 1635182080Srnoland DRM_DEBUG("called with bogus CP mode (%d)\n", 1636182080Srnoland dev_priv->cp_mode); 163795584Sanholt return 0; 163895584Sanholt } 163995584Sanholt 1640189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1641189499Srnoland r600_do_cp_start(dev_priv); 1642189499Srnoland else 1643189499Srnoland radeon_do_cp_start(dev_priv); 164495584Sanholt 164595584Sanholt return 0; 164695584Sanholt} 164795584Sanholt 164895584Sanholt/* Stop the CP. The engine must have been idled before calling this 164995584Sanholt * routine. 165095584Sanholt */ 1651182080Srnolandint radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv) 165295584Sanholt{ 165395584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1654182080Srnoland drm_radeon_cp_stop_t *stop = data; 165595584Sanholt int ret; 1656145132Sanholt DRM_DEBUG("\n"); 165795584Sanholt 1658182080Srnoland LOCK_TEST_WITH_RETURN(dev, file_priv); 165995584Sanholt 1660112015Sanholt if (!dev_priv->cp_running) 1661112015Sanholt return 0; 1662112015Sanholt 166395584Sanholt /* Flush any pending CP commands. This ensures any outstanding 166495584Sanholt * commands are exectuted by the engine before we turn it off. 166595584Sanholt */ 1666182080Srnoland if (stop->flush) { 1667145132Sanholt radeon_do_cp_flush(dev_priv); 166895584Sanholt } 166995584Sanholt 167095584Sanholt /* If we fail to make the engine go idle, we return an error 167195584Sanholt * code so that the DRM ioctl wrapper can try again. 167295584Sanholt */ 1673182080Srnoland if (stop->idle) { 1674189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1675189499Srnoland ret = r600_do_cp_idle(dev_priv); 1676189499Srnoland else 1677189499Srnoland ret = radeon_do_cp_idle(dev_priv); 1678145132Sanholt if (ret) 1679145132Sanholt return ret; 168095584Sanholt } 168195584Sanholt 168295584Sanholt /* Finally, we can turn off the CP. If the engine isn't idle, 168395584Sanholt * we will get some dropped triangles as they won't be fully 168495584Sanholt * rendered before the CP is shut down. 168595584Sanholt */ 1686189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1687189499Srnoland r600_do_cp_stop(dev_priv); 1688189499Srnoland else 1689189499Srnoland radeon_do_cp_stop(dev_priv); 169095584Sanholt 169195584Sanholt /* Reset the engine */ 1692189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1693189499Srnoland r600_do_engine_reset(dev); 1694189499Srnoland else 1695189499Srnoland radeon_do_engine_reset(dev); 169695584Sanholt 169795584Sanholt return 0; 169895584Sanholt} 169995584Sanholt 1700182080Srnolandvoid radeon_do_release(struct drm_device * dev) 1701112015Sanholt{ 1702112015Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1703145132Sanholt int i, ret; 1704112015Sanholt 1705112015Sanholt if (dev_priv) { 1706112015Sanholt if (dev_priv->cp_running) { 1707112015Sanholt /* Stop the cp */ 1708189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) { 1709189499Srnoland while ((ret = r600_do_cp_idle(dev_priv)) != 0) { 1710189499Srnoland DRM_DEBUG("radeon_do_cp_idle %d\n", ret); 1711112015Sanholt#ifdef __linux__ 1712189499Srnoland schedule(); 1713189499Srnoland#elsif defined(__FreeBSD__) 1714189499Srnoland mtx_sleep(&ret, &dev->dev_lock, 0, 1715189499Srnoland "rdnrel", 1); 1716112015Sanholt#else 1717189499Srnoland tsleep(&ret, PZERO, "rdnrel", 1); 1718189499Srnoland#endif 1719189499Srnoland } 1720189499Srnoland } else { 1721189499Srnoland while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { 1722189499Srnoland DRM_DEBUG("radeon_do_cp_idle %d\n", ret); 1723189499Srnoland#ifdef __linux__ 1724189499Srnoland schedule(); 1725189499Srnoland#elsif defined(__FreeBSD__) 1726189499Srnoland mtx_sleep(&ret, &dev->dev_lock, 0, 1727189499Srnoland "rdnrel", 1); 1728152909Sanholt#else 1729189499Srnoland tsleep(&ret, PZERO, "rdnrel", 1); 1730112015Sanholt#endif 1731189499Srnoland } 1732112015Sanholt } 1733189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { 1734189499Srnoland r600_do_cp_stop(dev_priv); 1735189499Srnoland r600_do_engine_reset(dev); 1736189499Srnoland } else { 1737189499Srnoland radeon_do_cp_stop(dev_priv); 1738189499Srnoland radeon_do_engine_reset(dev); 1739189499Srnoland } 1740112015Sanholt } 1741112015Sanholt 1742189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) { 1743189499Srnoland /* Disable *all* interrupts */ 1744189499Srnoland if (dev_priv->mmio) /* remove this after permanent addmaps */ 1745189499Srnoland RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 1746112015Sanholt 1747189499Srnoland if (dev_priv->mmio) { /* remove all surfaces */ 1748189499Srnoland for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1749189499Srnoland RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0); 1750189499Srnoland RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 1751189499Srnoland 16 * i, 0); 1752189499Srnoland RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 1753189499Srnoland 16 * i, 0); 1754189499Srnoland } 1755145132Sanholt } 1756145132Sanholt } 1757145132Sanholt 1758112015Sanholt /* Free memory heap structures */ 1759145132Sanholt radeon_mem_takedown(&(dev_priv->gart_heap)); 1760145132Sanholt radeon_mem_takedown(&(dev_priv->fb_heap)); 1761112015Sanholt 1762112015Sanholt /* deallocate kernel resources */ 1763189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1764189499Srnoland r600_do_cleanup_cp(dev); 1765189499Srnoland else 1766189499Srnoland radeon_do_cleanup_cp(dev); 1767112015Sanholt } 1768112015Sanholt} 1769112015Sanholt 177095584Sanholt/* Just reset the CP ring. Called as part of an X Server engine reset. 177195584Sanholt */ 1772182080Srnolandint radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) 177395584Sanholt{ 177495584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1775145132Sanholt DRM_DEBUG("\n"); 177695584Sanholt 1777182080Srnoland LOCK_TEST_WITH_RETURN(dev, file_priv); 177895584Sanholt 1779145132Sanholt if (!dev_priv) { 1780182080Srnoland DRM_DEBUG("called before init done\n"); 1781182080Srnoland return -EINVAL; 178295584Sanholt } 178395584Sanholt 1784189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1785189499Srnoland r600_do_cp_reset(dev_priv); 1786189499Srnoland else 1787189499Srnoland radeon_do_cp_reset(dev_priv); 178895584Sanholt 178995584Sanholt /* The CP is no longer running after an engine reset */ 179095584Sanholt dev_priv->cp_running = 0; 179195584Sanholt 179295584Sanholt return 0; 179395584Sanholt} 179495584Sanholt 1795182080Srnolandint radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv) 179695584Sanholt{ 179795584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1798145132Sanholt DRM_DEBUG("\n"); 179995584Sanholt 1800182080Srnoland LOCK_TEST_WITH_RETURN(dev, file_priv); 180195584Sanholt 1802189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1803189499Srnoland return r600_do_cp_idle(dev_priv); 1804189499Srnoland else 1805189499Srnoland return radeon_do_cp_idle(dev_priv); 180695584Sanholt} 180795584Sanholt 1808119098Sanholt/* Added by Charl P. Botha to call radeon_do_resume_cp(). 1809119098Sanholt */ 1810182080Srnolandint radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv) 1811119098Sanholt{ 1812189499Srnoland drm_radeon_private_t *dev_priv = dev->dev_private; 1813189499Srnoland DRM_DEBUG("\n"); 1814119098Sanholt 1815189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1816189499Srnoland return r600_do_resume_cp(dev, file_priv); 1817189499Srnoland else 1818189499Srnoland return radeon_do_resume_cp(dev, file_priv); 1819119098Sanholt} 1820119098Sanholt 1821182080Srnolandint radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) 182295584Sanholt{ 1823189499Srnoland drm_radeon_private_t *dev_priv = dev->dev_private; 1824145132Sanholt DRM_DEBUG("\n"); 182595584Sanholt 1826182080Srnoland LOCK_TEST_WITH_RETURN(dev, file_priv); 182795584Sanholt 1828189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1829189499Srnoland return r600_do_engine_reset(dev); 1830189499Srnoland else 1831189499Srnoland return radeon_do_engine_reset(dev); 183295584Sanholt} 183395584Sanholt 183495584Sanholt/* ================================================================ 183595584Sanholt * Fullscreen mode 183695584Sanholt */ 183795584Sanholt 1838112015Sanholt/* KW: Deprecated to say the least: 1839112015Sanholt */ 1840182080Srnolandint radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv) 184195584Sanholt{ 184295584Sanholt return 0; 184395584Sanholt} 184495584Sanholt 184595584Sanholt/* ================================================================ 184695584Sanholt * Freelist management 184795584Sanholt */ 184895584Sanholt 1849112015Sanholt/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through 1850112015Sanholt * bufs until freelist code is used. Note this hides a problem with 1851112015Sanholt * the scratch register * (used to keep track of last buffer 1852112015Sanholt * completed) being written to before * the last buffer has actually 1853145132Sanholt * completed rendering. 1854112015Sanholt * 1855112015Sanholt * KW: It's also a good way to find free buffers quickly. 1856112015Sanholt * 1857112015Sanholt * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't 1858112015Sanholt * sleep. However, bugs in older versions of radeon_accel.c mean that 1859112015Sanholt * we essentially have to do this, else old clients will break. 1860145132Sanholt * 1861112015Sanholt * However, it does leave open a potential deadlock where all the 1862112015Sanholt * buffers are held by other clients, which can't release them because 1863145132Sanholt * they can't get the lock. 1864112015Sanholt */ 1865112015Sanholt 1866182080Srnolandstruct drm_buf *radeon_freelist_get(struct drm_device * dev) 186795584Sanholt{ 1868182080Srnoland struct drm_device_dma *dma = dev->dma; 186995584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1870112015Sanholt drm_radeon_buf_priv_t *buf_priv; 1871182080Srnoland struct drm_buf *buf; 1872112015Sanholt int i, t; 1873112015Sanholt int start; 187495584Sanholt 1875145132Sanholt if (++dev_priv->last_buf >= dma->buf_count) 1876112015Sanholt dev_priv->last_buf = 0; 187795584Sanholt 1878112015Sanholt start = dev_priv->last_buf; 187995584Sanholt 1880145132Sanholt for (t = 0; t < dev_priv->usec_timeout; t++) { 1881189499Srnoland u32 done_age = GET_SCRATCH(dev_priv, 1); 1882145132Sanholt DRM_DEBUG("done_age = %d\n", done_age); 1883145132Sanholt for (i = start; i < dma->buf_count; i++) { 1884112015Sanholt buf = dma->buflist[i]; 1885112015Sanholt buf_priv = buf->dev_private; 1886182080Srnoland if (buf->file_priv == NULL || (buf->pending && 1887182080Srnoland buf_priv->age <= 1888182080Srnoland done_age)) { 1889112015Sanholt dev_priv->stats.requested_bufs++; 1890112015Sanholt buf->pending = 0; 1891112015Sanholt return buf; 1892112015Sanholt } 1893112015Sanholt start = 0; 1894112015Sanholt } 189595584Sanholt 1896112015Sanholt if (t) { 1897145132Sanholt DRM_UDELAY(1); 1898112015Sanholt dev_priv->stats.freelist_loops++; 1899112015Sanholt } 190095584Sanholt } 190195584Sanholt 1902145132Sanholt DRM_DEBUG("returning NULL!\n"); 1903112015Sanholt return NULL; 190495584Sanholt} 1905145132Sanholt 1906112015Sanholt#if 0 1907182080Srnolandstruct drm_buf *radeon_freelist_get(struct drm_device * dev) 190895584Sanholt{ 1909182080Srnoland struct drm_device_dma *dma = dev->dma; 191095584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 191195584Sanholt drm_radeon_buf_priv_t *buf_priv; 1912182080Srnoland struct drm_buf *buf; 191395584Sanholt int i, t; 191495584Sanholt int start; 1915189499Srnoland u32 done_age; 191695584Sanholt 1917189499Srnoland done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1)); 1918145132Sanholt if (++dev_priv->last_buf >= dma->buf_count) 191995584Sanholt dev_priv->last_buf = 0; 1920112015Sanholt 192195584Sanholt start = dev_priv->last_buf; 1922112015Sanholt dev_priv->stats.freelist_loops++; 1923145132Sanholt 1924145132Sanholt for (t = 0; t < 2; t++) { 1925145132Sanholt for (i = start; i < dma->buf_count; i++) { 192695584Sanholt buf = dma->buflist[i]; 192795584Sanholt buf_priv = buf->dev_private; 1928182080Srnoland if (buf->file_priv == 0 || (buf->pending && 1929182080Srnoland buf_priv->age <= 1930182080Srnoland done_age)) { 1931112015Sanholt dev_priv->stats.requested_bufs++; 193295584Sanholt buf->pending = 0; 193395584Sanholt return buf; 193495584Sanholt } 193595584Sanholt } 1936112015Sanholt start = 0; 193795584Sanholt } 193895584Sanholt 193995584Sanholt return NULL; 194095584Sanholt} 1941112015Sanholt#endif 194295584Sanholt 1943182080Srnolandvoid radeon_freelist_reset(struct drm_device * dev) 194495584Sanholt{ 1945182080Srnoland struct drm_device_dma *dma = dev->dma; 194695584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 194795584Sanholt int i; 194895584Sanholt 194995584Sanholt dev_priv->last_buf = 0; 1950145132Sanholt for (i = 0; i < dma->buf_count; i++) { 1951182080Srnoland struct drm_buf *buf = dma->buflist[i]; 195295584Sanholt drm_radeon_buf_priv_t *buf_priv = buf->dev_private; 195395584Sanholt buf_priv->age = 0; 195495584Sanholt } 195595584Sanholt} 195695584Sanholt 195795584Sanholt/* ================================================================ 195895584Sanholt * CP command submission 195995584Sanholt */ 196095584Sanholt 1961145132Sanholtint radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) 196295584Sanholt{ 196395584Sanholt drm_radeon_ring_buffer_t *ring = &dev_priv->ring; 196495584Sanholt int i; 1965145132Sanholt u32 last_head = GET_RING_HEAD(dev_priv); 196695584Sanholt 1967145132Sanholt for (i = 0; i < dev_priv->usec_timeout; i++) { 1968145132Sanholt u32 head = GET_RING_HEAD(dev_priv); 1969112015Sanholt 1970112015Sanholt ring->space = (head - ring->tail) * sizeof(u32); 1971145132Sanholt if (ring->space <= 0) 1972112015Sanholt ring->space += ring->size; 1973145132Sanholt if (ring->space > n) 197495584Sanholt return 0; 1975145132Sanholt 1976112015Sanholt dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 1977112015Sanholt 1978112015Sanholt if (head != last_head) 1979112015Sanholt i = 0; 1980112015Sanholt last_head = head; 1981112015Sanholt 1982145132Sanholt DRM_UDELAY(1); 198395584Sanholt } 198495584Sanholt 198595584Sanholt /* FIXME: This return value is ignored in the BEGIN_RING macro! */ 198695584Sanholt#if RADEON_FIFO_DEBUG 1987145132Sanholt radeon_status(dev_priv); 1988145132Sanholt DRM_ERROR("failed!\n"); 198995584Sanholt#endif 1990182080Srnoland return -EBUSY; 199195584Sanholt} 199295584Sanholt 1993182080Srnolandstatic int radeon_cp_get_buffers(struct drm_device *dev, 1994182080Srnoland struct drm_file *file_priv, 1995182080Srnoland struct drm_dma * d) 199695584Sanholt{ 199795584Sanholt int i; 1998182080Srnoland struct drm_buf *buf; 199995584Sanholt 2000145132Sanholt for (i = d->granted_count; i < d->request_count; i++) { 2001145132Sanholt buf = radeon_freelist_get(dev); 2002145132Sanholt if (!buf) 2003182080Srnoland return -EBUSY; /* NOTE: broken client */ 200495584Sanholt 2005182080Srnoland buf->file_priv = file_priv; 200695584Sanholt 2007145132Sanholt if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, 2008145132Sanholt sizeof(buf->idx))) 2009182080Srnoland return -EFAULT; 2010145132Sanholt if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, 2011145132Sanholt sizeof(buf->total))) 2012182080Srnoland return -EFAULT; 201395584Sanholt 201495584Sanholt d->granted_count++; 201595584Sanholt } 201695584Sanholt return 0; 201795584Sanholt} 201895584Sanholt 2019182080Srnolandint radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) 202095584Sanholt{ 2021182080Srnoland struct drm_device_dma *dma = dev->dma; 202295584Sanholt int ret = 0; 2023182080Srnoland struct drm_dma *d = data; 202495584Sanholt 2025182080Srnoland LOCK_TEST_WITH_RETURN(dev, file_priv); 202695584Sanholt 202795584Sanholt /* Please don't send us buffers. 202895584Sanholt */ 2029182080Srnoland if (d->send_count != 0) { 2030145132Sanholt DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", 2031182080Srnoland DRM_CURRENTPID, d->send_count); 2032182080Srnoland return -EINVAL; 203395584Sanholt } 203495584Sanholt 203595584Sanholt /* We'll send you buffers. 203695584Sanholt */ 2037182080Srnoland if (d->request_count < 0 || d->request_count > dma->buf_count) { 2038145132Sanholt DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", 2039182080Srnoland DRM_CURRENTPID, d->request_count, dma->buf_count); 2040182080Srnoland return -EINVAL; 204195584Sanholt } 204295584Sanholt 2043182080Srnoland d->granted_count = 0; 204495584Sanholt 2045182080Srnoland if (d->request_count) { 2046182080Srnoland ret = radeon_cp_get_buffers(dev, file_priv, d); 204795584Sanholt } 204895584Sanholt 204995584Sanholt return ret; 205095584Sanholt} 2051145132Sanholt 2052152909Sanholtint radeon_driver_load(struct drm_device *dev, unsigned long flags) 2053145132Sanholt{ 2054145132Sanholt drm_radeon_private_t *dev_priv; 2055145132Sanholt int ret = 0; 2056145132Sanholt 2057145132Sanholt dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); 2058145132Sanholt if (dev_priv == NULL) 2059182080Srnoland return -ENOMEM; 2060145132Sanholt 2061145132Sanholt memset(dev_priv, 0, sizeof(drm_radeon_private_t)); 2062145132Sanholt dev->dev_private = (void *)dev_priv; 2063145132Sanholt dev_priv->flags = flags; 2064145132Sanholt 2065182080Srnoland switch (flags & RADEON_FAMILY_MASK) { 2066145132Sanholt case CHIP_R100: 2067145132Sanholt case CHIP_RV200: 2068145132Sanholt case CHIP_R200: 2069145132Sanholt case CHIP_R300: 2070157617Sanholt case CHIP_R350: 2071148211Sanholt case CHIP_R420: 2072183830Srnoland case CHIP_R423: 2073157617Sanholt case CHIP_RV410: 2074182080Srnoland case CHIP_RV515: 2075182080Srnoland case CHIP_R520: 2076182080Srnoland case CHIP_RV570: 2077182080Srnoland case CHIP_R580: 2078182080Srnoland dev_priv->flags |= RADEON_HAS_HIERZ; 2079145132Sanholt break; 2080145132Sanholt default: 2081157617Sanholt /* all other chips have no hierarchical z buffer */ 2082145132Sanholt break; 2083145132Sanholt } 2084145132Sanholt 2085145132Sanholt if (drm_device_is_agp(dev)) 2086182080Srnoland dev_priv->flags |= RADEON_IS_AGP; 2087162132Sanholt else if (drm_device_is_pcie(dev)) 2088182080Srnoland dev_priv->flags |= RADEON_IS_PCIE; 2089162132Sanholt else 2090182080Srnoland dev_priv->flags |= RADEON_IS_PCI; 2091148211Sanholt 2092189499Srnoland ret = drm_addmap(dev, drm_get_resource_start(dev, 2), 2093189499Srnoland drm_get_resource_len(dev, 2), _DRM_REGISTERS, 2094189499Srnoland _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio); 2095189499Srnoland if (ret != 0) 2096189499Srnoland return ret; 2097189499Srnoland 2098189130Srnoland ret = drm_vblank_init(dev, 2); 2099189130Srnoland if (ret) { 2100189130Srnoland radeon_driver_unload(dev); 2101189130Srnoland return ret; 2102189130Srnoland } 2103189130Srnoland 2104145132Sanholt DRM_DEBUG("%s card detected\n", 2105182080Srnoland ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); 2106145132Sanholt return ret; 2107145132Sanholt} 2108145132Sanholt 2109152909Sanholt/* Create mappings for registers and framebuffer so userland doesn't necessarily 2110152909Sanholt * have to find them. 2111152909Sanholt */ 2112152909Sanholtint radeon_driver_firstopen(struct drm_device *dev) 2113145132Sanholt{ 2114152909Sanholt int ret; 2115152909Sanholt drm_local_map_t *map; 2116145132Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 2117145132Sanholt 2118182080Srnoland dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; 2119182080Srnoland 2120182080Srnoland dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); 2121182080Srnoland ret = drm_addmap(dev, dev_priv->fb_aper_offset, 2122152909Sanholt drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, 2123152909Sanholt _DRM_WRITE_COMBINING, &map); 2124152909Sanholt if (ret != 0) 2125152909Sanholt return ret; 2126152909Sanholt 2127152909Sanholt return 0; 2128152909Sanholt} 2129152909Sanholt 2130152909Sanholtint radeon_driver_unload(struct drm_device *dev) 2131152909Sanholt{ 2132152909Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 2133152909Sanholt 2134145132Sanholt DRM_DEBUG("\n"); 2135189499Srnoland 2136189499Srnoland drm_rmmap(dev, dev_priv->mmio); 2137189499Srnoland 2138145132Sanholt drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); 2139145132Sanholt 2140145132Sanholt dev->dev_private = NULL; 2141145132Sanholt return 0; 2142145132Sanholt} 2143189499Srnoland 2144189499Srnolandvoid radeon_commit_ring(drm_radeon_private_t *dev_priv) 2145189499Srnoland{ 2146189499Srnoland int i; 2147189499Srnoland u32 *ring; 2148189499Srnoland int tail_aligned; 2149189499Srnoland 2150189499Srnoland /* check if the ring is padded out to 16-dword alignment */ 2151189499Srnoland 2152189499Srnoland tail_aligned = dev_priv->ring.tail & 0xf; 2153189499Srnoland if (tail_aligned) { 2154189499Srnoland int num_p2 = 16 - tail_aligned; 2155189499Srnoland 2156189499Srnoland ring = dev_priv->ring.start; 2157189499Srnoland /* pad with some CP_PACKET2 */ 2158189499Srnoland for (i = 0; i < num_p2; i++) 2159189499Srnoland ring[dev_priv->ring.tail + i] = CP_PACKET2(); 2160189499Srnoland 2161189499Srnoland dev_priv->ring.tail += i; 2162189499Srnoland 2163189499Srnoland dev_priv->ring.space -= num_p2 * sizeof(u32); 2164189499Srnoland } 2165189499Srnoland 2166189499Srnoland dev_priv->ring.tail &= dev_priv->ring.tail_mask; 2167189499Srnoland 2168189499Srnoland DRM_MEMORYBARRIER(); 2169189499Srnoland GET_RING_HEAD( dev_priv ); 2170189499Srnoland 2171189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { 2172189499Srnoland RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail); 2173189499Srnoland /* read from PCI bus to ensure correct posting */ 2174189499Srnoland RADEON_READ(R600_CP_RB_RPTR); 2175189499Srnoland } else { 2176189499Srnoland RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail); 2177189499Srnoland /* read from PCI bus to ensure correct posting */ 2178189499Srnoland RADEON_READ(RADEON_CP_RB_RPTR); 2179189499Srnoland } 2180189499Srnoland} 2181