radeon_cp.c revision 183830
1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */ 2/*- 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2007 Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Kevin E. Martin <martin@valinux.com> 29 * Gareth Hughes <gareth@valinux.com> 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_cp.c 183830 2008-10-13 17:43:39Z rnoland $"); 34 35#include "dev/drm/drmP.h" 36#include "dev/drm/drm.h" 37#include "dev/drm/radeon_drm.h" 38#include "dev/drm/radeon_drv.h" 39#include "dev/drm/r300_reg.h" 40 41#include "dev/drm/radeon_microcode.h" 42#define RADEON_FIFO_DEBUG 0 43 44static int radeon_do_cleanup_cp(struct drm_device * dev); 45static void radeon_do_cp_start(drm_radeon_private_t * dev_priv); 46 47static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 48{ 49 u32 ret; 50 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); 51 ret = RADEON_READ(R520_MC_IND_DATA); 52 RADEON_WRITE(R520_MC_IND_INDEX, 0); 53 return ret; 54} 55 56static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 57{ 58 u32 ret; 59 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); 60 ret = RADEON_READ(RS480_NB_MC_DATA); 61 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); 62 return ret; 63} 64 65static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 66{ 67 u32 ret; 68 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); 69 ret = RADEON_READ(RS690_MC_DATA); 70 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK); 71 return ret; 72} 73 74static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 75{ 76 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 77 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 78 return RS690_READ_MCIND(dev_priv, addr); 79 else 80 return RS480_READ_MCIND(dev_priv, addr); 81} 82 83u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) 84{ 85 86 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 87 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); 88 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 89 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 90 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); 91 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 92 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); 93 else 94 return RADEON_READ(RADEON_MC_FB_LOCATION); 95} 96 97static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) 98{ 99 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 100 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); 101 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 102 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 103 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); 104 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 105 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); 106 else 107 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); 108} 109 110static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) 111{ 112 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 113 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); 114 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 115 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 116 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); 117 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 118 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); 119 else 120 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); 121} 122 123static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) 124{ 125 u32 agp_base_hi = upper_32_bits(agp_base); 126 u32 agp_base_lo = agp_base & 0xffffffff; 127 128 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) { 129 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo); 130 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi); 131 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 132 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 133 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo); 134 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi); 135 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { 136 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); 137 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); 138 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || 139 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { 140 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); 141 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi); 142 } else { 143 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); 144 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) 145 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi); 146 } 147} 148 149static int RADEON_READ_PLL(struct drm_device * dev, int addr) 150{ 151 drm_radeon_private_t *dev_priv = dev->dev_private; 152 153 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); 154 return RADEON_READ(RADEON_CLOCK_CNTL_DATA); 155} 156 157static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) 158{ 159 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); 160 return RADEON_READ(RADEON_PCIE_DATA); 161} 162 163#if RADEON_FIFO_DEBUG 164static void radeon_status(drm_radeon_private_t * dev_priv) 165{ 166 printk("%s:\n", __FUNCTION__); 167 printk("RBBM_STATUS = 0x%08x\n", 168 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); 169 printk("CP_RB_RTPR = 0x%08x\n", 170 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); 171 printk("CP_RB_WTPR = 0x%08x\n", 172 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); 173 printk("AIC_CNTL = 0x%08x\n", 174 (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); 175 printk("AIC_STAT = 0x%08x\n", 176 (unsigned int)RADEON_READ(RADEON_AIC_STAT)); 177 printk("AIC_PT_BASE = 0x%08x\n", 178 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); 179 printk("TLB_ADDR = 0x%08x\n", 180 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); 181 printk("TLB_DATA = 0x%08x\n", 182 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); 183} 184#endif 185 186/* ================================================================ 187 * Engine, FIFO control 188 */ 189 190static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) 191{ 192 u32 tmp; 193 int i; 194 195 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 196 197 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { 198 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); 199 tmp |= RADEON_RB3D_DC_FLUSH_ALL; 200 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); 201 202 for (i = 0; i < dev_priv->usec_timeout; i++) { 203 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) 204 & RADEON_RB3D_DC_BUSY)) { 205 return 0; 206 } 207 DRM_UDELAY(1); 208 } 209 } else { 210 /* don't flush or purge cache here or lockup */ 211 return 0; 212 } 213 214#if RADEON_FIFO_DEBUG 215 DRM_ERROR("failed!\n"); 216 radeon_status(dev_priv); 217#endif 218 return -EBUSY; 219} 220 221static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) 222{ 223 int i; 224 225 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 226 227 for (i = 0; i < dev_priv->usec_timeout; i++) { 228 int slots = (RADEON_READ(RADEON_RBBM_STATUS) 229 & RADEON_RBBM_FIFOCNT_MASK); 230 if (slots >= entries) 231 return 0; 232 DRM_UDELAY(1); 233 } 234 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", 235 RADEON_READ(RADEON_RBBM_STATUS), 236 RADEON_READ(R300_VAP_CNTL_STATUS)); 237 238#if RADEON_FIFO_DEBUG 239 DRM_ERROR("failed!\n"); 240 radeon_status(dev_priv); 241#endif 242 return -EBUSY; 243} 244 245static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) 246{ 247 int i, ret; 248 249 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 250 251 ret = radeon_do_wait_for_fifo(dev_priv, 64); 252 if (ret) 253 return ret; 254 255 for (i = 0; i < dev_priv->usec_timeout; i++) { 256 if (!(RADEON_READ(RADEON_RBBM_STATUS) 257 & RADEON_RBBM_ACTIVE)) { 258 radeon_do_pixcache_flush(dev_priv); 259 return 0; 260 } 261 DRM_UDELAY(1); 262 } 263 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", 264 RADEON_READ(RADEON_RBBM_STATUS), 265 RADEON_READ(R300_VAP_CNTL_STATUS)); 266 267#if RADEON_FIFO_DEBUG 268 DRM_ERROR("failed!\n"); 269 radeon_status(dev_priv); 270#endif 271 return -EBUSY; 272} 273 274static void radeon_init_pipes(drm_radeon_private_t * dev_priv) 275{ 276 uint32_t gb_tile_config, gb_pipe_sel = 0; 277 278 /* RS4xx/RS6xx/R4xx/R5xx */ 279 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { 280 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); 281 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; 282 } else { 283 /* R3xx */ 284 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || 285 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { 286 dev_priv->num_gb_pipes = 2; 287 } else { 288 /* R3Vxx */ 289 dev_priv->num_gb_pipes = 1; 290 } 291 } 292 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes); 293 294 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/); 295 296 switch(dev_priv->num_gb_pipes) { 297 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; 298 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; 299 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; 300 default: 301 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; 302 } 303 304 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { 305 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); 306 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); 307 } 308 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); 309 radeon_do_wait_for_idle(dev_priv); 310 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); 311 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) | 312 R300_DC_AUTOFLUSH_ENABLE | 313 R300_DC_DC_DISABLE_IGNORE_PE)); 314 315 316} 317 318/* ================================================================ 319 * CP control, initialization 320 */ 321 322/* Load the microcode for the CP */ 323static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) 324{ 325 int i; 326 DRM_DEBUG("\n"); 327 328 radeon_do_wait_for_idle(dev_priv); 329 330 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); 331 332 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || 333 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || 334 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || 335 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || 336 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { 337 DRM_INFO("Loading R100 Microcode\n"); 338 for (i = 0; i < 256; i++) { 339 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 340 R100_cp_microcode[i][1]); 341 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 342 R100_cp_microcode[i][0]); 343 } 344 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || 345 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || 346 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || 347 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { 348 DRM_INFO("Loading R200 Microcode\n"); 349 for (i = 0; i < 256; i++) { 350 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 351 R200_cp_microcode[i][1]); 352 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 353 R200_cp_microcode[i][0]); 354 } 355 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || 356 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || 357 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || 358 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || 359 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || 360 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { 361 DRM_INFO("Loading R300 Microcode\n"); 362 for (i = 0; i < 256; i++) { 363 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 364 R300_cp_microcode[i][1]); 365 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 366 R300_cp_microcode[i][0]); 367 } 368 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || 369 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) || 370 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { 371 DRM_INFO("Loading R400 Microcode\n"); 372 for (i = 0; i < 256; i++) { 373 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 374 R420_cp_microcode[i][1]); 375 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 376 R420_cp_microcode[i][0]); 377 } 378 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 379 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 380 DRM_INFO("Loading RS690/RS740 Microcode\n"); 381 for (i = 0; i < 256; i++) { 382 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 383 RS690_cp_microcode[i][1]); 384 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 385 RS690_cp_microcode[i][0]); 386 } 387 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || 388 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || 389 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || 390 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) || 391 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || 392 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { 393 DRM_INFO("Loading R500 Microcode\n"); 394 for (i = 0; i < 256; i++) { 395 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 396 R520_cp_microcode[i][1]); 397 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 398 R520_cp_microcode[i][0]); 399 } 400 } 401} 402 403/* Flush any pending commands to the CP. This should only be used just 404 * prior to a wait for idle, as it informs the engine that the command 405 * stream is ending. 406 */ 407static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) 408{ 409 DRM_DEBUG("\n"); 410#if 0 411 u32 tmp; 412 413 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); 414 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); 415#endif 416} 417 418/* Wait for the CP to go idle. 419 */ 420int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) 421{ 422 RING_LOCALS; 423 DRM_DEBUG("\n"); 424 425 BEGIN_RING(6); 426 427 RADEON_PURGE_CACHE(); 428 RADEON_PURGE_ZCACHE(); 429 RADEON_WAIT_UNTIL_IDLE(); 430 431 ADVANCE_RING(); 432 COMMIT_RING(); 433 434 return radeon_do_wait_for_idle(dev_priv); 435} 436 437/* Start the Command Processor. 438 */ 439static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) 440{ 441 RING_LOCALS; 442 DRM_DEBUG("\n"); 443 444 radeon_do_wait_for_idle(dev_priv); 445 446 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); 447 448 dev_priv->cp_running = 1; 449 450 BEGIN_RING(8); 451 /* isync can only be written through cp on r5xx write it here */ 452 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); 453 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | 454 RADEON_ISYNC_ANY3D_IDLE2D | 455 RADEON_ISYNC_WAIT_IDLEGUI | 456 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 457 RADEON_PURGE_CACHE(); 458 RADEON_PURGE_ZCACHE(); 459 RADEON_WAIT_UNTIL_IDLE(); 460 ADVANCE_RING(); 461 COMMIT_RING(); 462 463 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED; 464} 465 466/* Reset the Command Processor. This will not flush any pending 467 * commands, so you must wait for the CP command stream to complete 468 * before calling this routine. 469 */ 470static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) 471{ 472 u32 cur_read_ptr; 473 DRM_DEBUG("\n"); 474 475 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); 476 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); 477 SET_RING_HEAD(dev_priv, cur_read_ptr); 478 dev_priv->ring.tail = cur_read_ptr; 479} 480 481/* Stop the Command Processor. This will not flush any pending 482 * commands, so you must flush the command stream and wait for the CP 483 * to go idle before calling this routine. 484 */ 485static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) 486{ 487 DRM_DEBUG("\n"); 488 489 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); 490 491 dev_priv->cp_running = 0; 492} 493 494/* Reset the engine. This will stop the CP if it is running. 495 */ 496static int radeon_do_engine_reset(struct drm_device * dev) 497{ 498 drm_radeon_private_t *dev_priv = dev->dev_private; 499 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset; 500 DRM_DEBUG("\n"); 501 502 radeon_do_pixcache_flush(dev_priv); 503 504 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { 505 /* may need something similar for newer chips */ 506 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); 507 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); 508 509 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | 510 RADEON_FORCEON_MCLKA | 511 RADEON_FORCEON_MCLKB | 512 RADEON_FORCEON_YCLKA | 513 RADEON_FORCEON_YCLKB | 514 RADEON_FORCEON_MC | 515 RADEON_FORCEON_AIC)); 516 } 517 518 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); 519 520 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | 521 RADEON_SOFT_RESET_CP | 522 RADEON_SOFT_RESET_HI | 523 RADEON_SOFT_RESET_SE | 524 RADEON_SOFT_RESET_RE | 525 RADEON_SOFT_RESET_PP | 526 RADEON_SOFT_RESET_E2 | 527 RADEON_SOFT_RESET_RB)); 528 RADEON_READ(RADEON_RBBM_SOFT_RESET); 529 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & 530 ~(RADEON_SOFT_RESET_CP | 531 RADEON_SOFT_RESET_HI | 532 RADEON_SOFT_RESET_SE | 533 RADEON_SOFT_RESET_RE | 534 RADEON_SOFT_RESET_PP | 535 RADEON_SOFT_RESET_E2 | 536 RADEON_SOFT_RESET_RB))); 537 RADEON_READ(RADEON_RBBM_SOFT_RESET); 538 539 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { 540 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); 541 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); 542 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); 543 } 544 545 /* setup the raster pipes */ 546 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) 547 radeon_init_pipes(dev_priv); 548 549 /* Reset the CP ring */ 550 radeon_do_cp_reset(dev_priv); 551 552 /* The CP is no longer running after an engine reset */ 553 dev_priv->cp_running = 0; 554 555 /* Reset any pending vertex, indirect buffers */ 556 radeon_freelist_reset(dev); 557 558 return 0; 559} 560 561static void radeon_cp_init_ring_buffer(struct drm_device * dev, 562 drm_radeon_private_t * dev_priv) 563{ 564 u32 ring_start, cur_read_ptr; 565 u32 tmp; 566 567 /* Initialize the memory controller. With new memory map, the fb location 568 * is not changed, it should have been properly initialized already. Part 569 * of the problem is that the code below is bogus, assuming the GART is 570 * always appended to the fb which is not necessarily the case 571 */ 572 if (!dev_priv->new_memmap) 573 radeon_write_fb_location(dev_priv, 574 ((dev_priv->gart_vm_start - 1) & 0xffff0000) 575 | (dev_priv->fb_location >> 16)); 576 577#if __OS_HAS_AGP 578 if (dev_priv->flags & RADEON_IS_AGP) { 579 radeon_write_agp_base(dev_priv, dev->agp->base); 580 581 radeon_write_agp_location(dev_priv, 582 (((dev_priv->gart_vm_start - 1 + 583 dev_priv->gart_size) & 0xffff0000) | 584 (dev_priv->gart_vm_start >> 16))); 585 586 ring_start = (dev_priv->cp_ring->offset 587 - dev->agp->base 588 + dev_priv->gart_vm_start); 589 } else 590#endif 591 ring_start = (dev_priv->cp_ring->offset 592 - (unsigned long)dev->sg->virtual 593 + dev_priv->gart_vm_start); 594 595 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); 596 597 /* Set the write pointer delay */ 598 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); 599 600 /* Initialize the ring buffer's read and write pointers */ 601 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); 602 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); 603 SET_RING_HEAD(dev_priv, cur_read_ptr); 604 dev_priv->ring.tail = cur_read_ptr; 605 606#if __OS_HAS_AGP 607 if (dev_priv->flags & RADEON_IS_AGP) { 608 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, 609 dev_priv->ring_rptr->offset 610 - dev->agp->base + dev_priv->gart_vm_start); 611 } else 612#endif 613 { 614 struct drm_sg_mem *entry = dev->sg; 615 unsigned long tmp_ofs, page_ofs; 616 617 tmp_ofs = dev_priv->ring_rptr->offset - 618 (unsigned long)dev->sg->virtual; 619 page_ofs = tmp_ofs >> PAGE_SHIFT; 620 621 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); 622 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n", 623 (unsigned long)entry->busaddr[page_ofs], 624 entry->handle + tmp_ofs); 625 } 626 627 /* Set ring buffer size */ 628#ifdef __BIG_ENDIAN 629 RADEON_WRITE(RADEON_CP_RB_CNTL, 630 RADEON_BUF_SWAP_32BIT | 631 (dev_priv->ring.fetch_size_l2ow << 18) | 632 (dev_priv->ring.rptr_update_l2qw << 8) | 633 dev_priv->ring.size_l2qw); 634#else 635 RADEON_WRITE(RADEON_CP_RB_CNTL, 636 (dev_priv->ring.fetch_size_l2ow << 18) | 637 (dev_priv->ring.rptr_update_l2qw << 8) | 638 dev_priv->ring.size_l2qw); 639#endif 640 641 /* Initialize the scratch register pointer. This will cause 642 * the scratch register values to be written out to memory 643 * whenever they are updated. 644 * 645 * We simply put this behind the ring read pointer, this works 646 * with PCI GART as well as (whatever kind of) AGP GART 647 */ 648 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) 649 + RADEON_SCRATCH_REG_OFFSET); 650 651 dev_priv->scratch = ((__volatile__ u32 *) 652 dev_priv->ring_rptr->handle + 653 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); 654 655 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); 656 657 /* Turn on bus mastering */ 658 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || 659 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 660 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 661 /* rs400, rs690/rs740 */ 662 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS; 663 RADEON_WRITE(RADEON_BUS_CNTL, tmp); 664 } else if (!(((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || 665 ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R423))) { 666 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */ 667 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 668 RADEON_WRITE(RADEON_BUS_CNTL, tmp); 669 } /* PCIE cards appears to not need this */ 670 671 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; 672 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); 673 674 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; 675 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 676 dev_priv->sarea_priv->last_dispatch); 677 678 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; 679 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear); 680 681 radeon_do_wait_for_idle(dev_priv); 682 683 /* Sync everything up */ 684 RADEON_WRITE(RADEON_ISYNC_CNTL, 685 (RADEON_ISYNC_ANY2D_IDLE3D | 686 RADEON_ISYNC_ANY3D_IDLE2D | 687 RADEON_ISYNC_WAIT_IDLEGUI | 688 RADEON_ISYNC_CPSCRATCH_IDLEGUI)); 689 690} 691 692static void radeon_test_writeback(drm_radeon_private_t * dev_priv) 693{ 694 u32 tmp; 695 696 /* Writeback doesn't seem to work everywhere, test it here and possibly 697 * enable it if it appears to work 698 */ 699 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0); 700 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); 701 702 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 703 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) == 704 0xdeadbeef) 705 break; 706 DRM_UDELAY(1); 707 } 708 709 if (tmp < dev_priv->usec_timeout) { 710 dev_priv->writeback_works = 1; 711 DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 712 } else { 713 dev_priv->writeback_works = 0; 714 DRM_INFO("writeback test failed\n"); 715 } 716 if (radeon_no_wb == 1) { 717 dev_priv->writeback_works = 0; 718 DRM_INFO("writeback forced off\n"); 719 } 720 721 if (!dev_priv->writeback_works) { 722 /* Disable writeback to avoid unnecessary bus master transfers */ 723 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE); 724 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0); 725 } 726} 727 728/* Enable or disable IGP GART on the chip */ 729static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) 730{ 731 u32 temp; 732 733 if (on) { 734 DRM_DEBUG("programming igp gart %08X %08lX %08X\n", 735 dev_priv->gart_vm_start, 736 (long)dev_priv->gart_info.bus_addr, 737 dev_priv->gart_size); 738 739 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); 740 741 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 742 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 743 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | 744 RS690_BLOCK_GFX_D3_EN)); 745 else 746 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); 747 748 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | 749 RS480_VA_SIZE_32MB)); 750 751 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); 752 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN | 753 RS480_TLB_ENABLE | 754 RS480_GTW_LAC_EN | 755 RS480_1LEVEL_GART)); 756 757 temp = dev_priv->gart_info.bus_addr & 0xfffff000; 758 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; 759 IGP_WRITE_MCIND(RS480_GART_BASE, temp); 760 761 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); 762 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | 763 RS480_REQ_TYPE_SNOOP_DIS)); 764 765 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start); 766 767 dev_priv->gart_size = 32*1024*1024; 768 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & 769 0xffff0000) | (dev_priv->gart_vm_start >> 16)); 770 771 radeon_write_agp_location(dev_priv, temp); 772 773 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); 774 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | 775 RS480_VA_SIZE_32MB)); 776 777 do { 778 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 779 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) 780 break; 781 DRM_UDELAY(1); 782 } while(1); 783 784 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 785 RS480_GART_CACHE_INVALIDATE); 786 787 do { 788 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 789 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) 790 break; 791 DRM_UDELAY(1); 792 } while(1); 793 794 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); 795 } else { 796 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 797 } 798} 799 800static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) 801{ 802 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); 803 if (on) { 804 805 DRM_DEBUG("programming pcie %08X %08lX %08X\n", 806 dev_priv->gart_vm_start, 807 (long)dev_priv->gart_info.bus_addr, 808 dev_priv->gart_size); 809 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, 810 dev_priv->gart_vm_start); 811 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, 812 dev_priv->gart_info.bus_addr); 813 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, 814 dev_priv->gart_vm_start); 815 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, 816 dev_priv->gart_vm_start + 817 dev_priv->gart_size - 1); 818 819 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ 820 821 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, 822 RADEON_PCIE_TX_GART_EN); 823 } else { 824 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, 825 tmp & ~RADEON_PCIE_TX_GART_EN); 826 } 827} 828 829/* Enable or disable PCI GART on the chip */ 830static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) 831{ 832 u32 tmp; 833 834 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 835 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) || 836 (dev_priv->flags & RADEON_IS_IGPGART)) { 837 radeon_set_igpgart(dev_priv, on); 838 return; 839 } 840 841 if (dev_priv->flags & RADEON_IS_PCIE) { 842 radeon_set_pciegart(dev_priv, on); 843 return; 844 } 845 846 tmp = RADEON_READ(RADEON_AIC_CNTL); 847 848 if (on) { 849 RADEON_WRITE(RADEON_AIC_CNTL, 850 tmp | RADEON_PCIGART_TRANSLATE_EN); 851 852 /* set PCI GART page-table base address 853 */ 854 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); 855 856 /* set address range for PCI address translate 857 */ 858 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); 859 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start 860 + dev_priv->gart_size - 1); 861 862 /* Turn off AGP aperture -- is this required for PCI GART? 863 */ 864 radeon_write_agp_location(dev_priv, 0xffffffc0); 865 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ 866 } else { 867 RADEON_WRITE(RADEON_AIC_CNTL, 868 tmp & ~RADEON_PCIGART_TRANSLATE_EN); 869 } 870} 871 872static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) 873{ 874 drm_radeon_private_t *dev_priv = dev->dev_private; 875 876 DRM_DEBUG("\n"); 877 878 /* if we require new memory map but we don't have it fail */ 879 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 880 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 881 radeon_do_cleanup_cp(dev); 882 return -EINVAL; 883 } 884 885 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) 886 { 887 DRM_DEBUG("Forcing AGP card to PCI mode\n"); 888 dev_priv->flags &= ~RADEON_IS_AGP; 889 } 890 else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) 891 && !init->is_pci) 892 { 893 DRM_DEBUG("Restoring AGP flag\n"); 894 dev_priv->flags |= RADEON_IS_AGP; 895 } 896 897 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { 898 DRM_ERROR("PCI GART memory not allocated!\n"); 899 radeon_do_cleanup_cp(dev); 900 return -EINVAL; 901 } 902 903 dev_priv->usec_timeout = init->usec_timeout; 904 if (dev_priv->usec_timeout < 1 || 905 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 906 DRM_DEBUG("TIMEOUT problem!\n"); 907 radeon_do_cleanup_cp(dev); 908 return -EINVAL; 909 } 910 911 /* Enable vblank on CRTC1 for older X servers 912 */ 913 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 914 915 dev_priv->do_boxes = 0; 916 dev_priv->cp_mode = init->cp_mode; 917 918 /* We don't support anything other than bus-mastering ring mode, 919 * but the ring can be in either AGP or PCI space for the ring 920 * read pointer. 921 */ 922 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 923 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 924 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 925 radeon_do_cleanup_cp(dev); 926 return -EINVAL; 927 } 928 929 switch (init->fb_bpp) { 930 case 16: 931 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 932 break; 933 case 32: 934 default: 935 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 936 break; 937 } 938 dev_priv->front_offset = init->front_offset; 939 dev_priv->front_pitch = init->front_pitch; 940 dev_priv->back_offset = init->back_offset; 941 dev_priv->back_pitch = init->back_pitch; 942 943 switch (init->depth_bpp) { 944 case 16: 945 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 946 break; 947 case 32: 948 default: 949 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 950 break; 951 } 952 dev_priv->depth_offset = init->depth_offset; 953 dev_priv->depth_pitch = init->depth_pitch; 954 955 /* Hardware state for depth clears. Remove this if/when we no 956 * longer clear the depth buffer with a 3D rectangle. Hard-code 957 * all values to prevent unwanted 3D state from slipping through 958 * and screwing with the clear operation. 959 */ 960 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | 961 (dev_priv->color_fmt << 10) | 962 (dev_priv->chip_family < CHIP_R200 ? RADEON_ZBLOCK16 : 0)); 963 964 dev_priv->depth_clear.rb3d_zstencilcntl = 965 (dev_priv->depth_fmt | 966 RADEON_Z_TEST_ALWAYS | 967 RADEON_STENCIL_TEST_ALWAYS | 968 RADEON_STENCIL_S_FAIL_REPLACE | 969 RADEON_STENCIL_ZPASS_REPLACE | 970 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); 971 972 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | 973 RADEON_BFACE_SOLID | 974 RADEON_FFACE_SOLID | 975 RADEON_FLAT_SHADE_VTX_LAST | 976 RADEON_DIFFUSE_SHADE_FLAT | 977 RADEON_ALPHA_SHADE_FLAT | 978 RADEON_SPECULAR_SHADE_FLAT | 979 RADEON_FOG_SHADE_FLAT | 980 RADEON_VTX_PIX_CENTER_OGL | 981 RADEON_ROUND_MODE_TRUNC | 982 RADEON_ROUND_PREC_8TH_PIX); 983 984 985 dev_priv->ring_offset = init->ring_offset; 986 dev_priv->ring_rptr_offset = init->ring_rptr_offset; 987 dev_priv->buffers_offset = init->buffers_offset; 988 dev_priv->gart_textures_offset = init->gart_textures_offset; 989 990 dev_priv->sarea = drm_getsarea(dev); 991 if (!dev_priv->sarea) { 992 DRM_ERROR("could not find sarea!\n"); 993 radeon_do_cleanup_cp(dev); 994 return -EINVAL; 995 } 996 997 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 998 if (!dev_priv->cp_ring) { 999 DRM_ERROR("could not find cp ring region!\n"); 1000 radeon_do_cleanup_cp(dev); 1001 return -EINVAL; 1002 } 1003 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1004 if (!dev_priv->ring_rptr) { 1005 DRM_ERROR("could not find ring read pointer!\n"); 1006 radeon_do_cleanup_cp(dev); 1007 return -EINVAL; 1008 } 1009 dev->agp_buffer_token = init->buffers_offset; 1010 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1011 if (!dev->agp_buffer_map) { 1012 DRM_ERROR("could not find dma buffer region!\n"); 1013 radeon_do_cleanup_cp(dev); 1014 return -EINVAL; 1015 } 1016 1017 if (init->gart_textures_offset) { 1018 dev_priv->gart_textures = 1019 drm_core_findmap(dev, init->gart_textures_offset); 1020 if (!dev_priv->gart_textures) { 1021 DRM_ERROR("could not find GART texture region!\n"); 1022 radeon_do_cleanup_cp(dev); 1023 return -EINVAL; 1024 } 1025 } 1026 1027 dev_priv->sarea_priv = 1028 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + 1029 init->sarea_priv_offset); 1030 1031#if __OS_HAS_AGP 1032 if (dev_priv->flags & RADEON_IS_AGP) { 1033 drm_core_ioremap(dev_priv->cp_ring, dev); 1034 drm_core_ioremap(dev_priv->ring_rptr, dev); 1035 drm_core_ioremap(dev->agp_buffer_map, dev); 1036 if (!dev_priv->cp_ring->handle || 1037 !dev_priv->ring_rptr->handle || 1038 !dev->agp_buffer_map->handle) { 1039 DRM_ERROR("could not find ioremap agp regions!\n"); 1040 radeon_do_cleanup_cp(dev); 1041 return -EINVAL; 1042 } 1043 } else 1044#endif 1045 { 1046 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; 1047 dev_priv->ring_rptr->handle = 1048 (void *)dev_priv->ring_rptr->offset; 1049 dev->agp_buffer_map->handle = 1050 (void *)dev->agp_buffer_map->offset; 1051 1052 DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 1053 dev_priv->cp_ring->handle); 1054 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 1055 dev_priv->ring_rptr->handle); 1056 DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 1057 dev->agp_buffer_map->handle); 1058 } 1059 1060 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16; 1061 dev_priv->fb_size = 1062 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000) 1063 - dev_priv->fb_location; 1064 1065 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 1066 ((dev_priv->front_offset 1067 + dev_priv->fb_location) >> 10)); 1068 1069 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 1070 ((dev_priv->back_offset 1071 + dev_priv->fb_location) >> 10)); 1072 1073 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 1074 ((dev_priv->depth_offset 1075 + dev_priv->fb_location) >> 10)); 1076 1077 dev_priv->gart_size = init->gart_size; 1078 1079 /* New let's set the memory map ... */ 1080 if (dev_priv->new_memmap) { 1081 u32 base = 0; 1082 1083 DRM_INFO("Setting GART location based on new memory map\n"); 1084 1085 /* If using AGP, try to locate the AGP aperture at the same 1086 * location in the card and on the bus, though we have to 1087 * align it down. 1088 */ 1089#if __OS_HAS_AGP 1090 if (dev_priv->flags & RADEON_IS_AGP) { 1091 base = dev->agp->base; 1092 /* Check if valid */ 1093 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && 1094 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { 1095 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 1096 dev->agp->base); 1097 base = 0; 1098 } 1099 } 1100#endif 1101 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 1102 if (base == 0) { 1103 base = dev_priv->fb_location + dev_priv->fb_size; 1104 if (base < dev_priv->fb_location || 1105 ((base + dev_priv->gart_size) & 0xfffffffful) < base) 1106 base = dev_priv->fb_location 1107 - dev_priv->gart_size; 1108 } 1109 dev_priv->gart_vm_start = base & 0xffc00000u; 1110 if (dev_priv->gart_vm_start != base) 1111 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 1112 base, dev_priv->gart_vm_start); 1113 } else { 1114 DRM_INFO("Setting GART location based on old memory map\n"); 1115 dev_priv->gart_vm_start = dev_priv->fb_location + 1116 RADEON_READ(RADEON_CONFIG_APER_SIZE); 1117 } 1118 1119#if __OS_HAS_AGP 1120 if (dev_priv->flags & RADEON_IS_AGP) 1121 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1122 - dev->agp->base 1123 + dev_priv->gart_vm_start); 1124 else 1125#endif 1126 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1127 - (unsigned long)dev->sg->virtual 1128 + dev_priv->gart_vm_start); 1129 1130 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 1131 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); 1132 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", 1133 dev_priv->gart_buffers_offset); 1134 1135 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 1136 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 1137 + init->ring_size / sizeof(u32)); 1138 dev_priv->ring.size = init->ring_size; 1139 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 1140 1141 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; 1142 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8); 1143 1144 dev_priv->ring.fetch_size = /* init->fetch_size */ 32; 1145 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16); 1146 1147 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 1148 1149 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 1150 1151#if __OS_HAS_AGP 1152 if (dev_priv->flags & RADEON_IS_AGP) { 1153 /* Turn off PCI GART */ 1154 radeon_set_pcigart(dev_priv, 0); 1155 } else 1156#endif 1157 { 1158 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); 1159 /* if we have an offset set from userspace */ 1160 if (dev_priv->pcigart_offset_set) { 1161 dev_priv->gart_info.bus_addr = 1162 dev_priv->pcigart_offset + dev_priv->fb_location; 1163 dev_priv->gart_info.mapping.offset = 1164 dev_priv->pcigart_offset + dev_priv->fb_aper_offset; 1165 dev_priv->gart_info.mapping.size = 1166 dev_priv->gart_info.table_size; 1167 1168 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); 1169 dev_priv->gart_info.addr = 1170 dev_priv->gart_info.mapping.handle; 1171 1172 if (dev_priv->flags & RADEON_IS_PCIE) 1173 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE; 1174 else 1175 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; 1176 dev_priv->gart_info.gart_table_location = 1177 DRM_ATI_GART_FB; 1178 1179 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 1180 dev_priv->gart_info.addr, 1181 dev_priv->pcigart_offset); 1182 } else { 1183 if (dev_priv->flags & RADEON_IS_IGPGART) 1184 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP; 1185 else 1186 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; 1187 dev_priv->gart_info.gart_table_location = 1188 DRM_ATI_GART_MAIN; 1189 dev_priv->gart_info.addr = NULL; 1190 dev_priv->gart_info.bus_addr = 0; 1191 if (dev_priv->flags & RADEON_IS_PCIE) { 1192 DRM_ERROR 1193 ("Cannot use PCI Express without GART in FB memory\n"); 1194 radeon_do_cleanup_cp(dev); 1195 return -EINVAL; 1196 } 1197 } 1198 1199 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { 1200 DRM_ERROR("failed to init PCI GART!\n"); 1201 radeon_do_cleanup_cp(dev); 1202 return -ENOMEM; 1203 } 1204 1205 /* Turn on PCI GART */ 1206 radeon_set_pcigart(dev_priv, 1); 1207 } 1208 1209 /* Start with assuming that writeback doesn't work */ 1210 dev_priv->writeback_works = 0; 1211 1212 radeon_cp_load_microcode(dev_priv); 1213 radeon_cp_init_ring_buffer(dev, dev_priv); 1214 1215 dev_priv->last_buf = 0; 1216 1217 radeon_do_engine_reset(dev); 1218 radeon_test_writeback(dev_priv); 1219 1220 return 0; 1221} 1222 1223static int radeon_do_cleanup_cp(struct drm_device * dev) 1224{ 1225 drm_radeon_private_t *dev_priv = dev->dev_private; 1226 DRM_DEBUG("\n"); 1227 1228 /* Make sure interrupts are disabled here because the uninstall ioctl 1229 * may not have been called from userspace and after dev_private 1230 * is freed, it's too late. 1231 */ 1232 if (dev->irq_enabled) 1233 drm_irq_uninstall(dev); 1234 1235#if __OS_HAS_AGP 1236 if (dev_priv->flags & RADEON_IS_AGP) { 1237 if (dev_priv->cp_ring != NULL) { 1238 drm_core_ioremapfree(dev_priv->cp_ring, dev); 1239 dev_priv->cp_ring = NULL; 1240 } 1241 if (dev_priv->ring_rptr != NULL) { 1242 drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1243 dev_priv->ring_rptr = NULL; 1244 } 1245 if (dev->agp_buffer_map != NULL) { 1246 drm_core_ioremapfree(dev->agp_buffer_map, dev); 1247 dev->agp_buffer_map = NULL; 1248 } 1249 } else 1250#endif 1251 { 1252 1253 if (dev_priv->gart_info.bus_addr) { 1254 /* Turn off PCI GART */ 1255 radeon_set_pcigart(dev_priv, 0); 1256 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) 1257 DRM_ERROR("failed to cleanup PCI GART!\n"); 1258 } 1259 1260 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) 1261 { 1262 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 1263 dev_priv->gart_info.addr = 0; 1264 } 1265 } 1266 /* only clear to the start of flags */ 1267 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1268 1269 return 0; 1270} 1271 1272/* This code will reinit the Radeon CP hardware after a resume from disc. 1273 * AFAIK, it would be very difficult to pickle the state at suspend time, so 1274 * here we make sure that all Radeon hardware initialisation is re-done without 1275 * affecting running applications. 1276 * 1277 * Charl P. Botha <http://cpbotha.net> 1278 */ 1279static int radeon_do_resume_cp(struct drm_device * dev) 1280{ 1281 drm_radeon_private_t *dev_priv = dev->dev_private; 1282 1283 if (!dev_priv) { 1284 DRM_ERROR("Called with no initialization\n"); 1285 return -EINVAL; 1286 } 1287 1288 DRM_DEBUG("Starting radeon_do_resume_cp()\n"); 1289 1290#if __OS_HAS_AGP 1291 if (dev_priv->flags & RADEON_IS_AGP) { 1292 /* Turn off PCI GART */ 1293 radeon_set_pcigart(dev_priv, 0); 1294 } else 1295#endif 1296 { 1297 /* Turn on PCI GART */ 1298 radeon_set_pcigart(dev_priv, 1); 1299 } 1300 1301 radeon_cp_load_microcode(dev_priv); 1302 radeon_cp_init_ring_buffer(dev, dev_priv); 1303 1304 radeon_do_engine_reset(dev); 1305 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); 1306 1307 DRM_DEBUG("radeon_do_resume_cp() complete\n"); 1308 1309 return 0; 1310} 1311 1312int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) 1313{ 1314 drm_radeon_init_t *init = data; 1315 1316 LOCK_TEST_WITH_RETURN(dev, file_priv); 1317 1318 if (init->func == RADEON_INIT_R300_CP) 1319 r300_init_reg_flags(dev); 1320 1321 switch (init->func) { 1322 case RADEON_INIT_CP: 1323 case RADEON_INIT_R200_CP: 1324 case RADEON_INIT_R300_CP: 1325 return radeon_do_init_cp(dev, init); 1326 case RADEON_CLEANUP_CP: 1327 return radeon_do_cleanup_cp(dev); 1328 } 1329 1330 return -EINVAL; 1331} 1332 1333int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv) 1334{ 1335 drm_radeon_private_t *dev_priv = dev->dev_private; 1336 DRM_DEBUG("\n"); 1337 1338 LOCK_TEST_WITH_RETURN(dev, file_priv); 1339 1340 if (dev_priv->cp_running) { 1341 DRM_DEBUG("while CP running\n"); 1342 return 0; 1343 } 1344 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { 1345 DRM_DEBUG("called with bogus CP mode (%d)\n", 1346 dev_priv->cp_mode); 1347 return 0; 1348 } 1349 1350 radeon_do_cp_start(dev_priv); 1351 1352 return 0; 1353} 1354 1355/* Stop the CP. The engine must have been idled before calling this 1356 * routine. 1357 */ 1358int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv) 1359{ 1360 drm_radeon_private_t *dev_priv = dev->dev_private; 1361 drm_radeon_cp_stop_t *stop = data; 1362 int ret; 1363 DRM_DEBUG("\n"); 1364 1365 LOCK_TEST_WITH_RETURN(dev, file_priv); 1366 1367 if (!dev_priv->cp_running) 1368 return 0; 1369 1370 /* Flush any pending CP commands. This ensures any outstanding 1371 * commands are exectuted by the engine before we turn it off. 1372 */ 1373 if (stop->flush) { 1374 radeon_do_cp_flush(dev_priv); 1375 } 1376 1377 /* If we fail to make the engine go idle, we return an error 1378 * code so that the DRM ioctl wrapper can try again. 1379 */ 1380 if (stop->idle) { 1381 ret = radeon_do_cp_idle(dev_priv); 1382 if (ret) 1383 return ret; 1384 } 1385 1386 /* Finally, we can turn off the CP. If the engine isn't idle, 1387 * we will get some dropped triangles as they won't be fully 1388 * rendered before the CP is shut down. 1389 */ 1390 radeon_do_cp_stop(dev_priv); 1391 1392 /* Reset the engine */ 1393 radeon_do_engine_reset(dev); 1394 1395 return 0; 1396} 1397 1398void radeon_do_release(struct drm_device * dev) 1399{ 1400 drm_radeon_private_t *dev_priv = dev->dev_private; 1401 int i, ret; 1402 1403 if (dev_priv) { 1404 if (dev_priv->cp_running) { 1405 /* Stop the cp */ 1406 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { 1407 DRM_DEBUG("radeon_do_cp_idle %d\n", ret); 1408#ifdef __linux__ 1409 schedule(); 1410#else 1411#if defined(__FreeBSD__) && __FreeBSD_version > 500000 1412 mtx_sleep(&ret, &dev->dev_lock, PZERO, "rdnrel", 1413 1); 1414#else 1415 tsleep(&ret, PZERO, "rdnrel", 1); 1416#endif 1417#endif 1418 } 1419 radeon_do_cp_stop(dev_priv); 1420 radeon_do_engine_reset(dev); 1421 } 1422 1423 /* Disable *all* interrupts */ 1424 if (dev_priv->mmio) /* remove this after permanent addmaps */ 1425 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 1426 1427 if (dev_priv->mmio) { /* remove all surfaces */ 1428 for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1429 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0); 1430 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 1431 16 * i, 0); 1432 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 1433 16 * i, 0); 1434 } 1435 } 1436 1437 /* Free memory heap structures */ 1438 radeon_mem_takedown(&(dev_priv->gart_heap)); 1439 radeon_mem_takedown(&(dev_priv->fb_heap)); 1440 1441 /* deallocate kernel resources */ 1442 radeon_do_cleanup_cp(dev); 1443 } 1444} 1445 1446/* Just reset the CP ring. Called as part of an X Server engine reset. 1447 */ 1448int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) 1449{ 1450 drm_radeon_private_t *dev_priv = dev->dev_private; 1451 DRM_DEBUG("\n"); 1452 1453 LOCK_TEST_WITH_RETURN(dev, file_priv); 1454 1455 if (!dev_priv) { 1456 DRM_DEBUG("called before init done\n"); 1457 return -EINVAL; 1458 } 1459 1460 radeon_do_cp_reset(dev_priv); 1461 1462 /* The CP is no longer running after an engine reset */ 1463 dev_priv->cp_running = 0; 1464 1465 return 0; 1466} 1467 1468int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv) 1469{ 1470 drm_radeon_private_t *dev_priv = dev->dev_private; 1471 DRM_DEBUG("\n"); 1472 1473 LOCK_TEST_WITH_RETURN(dev, file_priv); 1474 1475 return radeon_do_cp_idle(dev_priv); 1476} 1477 1478/* Added by Charl P. Botha to call radeon_do_resume_cp(). 1479 */ 1480int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv) 1481{ 1482 1483 return radeon_do_resume_cp(dev); 1484} 1485 1486int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) 1487{ 1488 DRM_DEBUG("\n"); 1489 1490 LOCK_TEST_WITH_RETURN(dev, file_priv); 1491 1492 return radeon_do_engine_reset(dev); 1493} 1494 1495/* ================================================================ 1496 * Fullscreen mode 1497 */ 1498 1499/* KW: Deprecated to say the least: 1500 */ 1501int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv) 1502{ 1503 return 0; 1504} 1505 1506/* ================================================================ 1507 * Freelist management 1508 */ 1509 1510/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through 1511 * bufs until freelist code is used. Note this hides a problem with 1512 * the scratch register * (used to keep track of last buffer 1513 * completed) being written to before * the last buffer has actually 1514 * completed rendering. 1515 * 1516 * KW: It's also a good way to find free buffers quickly. 1517 * 1518 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't 1519 * sleep. However, bugs in older versions of radeon_accel.c mean that 1520 * we essentially have to do this, else old clients will break. 1521 * 1522 * However, it does leave open a potential deadlock where all the 1523 * buffers are held by other clients, which can't release them because 1524 * they can't get the lock. 1525 */ 1526 1527struct drm_buf *radeon_freelist_get(struct drm_device * dev) 1528{ 1529 struct drm_device_dma *dma = dev->dma; 1530 drm_radeon_private_t *dev_priv = dev->dev_private; 1531 drm_radeon_buf_priv_t *buf_priv; 1532 struct drm_buf *buf; 1533 int i, t; 1534 int start; 1535 1536 if (++dev_priv->last_buf >= dma->buf_count) 1537 dev_priv->last_buf = 0; 1538 1539 start = dev_priv->last_buf; 1540 1541 for (t = 0; t < dev_priv->usec_timeout; t++) { 1542 u32 done_age = GET_SCRATCH(1); 1543 DRM_DEBUG("done_age = %d\n", done_age); 1544 for (i = start; i < dma->buf_count; i++) { 1545 buf = dma->buflist[i]; 1546 buf_priv = buf->dev_private; 1547 if (buf->file_priv == NULL || (buf->pending && 1548 buf_priv->age <= 1549 done_age)) { 1550 dev_priv->stats.requested_bufs++; 1551 buf->pending = 0; 1552 return buf; 1553 } 1554 start = 0; 1555 } 1556 1557 if (t) { 1558 DRM_UDELAY(1); 1559 dev_priv->stats.freelist_loops++; 1560 } 1561 } 1562 1563 DRM_DEBUG("returning NULL!\n"); 1564 return NULL; 1565} 1566 1567#if 0 1568struct drm_buf *radeon_freelist_get(struct drm_device * dev) 1569{ 1570 struct drm_device_dma *dma = dev->dma; 1571 drm_radeon_private_t *dev_priv = dev->dev_private; 1572 drm_radeon_buf_priv_t *buf_priv; 1573 struct drm_buf *buf; 1574 int i, t; 1575 int start; 1576 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); 1577 1578 if (++dev_priv->last_buf >= dma->buf_count) 1579 dev_priv->last_buf = 0; 1580 1581 start = dev_priv->last_buf; 1582 dev_priv->stats.freelist_loops++; 1583 1584 for (t = 0; t < 2; t++) { 1585 for (i = start; i < dma->buf_count; i++) { 1586 buf = dma->buflist[i]; 1587 buf_priv = buf->dev_private; 1588 if (buf->file_priv == 0 || (buf->pending && 1589 buf_priv->age <= 1590 done_age)) { 1591 dev_priv->stats.requested_bufs++; 1592 buf->pending = 0; 1593 return buf; 1594 } 1595 } 1596 start = 0; 1597 } 1598 1599 return NULL; 1600} 1601#endif 1602 1603void radeon_freelist_reset(struct drm_device * dev) 1604{ 1605 struct drm_device_dma *dma = dev->dma; 1606 drm_radeon_private_t *dev_priv = dev->dev_private; 1607 int i; 1608 1609 dev_priv->last_buf = 0; 1610 for (i = 0; i < dma->buf_count; i++) { 1611 struct drm_buf *buf = dma->buflist[i]; 1612 drm_radeon_buf_priv_t *buf_priv = buf->dev_private; 1613 buf_priv->age = 0; 1614 } 1615} 1616 1617/* ================================================================ 1618 * CP command submission 1619 */ 1620 1621int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) 1622{ 1623 drm_radeon_ring_buffer_t *ring = &dev_priv->ring; 1624 int i; 1625 u32 last_head = GET_RING_HEAD(dev_priv); 1626 1627 for (i = 0; i < dev_priv->usec_timeout; i++) { 1628 u32 head = GET_RING_HEAD(dev_priv); 1629 1630 ring->space = (head - ring->tail) * sizeof(u32); 1631 if (ring->space <= 0) 1632 ring->space += ring->size; 1633 if (ring->space > n) 1634 return 0; 1635 1636 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 1637 1638 if (head != last_head) 1639 i = 0; 1640 last_head = head; 1641 1642 DRM_UDELAY(1); 1643 } 1644 1645 /* FIXME: This return value is ignored in the BEGIN_RING macro! */ 1646#if RADEON_FIFO_DEBUG 1647 radeon_status(dev_priv); 1648 DRM_ERROR("failed!\n"); 1649#endif 1650 return -EBUSY; 1651} 1652 1653static int radeon_cp_get_buffers(struct drm_device *dev, 1654 struct drm_file *file_priv, 1655 struct drm_dma * d) 1656{ 1657 int i; 1658 struct drm_buf *buf; 1659 1660 for (i = d->granted_count; i < d->request_count; i++) { 1661 buf = radeon_freelist_get(dev); 1662 if (!buf) 1663 return -EBUSY; /* NOTE: broken client */ 1664 1665 buf->file_priv = file_priv; 1666 1667 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, 1668 sizeof(buf->idx))) 1669 return -EFAULT; 1670 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, 1671 sizeof(buf->total))) 1672 return -EFAULT; 1673 1674 d->granted_count++; 1675 } 1676 return 0; 1677} 1678 1679int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) 1680{ 1681 struct drm_device_dma *dma = dev->dma; 1682 int ret = 0; 1683 struct drm_dma *d = data; 1684 1685 LOCK_TEST_WITH_RETURN(dev, file_priv); 1686 1687 /* Please don't send us buffers. 1688 */ 1689 if (d->send_count != 0) { 1690 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", 1691 DRM_CURRENTPID, d->send_count); 1692 return -EINVAL; 1693 } 1694 1695 /* We'll send you buffers. 1696 */ 1697 if (d->request_count < 0 || d->request_count > dma->buf_count) { 1698 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", 1699 DRM_CURRENTPID, d->request_count, dma->buf_count); 1700 return -EINVAL; 1701 } 1702 1703 d->granted_count = 0; 1704 1705 if (d->request_count) { 1706 ret = radeon_cp_get_buffers(dev, file_priv, d); 1707 } 1708 1709 return ret; 1710} 1711 1712int radeon_driver_load(struct drm_device *dev, unsigned long flags) 1713{ 1714 drm_radeon_private_t *dev_priv; 1715 int ret = 0; 1716 1717 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); 1718 if (dev_priv == NULL) 1719 return -ENOMEM; 1720 1721 memset(dev_priv, 0, sizeof(drm_radeon_private_t)); 1722 dev->dev_private = (void *)dev_priv; 1723 dev_priv->flags = flags; 1724 1725 switch (flags & RADEON_FAMILY_MASK) { 1726 case CHIP_R100: 1727 case CHIP_RV200: 1728 case CHIP_R200: 1729 case CHIP_R300: 1730 case CHIP_R350: 1731 case CHIP_R420: 1732 case CHIP_R423: 1733 case CHIP_RV410: 1734 case CHIP_RV515: 1735 case CHIP_R520: 1736 case CHIP_RV570: 1737 case CHIP_R580: 1738 dev_priv->flags |= RADEON_HAS_HIERZ; 1739 break; 1740 default: 1741 /* all other chips have no hierarchical z buffer */ 1742 break; 1743 } 1744 1745 dev_priv->chip_family = flags & RADEON_FAMILY_MASK; 1746 if (drm_device_is_agp(dev)) 1747 dev_priv->flags |= RADEON_IS_AGP; 1748 else if (drm_device_is_pcie(dev)) 1749 dev_priv->flags |= RADEON_IS_PCIE; 1750 else 1751 dev_priv->flags |= RADEON_IS_PCI; 1752 1753 DRM_DEBUG("%s card detected\n", 1754 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); 1755 return ret; 1756} 1757 1758/* Create mappings for registers and framebuffer so userland doesn't necessarily 1759 * have to find them. 1760 */ 1761int radeon_driver_firstopen(struct drm_device *dev) 1762{ 1763 int ret; 1764 drm_local_map_t *map; 1765 drm_radeon_private_t *dev_priv = dev->dev_private; 1766 1767 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; 1768 1769 ret = drm_addmap(dev, drm_get_resource_start(dev, 2), 1770 drm_get_resource_len(dev, 2), _DRM_REGISTERS, 1771 _DRM_READ_ONLY, &dev_priv->mmio); 1772 if (ret != 0) 1773 return ret; 1774 1775 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); 1776 ret = drm_addmap(dev, dev_priv->fb_aper_offset, 1777 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, 1778 _DRM_WRITE_COMBINING, &map); 1779 if (ret != 0) 1780 return ret; 1781 1782 return 0; 1783} 1784 1785int radeon_driver_unload(struct drm_device *dev) 1786{ 1787 drm_radeon_private_t *dev_priv = dev->dev_private; 1788 1789 DRM_DEBUG("\n"); 1790 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); 1791 1792 dev->dev_private = NULL; 1793 return 0; 1794} 1795