radeon_cp.c revision 157617
1139749Simp/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */ 2139749Simp/*- 395584Sanholt * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 495584Sanholt * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 595584Sanholt * All Rights Reserved. 695584Sanholt * 795584Sanholt * Permission is hereby granted, free of charge, to any person obtaining a 895584Sanholt * copy of this software and associated documentation files (the "Software"), 995584Sanholt * to deal in the Software without restriction, including without limitation 1095584Sanholt * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1195584Sanholt * and/or sell copies of the Software, and to permit persons to whom the 1295584Sanholt * Software is furnished to do so, subject to the following conditions: 1395584Sanholt * 1495584Sanholt * The above copyright notice and this permission notice (including the next 1595584Sanholt * paragraph) shall be included in all copies or substantial portions of the 1695584Sanholt * Software. 1795584Sanholt * 1895584Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1995584Sanholt * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2095584Sanholt * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2195584Sanholt * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 2295584Sanholt * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2395584Sanholt * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 2495584Sanholt * DEALINGS IN THE SOFTWARE. 2595584Sanholt * 2695584Sanholt * Authors: 2795584Sanholt * Kevin E. Martin <martin@valinux.com> 2895584Sanholt * Gareth Hughes <gareth@valinux.com> 2995584Sanholt */ 3095584Sanholt 31152909Sanholt#include <sys/cdefs.h> 32152909Sanholt__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_cp.c 157617 2006-04-09 20:45:45Z anholt $"); 33152909Sanholt 3495584Sanholt#include "dev/drm/drmP.h" 35112015Sanholt#include "dev/drm/drm.h" 3695746Sanholt#include "dev/drm/radeon_drm.h" 3795584Sanholt#include "dev/drm/radeon_drv.h" 38148211Sanholt#include "dev/drm/r300_reg.h" 3995584Sanholt 4095584Sanholt#define RADEON_FIFO_DEBUG 0 4195584Sanholt 42145132Sanholtstatic int radeon_do_cleanup_cp(drm_device_t * dev); 4395584Sanholt 4495584Sanholt/* CP microcode (from ATI) */ 45112015Sanholtstatic u32 R200_cp_microcode[][2] = { 46145132Sanholt {0x21007000, 0000000000}, 47145132Sanholt {0x20007000, 0000000000}, 48145132Sanholt {0x000000ab, 0x00000004}, 49145132Sanholt {0x000000af, 0x00000004}, 50145132Sanholt {0x66544a49, 0000000000}, 51145132Sanholt {0x49494174, 0000000000}, 52145132Sanholt {0x54517d83, 0000000000}, 53145132Sanholt {0x498d8b64, 0000000000}, 54145132Sanholt {0x49494949, 0000000000}, 55145132Sanholt {0x49da493c, 0000000000}, 56145132Sanholt {0x49989898, 0000000000}, 57145132Sanholt {0xd34949d5, 0000000000}, 58145132Sanholt {0x9dc90e11, 0000000000}, 59145132Sanholt {0xce9b9b9b, 0000000000}, 60145132Sanholt {0x000f0000, 0x00000016}, 61145132Sanholt {0x352e232c, 0000000000}, 62145132Sanholt {0x00000013, 0x00000004}, 63145132Sanholt {0x000f0000, 0x00000016}, 64145132Sanholt {0x352e272c, 0000000000}, 65145132Sanholt {0x000f0001, 0x00000016}, 66145132Sanholt {0x3239362f, 0000000000}, 67145132Sanholt {0x000077ef, 0x00000002}, 68145132Sanholt {0x00061000, 0x00000002}, 69145132Sanholt {0x00000020, 0x0000001a}, 70145132Sanholt {0x00004000, 0x0000001e}, 71145132Sanholt {0x00061000, 0x00000002}, 72145132Sanholt {0x00000020, 0x0000001a}, 73145132Sanholt {0x00004000, 0x0000001e}, 74145132Sanholt {0x00061000, 0x00000002}, 75145132Sanholt {0x00000020, 0x0000001a}, 76145132Sanholt {0x00004000, 0x0000001e}, 77145132Sanholt {0x00000016, 0x00000004}, 78145132Sanholt {0x0003802a, 0x00000002}, 79145132Sanholt {0x040067e0, 0x00000002}, 80145132Sanholt {0x00000016, 0x00000004}, 81145132Sanholt {0x000077e0, 0x00000002}, 82145132Sanholt {0x00065000, 0x00000002}, 83145132Sanholt {0x000037e1, 0x00000002}, 84145132Sanholt {0x040067e1, 0x00000006}, 85145132Sanholt {0x000077e0, 0x00000002}, 86145132Sanholt {0x000077e1, 0x00000002}, 87145132Sanholt {0x000077e1, 0x00000006}, 88145132Sanholt {0xffffffff, 0000000000}, 89145132Sanholt {0x10000000, 0000000000}, 90145132Sanholt {0x0003802a, 0x00000002}, 91145132Sanholt {0x040067e0, 0x00000006}, 92145132Sanholt {0x00007675, 0x00000002}, 93145132Sanholt {0x00007676, 0x00000002}, 94145132Sanholt {0x00007677, 0x00000002}, 95145132Sanholt {0x00007678, 0x00000006}, 96145132Sanholt {0x0003802b, 0x00000002}, 97145132Sanholt {0x04002676, 0x00000002}, 98145132Sanholt {0x00007677, 0x00000002}, 99145132Sanholt {0x00007678, 0x00000006}, 100145132Sanholt {0x0000002e, 0x00000018}, 101145132Sanholt {0x0000002e, 0x00000018}, 102145132Sanholt {0000000000, 0x00000006}, 103145132Sanholt {0x0000002f, 0x00000018}, 104145132Sanholt {0x0000002f, 0x00000018}, 105145132Sanholt {0000000000, 0x00000006}, 106145132Sanholt {0x01605000, 0x00000002}, 107145132Sanholt {0x00065000, 0x00000002}, 108145132Sanholt {0x00098000, 0x00000002}, 109145132Sanholt {0x00061000, 0x00000002}, 110145132Sanholt {0x64c0603d, 0x00000004}, 111145132Sanholt {0x00080000, 0x00000016}, 112145132Sanholt {0000000000, 0000000000}, 113145132Sanholt {0x0400251d, 0x00000002}, 114145132Sanholt {0x00007580, 0x00000002}, 115145132Sanholt {0x00067581, 0x00000002}, 116145132Sanholt {0x04002580, 0x00000002}, 117145132Sanholt {0x00067581, 0x00000002}, 118145132Sanholt {0x00000046, 0x00000004}, 119145132Sanholt {0x00005000, 0000000000}, 120145132Sanholt {0x00061000, 0x00000002}, 121145132Sanholt {0x0000750e, 0x00000002}, 122145132Sanholt {0x00019000, 0x00000002}, 123145132Sanholt {0x00011055, 0x00000014}, 124145132Sanholt {0x00000055, 0x00000012}, 125145132Sanholt {0x0400250f, 0x00000002}, 126145132Sanholt {0x0000504a, 0x00000004}, 127145132Sanholt {0x00007565, 0x00000002}, 128145132Sanholt {0x00007566, 0x00000002}, 129145132Sanholt {0x00000051, 0x00000004}, 130145132Sanholt {0x01e655b4, 0x00000002}, 131145132Sanholt {0x4401b0dc, 0x00000002}, 132145132Sanholt {0x01c110dc, 0x00000002}, 133145132Sanholt {0x2666705d, 0x00000018}, 134145132Sanholt {0x040c2565, 0x00000002}, 135145132Sanholt {0x0000005d, 0x00000018}, 136145132Sanholt {0x04002564, 0x00000002}, 137145132Sanholt {0x00007566, 0x00000002}, 138145132Sanholt {0x00000054, 0x00000004}, 139145132Sanholt {0x00401060, 0x00000008}, 140145132Sanholt {0x00101000, 0x00000002}, 141145132Sanholt {0x000d80ff, 0x00000002}, 142145132Sanholt {0x00800063, 0x00000008}, 143145132Sanholt {0x000f9000, 0x00000002}, 144145132Sanholt {0x000e00ff, 0x00000002}, 145145132Sanholt {0000000000, 0x00000006}, 146145132Sanholt {0x00000080, 0x00000018}, 147145132Sanholt {0x00000054, 0x00000004}, 148145132Sanholt {0x00007576, 0x00000002}, 149145132Sanholt {0x00065000, 0x00000002}, 150145132Sanholt {0x00009000, 0x00000002}, 151145132Sanholt {0x00041000, 0x00000002}, 152145132Sanholt {0x0c00350e, 0x00000002}, 153145132Sanholt {0x00049000, 0x00000002}, 154145132Sanholt {0x00051000, 0x00000002}, 155145132Sanholt {0x01e785f8, 0x00000002}, 156145132Sanholt {0x00200000, 0x00000002}, 157145132Sanholt {0x00600073, 0x0000000c}, 158145132Sanholt {0x00007563, 0x00000002}, 159145132Sanholt {0x006075f0, 0x00000021}, 160145132Sanholt {0x20007068, 0x00000004}, 161145132Sanholt {0x00005068, 0x00000004}, 162145132Sanholt {0x00007576, 0x00000002}, 163145132Sanholt {0x00007577, 0x00000002}, 164145132Sanholt {0x0000750e, 0x00000002}, 165145132Sanholt {0x0000750f, 0x00000002}, 166145132Sanholt {0x00a05000, 0x00000002}, 167145132Sanholt {0x00600076, 0x0000000c}, 168145132Sanholt {0x006075f0, 0x00000021}, 169145132Sanholt {0x000075f8, 0x00000002}, 170145132Sanholt {0x00000076, 0x00000004}, 171145132Sanholt {0x000a750e, 0x00000002}, 172145132Sanholt {0x0020750f, 0x00000002}, 173145132Sanholt {0x00600079, 0x00000004}, 174145132Sanholt {0x00007570, 0x00000002}, 175145132Sanholt {0x00007571, 0x00000002}, 176145132Sanholt {0x00007572, 0x00000006}, 177145132Sanholt {0x00005000, 0x00000002}, 178145132Sanholt {0x00a05000, 0x00000002}, 179145132Sanholt {0x00007568, 0x00000002}, 180145132Sanholt {0x00061000, 0x00000002}, 181145132Sanholt {0x00000084, 0x0000000c}, 182145132Sanholt {0x00058000, 0x00000002}, 183145132Sanholt {0x0c607562, 0x00000002}, 184145132Sanholt {0x00000086, 0x00000004}, 185145132Sanholt {0x00600085, 0x00000004}, 186145132Sanholt {0x400070dd, 0000000000}, 187145132Sanholt {0x000380dd, 0x00000002}, 188145132Sanholt {0x00000093, 0x0000001c}, 189145132Sanholt {0x00065095, 0x00000018}, 190145132Sanholt {0x040025bb, 0x00000002}, 191145132Sanholt {0x00061096, 0x00000018}, 192145132Sanholt {0x040075bc, 0000000000}, 193145132Sanholt {0x000075bb, 0x00000002}, 194145132Sanholt {0x000075bc, 0000000000}, 195145132Sanholt {0x00090000, 0x00000006}, 196145132Sanholt {0x00090000, 0x00000002}, 197145132Sanholt {0x000d8002, 0x00000006}, 198145132Sanholt {0x00005000, 0x00000002}, 199145132Sanholt {0x00007821, 0x00000002}, 200145132Sanholt {0x00007800, 0000000000}, 201145132Sanholt {0x00007821, 0x00000002}, 202145132Sanholt {0x00007800, 0000000000}, 203145132Sanholt {0x01665000, 0x00000002}, 204145132Sanholt {0x000a0000, 0x00000002}, 205145132Sanholt {0x000671cc, 0x00000002}, 206145132Sanholt {0x0286f1cd, 0x00000002}, 207145132Sanholt {0x000000a3, 0x00000010}, 208145132Sanholt {0x21007000, 0000000000}, 209145132Sanholt {0x000000aa, 0x0000001c}, 210145132Sanholt {0x00065000, 0x00000002}, 211145132Sanholt {0x000a0000, 0x00000002}, 212145132Sanholt {0x00061000, 0x00000002}, 213145132Sanholt {0x000b0000, 0x00000002}, 214145132Sanholt {0x38067000, 0x00000002}, 215145132Sanholt {0x000a00a6, 0x00000004}, 216145132Sanholt {0x20007000, 0000000000}, 217145132Sanholt {0x01200000, 0x00000002}, 218145132Sanholt {0x20077000, 0x00000002}, 219145132Sanholt {0x01200000, 0x00000002}, 220145132Sanholt {0x20007000, 0000000000}, 221145132Sanholt {0x00061000, 0x00000002}, 222145132Sanholt {0x0120751b, 0x00000002}, 223145132Sanholt {0x8040750a, 0x00000002}, 224145132Sanholt {0x8040750b, 0x00000002}, 225145132Sanholt {0x00110000, 0x00000002}, 226145132Sanholt {0x000380dd, 0x00000002}, 227145132Sanholt {0x000000bd, 0x0000001c}, 228145132Sanholt {0x00061096, 0x00000018}, 229145132Sanholt {0x844075bd, 0x00000002}, 230145132Sanholt {0x00061095, 0x00000018}, 231145132Sanholt {0x840075bb, 0x00000002}, 232145132Sanholt {0x00061096, 0x00000018}, 233145132Sanholt {0x844075bc, 0x00000002}, 234145132Sanholt {0x000000c0, 0x00000004}, 235145132Sanholt {0x804075bd, 0x00000002}, 236145132Sanholt {0x800075bb, 0x00000002}, 237145132Sanholt {0x804075bc, 0x00000002}, 238145132Sanholt {0x00108000, 0x00000002}, 239145132Sanholt {0x01400000, 0x00000002}, 240145132Sanholt {0x006000c4, 0x0000000c}, 241145132Sanholt {0x20c07000, 0x00000020}, 242145132Sanholt {0x000000c6, 0x00000012}, 243145132Sanholt {0x00800000, 0x00000006}, 244145132Sanholt {0x0080751d, 0x00000006}, 245145132Sanholt {0x000025bb, 0x00000002}, 246145132Sanholt {0x000040c0, 0x00000004}, 247145132Sanholt {0x0000775c, 0x00000002}, 248145132Sanholt {0x00a05000, 0x00000002}, 249145132Sanholt {0x00661000, 0x00000002}, 250145132Sanholt {0x0460275d, 0x00000020}, 251145132Sanholt {0x00004000, 0000000000}, 252145132Sanholt {0x00007999, 0x00000002}, 253145132Sanholt {0x00a05000, 0x00000002}, 254145132Sanholt {0x00661000, 0x00000002}, 255145132Sanholt {0x0460299b, 0x00000020}, 256145132Sanholt {0x00004000, 0000000000}, 257145132Sanholt {0x01e00830, 0x00000002}, 258145132Sanholt {0x21007000, 0000000000}, 259145132Sanholt {0x00005000, 0x00000002}, 260145132Sanholt {0x00038042, 0x00000002}, 261145132Sanholt {0x040025e0, 0x00000002}, 262145132Sanholt {0x000075e1, 0000000000}, 263145132Sanholt {0x00000001, 0000000000}, 264145132Sanholt {0x000380d9, 0x00000002}, 265145132Sanholt {0x04007394, 0000000000}, 266145132Sanholt {0000000000, 0000000000}, 267145132Sanholt {0000000000, 0000000000}, 268145132Sanholt {0000000000, 0000000000}, 269145132Sanholt {0000000000, 0000000000}, 270145132Sanholt {0000000000, 0000000000}, 271145132Sanholt {0000000000, 0000000000}, 272145132Sanholt {0000000000, 0000000000}, 273145132Sanholt {0000000000, 0000000000}, 274145132Sanholt {0000000000, 0000000000}, 275145132Sanholt {0000000000, 0000000000}, 276145132Sanholt {0000000000, 0000000000}, 277145132Sanholt {0000000000, 0000000000}, 278145132Sanholt {0000000000, 0000000000}, 279145132Sanholt {0000000000, 0000000000}, 280145132Sanholt {0000000000, 0000000000}, 281145132Sanholt {0000000000, 0000000000}, 282145132Sanholt {0000000000, 0000000000}, 283145132Sanholt {0000000000, 0000000000}, 284145132Sanholt {0000000000, 0000000000}, 285145132Sanholt {0000000000, 0000000000}, 286145132Sanholt {0000000000, 0000000000}, 287145132Sanholt {0000000000, 0000000000}, 288145132Sanholt {0000000000, 0000000000}, 289145132Sanholt {0000000000, 0000000000}, 290145132Sanholt {0000000000, 0000000000}, 291145132Sanholt {0000000000, 0000000000}, 292145132Sanholt {0000000000, 0000000000}, 293145132Sanholt {0000000000, 0000000000}, 294145132Sanholt {0000000000, 0000000000}, 295145132Sanholt {0000000000, 0000000000}, 296145132Sanholt {0000000000, 0000000000}, 297145132Sanholt {0000000000, 0000000000}, 298145132Sanholt {0000000000, 0000000000}, 299145132Sanholt {0000000000, 0000000000}, 300145132Sanholt {0000000000, 0000000000}, 301145132Sanholt {0000000000, 0000000000}, 302112015Sanholt}; 303112015Sanholt 304145132Sanholtstatic u32 radeon_cp_microcode[][2] = { 305145132Sanholt {0x21007000, 0000000000}, 306145132Sanholt {0x20007000, 0000000000}, 307145132Sanholt {0x000000b4, 0x00000004}, 308145132Sanholt {0x000000b8, 0x00000004}, 309145132Sanholt {0x6f5b4d4c, 0000000000}, 310145132Sanholt {0x4c4c427f, 0000000000}, 311145132Sanholt {0x5b568a92, 0000000000}, 312145132Sanholt {0x4ca09c6d, 0000000000}, 313145132Sanholt {0xad4c4c4c, 0000000000}, 314145132Sanholt {0x4ce1af3d, 0000000000}, 315145132Sanholt {0xd8afafaf, 0000000000}, 316145132Sanholt {0xd64c4cdc, 0000000000}, 317145132Sanholt {0x4cd10d10, 0000000000}, 318145132Sanholt {0x000f0000, 0x00000016}, 319145132Sanholt {0x362f242d, 0000000000}, 320145132Sanholt {0x00000012, 0x00000004}, 321145132Sanholt {0x000f0000, 0x00000016}, 322145132Sanholt {0x362f282d, 0000000000}, 323145132Sanholt {0x000380e7, 0x00000002}, 324145132Sanholt {0x04002c97, 0x00000002}, 325145132Sanholt {0x000f0001, 0x00000016}, 326145132Sanholt {0x333a3730, 0000000000}, 327145132Sanholt {0x000077ef, 0x00000002}, 328145132Sanholt {0x00061000, 0x00000002}, 329145132Sanholt {0x00000021, 0x0000001a}, 330145132Sanholt {0x00004000, 0x0000001e}, 331145132Sanholt {0x00061000, 0x00000002}, 332145132Sanholt {0x00000021, 0x0000001a}, 333145132Sanholt {0x00004000, 0x0000001e}, 334145132Sanholt {0x00061000, 0x00000002}, 335145132Sanholt {0x00000021, 0x0000001a}, 336145132Sanholt {0x00004000, 0x0000001e}, 337145132Sanholt {0x00000017, 0x00000004}, 338145132Sanholt {0x0003802b, 0x00000002}, 339145132Sanholt {0x040067e0, 0x00000002}, 340145132Sanholt {0x00000017, 0x00000004}, 341145132Sanholt {0x000077e0, 0x00000002}, 342145132Sanholt {0x00065000, 0x00000002}, 343145132Sanholt {0x000037e1, 0x00000002}, 344145132Sanholt {0x040067e1, 0x00000006}, 345145132Sanholt {0x000077e0, 0x00000002}, 346145132Sanholt {0x000077e1, 0x00000002}, 347145132Sanholt {0x000077e1, 0x00000006}, 348145132Sanholt {0xffffffff, 0000000000}, 349145132Sanholt {0x10000000, 0000000000}, 350145132Sanholt {0x0003802b, 0x00000002}, 351145132Sanholt {0x040067e0, 0x00000006}, 352145132Sanholt {0x00007675, 0x00000002}, 353145132Sanholt {0x00007676, 0x00000002}, 354145132Sanholt {0x00007677, 0x00000002}, 355145132Sanholt {0x00007678, 0x00000006}, 356145132Sanholt {0x0003802c, 0x00000002}, 357145132Sanholt {0x04002676, 0x00000002}, 358145132Sanholt {0x00007677, 0x00000002}, 359145132Sanholt {0x00007678, 0x00000006}, 360145132Sanholt {0x0000002f, 0x00000018}, 361145132Sanholt {0x0000002f, 0x00000018}, 362145132Sanholt {0000000000, 0x00000006}, 363145132Sanholt {0x00000030, 0x00000018}, 364145132Sanholt {0x00000030, 0x00000018}, 365145132Sanholt {0000000000, 0x00000006}, 366145132Sanholt {0x01605000, 0x00000002}, 367145132Sanholt {0x00065000, 0x00000002}, 368145132Sanholt {0x00098000, 0x00000002}, 369145132Sanholt {0x00061000, 0x00000002}, 370145132Sanholt {0x64c0603e, 0x00000004}, 371145132Sanholt {0x000380e6, 0x00000002}, 372145132Sanholt {0x040025c5, 0x00000002}, 373145132Sanholt {0x00080000, 0x00000016}, 374145132Sanholt {0000000000, 0000000000}, 375145132Sanholt {0x0400251d, 0x00000002}, 376145132Sanholt {0x00007580, 0x00000002}, 377145132Sanholt {0x00067581, 0x00000002}, 378145132Sanholt {0x04002580, 0x00000002}, 379145132Sanholt {0x00067581, 0x00000002}, 380145132Sanholt {0x00000049, 0x00000004}, 381145132Sanholt {0x00005000, 0000000000}, 382145132Sanholt {0x000380e6, 0x00000002}, 383145132Sanholt {0x040025c5, 0x00000002}, 384145132Sanholt {0x00061000, 0x00000002}, 385145132Sanholt {0x0000750e, 0x00000002}, 386145132Sanholt {0x00019000, 0x00000002}, 387145132Sanholt {0x00011055, 0x00000014}, 388145132Sanholt {0x00000055, 0x00000012}, 389145132Sanholt {0x0400250f, 0x00000002}, 390145132Sanholt {0x0000504f, 0x00000004}, 391145132Sanholt {0x000380e6, 0x00000002}, 392145132Sanholt {0x040025c5, 0x00000002}, 393145132Sanholt {0x00007565, 0x00000002}, 394145132Sanholt {0x00007566, 0x00000002}, 395145132Sanholt {0x00000058, 0x00000004}, 396145132Sanholt {0x000380e6, 0x00000002}, 397145132Sanholt {0x040025c5, 0x00000002}, 398145132Sanholt {0x01e655b4, 0x00000002}, 399145132Sanholt {0x4401b0e4, 0x00000002}, 400145132Sanholt {0x01c110e4, 0x00000002}, 401145132Sanholt {0x26667066, 0x00000018}, 402145132Sanholt {0x040c2565, 0x00000002}, 403145132Sanholt {0x00000066, 0x00000018}, 404145132Sanholt {0x04002564, 0x00000002}, 405145132Sanholt {0x00007566, 0x00000002}, 406145132Sanholt {0x0000005d, 0x00000004}, 407145132Sanholt {0x00401069, 0x00000008}, 408145132Sanholt {0x00101000, 0x00000002}, 409145132Sanholt {0x000d80ff, 0x00000002}, 410145132Sanholt {0x0080006c, 0x00000008}, 411145132Sanholt {0x000f9000, 0x00000002}, 412145132Sanholt {0x000e00ff, 0x00000002}, 413145132Sanholt {0000000000, 0x00000006}, 414145132Sanholt {0x0000008f, 0x00000018}, 415145132Sanholt {0x0000005b, 0x00000004}, 416145132Sanholt {0x000380e6, 0x00000002}, 417145132Sanholt {0x040025c5, 0x00000002}, 418145132Sanholt {0x00007576, 0x00000002}, 419145132Sanholt {0x00065000, 0x00000002}, 420145132Sanholt {0x00009000, 0x00000002}, 421145132Sanholt {0x00041000, 0x00000002}, 422145132Sanholt {0x0c00350e, 0x00000002}, 423145132Sanholt {0x00049000, 0x00000002}, 424145132Sanholt {0x00051000, 0x00000002}, 425145132Sanholt {0x01e785f8, 0x00000002}, 426145132Sanholt {0x00200000, 0x00000002}, 427145132Sanholt {0x0060007e, 0x0000000c}, 428145132Sanholt {0x00007563, 0x00000002}, 429145132Sanholt {0x006075f0, 0x00000021}, 430145132Sanholt {0x20007073, 0x00000004}, 431145132Sanholt {0x00005073, 0x00000004}, 432145132Sanholt {0x000380e6, 0x00000002}, 433145132Sanholt {0x040025c5, 0x00000002}, 434145132Sanholt {0x00007576, 0x00000002}, 435145132Sanholt {0x00007577, 0x00000002}, 436145132Sanholt {0x0000750e, 0x00000002}, 437145132Sanholt {0x0000750f, 0x00000002}, 438145132Sanholt {0x00a05000, 0x00000002}, 439145132Sanholt {0x00600083, 0x0000000c}, 440145132Sanholt {0x006075f0, 0x00000021}, 441145132Sanholt {0x000075f8, 0x00000002}, 442145132Sanholt {0x00000083, 0x00000004}, 443145132Sanholt {0x000a750e, 0x00000002}, 444145132Sanholt {0x000380e6, 0x00000002}, 445145132Sanholt {0x040025c5, 0x00000002}, 446145132Sanholt {0x0020750f, 0x00000002}, 447145132Sanholt {0x00600086, 0x00000004}, 448145132Sanholt {0x00007570, 0x00000002}, 449145132Sanholt {0x00007571, 0x00000002}, 450145132Sanholt {0x00007572, 0x00000006}, 451145132Sanholt {0x000380e6, 0x00000002}, 452145132Sanholt {0x040025c5, 0x00000002}, 453145132Sanholt {0x00005000, 0x00000002}, 454145132Sanholt {0x00a05000, 0x00000002}, 455145132Sanholt {0x00007568, 0x00000002}, 456145132Sanholt {0x00061000, 0x00000002}, 457145132Sanholt {0x00000095, 0x0000000c}, 458145132Sanholt {0x00058000, 0x00000002}, 459145132Sanholt {0x0c607562, 0x00000002}, 460145132Sanholt {0x00000097, 0x00000004}, 461145132Sanholt {0x000380e6, 0x00000002}, 462145132Sanholt {0x040025c5, 0x00000002}, 463145132Sanholt {0x00600096, 0x00000004}, 464145132Sanholt {0x400070e5, 0000000000}, 465145132Sanholt {0x000380e6, 0x00000002}, 466145132Sanholt {0x040025c5, 0x00000002}, 467145132Sanholt {0x000380e5, 0x00000002}, 468145132Sanholt {0x000000a8, 0x0000001c}, 469145132Sanholt {0x000650aa, 0x00000018}, 470145132Sanholt {0x040025bb, 0x00000002}, 471145132Sanholt {0x000610ab, 0x00000018}, 472145132Sanholt {0x040075bc, 0000000000}, 473145132Sanholt {0x000075bb, 0x00000002}, 474145132Sanholt {0x000075bc, 0000000000}, 475145132Sanholt {0x00090000, 0x00000006}, 476145132Sanholt {0x00090000, 0x00000002}, 477145132Sanholt {0x000d8002, 0x00000006}, 478145132Sanholt {0x00007832, 0x00000002}, 479145132Sanholt {0x00005000, 0x00000002}, 480145132Sanholt {0x000380e7, 0x00000002}, 481145132Sanholt {0x04002c97, 0x00000002}, 482145132Sanholt {0x00007820, 0x00000002}, 483145132Sanholt {0x00007821, 0x00000002}, 484145132Sanholt {0x00007800, 0000000000}, 485145132Sanholt {0x01200000, 0x00000002}, 486145132Sanholt {0x20077000, 0x00000002}, 487145132Sanholt {0x01200000, 0x00000002}, 488145132Sanholt {0x20007000, 0x00000002}, 489145132Sanholt {0x00061000, 0x00000002}, 490145132Sanholt {0x0120751b, 0x00000002}, 491145132Sanholt {0x8040750a, 0x00000002}, 492145132Sanholt {0x8040750b, 0x00000002}, 493145132Sanholt {0x00110000, 0x00000002}, 494145132Sanholt {0x000380e5, 0x00000002}, 495145132Sanholt {0x000000c6, 0x0000001c}, 496145132Sanholt {0x000610ab, 0x00000018}, 497145132Sanholt {0x844075bd, 0x00000002}, 498145132Sanholt {0x000610aa, 0x00000018}, 499145132Sanholt {0x840075bb, 0x00000002}, 500145132Sanholt {0x000610ab, 0x00000018}, 501145132Sanholt {0x844075bc, 0x00000002}, 502145132Sanholt {0x000000c9, 0x00000004}, 503145132Sanholt {0x804075bd, 0x00000002}, 504145132Sanholt {0x800075bb, 0x00000002}, 505145132Sanholt {0x804075bc, 0x00000002}, 506145132Sanholt {0x00108000, 0x00000002}, 507145132Sanholt {0x01400000, 0x00000002}, 508145132Sanholt {0x006000cd, 0x0000000c}, 509145132Sanholt {0x20c07000, 0x00000020}, 510145132Sanholt {0x000000cf, 0x00000012}, 511145132Sanholt {0x00800000, 0x00000006}, 512145132Sanholt {0x0080751d, 0x00000006}, 513145132Sanholt {0000000000, 0000000000}, 514145132Sanholt {0x0000775c, 0x00000002}, 515145132Sanholt {0x00a05000, 0x00000002}, 516145132Sanholt {0x00661000, 0x00000002}, 517145132Sanholt {0x0460275d, 0x00000020}, 518145132Sanholt {0x00004000, 0000000000}, 519145132Sanholt {0x01e00830, 0x00000002}, 520145132Sanholt {0x21007000, 0000000000}, 521145132Sanholt {0x6464614d, 0000000000}, 522145132Sanholt {0x69687420, 0000000000}, 523145132Sanholt {0x00000073, 0000000000}, 524145132Sanholt {0000000000, 0000000000}, 525145132Sanholt {0x00005000, 0x00000002}, 526145132Sanholt {0x000380d0, 0x00000002}, 527145132Sanholt {0x040025e0, 0x00000002}, 528145132Sanholt {0x000075e1, 0000000000}, 529145132Sanholt {0x00000001, 0000000000}, 530145132Sanholt {0x000380e0, 0x00000002}, 531145132Sanholt {0x04002394, 0x00000002}, 532145132Sanholt {0x00005000, 0000000000}, 533145132Sanholt {0000000000, 0000000000}, 534145132Sanholt {0000000000, 0000000000}, 535145132Sanholt {0x00000008, 0000000000}, 536145132Sanholt {0x00000004, 0000000000}, 537145132Sanholt {0000000000, 0000000000}, 538145132Sanholt {0000000000, 0000000000}, 539145132Sanholt {0000000000, 0000000000}, 540145132Sanholt {0000000000, 0000000000}, 541145132Sanholt {0000000000, 0000000000}, 542145132Sanholt {0000000000, 0000000000}, 543145132Sanholt {0000000000, 0000000000}, 544145132Sanholt {0000000000, 0000000000}, 545145132Sanholt {0000000000, 0000000000}, 546145132Sanholt {0000000000, 0000000000}, 547145132Sanholt {0000000000, 0000000000}, 548145132Sanholt {0000000000, 0000000000}, 549145132Sanholt {0000000000, 0000000000}, 550145132Sanholt {0000000000, 0000000000}, 551145132Sanholt {0000000000, 0000000000}, 552145132Sanholt {0000000000, 0000000000}, 553145132Sanholt {0000000000, 0000000000}, 554145132Sanholt {0000000000, 0000000000}, 555145132Sanholt {0000000000, 0000000000}, 556145132Sanholt {0000000000, 0000000000}, 557145132Sanholt {0000000000, 0000000000}, 558145132Sanholt {0000000000, 0000000000}, 559145132Sanholt {0000000000, 0000000000}, 560145132Sanholt {0000000000, 0000000000}, 561145132Sanholt}; 562112015Sanholt 563145132Sanholtstatic u32 R300_cp_microcode[][2] = { 564145132Sanholt { 0x4200e000, 0000000000 }, 565145132Sanholt { 0x4000e000, 0000000000 }, 566145132Sanholt { 0x000000af, 0x00000008 }, 567145132Sanholt { 0x000000b3, 0x00000008 }, 568145132Sanholt { 0x6c5a504f, 0000000000 }, 569145132Sanholt { 0x4f4f497a, 0000000000 }, 570145132Sanholt { 0x5a578288, 0000000000 }, 571145132Sanholt { 0x4f91906a, 0000000000 }, 572145132Sanholt { 0x4f4f4f4f, 0000000000 }, 573145132Sanholt { 0x4fe24f44, 0000000000 }, 574145132Sanholt { 0x4f9c9c9c, 0000000000 }, 575145132Sanholt { 0xdc4f4fde, 0000000000 }, 576145132Sanholt { 0xa1cd4f4f, 0000000000 }, 577145132Sanholt { 0xd29d9d9d, 0000000000 }, 578145132Sanholt { 0x4f0f9fd7, 0000000000 }, 579145132Sanholt { 0x000ca000, 0x00000004 }, 580145132Sanholt { 0x000d0012, 0x00000038 }, 581145132Sanholt { 0x0000e8b4, 0x00000004 }, 582145132Sanholt { 0x000d0014, 0x00000038 }, 583145132Sanholt { 0x0000e8b6, 0x00000004 }, 584145132Sanholt { 0x000d0016, 0x00000038 }, 585145132Sanholt { 0x0000e854, 0x00000004 }, 586145132Sanholt { 0x000d0018, 0x00000038 }, 587145132Sanholt { 0x0000e855, 0x00000004 }, 588145132Sanholt { 0x000d001a, 0x00000038 }, 589145132Sanholt { 0x0000e856, 0x00000004 }, 590145132Sanholt { 0x000d001c, 0x00000038 }, 591145132Sanholt { 0x0000e857, 0x00000004 }, 592145132Sanholt { 0x000d001e, 0x00000038 }, 593145132Sanholt { 0x0000e824, 0x00000004 }, 594145132Sanholt { 0x000d0020, 0x00000038 }, 595145132Sanholt { 0x0000e825, 0x00000004 }, 596145132Sanholt { 0x000d0022, 0x00000038 }, 597145132Sanholt { 0x0000e830, 0x00000004 }, 598145132Sanholt { 0x000d0024, 0x00000038 }, 599145132Sanholt { 0x0000f0c0, 0x00000004 }, 600145132Sanholt { 0x000d0026, 0x00000038 }, 601145132Sanholt { 0x0000f0c1, 0x00000004 }, 602145132Sanholt { 0x000d0028, 0x00000038 }, 603145132Sanholt { 0x0000f041, 0x00000004 }, 604145132Sanholt { 0x000d002a, 0x00000038 }, 605145132Sanholt { 0x0000f184, 0x00000004 }, 606145132Sanholt { 0x000d002c, 0x00000038 }, 607145132Sanholt { 0x0000f185, 0x00000004 }, 608145132Sanholt { 0x000d002e, 0x00000038 }, 609145132Sanholt { 0x0000f186, 0x00000004 }, 610145132Sanholt { 0x000d0030, 0x00000038 }, 611145132Sanholt { 0x0000f187, 0x00000004 }, 612145132Sanholt { 0x000d0032, 0x00000038 }, 613145132Sanholt { 0x0000f180, 0x00000004 }, 614145132Sanholt { 0x000d0034, 0x00000038 }, 615145132Sanholt { 0x0000f393, 0x00000004 }, 616145132Sanholt { 0x000d0036, 0x00000038 }, 617145132Sanholt { 0x0000f38a, 0x00000004 }, 618145132Sanholt { 0x000d0038, 0x00000038 }, 619145132Sanholt { 0x0000f38e, 0x00000004 }, 620145132Sanholt { 0x0000e821, 0x00000004 }, 621145132Sanholt { 0x0140a000, 0x00000004 }, 622145132Sanholt { 0x00000043, 0x00000018 }, 623145132Sanholt { 0x00cce800, 0x00000004 }, 624145132Sanholt { 0x001b0001, 0x00000004 }, 625145132Sanholt { 0x08004800, 0x00000004 }, 626145132Sanholt { 0x001b0001, 0x00000004 }, 627145132Sanholt { 0x08004800, 0x00000004 }, 628145132Sanholt { 0x001b0001, 0x00000004 }, 629145132Sanholt { 0x08004800, 0x00000004 }, 630145132Sanholt { 0x0000003a, 0x00000008 }, 631145132Sanholt { 0x0000a000, 0000000000 }, 632145132Sanholt { 0x02c0a000, 0x00000004 }, 633145132Sanholt { 0x000ca000, 0x00000004 }, 634145132Sanholt { 0x00130000, 0x00000004 }, 635145132Sanholt { 0x000c2000, 0x00000004 }, 636145132Sanholt { 0xc980c045, 0x00000008 }, 637145132Sanholt { 0x2000451d, 0x00000004 }, 638145132Sanholt { 0x0000e580, 0x00000004 }, 639145132Sanholt { 0x000ce581, 0x00000004 }, 640145132Sanholt { 0x08004580, 0x00000004 }, 641145132Sanholt { 0x000ce581, 0x00000004 }, 642145132Sanholt { 0x0000004c, 0x00000008 }, 643145132Sanholt { 0x0000a000, 0000000000 }, 644145132Sanholt { 0x000c2000, 0x00000004 }, 645145132Sanholt { 0x0000e50e, 0x00000004 }, 646145132Sanholt { 0x00032000, 0x00000004 }, 647145132Sanholt { 0x00022056, 0x00000028 }, 648145132Sanholt { 0x00000056, 0x00000024 }, 649145132Sanholt { 0x0800450f, 0x00000004 }, 650145132Sanholt { 0x0000a050, 0x00000008 }, 651145132Sanholt { 0x0000e565, 0x00000004 }, 652145132Sanholt { 0x0000e566, 0x00000004 }, 653145132Sanholt { 0x00000057, 0x00000008 }, 654145132Sanholt { 0x03cca5b4, 0x00000004 }, 655145132Sanholt { 0x05432000, 0x00000004 }, 656145132Sanholt { 0x00022000, 0x00000004 }, 657145132Sanholt { 0x4ccce063, 0x00000030 }, 658145132Sanholt { 0x08274565, 0x00000004 }, 659145132Sanholt { 0x00000063, 0x00000030 }, 660145132Sanholt { 0x08004564, 0x00000004 }, 661145132Sanholt { 0x0000e566, 0x00000004 }, 662145132Sanholt { 0x0000005a, 0x00000008 }, 663145132Sanholt { 0x00802066, 0x00000010 }, 664145132Sanholt { 0x00202000, 0x00000004 }, 665145132Sanholt { 0x001b00ff, 0x00000004 }, 666145132Sanholt { 0x01000069, 0x00000010 }, 667145132Sanholt { 0x001f2000, 0x00000004 }, 668145132Sanholt { 0x001c00ff, 0x00000004 }, 669145132Sanholt { 0000000000, 0x0000000c }, 670145132Sanholt { 0x00000085, 0x00000030 }, 671145132Sanholt { 0x0000005a, 0x00000008 }, 672145132Sanholt { 0x0000e576, 0x00000004 }, 673145132Sanholt { 0x000ca000, 0x00000004 }, 674145132Sanholt { 0x00012000, 0x00000004 }, 675145132Sanholt { 0x00082000, 0x00000004 }, 676145132Sanholt { 0x1800650e, 0x00000004 }, 677145132Sanholt { 0x00092000, 0x00000004 }, 678145132Sanholt { 0x000a2000, 0x00000004 }, 679145132Sanholt { 0x000f0000, 0x00000004 }, 680145132Sanholt { 0x00400000, 0x00000004 }, 681145132Sanholt { 0x00000079, 0x00000018 }, 682145132Sanholt { 0x0000e563, 0x00000004 }, 683145132Sanholt { 0x00c0e5f9, 0x000000c2 }, 684145132Sanholt { 0x0000006e, 0x00000008 }, 685145132Sanholt { 0x0000a06e, 0x00000008 }, 686145132Sanholt { 0x0000e576, 0x00000004 }, 687145132Sanholt { 0x0000e577, 0x00000004 }, 688145132Sanholt { 0x0000e50e, 0x00000004 }, 689145132Sanholt { 0x0000e50f, 0x00000004 }, 690145132Sanholt { 0x0140a000, 0x00000004 }, 691145132Sanholt { 0x0000007c, 0x00000018 }, 692145132Sanholt { 0x00c0e5f9, 0x000000c2 }, 693145132Sanholt { 0x0000007c, 0x00000008 }, 694145132Sanholt { 0x0014e50e, 0x00000004 }, 695145132Sanholt { 0x0040e50f, 0x00000004 }, 696145132Sanholt { 0x00c0007f, 0x00000008 }, 697145132Sanholt { 0x0000e570, 0x00000004 }, 698145132Sanholt { 0x0000e571, 0x00000004 }, 699145132Sanholt { 0x0000e572, 0x0000000c }, 700145132Sanholt { 0x0000a000, 0x00000004 }, 701145132Sanholt { 0x0140a000, 0x00000004 }, 702145132Sanholt { 0x0000e568, 0x00000004 }, 703145132Sanholt { 0x000c2000, 0x00000004 }, 704145132Sanholt { 0x00000089, 0x00000018 }, 705145132Sanholt { 0x000b0000, 0x00000004 }, 706145132Sanholt { 0x18c0e562, 0x00000004 }, 707145132Sanholt { 0x0000008b, 0x00000008 }, 708145132Sanholt { 0x00c0008a, 0x00000008 }, 709145132Sanholt { 0x000700e4, 0x00000004 }, 710145132Sanholt { 0x00000097, 0x00000038 }, 711145132Sanholt { 0x000ca099, 0x00000030 }, 712145132Sanholt { 0x080045bb, 0x00000004 }, 713145132Sanholt { 0x000c209a, 0x00000030 }, 714145132Sanholt { 0x0800e5bc, 0000000000 }, 715145132Sanholt { 0x0000e5bb, 0x00000004 }, 716145132Sanholt { 0x0000e5bc, 0000000000 }, 717145132Sanholt { 0x00120000, 0x0000000c }, 718145132Sanholt { 0x00120000, 0x00000004 }, 719145132Sanholt { 0x001b0002, 0x0000000c }, 720145132Sanholt { 0x0000a000, 0x00000004 }, 721145132Sanholt { 0x0000e821, 0x00000004 }, 722145132Sanholt { 0x0000e800, 0000000000 }, 723145132Sanholt { 0x0000e821, 0x00000004 }, 724145132Sanholt { 0x0000e82e, 0000000000 }, 725145132Sanholt { 0x02cca000, 0x00000004 }, 726145132Sanholt { 0x00140000, 0x00000004 }, 727145132Sanholt { 0x000ce1cc, 0x00000004 }, 728145132Sanholt { 0x050de1cd, 0x00000004 }, 729145132Sanholt { 0x000000a7, 0x00000020 }, 730145132Sanholt { 0x4200e000, 0000000000 }, 731145132Sanholt { 0x000000ae, 0x00000038 }, 732145132Sanholt { 0x000ca000, 0x00000004 }, 733145132Sanholt { 0x00140000, 0x00000004 }, 734145132Sanholt { 0x000c2000, 0x00000004 }, 735145132Sanholt { 0x00160000, 0x00000004 }, 736145132Sanholt { 0x700ce000, 0x00000004 }, 737145132Sanholt { 0x001400aa, 0x00000008 }, 738145132Sanholt { 0x4000e000, 0000000000 }, 739145132Sanholt { 0x02400000, 0x00000004 }, 740145132Sanholt { 0x400ee000, 0x00000004 }, 741145132Sanholt { 0x02400000, 0x00000004 }, 742145132Sanholt { 0x4000e000, 0000000000 }, 743145132Sanholt { 0x000c2000, 0x00000004 }, 744145132Sanholt { 0x0240e51b, 0x00000004 }, 745145132Sanholt { 0x0080e50a, 0x00000005 }, 746145132Sanholt { 0x0080e50b, 0x00000005 }, 747145132Sanholt { 0x00220000, 0x00000004 }, 748145132Sanholt { 0x000700e4, 0x00000004 }, 749145132Sanholt { 0x000000c1, 0x00000038 }, 750145132Sanholt { 0x000c209a, 0x00000030 }, 751145132Sanholt { 0x0880e5bd, 0x00000005 }, 752145132Sanholt { 0x000c2099, 0x00000030 }, 753145132Sanholt { 0x0800e5bb, 0x00000005 }, 754145132Sanholt { 0x000c209a, 0x00000030 }, 755145132Sanholt { 0x0880e5bc, 0x00000005 }, 756145132Sanholt { 0x000000c4, 0x00000008 }, 757145132Sanholt { 0x0080e5bd, 0x00000005 }, 758145132Sanholt { 0x0000e5bb, 0x00000005 }, 759145132Sanholt { 0x0080e5bc, 0x00000005 }, 760145132Sanholt { 0x00210000, 0x00000004 }, 761145132Sanholt { 0x02800000, 0x00000004 }, 762145132Sanholt { 0x00c000c8, 0x00000018 }, 763145132Sanholt { 0x4180e000, 0x00000040 }, 764145132Sanholt { 0x000000ca, 0x00000024 }, 765145132Sanholt { 0x01000000, 0x0000000c }, 766145132Sanholt { 0x0100e51d, 0x0000000c }, 767145132Sanholt { 0x000045bb, 0x00000004 }, 768145132Sanholt { 0x000080c4, 0x00000008 }, 769145132Sanholt { 0x0000f3ce, 0x00000004 }, 770145132Sanholt { 0x0140a000, 0x00000004 }, 771145132Sanholt { 0x00cc2000, 0x00000004 }, 772145132Sanholt { 0x08c053cf, 0x00000040 }, 773145132Sanholt { 0x00008000, 0000000000 }, 774145132Sanholt { 0x0000f3d2, 0x00000004 }, 775145132Sanholt { 0x0140a000, 0x00000004 }, 776145132Sanholt { 0x00cc2000, 0x00000004 }, 777145132Sanholt { 0x08c053d3, 0x00000040 }, 778145132Sanholt { 0x00008000, 0000000000 }, 779145132Sanholt { 0x0000f39d, 0x00000004 }, 780145132Sanholt { 0x0140a000, 0x00000004 }, 781145132Sanholt { 0x00cc2000, 0x00000004 }, 782145132Sanholt { 0x08c0539e, 0x00000040 }, 783145132Sanholt { 0x00008000, 0000000000 }, 784145132Sanholt { 0x03c00830, 0x00000004 }, 785145132Sanholt { 0x4200e000, 0000000000 }, 786145132Sanholt { 0x0000a000, 0x00000004 }, 787145132Sanholt { 0x200045e0, 0x00000004 }, 788145132Sanholt { 0x0000e5e1, 0000000000 }, 789145132Sanholt { 0x00000001, 0000000000 }, 790145132Sanholt { 0x000700e1, 0x00000004 }, 791145132Sanholt { 0x0800e394, 0000000000 }, 79295584Sanholt { 0000000000, 0000000000 }, 79395584Sanholt { 0000000000, 0000000000 }, 79495584Sanholt { 0000000000, 0000000000 }, 79595584Sanholt { 0000000000, 0000000000 }, 79695584Sanholt { 0000000000, 0000000000 }, 79795584Sanholt { 0000000000, 0000000000 }, 79895584Sanholt { 0000000000, 0000000000 }, 79995584Sanholt { 0000000000, 0000000000 }, 80095584Sanholt { 0000000000, 0000000000 }, 80195584Sanholt { 0000000000, 0000000000 }, 80295584Sanholt { 0000000000, 0000000000 }, 80395584Sanholt { 0000000000, 0000000000 }, 80495584Sanholt { 0000000000, 0000000000 }, 80595584Sanholt { 0000000000, 0000000000 }, 80695584Sanholt { 0000000000, 0000000000 }, 80795584Sanholt { 0000000000, 0000000000 }, 80895584Sanholt { 0000000000, 0000000000 }, 80995584Sanholt { 0000000000, 0000000000 }, 81095584Sanholt { 0000000000, 0000000000 }, 81195584Sanholt { 0000000000, 0000000000 }, 81295584Sanholt { 0000000000, 0000000000 }, 81395584Sanholt { 0000000000, 0000000000 }, 81495584Sanholt { 0000000000, 0000000000 }, 81595584Sanholt { 0000000000, 0000000000 }, 81695584Sanholt { 0000000000, 0000000000 }, 81795584Sanholt { 0000000000, 0000000000 }, 81895584Sanholt { 0000000000, 0000000000 }, 81995584Sanholt { 0000000000, 0000000000 }, 82095584Sanholt}; 82195584Sanholt 822145132Sanholtstatic int RADEON_READ_PLL(drm_device_t * dev, int addr) 82395584Sanholt{ 82495584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 82595584Sanholt 82695584Sanholt RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); 82795584Sanholt return RADEON_READ(RADEON_CLOCK_CNTL_DATA); 82895584Sanholt} 82995584Sanholt 830148211Sanholtstatic int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) 831148211Sanholt{ 832148211Sanholt RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); 833148211Sanholt return RADEON_READ(RADEON_PCIE_DATA); 834148211Sanholt} 835148211Sanholt 83695584Sanholt#if RADEON_FIFO_DEBUG 837145132Sanholtstatic void radeon_status(drm_radeon_private_t * dev_priv) 83895584Sanholt{ 839145132Sanholt printk("%s:\n", __FUNCTION__); 840145132Sanholt printk("RBBM_STATUS = 0x%08x\n", 841145132Sanholt (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); 842145132Sanholt printk("CP_RB_RTPR = 0x%08x\n", 843145132Sanholt (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); 844145132Sanholt printk("CP_RB_WTPR = 0x%08x\n", 845145132Sanholt (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); 846145132Sanholt printk("AIC_CNTL = 0x%08x\n", 847145132Sanholt (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); 848145132Sanholt printk("AIC_STAT = 0x%08x\n", 849145132Sanholt (unsigned int)RADEON_READ(RADEON_AIC_STAT)); 850145132Sanholt printk("AIC_PT_BASE = 0x%08x\n", 851145132Sanholt (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); 852145132Sanholt printk("TLB_ADDR = 0x%08x\n", 853145132Sanholt (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); 854145132Sanholt printk("TLB_DATA = 0x%08x\n", 855145132Sanholt (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); 85695584Sanholt} 85795584Sanholt#endif 85895584Sanholt 85995584Sanholt/* ================================================================ 86095584Sanholt * Engine, FIFO control 86195584Sanholt */ 86295584Sanholt 863145132Sanholtstatic int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) 86495584Sanholt{ 86595584Sanholt u32 tmp; 86695584Sanholt int i; 86795584Sanholt 868112015Sanholt dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 869112015Sanholt 870145132Sanholt tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT); 87195584Sanholt tmp |= RADEON_RB2D_DC_FLUSH_ALL; 872145132Sanholt RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp); 87395584Sanholt 874145132Sanholt for (i = 0; i < dev_priv->usec_timeout; i++) { 875145132Sanholt if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT) 876145132Sanholt & RADEON_RB2D_DC_BUSY)) { 87795584Sanholt return 0; 87895584Sanholt } 879145132Sanholt DRM_UDELAY(1); 88095584Sanholt } 88195584Sanholt 88295584Sanholt#if RADEON_FIFO_DEBUG 883145132Sanholt DRM_ERROR("failed!\n"); 884145132Sanholt radeon_status(dev_priv); 88595584Sanholt#endif 886112015Sanholt return DRM_ERR(EBUSY); 88795584Sanholt} 88895584Sanholt 889145132Sanholtstatic int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) 89095584Sanholt{ 89195584Sanholt int i; 89295584Sanholt 893112015Sanholt dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 894112015Sanholt 895145132Sanholt for (i = 0; i < dev_priv->usec_timeout; i++) { 896145132Sanholt int slots = (RADEON_READ(RADEON_RBBM_STATUS) 897145132Sanholt & RADEON_RBBM_FIFOCNT_MASK); 898145132Sanholt if (slots >= entries) 899145132Sanholt return 0; 900145132Sanholt DRM_UDELAY(1); 90195584Sanholt } 90295584Sanholt 90395584Sanholt#if RADEON_FIFO_DEBUG 904145132Sanholt DRM_ERROR("failed!\n"); 905145132Sanholt radeon_status(dev_priv); 90695584Sanholt#endif 907112015Sanholt return DRM_ERR(EBUSY); 90895584Sanholt} 90995584Sanholt 910145132Sanholtstatic int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) 91195584Sanholt{ 91295584Sanholt int i, ret; 91395584Sanholt 914112015Sanholt dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 915112015Sanholt 916145132Sanholt ret = radeon_do_wait_for_fifo(dev_priv, 64); 917145132Sanholt if (ret) 918145132Sanholt return ret; 919112015Sanholt 920145132Sanholt for (i = 0; i < dev_priv->usec_timeout; i++) { 921145132Sanholt if (!(RADEON_READ(RADEON_RBBM_STATUS) 922145132Sanholt & RADEON_RBBM_ACTIVE)) { 923145132Sanholt radeon_do_pixcache_flush(dev_priv); 92495584Sanholt return 0; 92595584Sanholt } 926145132Sanholt DRM_UDELAY(1); 92795584Sanholt } 92895584Sanholt 92995584Sanholt#if RADEON_FIFO_DEBUG 930145132Sanholt DRM_ERROR("failed!\n"); 931145132Sanholt radeon_status(dev_priv); 93295584Sanholt#endif 933112015Sanholt return DRM_ERR(EBUSY); 93495584Sanholt} 93595584Sanholt 93695584Sanholt/* ================================================================ 93795584Sanholt * CP control, initialization 93895584Sanholt */ 93995584Sanholt 94095584Sanholt/* Load the microcode for the CP */ 941145132Sanholtstatic void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) 94295584Sanholt{ 94395584Sanholt int i; 944145132Sanholt DRM_DEBUG("\n"); 94595584Sanholt 946145132Sanholt radeon_do_wait_for_idle(dev_priv); 94795584Sanholt 948145132Sanholt RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); 949112015Sanholt 950157617Sanholt if (dev_priv->microcode_version == UCODE_R200) { 951112015Sanholt DRM_INFO("Loading R200 Microcode\n"); 952145132Sanholt for (i = 0; i < 256; i++) { 953145132Sanholt RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 954145132Sanholt R200_cp_microcode[i][1]); 955145132Sanholt RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 956145132Sanholt R200_cp_microcode[i][0]); 957112015Sanholt } 958157617Sanholt } else if (dev_priv->microcode_version == UCODE_R300) { 959145132Sanholt DRM_INFO("Loading R300 Microcode\n"); 960157617Sanholt for (i = 0; i < 256; i++) { 961157617Sanholt RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 962157617Sanholt R300_cp_microcode[i][1]); 963157617Sanholt RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 964157617Sanholt R300_cp_microcode[i][0]); 965112015Sanholt } 966145132Sanholt } else { 967145132Sanholt for (i = 0; i < 256; i++) { 968145132Sanholt RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 969145132Sanholt radeon_cp_microcode[i][1]); 970145132Sanholt RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 971145132Sanholt radeon_cp_microcode[i][0]); 972145132Sanholt } 973112015Sanholt } 97495584Sanholt} 97595584Sanholt 97695584Sanholt/* Flush any pending commands to the CP. This should only be used just 97795584Sanholt * prior to a wait for idle, as it informs the engine that the command 97895584Sanholt * stream is ending. 97995584Sanholt */ 980145132Sanholtstatic void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) 98195584Sanholt{ 982145132Sanholt DRM_DEBUG("\n"); 98395584Sanholt#if 0 98495584Sanholt u32 tmp; 98595584Sanholt 986145132Sanholt tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); 987145132Sanholt RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); 98895584Sanholt#endif 98995584Sanholt} 99095584Sanholt 99195584Sanholt/* Wait for the CP to go idle. 99295584Sanholt */ 993145132Sanholtint radeon_do_cp_idle(drm_radeon_private_t * dev_priv) 99495584Sanholt{ 99595584Sanholt RING_LOCALS; 996145132Sanholt DRM_DEBUG("\n"); 99795584Sanholt 998145132Sanholt BEGIN_RING(6); 99995584Sanholt 100095584Sanholt RADEON_PURGE_CACHE(); 100195584Sanholt RADEON_PURGE_ZCACHE(); 100295584Sanholt RADEON_WAIT_UNTIL_IDLE(); 100395584Sanholt 100495584Sanholt ADVANCE_RING(); 1005112015Sanholt COMMIT_RING(); 100695584Sanholt 1007145132Sanholt return radeon_do_wait_for_idle(dev_priv); 100895584Sanholt} 100995584Sanholt 101095584Sanholt/* Start the Command Processor. 101195584Sanholt */ 1012145132Sanholtstatic void radeon_do_cp_start(drm_radeon_private_t * dev_priv) 101395584Sanholt{ 101495584Sanholt RING_LOCALS; 1015145132Sanholt DRM_DEBUG("\n"); 101695584Sanholt 1017145132Sanholt radeon_do_wait_for_idle(dev_priv); 101895584Sanholt 1019145132Sanholt RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); 102095584Sanholt 102195584Sanholt dev_priv->cp_running = 1; 102295584Sanholt 1023145132Sanholt BEGIN_RING(6); 102495584Sanholt 102595584Sanholt RADEON_PURGE_CACHE(); 102695584Sanholt RADEON_PURGE_ZCACHE(); 102795584Sanholt RADEON_WAIT_UNTIL_IDLE(); 102895584Sanholt 102995584Sanholt ADVANCE_RING(); 1030112015Sanholt COMMIT_RING(); 103195584Sanholt} 103295584Sanholt 103395584Sanholt/* Reset the Command Processor. This will not flush any pending 103495584Sanholt * commands, so you must wait for the CP command stream to complete 103595584Sanholt * before calling this routine. 103695584Sanholt */ 1037145132Sanholtstatic void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) 103895584Sanholt{ 103995584Sanholt u32 cur_read_ptr; 1040145132Sanholt DRM_DEBUG("\n"); 104195584Sanholt 1042145132Sanholt cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); 1043145132Sanholt RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); 1044145132Sanholt SET_RING_HEAD(dev_priv, cur_read_ptr); 104595584Sanholt dev_priv->ring.tail = cur_read_ptr; 104695584Sanholt} 104795584Sanholt 104895584Sanholt/* Stop the Command Processor. This will not flush any pending 104995584Sanholt * commands, so you must flush the command stream and wait for the CP 105095584Sanholt * to go idle before calling this routine. 105195584Sanholt */ 1052145132Sanholtstatic void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) 105395584Sanholt{ 1054145132Sanholt DRM_DEBUG("\n"); 105595584Sanholt 1056145132Sanholt RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); 105795584Sanholt 105895584Sanholt dev_priv->cp_running = 0; 105995584Sanholt} 106095584Sanholt 106195584Sanholt/* Reset the engine. This will stop the CP if it is running. 106295584Sanholt */ 1063145132Sanholtstatic int radeon_do_engine_reset(drm_device_t * dev) 106495584Sanholt{ 106595584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 106695584Sanholt u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; 1067145132Sanholt DRM_DEBUG("\n"); 106895584Sanholt 1069145132Sanholt radeon_do_pixcache_flush(dev_priv); 107095584Sanholt 1071145132Sanholt clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); 1072145132Sanholt mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); 107395584Sanholt 1074145132Sanholt RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | 1075145132Sanholt RADEON_FORCEON_MCLKA | 1076145132Sanholt RADEON_FORCEON_MCLKB | 1077145132Sanholt RADEON_FORCEON_YCLKA | 1078145132Sanholt RADEON_FORCEON_YCLKB | 1079145132Sanholt RADEON_FORCEON_MC | 1080145132Sanholt RADEON_FORCEON_AIC)); 108195584Sanholt 1082145132Sanholt rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); 108395584Sanholt 1084145132Sanholt RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | 1085145132Sanholt RADEON_SOFT_RESET_CP | 1086145132Sanholt RADEON_SOFT_RESET_HI | 1087145132Sanholt RADEON_SOFT_RESET_SE | 1088145132Sanholt RADEON_SOFT_RESET_RE | 1089145132Sanholt RADEON_SOFT_RESET_PP | 1090145132Sanholt RADEON_SOFT_RESET_E2 | 1091145132Sanholt RADEON_SOFT_RESET_RB)); 1092145132Sanholt RADEON_READ(RADEON_RBBM_SOFT_RESET); 1093145132Sanholt RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & 1094145132Sanholt ~(RADEON_SOFT_RESET_CP | 109595584Sanholt RADEON_SOFT_RESET_HI | 109695584Sanholt RADEON_SOFT_RESET_SE | 109795584Sanholt RADEON_SOFT_RESET_RE | 109895584Sanholt RADEON_SOFT_RESET_PP | 109995584Sanholt RADEON_SOFT_RESET_E2 | 1100145132Sanholt RADEON_SOFT_RESET_RB))); 1101145132Sanholt RADEON_READ(RADEON_RBBM_SOFT_RESET); 110295584Sanholt 1103145132Sanholt RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); 1104145132Sanholt RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); 1105145132Sanholt RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); 110695584Sanholt 110795584Sanholt /* Reset the CP ring */ 1108145132Sanholt radeon_do_cp_reset(dev_priv); 110995584Sanholt 111095584Sanholt /* The CP is no longer running after an engine reset */ 111195584Sanholt dev_priv->cp_running = 0; 111295584Sanholt 111395584Sanholt /* Reset any pending vertex, indirect buffers */ 1114145132Sanholt radeon_freelist_reset(dev); 111595584Sanholt 111695584Sanholt return 0; 111795584Sanholt} 111895584Sanholt 1119145132Sanholtstatic void radeon_cp_init_ring_buffer(drm_device_t * dev, 1120145132Sanholt drm_radeon_private_t * dev_priv) 112195584Sanholt{ 112295584Sanholt u32 ring_start, cur_read_ptr; 112395584Sanholt u32 tmp; 1124157617Sanholt 1125157617Sanholt /* Initialize the memory controller. With new memory map, the fb location 1126157617Sanholt * is not changed, it should have been properly initialized already. Part 1127157617Sanholt * of the problem is that the code below is bogus, assuming the GART is 1128157617Sanholt * always appended to the fb which is not necessarily the case 1129157617Sanholt */ 1130157617Sanholt if (!dev_priv->new_memmap) 1131157617Sanholt RADEON_WRITE(RADEON_MC_FB_LOCATION, 1132157617Sanholt ((dev_priv->gart_vm_start - 1) & 0xffff0000) 1133157617Sanholt | (dev_priv->fb_location >> 16)); 113495584Sanholt 1135145132Sanholt#if __OS_HAS_AGP 1136145132Sanholt if (dev_priv->flags & CHIP_IS_AGP) { 1137157617Sanholt RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); 1138145132Sanholt RADEON_WRITE(RADEON_MC_AGP_LOCATION, 1139145132Sanholt (((dev_priv->gart_vm_start - 1 + 1140145132Sanholt dev_priv->gart_size) & 0xffff0000) | 1141145132Sanholt (dev_priv->gart_vm_start >> 16))); 114295584Sanholt 114395584Sanholt ring_start = (dev_priv->cp_ring->offset 1144157617Sanholt - dev->agp->base 1145157617Sanholt + dev_priv->gart_vm_start); 1146145132Sanholt } else 114795584Sanholt#endif 114895584Sanholt ring_start = (dev_priv->cp_ring->offset 1149157617Sanholt - (unsigned long)dev->sg->virtual 1150157617Sanholt + dev_priv->gart_vm_start); 115195584Sanholt 1152145132Sanholt RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); 115395584Sanholt 115495584Sanholt /* Set the write pointer delay */ 1155145132Sanholt RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); 115695584Sanholt 115795584Sanholt /* Initialize the ring buffer's read and write pointers */ 1158145132Sanholt cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); 1159145132Sanholt RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); 1160145132Sanholt SET_RING_HEAD(dev_priv, cur_read_ptr); 116195584Sanholt dev_priv->ring.tail = cur_read_ptr; 116295584Sanholt 1163145132Sanholt#if __OS_HAS_AGP 1164145132Sanholt if (dev_priv->flags & CHIP_IS_AGP) { 1165145132Sanholt RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, 1166145132Sanholt dev_priv->ring_rptr->offset 1167145132Sanholt - dev->agp->base + dev_priv->gart_vm_start); 1168113995Sanholt } else 1169113995Sanholt#endif 1170113995Sanholt { 117195584Sanholt drm_sg_mem_t *entry = dev->sg; 117295584Sanholt unsigned long tmp_ofs, page_ofs; 117395584Sanholt 1174157617Sanholt tmp_ofs = dev_priv->ring_rptr->offset - 1175157617Sanholt (unsigned long)dev->sg->virtual; 117695584Sanholt page_ofs = tmp_ofs >> PAGE_SHIFT; 117795584Sanholt 1178145132Sanholt RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); 1179145132Sanholt DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n", 1180145132Sanholt (unsigned long)entry->busaddr[page_ofs], 1181145132Sanholt entry->handle + tmp_ofs); 118295584Sanholt } 118395584Sanholt 1184157617Sanholt /* Set ring buffer size */ 1185157617Sanholt#ifdef __BIG_ENDIAN 1186157617Sanholt RADEON_WRITE(RADEON_CP_RB_CNTL, 1187157617Sanholt dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT); 1188157617Sanholt#else 1189157617Sanholt RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw); 1190157617Sanholt#endif 1191157617Sanholt 1192157617Sanholt /* Start with assuming that writeback doesn't work */ 1193157617Sanholt dev_priv->writeback_works = 0; 1194157617Sanholt 1195112015Sanholt /* Initialize the scratch register pointer. This will cause 1196112015Sanholt * the scratch register values to be written out to memory 1197112015Sanholt * whenever they are updated. 1198112015Sanholt * 1199112015Sanholt * We simply put this behind the ring read pointer, this works 1200112015Sanholt * with PCI GART as well as (whatever kind of) AGP GART 1201112015Sanholt */ 1202145132Sanholt RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) 1203145132Sanholt + RADEON_SCRATCH_REG_OFFSET); 1204112015Sanholt 1205112015Sanholt dev_priv->scratch = ((__volatile__ u32 *) 1206113995Sanholt dev_priv->ring_rptr->handle + 1207112015Sanholt (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); 1208112015Sanholt 1209145132Sanholt RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); 1210112015Sanholt 1211157617Sanholt /* Turn on bus mastering */ 1212157617Sanholt tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 1213157617Sanholt RADEON_WRITE(RADEON_BUS_CNTL, tmp); 1214112015Sanholt 1215112015Sanholt dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; 1216145132Sanholt RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); 1217112015Sanholt 1218112015Sanholt dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; 1219145132Sanholt RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 1220145132Sanholt dev_priv->sarea_priv->last_dispatch); 1221112015Sanholt 1222112015Sanholt dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; 1223145132Sanholt RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear); 1224112015Sanholt 1225145132Sanholt radeon_do_wait_for_idle(dev_priv); 122695584Sanholt 122795584Sanholt /* Sync everything up */ 1228145132Sanholt RADEON_WRITE(RADEON_ISYNC_CNTL, 1229145132Sanholt (RADEON_ISYNC_ANY2D_IDLE3D | 1230145132Sanholt RADEON_ISYNC_ANY3D_IDLE2D | 1231145132Sanholt RADEON_ISYNC_WAIT_IDLEGUI | 1232145132Sanholt RADEON_ISYNC_CPSCRATCH_IDLEGUI)); 1233157617Sanholt 123495584Sanholt} 123595584Sanholt 1236157617Sanholtstatic void radeon_test_writeback(drm_radeon_private_t * dev_priv) 1237157617Sanholt{ 1238157617Sanholt u32 tmp; 1239157617Sanholt 1240157617Sanholt /* Writeback doesn't seem to work everywhere, test it here and possibly 1241157617Sanholt * enable it if it appears to work 1242157617Sanholt */ 1243157617Sanholt DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0); 1244157617Sanholt RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); 1245157617Sanholt 1246157617Sanholt for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 1247157617Sanholt if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) == 1248157617Sanholt 0xdeadbeef) 1249157617Sanholt break; 1250157617Sanholt DRM_UDELAY(1); 1251157617Sanholt } 1252157617Sanholt 1253157617Sanholt if (tmp < dev_priv->usec_timeout) { 1254157617Sanholt dev_priv->writeback_works = 1; 1255157617Sanholt DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 1256157617Sanholt } else { 1257157617Sanholt dev_priv->writeback_works = 0; 1258157617Sanholt DRM_INFO("writeback test failed\n"); 1259157617Sanholt } 1260157617Sanholt if (radeon_no_wb == 1) { 1261157617Sanholt dev_priv->writeback_works = 0; 1262157617Sanholt DRM_INFO("writeback forced off\n"); 1263157617Sanholt } 1264157617Sanholt} 1265157617Sanholt 1266148211Sanholt/* Enable or disable PCI-E GART on the chip */ 1267148211Sanholtstatic void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) 1268148211Sanholt{ 1269148211Sanholt u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); 1270148211Sanholt if (on) { 1271148211Sanholt 1272152909Sanholt DRM_DEBUG("programming pcie %08X %08lX %08X\n", 1273157617Sanholt dev_priv->gart_vm_start, 1274157617Sanholt (long)dev_priv->gart_info.bus_addr, 1275152909Sanholt dev_priv->gart_size); 1276157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, 1277157617Sanholt dev_priv->gart_vm_start); 1278157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, 1279157617Sanholt dev_priv->gart_info.bus_addr); 1280157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, 1281157617Sanholt dev_priv->gart_vm_start); 1282157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, 1283157617Sanholt dev_priv->gart_vm_start + 1284157617Sanholt dev_priv->gart_size - 1); 1285148211Sanholt 1286148211Sanholt RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */ 1287148211Sanholt 1288157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, 1289157617Sanholt RADEON_PCIE_TX_GART_EN); 1290148211Sanholt } else { 1291157617Sanholt RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, 1292157617Sanholt tmp & ~RADEON_PCIE_TX_GART_EN); 1293148211Sanholt } 1294148211Sanholt} 1295148211Sanholt 1296119098Sanholt/* Enable or disable PCI GART on the chip */ 1297145132Sanholtstatic void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) 1298119098Sanholt{ 1299152909Sanholt u32 tmp; 1300119098Sanholt 1301157617Sanholt if (dev_priv->flags & CHIP_IS_PCIE) { 1302148211Sanholt radeon_set_pciegart(dev_priv, on); 1303148211Sanholt return; 1304148211Sanholt } 1305148211Sanholt 1306152909Sanholt tmp = RADEON_READ(RADEON_AIC_CNTL); 1307152909Sanholt 1308145132Sanholt if (on) { 1309145132Sanholt RADEON_WRITE(RADEON_AIC_CNTL, 1310145132Sanholt tmp | RADEON_PCIGART_TRANSLATE_EN); 1311119098Sanholt 1312119098Sanholt /* set PCI GART page-table base address 1313119098Sanholt */ 1314152909Sanholt RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); 1315119098Sanholt 1316119098Sanholt /* set address range for PCI address translate 1317119098Sanholt */ 1318145132Sanholt RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); 1319145132Sanholt RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start 1320145132Sanholt + dev_priv->gart_size - 1); 1321119098Sanholt 1322119895Sanholt /* Turn off AGP aperture -- is this required for PCI GART? 1323119098Sanholt */ 1324145132Sanholt RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */ 1325145132Sanholt RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ 1326119098Sanholt } else { 1327145132Sanholt RADEON_WRITE(RADEON_AIC_CNTL, 1328145132Sanholt tmp & ~RADEON_PCIGART_TRANSLATE_EN); 1329119098Sanholt } 1330119098Sanholt} 1331119098Sanholt 1332145132Sanholtstatic int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init) 133395584Sanholt{ 1334145132Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1335157617Sanholt 1336145132Sanholt DRM_DEBUG("\n"); 133795584Sanholt 1338157617Sanholt /* if we require new memory map but we don't have it fail */ 1339157617Sanholt if ((dev_priv->flags & CHIP_NEW_MEMMAP) && !dev_priv->new_memmap) 1340157617Sanholt { 1341157617Sanholt DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 1342157617Sanholt radeon_do_cleanup_cp(dev); 1343157617Sanholt return DRM_ERR(EINVAL); 1344157617Sanholt } 1345157617Sanholt 1346152909Sanholt if (init->is_pci && (dev_priv->flags & CHIP_IS_AGP)) 1347152909Sanholt { 1348152909Sanholt DRM_DEBUG("Forcing AGP card to PCI mode\n"); 1349152909Sanholt dev_priv->flags &= ~CHIP_IS_AGP; 1350152909Sanholt } 1351152909Sanholt 1352145132Sanholt if ((!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg) { 1353145132Sanholt DRM_ERROR("PCI GART memory not allocated!\n"); 135495584Sanholt radeon_do_cleanup_cp(dev); 1355112015Sanholt return DRM_ERR(EINVAL); 135695584Sanholt } 135795584Sanholt 135895584Sanholt dev_priv->usec_timeout = init->usec_timeout; 1359145132Sanholt if (dev_priv->usec_timeout < 1 || 1360145132Sanholt dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 1361145132Sanholt DRM_DEBUG("TIMEOUT problem!\n"); 136295584Sanholt radeon_do_cleanup_cp(dev); 1363112015Sanholt return DRM_ERR(EINVAL); 136495584Sanholt } 136595584Sanholt 1366145132Sanholt switch(init->func) { 1367145132Sanholt case RADEON_INIT_R200_CP: 1368157617Sanholt dev_priv->microcode_version = UCODE_R200; 1369145132Sanholt break; 1370145132Sanholt case RADEON_INIT_R300_CP: 1371157617Sanholt dev_priv->microcode_version = UCODE_R300; 1372145132Sanholt break; 1373145132Sanholt default: 1374157617Sanholt dev_priv->microcode_version = UCODE_R100; 1375145132Sanholt } 1376145132Sanholt 1377112015Sanholt dev_priv->do_boxes = 0; 137895584Sanholt dev_priv->cp_mode = init->cp_mode; 137995584Sanholt 138095584Sanholt /* We don't support anything other than bus-mastering ring mode, 138195584Sanholt * but the ring can be in either AGP or PCI space for the ring 138295584Sanholt * read pointer. 138395584Sanholt */ 1384145132Sanholt if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 1385145132Sanholt (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 1386145132Sanholt DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 138795584Sanholt radeon_do_cleanup_cp(dev); 1388112015Sanholt return DRM_ERR(EINVAL); 138995584Sanholt } 139095584Sanholt 1391145132Sanholt switch (init->fb_bpp) { 139295584Sanholt case 16: 139395584Sanholt dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 139495584Sanholt break; 139595584Sanholt case 32: 139695584Sanholt default: 139795584Sanholt dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 139895584Sanholt break; 139995584Sanholt } 1400145132Sanholt dev_priv->front_offset = init->front_offset; 1401145132Sanholt dev_priv->front_pitch = init->front_pitch; 1402145132Sanholt dev_priv->back_offset = init->back_offset; 1403145132Sanholt dev_priv->back_pitch = init->back_pitch; 140495584Sanholt 1405145132Sanholt switch (init->depth_bpp) { 140695584Sanholt case 16: 140795584Sanholt dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 140895584Sanholt break; 140995584Sanholt case 32: 141095584Sanholt default: 141195584Sanholt dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 141295584Sanholt break; 141395584Sanholt } 1414145132Sanholt dev_priv->depth_offset = init->depth_offset; 1415145132Sanholt dev_priv->depth_pitch = init->depth_pitch; 141695584Sanholt 141795584Sanholt /* Hardware state for depth clears. Remove this if/when we no 141895584Sanholt * longer clear the depth buffer with a 3D rectangle. Hard-code 141995584Sanholt * all values to prevent unwanted 3D state from slipping through 142095584Sanholt * and screwing with the clear operation. 142195584Sanholt */ 142295584Sanholt dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | 142395584Sanholt (dev_priv->color_fmt << 10) | 1424157617Sanholt (dev_priv->microcode_version == 1425157617Sanholt UCODE_R100 ? RADEON_ZBLOCK16 : 0)); 142695584Sanholt 1427145132Sanholt dev_priv->depth_clear.rb3d_zstencilcntl = 1428145132Sanholt (dev_priv->depth_fmt | 1429145132Sanholt RADEON_Z_TEST_ALWAYS | 1430145132Sanholt RADEON_STENCIL_TEST_ALWAYS | 1431145132Sanholt RADEON_STENCIL_S_FAIL_REPLACE | 1432145132Sanholt RADEON_STENCIL_ZPASS_REPLACE | 1433145132Sanholt RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); 143495584Sanholt 143595584Sanholt dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | 143695584Sanholt RADEON_BFACE_SOLID | 143795584Sanholt RADEON_FFACE_SOLID | 143895584Sanholt RADEON_FLAT_SHADE_VTX_LAST | 143995584Sanholt RADEON_DIFFUSE_SHADE_FLAT | 144095584Sanholt RADEON_ALPHA_SHADE_FLAT | 144195584Sanholt RADEON_SPECULAR_SHADE_FLAT | 144295584Sanholt RADEON_FOG_SHADE_FLAT | 144395584Sanholt RADEON_VTX_PIX_CENTER_OGL | 144495584Sanholt RADEON_ROUND_MODE_TRUNC | 144595584Sanholt RADEON_ROUND_PREC_8TH_PIX); 144695584Sanholt 1447112015Sanholt DRM_GETSAREA(); 1448113995Sanholt 1449113995Sanholt dev_priv->ring_offset = init->ring_offset; 1450113995Sanholt dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1451113995Sanholt dev_priv->buffers_offset = init->buffers_offset; 1452119895Sanholt dev_priv->gart_textures_offset = init->gart_textures_offset; 1453145132Sanholt 1454145132Sanholt if (!dev_priv->sarea) { 145595584Sanholt DRM_ERROR("could not find sarea!\n"); 145695584Sanholt radeon_do_cleanup_cp(dev); 1457112015Sanholt return DRM_ERR(EINVAL); 145895584Sanholt } 145995584Sanholt 1460145132Sanholt dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 1461145132Sanholt if (!dev_priv->cp_ring) { 146295584Sanholt DRM_ERROR("could not find cp ring region!\n"); 146395584Sanholt radeon_do_cleanup_cp(dev); 1464112015Sanholt return DRM_ERR(EINVAL); 146595584Sanholt } 1466145132Sanholt dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1467145132Sanholt if (!dev_priv->ring_rptr) { 146895584Sanholt DRM_ERROR("could not find ring read pointer!\n"); 146995584Sanholt radeon_do_cleanup_cp(dev); 1470112015Sanholt return DRM_ERR(EINVAL); 147195584Sanholt } 1472152909Sanholt dev->agp_buffer_token = init->buffers_offset; 1473145132Sanholt dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1474145132Sanholt if (!dev->agp_buffer_map) { 147595584Sanholt DRM_ERROR("could not find dma buffer region!\n"); 147695584Sanholt radeon_do_cleanup_cp(dev); 1477112015Sanholt return DRM_ERR(EINVAL); 147895584Sanholt } 147995584Sanholt 1480145132Sanholt if (init->gart_textures_offset) { 1481145132Sanholt dev_priv->gart_textures = 1482145132Sanholt drm_core_findmap(dev, init->gart_textures_offset); 1483145132Sanholt if (!dev_priv->gart_textures) { 1484119895Sanholt DRM_ERROR("could not find GART texture region!\n"); 148595584Sanholt radeon_do_cleanup_cp(dev); 1486112015Sanholt return DRM_ERR(EINVAL); 148795584Sanholt } 148895584Sanholt } 148995584Sanholt 149095584Sanholt dev_priv->sarea_priv = 1491145132Sanholt (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + 1492145132Sanholt init->sarea_priv_offset); 149395584Sanholt 1494145132Sanholt#if __OS_HAS_AGP 1495145132Sanholt if (dev_priv->flags & CHIP_IS_AGP) { 1496145132Sanholt drm_core_ioremap(dev_priv->cp_ring, dev); 1497145132Sanholt drm_core_ioremap(dev_priv->ring_rptr, dev); 1498145132Sanholt drm_core_ioremap(dev->agp_buffer_map, dev); 1499145132Sanholt if (!dev_priv->cp_ring->handle || 1500145132Sanholt !dev_priv->ring_rptr->handle || 1501145132Sanholt !dev->agp_buffer_map->handle) { 150295584Sanholt DRM_ERROR("could not find ioremap agp regions!\n"); 150395584Sanholt radeon_do_cleanup_cp(dev); 1504112015Sanholt return DRM_ERR(EINVAL); 150595584Sanholt } 1506119098Sanholt } else 1507119098Sanholt#endif 1508119098Sanholt { 1509145132Sanholt dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; 151095584Sanholt dev_priv->ring_rptr->handle = 1511145132Sanholt (void *)dev_priv->ring_rptr->offset; 1512145132Sanholt dev->agp_buffer_map->handle = 1513145132Sanholt (void *)dev->agp_buffer_map->offset; 151495584Sanholt 1515145132Sanholt DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 1516145132Sanholt dev_priv->cp_ring->handle); 1517145132Sanholt DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 1518145132Sanholt dev_priv->ring_rptr->handle); 1519145132Sanholt DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 1520145132Sanholt dev->agp_buffer_map->handle); 152195584Sanholt } 152295584Sanholt 1523145132Sanholt dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION) 1524145132Sanholt & 0xffff) << 16; 1525157617Sanholt dev_priv->fb_size = 1526157617Sanholt ((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000) 1527157617Sanholt - dev_priv->fb_location; 152895584Sanholt 1529145132Sanholt dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 1530145132Sanholt ((dev_priv->front_offset 1531145132Sanholt + dev_priv->fb_location) >> 10)); 1532122580Sanholt 1533145132Sanholt dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 1534145132Sanholt ((dev_priv->back_offset 1535145132Sanholt + dev_priv->fb_location) >> 10)); 1536122580Sanholt 1537145132Sanholt dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 1538145132Sanholt ((dev_priv->depth_offset 1539145132Sanholt + dev_priv->fb_location) >> 10)); 1540122580Sanholt 1541119895Sanholt dev_priv->gart_size = init->gart_size; 1542122580Sanholt 1543157617Sanholt /* New let's set the memory map ... */ 1544157617Sanholt if (dev_priv->new_memmap) { 1545157617Sanholt u32 base = 0; 1546157617Sanholt 1547157617Sanholt DRM_INFO("Setting GART location based on new memory map\n"); 1548157617Sanholt 1549157617Sanholt /* If using AGP, try to locate the AGP aperture at the same 1550157617Sanholt * location in the card and on the bus, though we have to 1551157617Sanholt * align it down. 1552157617Sanholt */ 1553145132Sanholt#if __OS_HAS_AGP 1554157617Sanholt if (dev_priv->flags & CHIP_IS_AGP) { 1555157617Sanholt base = dev->agp->base; 1556157617Sanholt /* Check if valid */ 1557157617Sanholt if ((base + dev_priv->gart_size) > dev_priv->fb_location && 1558157617Sanholt base < (dev_priv->fb_location + dev_priv->fb_size)) { 1559157617Sanholt DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 1560157617Sanholt dev->agp->base); 1561157617Sanholt base = 0; 1562157617Sanholt } 1563157617Sanholt } 1564157617Sanholt#endif 1565157617Sanholt /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 1566157617Sanholt if (base == 0) { 1567157617Sanholt base = dev_priv->fb_location + dev_priv->fb_size; 1568157617Sanholt if (((base + dev_priv->gart_size) & 0xfffffffful) 1569157617Sanholt < base) 1570157617Sanholt base = dev_priv->fb_location 1571157617Sanholt - dev_priv->gart_size; 1572157617Sanholt } 1573157617Sanholt dev_priv->gart_vm_start = base & 0xffc00000u; 1574157617Sanholt if (dev_priv->gart_vm_start != base) 1575157617Sanholt DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 1576157617Sanholt base, dev_priv->gart_vm_start); 1577157617Sanholt } else { 1578157617Sanholt DRM_INFO("Setting GART location based on old memory map\n"); 1579157617Sanholt dev_priv->gart_vm_start = dev_priv->fb_location + 1580157617Sanholt RADEON_READ(RADEON_CONFIG_APER_SIZE); 1581157617Sanholt } 1582157617Sanholt 1583157617Sanholt#if __OS_HAS_AGP 1584145132Sanholt if (dev_priv->flags & CHIP_IS_AGP) 1585145132Sanholt dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1586145132Sanholt - dev->agp->base 1587145132Sanholt + dev_priv->gart_vm_start); 158895584Sanholt else 158995584Sanholt#endif 1590145132Sanholt dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1591157617Sanholt - (unsigned long)dev->sg->virtual 1592157617Sanholt + dev_priv->gart_vm_start); 159395584Sanholt 1594145132Sanholt DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 1595145132Sanholt DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); 1596145132Sanholt DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", 1597145132Sanholt dev_priv->gart_buffers_offset); 159895584Sanholt 1599145132Sanholt dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 1600145132Sanholt dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 160195584Sanholt + init->ring_size / sizeof(u32)); 160295584Sanholt dev_priv->ring.size = init->ring_size; 1603145132Sanholt dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 160495584Sanholt 1605145132Sanholt dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 160695584Sanholt 160795584Sanholt dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 160895584Sanholt 1609145132Sanholt#if __OS_HAS_AGP 1610145132Sanholt if (dev_priv->flags & CHIP_IS_AGP) { 1611119098Sanholt /* Turn off PCI GART */ 1612145132Sanholt radeon_set_pcigart(dev_priv, 0); 1613119098Sanholt } else 1614119098Sanholt#endif 1615119098Sanholt { 1616152909Sanholt /* if we have an offset set from userspace */ 1617152909Sanholt if (dev_priv->pcigart_offset) { 1618157617Sanholt dev_priv->gart_info.bus_addr = 1619157617Sanholt dev_priv->pcigart_offset + dev_priv->fb_location; 1620157617Sanholt dev_priv->gart_info.mapping.offset = 1621157617Sanholt dev_priv->gart_info.bus_addr; 1622157617Sanholt dev_priv->gart_info.mapping.size = 1623157617Sanholt RADEON_PCIGART_TABLE_SIZE; 1624157617Sanholt 1625152909Sanholt drm_core_ioremap(&dev_priv->gart_info.mapping, dev); 1626157617Sanholt dev_priv->gart_info.addr = 1627157617Sanholt dev_priv->gart_info.mapping.handle; 1628152909Sanholt 1629157617Sanholt dev_priv->gart_info.is_pcie = 1630157617Sanholt !!(dev_priv->flags & CHIP_IS_PCIE); 1631157617Sanholt dev_priv->gart_info.gart_table_location = 1632157617Sanholt DRM_ATI_GART_FB; 1633157617Sanholt 1634157617Sanholt DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 1635157617Sanholt dev_priv->gart_info.addr, 1636157617Sanholt dev_priv->pcigart_offset); 1637157617Sanholt } else { 1638157617Sanholt dev_priv->gart_info.gart_table_location = 1639157617Sanholt DRM_ATI_GART_MAIN; 1640152909Sanholt dev_priv->gart_info.addr = NULL; 1641152909Sanholt dev_priv->gart_info.bus_addr = 0; 1642157617Sanholt if (dev_priv->flags & CHIP_IS_PCIE) { 1643157617Sanholt DRM_ERROR 1644157617Sanholt ("Cannot use PCI Express without GART in FB memory\n"); 1645152909Sanholt radeon_do_cleanup_cp(dev); 1646152909Sanholt return DRM_ERR(EINVAL); 1647152909Sanholt } 1648152909Sanholt } 1649152909Sanholt 1650152909Sanholt if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { 1651145132Sanholt DRM_ERROR("failed to init PCI GART!\n"); 165295584Sanholt radeon_do_cleanup_cp(dev); 1653112015Sanholt return DRM_ERR(ENOMEM); 165495584Sanholt } 165595584Sanholt 1656119098Sanholt /* Turn on PCI GART */ 1657145132Sanholt radeon_set_pcigart(dev_priv, 1); 165895584Sanholt } 165995584Sanholt 1660145132Sanholt radeon_cp_load_microcode(dev_priv); 1661145132Sanholt radeon_cp_init_ring_buffer(dev, dev_priv); 166295584Sanholt 166395584Sanholt dev_priv->last_buf = 0; 166495584Sanholt 1665145132Sanholt radeon_do_engine_reset(dev); 1666157617Sanholt radeon_test_writeback(dev_priv); 166795584Sanholt 166895584Sanholt return 0; 166995584Sanholt} 167095584Sanholt 1671145132Sanholtstatic int radeon_do_cleanup_cp(drm_device_t * dev) 167295584Sanholt{ 1673145132Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1674145132Sanholt DRM_DEBUG("\n"); 167595584Sanholt 1676119098Sanholt /* Make sure interrupts are disabled here because the uninstall ioctl 1677119098Sanholt * may not have been called from userspace and after dev_private 1678119098Sanholt * is freed, it's too late. 1679119098Sanholt */ 1680145132Sanholt if (dev->irq_enabled) 1681145132Sanholt drm_irq_uninstall(dev); 1682119098Sanholt 1683145132Sanholt#if __OS_HAS_AGP 1684145132Sanholt if (dev_priv->flags & CHIP_IS_AGP) { 1685145132Sanholt if (dev_priv->cp_ring != NULL) { 1686145132Sanholt drm_core_ioremapfree(dev_priv->cp_ring, dev); 1687145132Sanholt dev_priv->cp_ring = NULL; 1688145132Sanholt } 1689145132Sanholt if (dev_priv->ring_rptr != NULL) { 1690145132Sanholt drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1691145132Sanholt dev_priv->ring_rptr = NULL; 1692145132Sanholt } 1693145132Sanholt if (dev->agp_buffer_map != NULL) { 1694145132Sanholt drm_core_ioremapfree(dev->agp_buffer_map, dev); 1695145132Sanholt dev->agp_buffer_map = NULL; 1696145132Sanholt } 1697145132Sanholt } else 1698119098Sanholt#endif 1699145132Sanholt { 1700152909Sanholt 1701152909Sanholt if (dev_priv->gart_info.bus_addr) { 1702152909Sanholt /* Turn off PCI GART */ 1703152909Sanholt radeon_set_pcigart(dev_priv, 0); 1704152909Sanholt if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) 1705152909Sanholt DRM_ERROR("failed to cleanup PCI GART!\n"); 1706152909Sanholt } 1707152909Sanholt 1708152909Sanholt if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) 1709152909Sanholt { 1710152909Sanholt drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 1711152909Sanholt dev_priv->gart_info.addr = 0; 1712152909Sanholt } 171395584Sanholt } 1714145132Sanholt /* only clear to the start of flags */ 1715145132Sanholt memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 171695584Sanholt 171795584Sanholt return 0; 171895584Sanholt} 171995584Sanholt 1720145132Sanholt/* This code will reinit the Radeon CP hardware after a resume from disc. 1721145132Sanholt * AFAIK, it would be very difficult to pickle the state at suspend time, so 1722119098Sanholt * here we make sure that all Radeon hardware initialisation is re-done without 1723119098Sanholt * affecting running applications. 1724119098Sanholt * 1725119098Sanholt * Charl P. Botha <http://cpbotha.net> 1726119098Sanholt */ 1727145132Sanholtstatic int radeon_do_resume_cp(drm_device_t * dev) 1728119098Sanholt{ 1729119098Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1730119098Sanholt 1731145132Sanholt if (!dev_priv) { 1732145132Sanholt DRM_ERROR("Called with no initialization\n"); 1733145132Sanholt return DRM_ERR(EINVAL); 1734119098Sanholt } 1735119098Sanholt 1736119098Sanholt DRM_DEBUG("Starting radeon_do_resume_cp()\n"); 1737119098Sanholt 1738145132Sanholt#if __OS_HAS_AGP 1739145132Sanholt if (dev_priv->flags & CHIP_IS_AGP) { 1740119098Sanholt /* Turn off PCI GART */ 1741145132Sanholt radeon_set_pcigart(dev_priv, 0); 1742119098Sanholt } else 1743119098Sanholt#endif 1744119098Sanholt { 1745119098Sanholt /* Turn on PCI GART */ 1746145132Sanholt radeon_set_pcigart(dev_priv, 1); 1747119098Sanholt } 1748119098Sanholt 1749145132Sanholt radeon_cp_load_microcode(dev_priv); 1750145132Sanholt radeon_cp_init_ring_buffer(dev, dev_priv); 1751119098Sanholt 1752145132Sanholt radeon_do_engine_reset(dev); 1753119098Sanholt 1754119098Sanholt DRM_DEBUG("radeon_do_resume_cp() complete\n"); 1755119098Sanholt 1756119098Sanholt return 0; 1757119098Sanholt} 1758119098Sanholt 1759145132Sanholtint radeon_cp_init(DRM_IOCTL_ARGS) 176095584Sanholt{ 1761112015Sanholt DRM_DEVICE; 176295584Sanholt drm_radeon_init_t init; 176395584Sanholt 1764145132Sanholt LOCK_TEST_WITH_RETURN(dev, filp); 1765119098Sanholt 1766145132Sanholt DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data, 1767145132Sanholt sizeof(init)); 176895584Sanholt 1769157617Sanholt if (init.func == RADEON_INIT_R300_CP) 1770148211Sanholt r300_init_reg_flags(); 1771157617Sanholt 1772145132Sanholt switch (init.func) { 177395584Sanholt case RADEON_INIT_CP: 1774112015Sanholt case RADEON_INIT_R200_CP: 1775145132Sanholt case RADEON_INIT_R300_CP: 1776145132Sanholt return radeon_do_init_cp(dev, &init); 177795584Sanholt case RADEON_CLEANUP_CP: 1778145132Sanholt return radeon_do_cleanup_cp(dev); 177995584Sanholt } 178095584Sanholt 1781112015Sanholt return DRM_ERR(EINVAL); 178295584Sanholt} 178395584Sanholt 1784145132Sanholtint radeon_cp_start(DRM_IOCTL_ARGS) 178595584Sanholt{ 1786112015Sanholt DRM_DEVICE; 178795584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1788145132Sanholt DRM_DEBUG("\n"); 178995584Sanholt 1790145132Sanholt LOCK_TEST_WITH_RETURN(dev, filp); 179195584Sanholt 1792145132Sanholt if (dev_priv->cp_running) { 1793145132Sanholt DRM_DEBUG("%s while CP running\n", __FUNCTION__); 179495584Sanholt return 0; 179595584Sanholt } 1796145132Sanholt if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { 1797145132Sanholt DRM_DEBUG("%s called with bogus CP mode (%d)\n", 1798145132Sanholt __FUNCTION__, dev_priv->cp_mode); 179995584Sanholt return 0; 180095584Sanholt } 180195584Sanholt 1802145132Sanholt radeon_do_cp_start(dev_priv); 180395584Sanholt 180495584Sanholt return 0; 180595584Sanholt} 180695584Sanholt 180795584Sanholt/* Stop the CP. The engine must have been idled before calling this 180895584Sanholt * routine. 180995584Sanholt */ 1810145132Sanholtint radeon_cp_stop(DRM_IOCTL_ARGS) 181195584Sanholt{ 1812112015Sanholt DRM_DEVICE; 181395584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 181495584Sanholt drm_radeon_cp_stop_t stop; 181595584Sanholt int ret; 1816145132Sanholt DRM_DEBUG("\n"); 181795584Sanholt 1818145132Sanholt LOCK_TEST_WITH_RETURN(dev, filp); 181995584Sanholt 1820145132Sanholt DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data, 1821145132Sanholt sizeof(stop)); 182295584Sanholt 1823112015Sanholt if (!dev_priv->cp_running) 1824112015Sanholt return 0; 1825112015Sanholt 182695584Sanholt /* Flush any pending CP commands. This ensures any outstanding 182795584Sanholt * commands are exectuted by the engine before we turn it off. 182895584Sanholt */ 1829145132Sanholt if (stop.flush) { 1830145132Sanholt radeon_do_cp_flush(dev_priv); 183195584Sanholt } 183295584Sanholt 183395584Sanholt /* If we fail to make the engine go idle, we return an error 183495584Sanholt * code so that the DRM ioctl wrapper can try again. 183595584Sanholt */ 1836145132Sanholt if (stop.idle) { 1837145132Sanholt ret = radeon_do_cp_idle(dev_priv); 1838145132Sanholt if (ret) 1839145132Sanholt return ret; 184095584Sanholt } 184195584Sanholt 184295584Sanholt /* Finally, we can turn off the CP. If the engine isn't idle, 184395584Sanholt * we will get some dropped triangles as they won't be fully 184495584Sanholt * rendered before the CP is shut down. 184595584Sanholt */ 1846145132Sanholt radeon_do_cp_stop(dev_priv); 184795584Sanholt 184895584Sanholt /* Reset the engine */ 1849145132Sanholt radeon_do_engine_reset(dev); 185095584Sanholt 185195584Sanholt return 0; 185295584Sanholt} 185395584Sanholt 1854145132Sanholtvoid radeon_do_release(drm_device_t * dev) 1855112015Sanholt{ 1856112015Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1857145132Sanholt int i, ret; 1858112015Sanholt 1859112015Sanholt if (dev_priv) { 1860112015Sanholt if (dev_priv->cp_running) { 1861112015Sanholt /* Stop the cp */ 1862145132Sanholt while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { 1863112015Sanholt DRM_DEBUG("radeon_do_cp_idle %d\n", ret); 1864112015Sanholt#ifdef __linux__ 1865112015Sanholt schedule(); 1866112015Sanholt#else 1867152909Sanholt#if defined(__FreeBSD__) && __FreeBSD_version > 500000 1868152909Sanholt msleep(&ret, &dev->dev_lock, PZERO, "rdnrel", 1869152909Sanholt 1); 1870152909Sanholt#else 1871112015Sanholt tsleep(&ret, PZERO, "rdnrel", 1); 1872112015Sanholt#endif 1873152909Sanholt#endif 1874112015Sanholt } 1875145132Sanholt radeon_do_cp_stop(dev_priv); 1876145132Sanholt radeon_do_engine_reset(dev); 1877112015Sanholt } 1878112015Sanholt 1879112015Sanholt /* Disable *all* interrupts */ 1880145132Sanholt if (dev_priv->mmio) /* remove this after permanent addmaps */ 1881145132Sanholt RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 1882112015Sanholt 1883157617Sanholt if (dev_priv->mmio) { /* remove all surfaces */ 1884145132Sanholt for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1885157617Sanholt RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0); 1886157617Sanholt RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 1887157617Sanholt 16 * i, 0); 1888157617Sanholt RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 1889157617Sanholt 16 * i, 0); 1890145132Sanholt } 1891145132Sanholt } 1892145132Sanholt 1893112015Sanholt /* Free memory heap structures */ 1894145132Sanholt radeon_mem_takedown(&(dev_priv->gart_heap)); 1895145132Sanholt radeon_mem_takedown(&(dev_priv->fb_heap)); 1896112015Sanholt 1897112015Sanholt /* deallocate kernel resources */ 1898145132Sanholt radeon_do_cleanup_cp(dev); 1899112015Sanholt } 1900112015Sanholt} 1901112015Sanholt 190295584Sanholt/* Just reset the CP ring. Called as part of an X Server engine reset. 190395584Sanholt */ 1904145132Sanholtint radeon_cp_reset(DRM_IOCTL_ARGS) 190595584Sanholt{ 1906112015Sanholt DRM_DEVICE; 190795584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1908145132Sanholt DRM_DEBUG("\n"); 190995584Sanholt 1910145132Sanholt LOCK_TEST_WITH_RETURN(dev, filp); 191195584Sanholt 1912145132Sanholt if (!dev_priv) { 1913145132Sanholt DRM_DEBUG("%s called before init done\n", __FUNCTION__); 1914112015Sanholt return DRM_ERR(EINVAL); 191595584Sanholt } 191695584Sanholt 1917145132Sanholt radeon_do_cp_reset(dev_priv); 191895584Sanholt 191995584Sanholt /* The CP is no longer running after an engine reset */ 192095584Sanholt dev_priv->cp_running = 0; 192195584Sanholt 192295584Sanholt return 0; 192395584Sanholt} 192495584Sanholt 1925145132Sanholtint radeon_cp_idle(DRM_IOCTL_ARGS) 192695584Sanholt{ 1927112015Sanholt DRM_DEVICE; 192895584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1929145132Sanholt DRM_DEBUG("\n"); 193095584Sanholt 1931145132Sanholt LOCK_TEST_WITH_RETURN(dev, filp); 193295584Sanholt 1933145132Sanholt return radeon_do_cp_idle(dev_priv); 193495584Sanholt} 193595584Sanholt 1936119098Sanholt/* Added by Charl P. Botha to call radeon_do_resume_cp(). 1937119098Sanholt */ 1938145132Sanholtint radeon_cp_resume(DRM_IOCTL_ARGS) 1939119098Sanholt{ 1940119098Sanholt DRM_DEVICE; 1941119098Sanholt 1942119098Sanholt return radeon_do_resume_cp(dev); 1943119098Sanholt} 1944119098Sanholt 1945145132Sanholtint radeon_engine_reset(DRM_IOCTL_ARGS) 194695584Sanholt{ 1947112015Sanholt DRM_DEVICE; 1948145132Sanholt DRM_DEBUG("\n"); 194995584Sanholt 1950145132Sanholt LOCK_TEST_WITH_RETURN(dev, filp); 195195584Sanholt 1952145132Sanholt return radeon_do_engine_reset(dev); 195395584Sanholt} 195495584Sanholt 195595584Sanholt/* ================================================================ 195695584Sanholt * Fullscreen mode 195795584Sanholt */ 195895584Sanholt 1959112015Sanholt/* KW: Deprecated to say the least: 1960112015Sanholt */ 1961145132Sanholtint radeon_fullscreen(DRM_IOCTL_ARGS) 196295584Sanholt{ 196395584Sanholt return 0; 196495584Sanholt} 196595584Sanholt 196695584Sanholt/* ================================================================ 196795584Sanholt * Freelist management 196895584Sanholt */ 196995584Sanholt 1970112015Sanholt/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through 1971112015Sanholt * bufs until freelist code is used. Note this hides a problem with 1972112015Sanholt * the scratch register * (used to keep track of last buffer 1973112015Sanholt * completed) being written to before * the last buffer has actually 1974145132Sanholt * completed rendering. 1975112015Sanholt * 1976112015Sanholt * KW: It's also a good way to find free buffers quickly. 1977112015Sanholt * 1978112015Sanholt * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't 1979112015Sanholt * sleep. However, bugs in older versions of radeon_accel.c mean that 1980112015Sanholt * we essentially have to do this, else old clients will break. 1981145132Sanholt * 1982112015Sanholt * However, it does leave open a potential deadlock where all the 1983112015Sanholt * buffers are held by other clients, which can't release them because 1984145132Sanholt * they can't get the lock. 1985112015Sanholt */ 1986112015Sanholt 1987145132Sanholtdrm_buf_t *radeon_freelist_get(drm_device_t * dev) 198895584Sanholt{ 198995584Sanholt drm_device_dma_t *dma = dev->dma; 199095584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 1991112015Sanholt drm_radeon_buf_priv_t *buf_priv; 199295584Sanholt drm_buf_t *buf; 1993112015Sanholt int i, t; 1994112015Sanholt int start; 199595584Sanholt 1996145132Sanholt if (++dev_priv->last_buf >= dma->buf_count) 1997112015Sanholt dev_priv->last_buf = 0; 199895584Sanholt 1999112015Sanholt start = dev_priv->last_buf; 200095584Sanholt 2001145132Sanholt for (t = 0; t < dev_priv->usec_timeout; t++) { 2002145132Sanholt u32 done_age = GET_SCRATCH(1); 2003145132Sanholt DRM_DEBUG("done_age = %d\n", done_age); 2004145132Sanholt for (i = start; i < dma->buf_count; i++) { 2005112015Sanholt buf = dma->buflist[i]; 2006112015Sanholt buf_priv = buf->dev_private; 2007145132Sanholt if (buf->filp == 0 || (buf->pending && 2008145132Sanholt buf_priv->age <= done_age)) { 2009112015Sanholt dev_priv->stats.requested_bufs++; 2010112015Sanholt buf->pending = 0; 2011112015Sanholt return buf; 2012112015Sanholt } 2013112015Sanholt start = 0; 2014112015Sanholt } 201595584Sanholt 2016112015Sanholt if (t) { 2017145132Sanholt DRM_UDELAY(1); 2018112015Sanholt dev_priv->stats.freelist_loops++; 2019112015Sanholt } 202095584Sanholt } 202195584Sanholt 2022145132Sanholt DRM_DEBUG("returning NULL!\n"); 2023112015Sanholt return NULL; 202495584Sanholt} 2025145132Sanholt 2026112015Sanholt#if 0 2027145132Sanholtdrm_buf_t *radeon_freelist_get(drm_device_t * dev) 202895584Sanholt{ 202995584Sanholt drm_device_dma_t *dma = dev->dma; 203095584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 203195584Sanholt drm_radeon_buf_priv_t *buf_priv; 203295584Sanholt drm_buf_t *buf; 203395584Sanholt int i, t; 203495584Sanholt int start; 2035112015Sanholt u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); 203695584Sanholt 2037145132Sanholt if (++dev_priv->last_buf >= dma->buf_count) 203895584Sanholt dev_priv->last_buf = 0; 2039112015Sanholt 204095584Sanholt start = dev_priv->last_buf; 2041112015Sanholt dev_priv->stats.freelist_loops++; 2042145132Sanholt 2043145132Sanholt for (t = 0; t < 2; t++) { 2044145132Sanholt for (i = start; i < dma->buf_count; i++) { 204595584Sanholt buf = dma->buflist[i]; 204695584Sanholt buf_priv = buf->dev_private; 2047145132Sanholt if (buf->filp == 0 || (buf->pending && 2048145132Sanholt buf_priv->age <= done_age)) { 2049112015Sanholt dev_priv->stats.requested_bufs++; 205095584Sanholt buf->pending = 0; 205195584Sanholt return buf; 205295584Sanholt } 205395584Sanholt } 2054112015Sanholt start = 0; 205595584Sanholt } 205695584Sanholt 205795584Sanholt return NULL; 205895584Sanholt} 2059112015Sanholt#endif 206095584Sanholt 2061145132Sanholtvoid radeon_freelist_reset(drm_device_t * dev) 206295584Sanholt{ 206395584Sanholt drm_device_dma_t *dma = dev->dma; 206495584Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 206595584Sanholt int i; 206695584Sanholt 206795584Sanholt dev_priv->last_buf = 0; 2068145132Sanholt for (i = 0; i < dma->buf_count; i++) { 206995584Sanholt drm_buf_t *buf = dma->buflist[i]; 207095584Sanholt drm_radeon_buf_priv_t *buf_priv = buf->dev_private; 207195584Sanholt buf_priv->age = 0; 207295584Sanholt } 207395584Sanholt} 207495584Sanholt 207595584Sanholt/* ================================================================ 207695584Sanholt * CP command submission 207795584Sanholt */ 207895584Sanholt 2079145132Sanholtint radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) 208095584Sanholt{ 208195584Sanholt drm_radeon_ring_buffer_t *ring = &dev_priv->ring; 208295584Sanholt int i; 2083145132Sanholt u32 last_head = GET_RING_HEAD(dev_priv); 208495584Sanholt 2085145132Sanholt for (i = 0; i < dev_priv->usec_timeout; i++) { 2086145132Sanholt u32 head = GET_RING_HEAD(dev_priv); 2087112015Sanholt 2088112015Sanholt ring->space = (head - ring->tail) * sizeof(u32); 2089145132Sanholt if (ring->space <= 0) 2090112015Sanholt ring->space += ring->size; 2091145132Sanholt if (ring->space > n) 209295584Sanholt return 0; 2093145132Sanholt 2094112015Sanholt dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 2095112015Sanholt 2096112015Sanholt if (head != last_head) 2097112015Sanholt i = 0; 2098112015Sanholt last_head = head; 2099112015Sanholt 2100145132Sanholt DRM_UDELAY(1); 210195584Sanholt } 210295584Sanholt 210395584Sanholt /* FIXME: This return value is ignored in the BEGIN_RING macro! */ 210495584Sanholt#if RADEON_FIFO_DEBUG 2105145132Sanholt radeon_status(dev_priv); 2106145132Sanholt DRM_ERROR("failed!\n"); 210795584Sanholt#endif 2108112015Sanholt return DRM_ERR(EBUSY); 210995584Sanholt} 211095584Sanholt 2111145132Sanholtstatic int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev, 2112145132Sanholt drm_dma_t * d) 211395584Sanholt{ 211495584Sanholt int i; 211595584Sanholt drm_buf_t *buf; 211695584Sanholt 2117145132Sanholt for (i = d->granted_count; i < d->request_count; i++) { 2118145132Sanholt buf = radeon_freelist_get(dev); 2119145132Sanholt if (!buf) 2120145132Sanholt return DRM_ERR(EBUSY); /* NOTE: broken client */ 212195584Sanholt 2122113995Sanholt buf->filp = filp; 212395584Sanholt 2124145132Sanholt if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, 2125145132Sanholt sizeof(buf->idx))) 2126112015Sanholt return DRM_ERR(EFAULT); 2127145132Sanholt if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, 2128145132Sanholt sizeof(buf->total))) 2129112015Sanholt return DRM_ERR(EFAULT); 213095584Sanholt 213195584Sanholt d->granted_count++; 213295584Sanholt } 213395584Sanholt return 0; 213495584Sanholt} 213595584Sanholt 2136145132Sanholtint radeon_cp_buffers(DRM_IOCTL_ARGS) 213795584Sanholt{ 2138112015Sanholt DRM_DEVICE; 213995584Sanholt drm_device_dma_t *dma = dev->dma; 214095584Sanholt int ret = 0; 2141145132Sanholt drm_dma_t __user *argp = (void __user *)data; 214295584Sanholt drm_dma_t d; 214395584Sanholt 2144145132Sanholt LOCK_TEST_WITH_RETURN(dev, filp); 214595584Sanholt 2146145132Sanholt DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); 214795584Sanholt 214895584Sanholt /* Please don't send us buffers. 214995584Sanholt */ 2150145132Sanholt if (d.send_count != 0) { 2151145132Sanholt DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", 2152145132Sanholt DRM_CURRENTPID, d.send_count); 2153112015Sanholt return DRM_ERR(EINVAL); 215495584Sanholt } 215595584Sanholt 215695584Sanholt /* We'll send you buffers. 215795584Sanholt */ 2158145132Sanholt if (d.request_count < 0 || d.request_count > dma->buf_count) { 2159145132Sanholt DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", 2160145132Sanholt DRM_CURRENTPID, d.request_count, dma->buf_count); 2161112015Sanholt return DRM_ERR(EINVAL); 216295584Sanholt } 216395584Sanholt 216495584Sanholt d.granted_count = 0; 216595584Sanholt 2166145132Sanholt if (d.request_count) { 2167145132Sanholt ret = radeon_cp_get_buffers(filp, dev, &d); 216895584Sanholt } 216995584Sanholt 2170145132Sanholt DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); 217195584Sanholt 217295584Sanholt return ret; 217395584Sanholt} 2174145132Sanholt 2175152909Sanholtint radeon_driver_load(struct drm_device *dev, unsigned long flags) 2176145132Sanholt{ 2177145132Sanholt drm_radeon_private_t *dev_priv; 2178145132Sanholt int ret = 0; 2179145132Sanholt 2180145132Sanholt dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); 2181145132Sanholt if (dev_priv == NULL) 2182145132Sanholt return DRM_ERR(ENOMEM); 2183145132Sanholt 2184145132Sanholt memset(dev_priv, 0, sizeof(drm_radeon_private_t)); 2185145132Sanholt dev->dev_private = (void *)dev_priv; 2186145132Sanholt dev_priv->flags = flags; 2187145132Sanholt 2188145132Sanholt switch (flags & CHIP_FAMILY_MASK) { 2189145132Sanholt case CHIP_R100: 2190145132Sanholt case CHIP_RV200: 2191145132Sanholt case CHIP_R200: 2192145132Sanholt case CHIP_R300: 2193157617Sanholt case CHIP_R350: 2194148211Sanholt case CHIP_R420: 2195157617Sanholt case CHIP_RV410: 2196145132Sanholt dev_priv->flags |= CHIP_HAS_HIERZ; 2197145132Sanholt break; 2198145132Sanholt default: 2199157617Sanholt /* all other chips have no hierarchical z buffer */ 2200145132Sanholt break; 2201145132Sanholt } 2202145132Sanholt 2203145132Sanholt if (drm_device_is_agp(dev)) 2204145132Sanholt dev_priv->flags |= CHIP_IS_AGP; 2205145132Sanholt 2206148211Sanholt if (drm_device_is_pcie(dev)) 2207148211Sanholt dev_priv->flags |= CHIP_IS_PCIE; 2208148211Sanholt 2209145132Sanholt DRM_DEBUG("%s card detected\n", 2210148211Sanholt ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : (((dev_priv->flags & CHIP_IS_PCIE) ? "PCIE" : "PCI")))); 2211145132Sanholt return ret; 2212145132Sanholt} 2213145132Sanholt 2214152909Sanholt/* Create mappings for registers and framebuffer so userland doesn't necessarily 2215152909Sanholt * have to find them. 2216152909Sanholt */ 2217152909Sanholtint radeon_driver_firstopen(struct drm_device *dev) 2218145132Sanholt{ 2219152909Sanholt int ret; 2220152909Sanholt drm_local_map_t *map; 2221145132Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 2222145132Sanholt 2223152909Sanholt ret = drm_addmap(dev, drm_get_resource_start(dev, 2), 2224152909Sanholt drm_get_resource_len(dev, 2), _DRM_REGISTERS, 2225152909Sanholt _DRM_READ_ONLY, &dev_priv->mmio); 2226152909Sanholt if (ret != 0) 2227152909Sanholt return ret; 2228152909Sanholt 2229152909Sanholt ret = drm_addmap(dev, drm_get_resource_start(dev, 0), 2230152909Sanholt drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, 2231152909Sanholt _DRM_WRITE_COMBINING, &map); 2232152909Sanholt if (ret != 0) 2233152909Sanholt return ret; 2234152909Sanholt 2235152909Sanholt return 0; 2236152909Sanholt} 2237152909Sanholt 2238152909Sanholtint radeon_driver_unload(struct drm_device *dev) 2239152909Sanholt{ 2240152909Sanholt drm_radeon_private_t *dev_priv = dev->dev_private; 2241152909Sanholt 2242145132Sanholt DRM_DEBUG("\n"); 2243145132Sanholt drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); 2244145132Sanholt 2245145132Sanholt dev->dev_private = NULL; 2246145132Sanholt return 0; 2247145132Sanholt} 2248