radeon_cp.c revision 148211
1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */ 2/*- 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * 30 * $FreeBSD: head/sys/dev/drm/radeon_cp.c 148211 2005-07-20 21:10:57Z anholt $ 31 */ 32 33#include "dev/drm/drmP.h" 34#include "dev/drm/drm.h" 35#include "dev/drm/radeon_drm.h" 36#include "dev/drm/radeon_drv.h" 37#include "dev/drm/r300_reg.h" 38 39#define RADEON_FIFO_DEBUG 0 40 41static int radeon_do_cleanup_cp(drm_device_t * dev); 42 43/* CP microcode (from ATI) */ 44static u32 R200_cp_microcode[][2] = { 45 {0x21007000, 0000000000}, 46 {0x20007000, 0000000000}, 47 {0x000000ab, 0x00000004}, 48 {0x000000af, 0x00000004}, 49 {0x66544a49, 0000000000}, 50 {0x49494174, 0000000000}, 51 {0x54517d83, 0000000000}, 52 {0x498d8b64, 0000000000}, 53 {0x49494949, 0000000000}, 54 {0x49da493c, 0000000000}, 55 {0x49989898, 0000000000}, 56 {0xd34949d5, 0000000000}, 57 {0x9dc90e11, 0000000000}, 58 {0xce9b9b9b, 0000000000}, 59 {0x000f0000, 0x00000016}, 60 {0x352e232c, 0000000000}, 61 {0x00000013, 0x00000004}, 62 {0x000f0000, 0x00000016}, 63 {0x352e272c, 0000000000}, 64 {0x000f0001, 0x00000016}, 65 {0x3239362f, 0000000000}, 66 {0x000077ef, 0x00000002}, 67 {0x00061000, 0x00000002}, 68 {0x00000020, 0x0000001a}, 69 {0x00004000, 0x0000001e}, 70 {0x00061000, 0x00000002}, 71 {0x00000020, 0x0000001a}, 72 {0x00004000, 0x0000001e}, 73 {0x00061000, 0x00000002}, 74 {0x00000020, 0x0000001a}, 75 {0x00004000, 0x0000001e}, 76 {0x00000016, 0x00000004}, 77 {0x0003802a, 0x00000002}, 78 {0x040067e0, 0x00000002}, 79 {0x00000016, 0x00000004}, 80 {0x000077e0, 0x00000002}, 81 {0x00065000, 0x00000002}, 82 {0x000037e1, 0x00000002}, 83 {0x040067e1, 0x00000006}, 84 {0x000077e0, 0x00000002}, 85 {0x000077e1, 0x00000002}, 86 {0x000077e1, 0x00000006}, 87 {0xffffffff, 0000000000}, 88 {0x10000000, 0000000000}, 89 {0x0003802a, 0x00000002}, 90 {0x040067e0, 0x00000006}, 91 {0x00007675, 0x00000002}, 92 {0x00007676, 0x00000002}, 93 {0x00007677, 0x00000002}, 94 {0x00007678, 0x00000006}, 95 {0x0003802b, 0x00000002}, 96 {0x04002676, 0x00000002}, 97 {0x00007677, 0x00000002}, 98 {0x00007678, 0x00000006}, 99 {0x0000002e, 0x00000018}, 100 {0x0000002e, 0x00000018}, 101 {0000000000, 0x00000006}, 102 {0x0000002f, 0x00000018}, 103 {0x0000002f, 0x00000018}, 104 {0000000000, 0x00000006}, 105 {0x01605000, 0x00000002}, 106 {0x00065000, 0x00000002}, 107 {0x00098000, 0x00000002}, 108 {0x00061000, 0x00000002}, 109 {0x64c0603d, 0x00000004}, 110 {0x00080000, 0x00000016}, 111 {0000000000, 0000000000}, 112 {0x0400251d, 0x00000002}, 113 {0x00007580, 0x00000002}, 114 {0x00067581, 0x00000002}, 115 {0x04002580, 0x00000002}, 116 {0x00067581, 0x00000002}, 117 {0x00000046, 0x00000004}, 118 {0x00005000, 0000000000}, 119 {0x00061000, 0x00000002}, 120 {0x0000750e, 0x00000002}, 121 {0x00019000, 0x00000002}, 122 {0x00011055, 0x00000014}, 123 {0x00000055, 0x00000012}, 124 {0x0400250f, 0x00000002}, 125 {0x0000504a, 0x00000004}, 126 {0x00007565, 0x00000002}, 127 {0x00007566, 0x00000002}, 128 {0x00000051, 0x00000004}, 129 {0x01e655b4, 0x00000002}, 130 {0x4401b0dc, 0x00000002}, 131 {0x01c110dc, 0x00000002}, 132 {0x2666705d, 0x00000018}, 133 {0x040c2565, 0x00000002}, 134 {0x0000005d, 0x00000018}, 135 {0x04002564, 0x00000002}, 136 {0x00007566, 0x00000002}, 137 {0x00000054, 0x00000004}, 138 {0x00401060, 0x00000008}, 139 {0x00101000, 0x00000002}, 140 {0x000d80ff, 0x00000002}, 141 {0x00800063, 0x00000008}, 142 {0x000f9000, 0x00000002}, 143 {0x000e00ff, 0x00000002}, 144 {0000000000, 0x00000006}, 145 {0x00000080, 0x00000018}, 146 {0x00000054, 0x00000004}, 147 {0x00007576, 0x00000002}, 148 {0x00065000, 0x00000002}, 149 {0x00009000, 0x00000002}, 150 {0x00041000, 0x00000002}, 151 {0x0c00350e, 0x00000002}, 152 {0x00049000, 0x00000002}, 153 {0x00051000, 0x00000002}, 154 {0x01e785f8, 0x00000002}, 155 {0x00200000, 0x00000002}, 156 {0x00600073, 0x0000000c}, 157 {0x00007563, 0x00000002}, 158 {0x006075f0, 0x00000021}, 159 {0x20007068, 0x00000004}, 160 {0x00005068, 0x00000004}, 161 {0x00007576, 0x00000002}, 162 {0x00007577, 0x00000002}, 163 {0x0000750e, 0x00000002}, 164 {0x0000750f, 0x00000002}, 165 {0x00a05000, 0x00000002}, 166 {0x00600076, 0x0000000c}, 167 {0x006075f0, 0x00000021}, 168 {0x000075f8, 0x00000002}, 169 {0x00000076, 0x00000004}, 170 {0x000a750e, 0x00000002}, 171 {0x0020750f, 0x00000002}, 172 {0x00600079, 0x00000004}, 173 {0x00007570, 0x00000002}, 174 {0x00007571, 0x00000002}, 175 {0x00007572, 0x00000006}, 176 {0x00005000, 0x00000002}, 177 {0x00a05000, 0x00000002}, 178 {0x00007568, 0x00000002}, 179 {0x00061000, 0x00000002}, 180 {0x00000084, 0x0000000c}, 181 {0x00058000, 0x00000002}, 182 {0x0c607562, 0x00000002}, 183 {0x00000086, 0x00000004}, 184 {0x00600085, 0x00000004}, 185 {0x400070dd, 0000000000}, 186 {0x000380dd, 0x00000002}, 187 {0x00000093, 0x0000001c}, 188 {0x00065095, 0x00000018}, 189 {0x040025bb, 0x00000002}, 190 {0x00061096, 0x00000018}, 191 {0x040075bc, 0000000000}, 192 {0x000075bb, 0x00000002}, 193 {0x000075bc, 0000000000}, 194 {0x00090000, 0x00000006}, 195 {0x00090000, 0x00000002}, 196 {0x000d8002, 0x00000006}, 197 {0x00005000, 0x00000002}, 198 {0x00007821, 0x00000002}, 199 {0x00007800, 0000000000}, 200 {0x00007821, 0x00000002}, 201 {0x00007800, 0000000000}, 202 {0x01665000, 0x00000002}, 203 {0x000a0000, 0x00000002}, 204 {0x000671cc, 0x00000002}, 205 {0x0286f1cd, 0x00000002}, 206 {0x000000a3, 0x00000010}, 207 {0x21007000, 0000000000}, 208 {0x000000aa, 0x0000001c}, 209 {0x00065000, 0x00000002}, 210 {0x000a0000, 0x00000002}, 211 {0x00061000, 0x00000002}, 212 {0x000b0000, 0x00000002}, 213 {0x38067000, 0x00000002}, 214 {0x000a00a6, 0x00000004}, 215 {0x20007000, 0000000000}, 216 {0x01200000, 0x00000002}, 217 {0x20077000, 0x00000002}, 218 {0x01200000, 0x00000002}, 219 {0x20007000, 0000000000}, 220 {0x00061000, 0x00000002}, 221 {0x0120751b, 0x00000002}, 222 {0x8040750a, 0x00000002}, 223 {0x8040750b, 0x00000002}, 224 {0x00110000, 0x00000002}, 225 {0x000380dd, 0x00000002}, 226 {0x000000bd, 0x0000001c}, 227 {0x00061096, 0x00000018}, 228 {0x844075bd, 0x00000002}, 229 {0x00061095, 0x00000018}, 230 {0x840075bb, 0x00000002}, 231 {0x00061096, 0x00000018}, 232 {0x844075bc, 0x00000002}, 233 {0x000000c0, 0x00000004}, 234 {0x804075bd, 0x00000002}, 235 {0x800075bb, 0x00000002}, 236 {0x804075bc, 0x00000002}, 237 {0x00108000, 0x00000002}, 238 {0x01400000, 0x00000002}, 239 {0x006000c4, 0x0000000c}, 240 {0x20c07000, 0x00000020}, 241 {0x000000c6, 0x00000012}, 242 {0x00800000, 0x00000006}, 243 {0x0080751d, 0x00000006}, 244 {0x000025bb, 0x00000002}, 245 {0x000040c0, 0x00000004}, 246 {0x0000775c, 0x00000002}, 247 {0x00a05000, 0x00000002}, 248 {0x00661000, 0x00000002}, 249 {0x0460275d, 0x00000020}, 250 {0x00004000, 0000000000}, 251 {0x00007999, 0x00000002}, 252 {0x00a05000, 0x00000002}, 253 {0x00661000, 0x00000002}, 254 {0x0460299b, 0x00000020}, 255 {0x00004000, 0000000000}, 256 {0x01e00830, 0x00000002}, 257 {0x21007000, 0000000000}, 258 {0x00005000, 0x00000002}, 259 {0x00038042, 0x00000002}, 260 {0x040025e0, 0x00000002}, 261 {0x000075e1, 0000000000}, 262 {0x00000001, 0000000000}, 263 {0x000380d9, 0x00000002}, 264 {0x04007394, 0000000000}, 265 {0000000000, 0000000000}, 266 {0000000000, 0000000000}, 267 {0000000000, 0000000000}, 268 {0000000000, 0000000000}, 269 {0000000000, 0000000000}, 270 {0000000000, 0000000000}, 271 {0000000000, 0000000000}, 272 {0000000000, 0000000000}, 273 {0000000000, 0000000000}, 274 {0000000000, 0000000000}, 275 {0000000000, 0000000000}, 276 {0000000000, 0000000000}, 277 {0000000000, 0000000000}, 278 {0000000000, 0000000000}, 279 {0000000000, 0000000000}, 280 {0000000000, 0000000000}, 281 {0000000000, 0000000000}, 282 {0000000000, 0000000000}, 283 {0000000000, 0000000000}, 284 {0000000000, 0000000000}, 285 {0000000000, 0000000000}, 286 {0000000000, 0000000000}, 287 {0000000000, 0000000000}, 288 {0000000000, 0000000000}, 289 {0000000000, 0000000000}, 290 {0000000000, 0000000000}, 291 {0000000000, 0000000000}, 292 {0000000000, 0000000000}, 293 {0000000000, 0000000000}, 294 {0000000000, 0000000000}, 295 {0000000000, 0000000000}, 296 {0000000000, 0000000000}, 297 {0000000000, 0000000000}, 298 {0000000000, 0000000000}, 299 {0000000000, 0000000000}, 300 {0000000000, 0000000000}, 301}; 302 303static u32 radeon_cp_microcode[][2] = { 304 {0x21007000, 0000000000}, 305 {0x20007000, 0000000000}, 306 {0x000000b4, 0x00000004}, 307 {0x000000b8, 0x00000004}, 308 {0x6f5b4d4c, 0000000000}, 309 {0x4c4c427f, 0000000000}, 310 {0x5b568a92, 0000000000}, 311 {0x4ca09c6d, 0000000000}, 312 {0xad4c4c4c, 0000000000}, 313 {0x4ce1af3d, 0000000000}, 314 {0xd8afafaf, 0000000000}, 315 {0xd64c4cdc, 0000000000}, 316 {0x4cd10d10, 0000000000}, 317 {0x000f0000, 0x00000016}, 318 {0x362f242d, 0000000000}, 319 {0x00000012, 0x00000004}, 320 {0x000f0000, 0x00000016}, 321 {0x362f282d, 0000000000}, 322 {0x000380e7, 0x00000002}, 323 {0x04002c97, 0x00000002}, 324 {0x000f0001, 0x00000016}, 325 {0x333a3730, 0000000000}, 326 {0x000077ef, 0x00000002}, 327 {0x00061000, 0x00000002}, 328 {0x00000021, 0x0000001a}, 329 {0x00004000, 0x0000001e}, 330 {0x00061000, 0x00000002}, 331 {0x00000021, 0x0000001a}, 332 {0x00004000, 0x0000001e}, 333 {0x00061000, 0x00000002}, 334 {0x00000021, 0x0000001a}, 335 {0x00004000, 0x0000001e}, 336 {0x00000017, 0x00000004}, 337 {0x0003802b, 0x00000002}, 338 {0x040067e0, 0x00000002}, 339 {0x00000017, 0x00000004}, 340 {0x000077e0, 0x00000002}, 341 {0x00065000, 0x00000002}, 342 {0x000037e1, 0x00000002}, 343 {0x040067e1, 0x00000006}, 344 {0x000077e0, 0x00000002}, 345 {0x000077e1, 0x00000002}, 346 {0x000077e1, 0x00000006}, 347 {0xffffffff, 0000000000}, 348 {0x10000000, 0000000000}, 349 {0x0003802b, 0x00000002}, 350 {0x040067e0, 0x00000006}, 351 {0x00007675, 0x00000002}, 352 {0x00007676, 0x00000002}, 353 {0x00007677, 0x00000002}, 354 {0x00007678, 0x00000006}, 355 {0x0003802c, 0x00000002}, 356 {0x04002676, 0x00000002}, 357 {0x00007677, 0x00000002}, 358 {0x00007678, 0x00000006}, 359 {0x0000002f, 0x00000018}, 360 {0x0000002f, 0x00000018}, 361 {0000000000, 0x00000006}, 362 {0x00000030, 0x00000018}, 363 {0x00000030, 0x00000018}, 364 {0000000000, 0x00000006}, 365 {0x01605000, 0x00000002}, 366 {0x00065000, 0x00000002}, 367 {0x00098000, 0x00000002}, 368 {0x00061000, 0x00000002}, 369 {0x64c0603e, 0x00000004}, 370 {0x000380e6, 0x00000002}, 371 {0x040025c5, 0x00000002}, 372 {0x00080000, 0x00000016}, 373 {0000000000, 0000000000}, 374 {0x0400251d, 0x00000002}, 375 {0x00007580, 0x00000002}, 376 {0x00067581, 0x00000002}, 377 {0x04002580, 0x00000002}, 378 {0x00067581, 0x00000002}, 379 {0x00000049, 0x00000004}, 380 {0x00005000, 0000000000}, 381 {0x000380e6, 0x00000002}, 382 {0x040025c5, 0x00000002}, 383 {0x00061000, 0x00000002}, 384 {0x0000750e, 0x00000002}, 385 {0x00019000, 0x00000002}, 386 {0x00011055, 0x00000014}, 387 {0x00000055, 0x00000012}, 388 {0x0400250f, 0x00000002}, 389 {0x0000504f, 0x00000004}, 390 {0x000380e6, 0x00000002}, 391 {0x040025c5, 0x00000002}, 392 {0x00007565, 0x00000002}, 393 {0x00007566, 0x00000002}, 394 {0x00000058, 0x00000004}, 395 {0x000380e6, 0x00000002}, 396 {0x040025c5, 0x00000002}, 397 {0x01e655b4, 0x00000002}, 398 {0x4401b0e4, 0x00000002}, 399 {0x01c110e4, 0x00000002}, 400 {0x26667066, 0x00000018}, 401 {0x040c2565, 0x00000002}, 402 {0x00000066, 0x00000018}, 403 {0x04002564, 0x00000002}, 404 {0x00007566, 0x00000002}, 405 {0x0000005d, 0x00000004}, 406 {0x00401069, 0x00000008}, 407 {0x00101000, 0x00000002}, 408 {0x000d80ff, 0x00000002}, 409 {0x0080006c, 0x00000008}, 410 {0x000f9000, 0x00000002}, 411 {0x000e00ff, 0x00000002}, 412 {0000000000, 0x00000006}, 413 {0x0000008f, 0x00000018}, 414 {0x0000005b, 0x00000004}, 415 {0x000380e6, 0x00000002}, 416 {0x040025c5, 0x00000002}, 417 {0x00007576, 0x00000002}, 418 {0x00065000, 0x00000002}, 419 {0x00009000, 0x00000002}, 420 {0x00041000, 0x00000002}, 421 {0x0c00350e, 0x00000002}, 422 {0x00049000, 0x00000002}, 423 {0x00051000, 0x00000002}, 424 {0x01e785f8, 0x00000002}, 425 {0x00200000, 0x00000002}, 426 {0x0060007e, 0x0000000c}, 427 {0x00007563, 0x00000002}, 428 {0x006075f0, 0x00000021}, 429 {0x20007073, 0x00000004}, 430 {0x00005073, 0x00000004}, 431 {0x000380e6, 0x00000002}, 432 {0x040025c5, 0x00000002}, 433 {0x00007576, 0x00000002}, 434 {0x00007577, 0x00000002}, 435 {0x0000750e, 0x00000002}, 436 {0x0000750f, 0x00000002}, 437 {0x00a05000, 0x00000002}, 438 {0x00600083, 0x0000000c}, 439 {0x006075f0, 0x00000021}, 440 {0x000075f8, 0x00000002}, 441 {0x00000083, 0x00000004}, 442 {0x000a750e, 0x00000002}, 443 {0x000380e6, 0x00000002}, 444 {0x040025c5, 0x00000002}, 445 {0x0020750f, 0x00000002}, 446 {0x00600086, 0x00000004}, 447 {0x00007570, 0x00000002}, 448 {0x00007571, 0x00000002}, 449 {0x00007572, 0x00000006}, 450 {0x000380e6, 0x00000002}, 451 {0x040025c5, 0x00000002}, 452 {0x00005000, 0x00000002}, 453 {0x00a05000, 0x00000002}, 454 {0x00007568, 0x00000002}, 455 {0x00061000, 0x00000002}, 456 {0x00000095, 0x0000000c}, 457 {0x00058000, 0x00000002}, 458 {0x0c607562, 0x00000002}, 459 {0x00000097, 0x00000004}, 460 {0x000380e6, 0x00000002}, 461 {0x040025c5, 0x00000002}, 462 {0x00600096, 0x00000004}, 463 {0x400070e5, 0000000000}, 464 {0x000380e6, 0x00000002}, 465 {0x040025c5, 0x00000002}, 466 {0x000380e5, 0x00000002}, 467 {0x000000a8, 0x0000001c}, 468 {0x000650aa, 0x00000018}, 469 {0x040025bb, 0x00000002}, 470 {0x000610ab, 0x00000018}, 471 {0x040075bc, 0000000000}, 472 {0x000075bb, 0x00000002}, 473 {0x000075bc, 0000000000}, 474 {0x00090000, 0x00000006}, 475 {0x00090000, 0x00000002}, 476 {0x000d8002, 0x00000006}, 477 {0x00007832, 0x00000002}, 478 {0x00005000, 0x00000002}, 479 {0x000380e7, 0x00000002}, 480 {0x04002c97, 0x00000002}, 481 {0x00007820, 0x00000002}, 482 {0x00007821, 0x00000002}, 483 {0x00007800, 0000000000}, 484 {0x01200000, 0x00000002}, 485 {0x20077000, 0x00000002}, 486 {0x01200000, 0x00000002}, 487 {0x20007000, 0x00000002}, 488 {0x00061000, 0x00000002}, 489 {0x0120751b, 0x00000002}, 490 {0x8040750a, 0x00000002}, 491 {0x8040750b, 0x00000002}, 492 {0x00110000, 0x00000002}, 493 {0x000380e5, 0x00000002}, 494 {0x000000c6, 0x0000001c}, 495 {0x000610ab, 0x00000018}, 496 {0x844075bd, 0x00000002}, 497 {0x000610aa, 0x00000018}, 498 {0x840075bb, 0x00000002}, 499 {0x000610ab, 0x00000018}, 500 {0x844075bc, 0x00000002}, 501 {0x000000c9, 0x00000004}, 502 {0x804075bd, 0x00000002}, 503 {0x800075bb, 0x00000002}, 504 {0x804075bc, 0x00000002}, 505 {0x00108000, 0x00000002}, 506 {0x01400000, 0x00000002}, 507 {0x006000cd, 0x0000000c}, 508 {0x20c07000, 0x00000020}, 509 {0x000000cf, 0x00000012}, 510 {0x00800000, 0x00000006}, 511 {0x0080751d, 0x00000006}, 512 {0000000000, 0000000000}, 513 {0x0000775c, 0x00000002}, 514 {0x00a05000, 0x00000002}, 515 {0x00661000, 0x00000002}, 516 {0x0460275d, 0x00000020}, 517 {0x00004000, 0000000000}, 518 {0x01e00830, 0x00000002}, 519 {0x21007000, 0000000000}, 520 {0x6464614d, 0000000000}, 521 {0x69687420, 0000000000}, 522 {0x00000073, 0000000000}, 523 {0000000000, 0000000000}, 524 {0x00005000, 0x00000002}, 525 {0x000380d0, 0x00000002}, 526 {0x040025e0, 0x00000002}, 527 {0x000075e1, 0000000000}, 528 {0x00000001, 0000000000}, 529 {0x000380e0, 0x00000002}, 530 {0x04002394, 0x00000002}, 531 {0x00005000, 0000000000}, 532 {0000000000, 0000000000}, 533 {0000000000, 0000000000}, 534 {0x00000008, 0000000000}, 535 {0x00000004, 0000000000}, 536 {0000000000, 0000000000}, 537 {0000000000, 0000000000}, 538 {0000000000, 0000000000}, 539 {0000000000, 0000000000}, 540 {0000000000, 0000000000}, 541 {0000000000, 0000000000}, 542 {0000000000, 0000000000}, 543 {0000000000, 0000000000}, 544 {0000000000, 0000000000}, 545 {0000000000, 0000000000}, 546 {0000000000, 0000000000}, 547 {0000000000, 0000000000}, 548 {0000000000, 0000000000}, 549 {0000000000, 0000000000}, 550 {0000000000, 0000000000}, 551 {0000000000, 0000000000}, 552 {0000000000, 0000000000}, 553 {0000000000, 0000000000}, 554 {0000000000, 0000000000}, 555 {0000000000, 0000000000}, 556 {0000000000, 0000000000}, 557 {0000000000, 0000000000}, 558 {0000000000, 0000000000}, 559 {0000000000, 0000000000}, 560}; 561 562static u32 R300_cp_microcode[][2] = { 563 { 0x4200e000, 0000000000 }, 564 { 0x4000e000, 0000000000 }, 565 { 0x000000af, 0x00000008 }, 566 { 0x000000b3, 0x00000008 }, 567 { 0x6c5a504f, 0000000000 }, 568 { 0x4f4f497a, 0000000000 }, 569 { 0x5a578288, 0000000000 }, 570 { 0x4f91906a, 0000000000 }, 571 { 0x4f4f4f4f, 0000000000 }, 572 { 0x4fe24f44, 0000000000 }, 573 { 0x4f9c9c9c, 0000000000 }, 574 { 0xdc4f4fde, 0000000000 }, 575 { 0xa1cd4f4f, 0000000000 }, 576 { 0xd29d9d9d, 0000000000 }, 577 { 0x4f0f9fd7, 0000000000 }, 578 { 0x000ca000, 0x00000004 }, 579 { 0x000d0012, 0x00000038 }, 580 { 0x0000e8b4, 0x00000004 }, 581 { 0x000d0014, 0x00000038 }, 582 { 0x0000e8b6, 0x00000004 }, 583 { 0x000d0016, 0x00000038 }, 584 { 0x0000e854, 0x00000004 }, 585 { 0x000d0018, 0x00000038 }, 586 { 0x0000e855, 0x00000004 }, 587 { 0x000d001a, 0x00000038 }, 588 { 0x0000e856, 0x00000004 }, 589 { 0x000d001c, 0x00000038 }, 590 { 0x0000e857, 0x00000004 }, 591 { 0x000d001e, 0x00000038 }, 592 { 0x0000e824, 0x00000004 }, 593 { 0x000d0020, 0x00000038 }, 594 { 0x0000e825, 0x00000004 }, 595 { 0x000d0022, 0x00000038 }, 596 { 0x0000e830, 0x00000004 }, 597 { 0x000d0024, 0x00000038 }, 598 { 0x0000f0c0, 0x00000004 }, 599 { 0x000d0026, 0x00000038 }, 600 { 0x0000f0c1, 0x00000004 }, 601 { 0x000d0028, 0x00000038 }, 602 { 0x0000f041, 0x00000004 }, 603 { 0x000d002a, 0x00000038 }, 604 { 0x0000f184, 0x00000004 }, 605 { 0x000d002c, 0x00000038 }, 606 { 0x0000f185, 0x00000004 }, 607 { 0x000d002e, 0x00000038 }, 608 { 0x0000f186, 0x00000004 }, 609 { 0x000d0030, 0x00000038 }, 610 { 0x0000f187, 0x00000004 }, 611 { 0x000d0032, 0x00000038 }, 612 { 0x0000f180, 0x00000004 }, 613 { 0x000d0034, 0x00000038 }, 614 { 0x0000f393, 0x00000004 }, 615 { 0x000d0036, 0x00000038 }, 616 { 0x0000f38a, 0x00000004 }, 617 { 0x000d0038, 0x00000038 }, 618 { 0x0000f38e, 0x00000004 }, 619 { 0x0000e821, 0x00000004 }, 620 { 0x0140a000, 0x00000004 }, 621 { 0x00000043, 0x00000018 }, 622 { 0x00cce800, 0x00000004 }, 623 { 0x001b0001, 0x00000004 }, 624 { 0x08004800, 0x00000004 }, 625 { 0x001b0001, 0x00000004 }, 626 { 0x08004800, 0x00000004 }, 627 { 0x001b0001, 0x00000004 }, 628 { 0x08004800, 0x00000004 }, 629 { 0x0000003a, 0x00000008 }, 630 { 0x0000a000, 0000000000 }, 631 { 0x02c0a000, 0x00000004 }, 632 { 0x000ca000, 0x00000004 }, 633 { 0x00130000, 0x00000004 }, 634 { 0x000c2000, 0x00000004 }, 635 { 0xc980c045, 0x00000008 }, 636 { 0x2000451d, 0x00000004 }, 637 { 0x0000e580, 0x00000004 }, 638 { 0x000ce581, 0x00000004 }, 639 { 0x08004580, 0x00000004 }, 640 { 0x000ce581, 0x00000004 }, 641 { 0x0000004c, 0x00000008 }, 642 { 0x0000a000, 0000000000 }, 643 { 0x000c2000, 0x00000004 }, 644 { 0x0000e50e, 0x00000004 }, 645 { 0x00032000, 0x00000004 }, 646 { 0x00022056, 0x00000028 }, 647 { 0x00000056, 0x00000024 }, 648 { 0x0800450f, 0x00000004 }, 649 { 0x0000a050, 0x00000008 }, 650 { 0x0000e565, 0x00000004 }, 651 { 0x0000e566, 0x00000004 }, 652 { 0x00000057, 0x00000008 }, 653 { 0x03cca5b4, 0x00000004 }, 654 { 0x05432000, 0x00000004 }, 655 { 0x00022000, 0x00000004 }, 656 { 0x4ccce063, 0x00000030 }, 657 { 0x08274565, 0x00000004 }, 658 { 0x00000063, 0x00000030 }, 659 { 0x08004564, 0x00000004 }, 660 { 0x0000e566, 0x00000004 }, 661 { 0x0000005a, 0x00000008 }, 662 { 0x00802066, 0x00000010 }, 663 { 0x00202000, 0x00000004 }, 664 { 0x001b00ff, 0x00000004 }, 665 { 0x01000069, 0x00000010 }, 666 { 0x001f2000, 0x00000004 }, 667 { 0x001c00ff, 0x00000004 }, 668 { 0000000000, 0x0000000c }, 669 { 0x00000085, 0x00000030 }, 670 { 0x0000005a, 0x00000008 }, 671 { 0x0000e576, 0x00000004 }, 672 { 0x000ca000, 0x00000004 }, 673 { 0x00012000, 0x00000004 }, 674 { 0x00082000, 0x00000004 }, 675 { 0x1800650e, 0x00000004 }, 676 { 0x00092000, 0x00000004 }, 677 { 0x000a2000, 0x00000004 }, 678 { 0x000f0000, 0x00000004 }, 679 { 0x00400000, 0x00000004 }, 680 { 0x00000079, 0x00000018 }, 681 { 0x0000e563, 0x00000004 }, 682 { 0x00c0e5f9, 0x000000c2 }, 683 { 0x0000006e, 0x00000008 }, 684 { 0x0000a06e, 0x00000008 }, 685 { 0x0000e576, 0x00000004 }, 686 { 0x0000e577, 0x00000004 }, 687 { 0x0000e50e, 0x00000004 }, 688 { 0x0000e50f, 0x00000004 }, 689 { 0x0140a000, 0x00000004 }, 690 { 0x0000007c, 0x00000018 }, 691 { 0x00c0e5f9, 0x000000c2 }, 692 { 0x0000007c, 0x00000008 }, 693 { 0x0014e50e, 0x00000004 }, 694 { 0x0040e50f, 0x00000004 }, 695 { 0x00c0007f, 0x00000008 }, 696 { 0x0000e570, 0x00000004 }, 697 { 0x0000e571, 0x00000004 }, 698 { 0x0000e572, 0x0000000c }, 699 { 0x0000a000, 0x00000004 }, 700 { 0x0140a000, 0x00000004 }, 701 { 0x0000e568, 0x00000004 }, 702 { 0x000c2000, 0x00000004 }, 703 { 0x00000089, 0x00000018 }, 704 { 0x000b0000, 0x00000004 }, 705 { 0x18c0e562, 0x00000004 }, 706 { 0x0000008b, 0x00000008 }, 707 { 0x00c0008a, 0x00000008 }, 708 { 0x000700e4, 0x00000004 }, 709 { 0x00000097, 0x00000038 }, 710 { 0x000ca099, 0x00000030 }, 711 { 0x080045bb, 0x00000004 }, 712 { 0x000c209a, 0x00000030 }, 713 { 0x0800e5bc, 0000000000 }, 714 { 0x0000e5bb, 0x00000004 }, 715 { 0x0000e5bc, 0000000000 }, 716 { 0x00120000, 0x0000000c }, 717 { 0x00120000, 0x00000004 }, 718 { 0x001b0002, 0x0000000c }, 719 { 0x0000a000, 0x00000004 }, 720 { 0x0000e821, 0x00000004 }, 721 { 0x0000e800, 0000000000 }, 722 { 0x0000e821, 0x00000004 }, 723 { 0x0000e82e, 0000000000 }, 724 { 0x02cca000, 0x00000004 }, 725 { 0x00140000, 0x00000004 }, 726 { 0x000ce1cc, 0x00000004 }, 727 { 0x050de1cd, 0x00000004 }, 728 { 0x000000a7, 0x00000020 }, 729 { 0x4200e000, 0000000000 }, 730 { 0x000000ae, 0x00000038 }, 731 { 0x000ca000, 0x00000004 }, 732 { 0x00140000, 0x00000004 }, 733 { 0x000c2000, 0x00000004 }, 734 { 0x00160000, 0x00000004 }, 735 { 0x700ce000, 0x00000004 }, 736 { 0x001400aa, 0x00000008 }, 737 { 0x4000e000, 0000000000 }, 738 { 0x02400000, 0x00000004 }, 739 { 0x400ee000, 0x00000004 }, 740 { 0x02400000, 0x00000004 }, 741 { 0x4000e000, 0000000000 }, 742 { 0x000c2000, 0x00000004 }, 743 { 0x0240e51b, 0x00000004 }, 744 { 0x0080e50a, 0x00000005 }, 745 { 0x0080e50b, 0x00000005 }, 746 { 0x00220000, 0x00000004 }, 747 { 0x000700e4, 0x00000004 }, 748 { 0x000000c1, 0x00000038 }, 749 { 0x000c209a, 0x00000030 }, 750 { 0x0880e5bd, 0x00000005 }, 751 { 0x000c2099, 0x00000030 }, 752 { 0x0800e5bb, 0x00000005 }, 753 { 0x000c209a, 0x00000030 }, 754 { 0x0880e5bc, 0x00000005 }, 755 { 0x000000c4, 0x00000008 }, 756 { 0x0080e5bd, 0x00000005 }, 757 { 0x0000e5bb, 0x00000005 }, 758 { 0x0080e5bc, 0x00000005 }, 759 { 0x00210000, 0x00000004 }, 760 { 0x02800000, 0x00000004 }, 761 { 0x00c000c8, 0x00000018 }, 762 { 0x4180e000, 0x00000040 }, 763 { 0x000000ca, 0x00000024 }, 764 { 0x01000000, 0x0000000c }, 765 { 0x0100e51d, 0x0000000c }, 766 { 0x000045bb, 0x00000004 }, 767 { 0x000080c4, 0x00000008 }, 768 { 0x0000f3ce, 0x00000004 }, 769 { 0x0140a000, 0x00000004 }, 770 { 0x00cc2000, 0x00000004 }, 771 { 0x08c053cf, 0x00000040 }, 772 { 0x00008000, 0000000000 }, 773 { 0x0000f3d2, 0x00000004 }, 774 { 0x0140a000, 0x00000004 }, 775 { 0x00cc2000, 0x00000004 }, 776 { 0x08c053d3, 0x00000040 }, 777 { 0x00008000, 0000000000 }, 778 { 0x0000f39d, 0x00000004 }, 779 { 0x0140a000, 0x00000004 }, 780 { 0x00cc2000, 0x00000004 }, 781 { 0x08c0539e, 0x00000040 }, 782 { 0x00008000, 0000000000 }, 783 { 0x03c00830, 0x00000004 }, 784 { 0x4200e000, 0000000000 }, 785 { 0x0000a000, 0x00000004 }, 786 { 0x200045e0, 0x00000004 }, 787 { 0x0000e5e1, 0000000000 }, 788 { 0x00000001, 0000000000 }, 789 { 0x000700e1, 0x00000004 }, 790 { 0x0800e394, 0000000000 }, 791 { 0000000000, 0000000000 }, 792 { 0000000000, 0000000000 }, 793 { 0000000000, 0000000000 }, 794 { 0000000000, 0000000000 }, 795 { 0000000000, 0000000000 }, 796 { 0000000000, 0000000000 }, 797 { 0000000000, 0000000000 }, 798 { 0000000000, 0000000000 }, 799 { 0000000000, 0000000000 }, 800 { 0000000000, 0000000000 }, 801 { 0000000000, 0000000000 }, 802 { 0000000000, 0000000000 }, 803 { 0000000000, 0000000000 }, 804 { 0000000000, 0000000000 }, 805 { 0000000000, 0000000000 }, 806 { 0000000000, 0000000000 }, 807 { 0000000000, 0000000000 }, 808 { 0000000000, 0000000000 }, 809 { 0000000000, 0000000000 }, 810 { 0000000000, 0000000000 }, 811 { 0000000000, 0000000000 }, 812 { 0000000000, 0000000000 }, 813 { 0000000000, 0000000000 }, 814 { 0000000000, 0000000000 }, 815 { 0000000000, 0000000000 }, 816 { 0000000000, 0000000000 }, 817 { 0000000000, 0000000000 }, 818 { 0000000000, 0000000000 }, 819}; 820 821static int RADEON_READ_PLL(drm_device_t * dev, int addr) 822{ 823 drm_radeon_private_t *dev_priv = dev->dev_private; 824 825 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); 826 return RADEON_READ(RADEON_CLOCK_CNTL_DATA); 827} 828 829static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) 830{ 831 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); 832 return RADEON_READ(RADEON_PCIE_DATA); 833} 834 835#if RADEON_FIFO_DEBUG 836static void radeon_status(drm_radeon_private_t * dev_priv) 837{ 838 printk("%s:\n", __FUNCTION__); 839 printk("RBBM_STATUS = 0x%08x\n", 840 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); 841 printk("CP_RB_RTPR = 0x%08x\n", 842 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); 843 printk("CP_RB_WTPR = 0x%08x\n", 844 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); 845 printk("AIC_CNTL = 0x%08x\n", 846 (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); 847 printk("AIC_STAT = 0x%08x\n", 848 (unsigned int)RADEON_READ(RADEON_AIC_STAT)); 849 printk("AIC_PT_BASE = 0x%08x\n", 850 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); 851 printk("TLB_ADDR = 0x%08x\n", 852 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); 853 printk("TLB_DATA = 0x%08x\n", 854 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); 855} 856#endif 857 858/* ================================================================ 859 * Engine, FIFO control 860 */ 861 862static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) 863{ 864 u32 tmp; 865 int i; 866 867 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 868 869 tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT); 870 tmp |= RADEON_RB2D_DC_FLUSH_ALL; 871 RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp); 872 873 for (i = 0; i < dev_priv->usec_timeout; i++) { 874 if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT) 875 & RADEON_RB2D_DC_BUSY)) { 876 return 0; 877 } 878 DRM_UDELAY(1); 879 } 880 881#if RADEON_FIFO_DEBUG 882 DRM_ERROR("failed!\n"); 883 radeon_status(dev_priv); 884#endif 885 return DRM_ERR(EBUSY); 886} 887 888static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) 889{ 890 int i; 891 892 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 893 894 for (i = 0; i < dev_priv->usec_timeout; i++) { 895 int slots = (RADEON_READ(RADEON_RBBM_STATUS) 896 & RADEON_RBBM_FIFOCNT_MASK); 897 if (slots >= entries) 898 return 0; 899 DRM_UDELAY(1); 900 } 901 902#if RADEON_FIFO_DEBUG 903 DRM_ERROR("failed!\n"); 904 radeon_status(dev_priv); 905#endif 906 return DRM_ERR(EBUSY); 907} 908 909static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) 910{ 911 int i, ret; 912 913 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 914 915 ret = radeon_do_wait_for_fifo(dev_priv, 64); 916 if (ret) 917 return ret; 918 919 for (i = 0; i < dev_priv->usec_timeout; i++) { 920 if (!(RADEON_READ(RADEON_RBBM_STATUS) 921 & RADEON_RBBM_ACTIVE)) { 922 radeon_do_pixcache_flush(dev_priv); 923 return 0; 924 } 925 DRM_UDELAY(1); 926 } 927 928#if RADEON_FIFO_DEBUG 929 DRM_ERROR("failed!\n"); 930 radeon_status(dev_priv); 931#endif 932 return DRM_ERR(EBUSY); 933} 934 935/* ================================================================ 936 * CP control, initialization 937 */ 938 939/* Load the microcode for the CP */ 940static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) 941{ 942 int i; 943 DRM_DEBUG("\n"); 944 945 radeon_do_wait_for_idle(dev_priv); 946 947 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); 948 949 if (dev_priv->microcode_version==UCODE_R200) { 950 DRM_INFO("Loading R200 Microcode\n"); 951 for (i = 0; i < 256; i++) { 952 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 953 R200_cp_microcode[i][1]); 954 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 955 R200_cp_microcode[i][0]); 956 } 957 } else if (dev_priv->microcode_version==UCODE_R300) { 958 DRM_INFO("Loading R300 Microcode\n"); 959 for ( i = 0 ; i < 256 ; i++ ) { 960 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, 961 R300_cp_microcode[i][1] ); 962 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, 963 R300_cp_microcode[i][0] ); 964 } 965 } else { 966 for (i = 0; i < 256; i++) { 967 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 968 radeon_cp_microcode[i][1]); 969 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 970 radeon_cp_microcode[i][0]); 971 } 972 } 973} 974 975/* Flush any pending commands to the CP. This should only be used just 976 * prior to a wait for idle, as it informs the engine that the command 977 * stream is ending. 978 */ 979static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) 980{ 981 DRM_DEBUG("\n"); 982#if 0 983 u32 tmp; 984 985 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); 986 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); 987#endif 988} 989 990/* Wait for the CP to go idle. 991 */ 992int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) 993{ 994 RING_LOCALS; 995 DRM_DEBUG("\n"); 996 997 BEGIN_RING(6); 998 999 RADEON_PURGE_CACHE(); 1000 RADEON_PURGE_ZCACHE(); 1001 RADEON_WAIT_UNTIL_IDLE(); 1002 1003 ADVANCE_RING(); 1004 COMMIT_RING(); 1005 1006 return radeon_do_wait_for_idle(dev_priv); 1007} 1008 1009/* Start the Command Processor. 1010 */ 1011static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) 1012{ 1013 RING_LOCALS; 1014 DRM_DEBUG("\n"); 1015 1016 radeon_do_wait_for_idle(dev_priv); 1017 1018 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); 1019 1020 dev_priv->cp_running = 1; 1021 1022 BEGIN_RING(6); 1023 1024 RADEON_PURGE_CACHE(); 1025 RADEON_PURGE_ZCACHE(); 1026 RADEON_WAIT_UNTIL_IDLE(); 1027 1028 ADVANCE_RING(); 1029 COMMIT_RING(); 1030} 1031 1032/* Reset the Command Processor. This will not flush any pending 1033 * commands, so you must wait for the CP command stream to complete 1034 * before calling this routine. 1035 */ 1036static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) 1037{ 1038 u32 cur_read_ptr; 1039 DRM_DEBUG("\n"); 1040 1041 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); 1042 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); 1043 SET_RING_HEAD(dev_priv, cur_read_ptr); 1044 dev_priv->ring.tail = cur_read_ptr; 1045} 1046 1047/* Stop the Command Processor. This will not flush any pending 1048 * commands, so you must flush the command stream and wait for the CP 1049 * to go idle before calling this routine. 1050 */ 1051static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) 1052{ 1053 DRM_DEBUG("\n"); 1054 1055 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); 1056 1057 dev_priv->cp_running = 0; 1058} 1059 1060/* Reset the engine. This will stop the CP if it is running. 1061 */ 1062static int radeon_do_engine_reset(drm_device_t * dev) 1063{ 1064 drm_radeon_private_t *dev_priv = dev->dev_private; 1065 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; 1066 DRM_DEBUG("\n"); 1067 1068 radeon_do_pixcache_flush(dev_priv); 1069 1070 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); 1071 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); 1072 1073 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | 1074 RADEON_FORCEON_MCLKA | 1075 RADEON_FORCEON_MCLKB | 1076 RADEON_FORCEON_YCLKA | 1077 RADEON_FORCEON_YCLKB | 1078 RADEON_FORCEON_MC | 1079 RADEON_FORCEON_AIC)); 1080 1081 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); 1082 1083 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | 1084 RADEON_SOFT_RESET_CP | 1085 RADEON_SOFT_RESET_HI | 1086 RADEON_SOFT_RESET_SE | 1087 RADEON_SOFT_RESET_RE | 1088 RADEON_SOFT_RESET_PP | 1089 RADEON_SOFT_RESET_E2 | 1090 RADEON_SOFT_RESET_RB)); 1091 RADEON_READ(RADEON_RBBM_SOFT_RESET); 1092 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & 1093 ~(RADEON_SOFT_RESET_CP | 1094 RADEON_SOFT_RESET_HI | 1095 RADEON_SOFT_RESET_SE | 1096 RADEON_SOFT_RESET_RE | 1097 RADEON_SOFT_RESET_PP | 1098 RADEON_SOFT_RESET_E2 | 1099 RADEON_SOFT_RESET_RB))); 1100 RADEON_READ(RADEON_RBBM_SOFT_RESET); 1101 1102 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); 1103 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); 1104 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); 1105 1106 /* Reset the CP ring */ 1107 radeon_do_cp_reset(dev_priv); 1108 1109 /* The CP is no longer running after an engine reset */ 1110 dev_priv->cp_running = 0; 1111 1112 /* Reset any pending vertex, indirect buffers */ 1113 radeon_freelist_reset(dev); 1114 1115 return 0; 1116} 1117 1118static void radeon_cp_init_ring_buffer(drm_device_t * dev, 1119 drm_radeon_private_t * dev_priv) 1120{ 1121 u32 ring_start, cur_read_ptr; 1122 u32 tmp; 1123 1124 /* Initialize the memory controller */ 1125 RADEON_WRITE(RADEON_MC_FB_LOCATION, 1126 ((dev_priv->gart_vm_start - 1) & 0xffff0000) 1127 | (dev_priv->fb_location >> 16)); 1128 1129#if __OS_HAS_AGP 1130 if (dev_priv->flags & CHIP_IS_AGP) { 1131 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 1132 (((dev_priv->gart_vm_start - 1 + 1133 dev_priv->gart_size) & 0xffff0000) | 1134 (dev_priv->gart_vm_start >> 16))); 1135 1136 ring_start = (dev_priv->cp_ring->offset 1137 - dev->agp->base + dev_priv->gart_vm_start); 1138 } else 1139#endif 1140 ring_start = (dev_priv->cp_ring->offset 1141 - dev->sg->handle + dev_priv->gart_vm_start); 1142 1143 1144 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); 1145 1146 /* Set the write pointer delay */ 1147 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); 1148 1149 /* Initialize the ring buffer's read and write pointers */ 1150 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); 1151 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); 1152 SET_RING_HEAD(dev_priv, cur_read_ptr); 1153 dev_priv->ring.tail = cur_read_ptr; 1154 1155#if __OS_HAS_AGP 1156 if (dev_priv->flags & CHIP_IS_AGP) { 1157 /* set RADEON_AGP_BASE here instead of relying on X from user space */ 1158 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); 1159 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, 1160 dev_priv->ring_rptr->offset 1161 - dev->agp->base + dev_priv->gart_vm_start); 1162 } else 1163#endif 1164 { 1165 drm_sg_mem_t *entry = dev->sg; 1166 unsigned long tmp_ofs, page_ofs; 1167 1168 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; 1169 page_ofs = tmp_ofs >> PAGE_SHIFT; 1170 1171 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); 1172 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n", 1173 (unsigned long)entry->busaddr[page_ofs], 1174 entry->handle + tmp_ofs); 1175 } 1176 1177 /* Initialize the scratch register pointer. This will cause 1178 * the scratch register values to be written out to memory 1179 * whenever they are updated. 1180 * 1181 * We simply put this behind the ring read pointer, this works 1182 * with PCI GART as well as (whatever kind of) AGP GART 1183 */ 1184 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) 1185 + RADEON_SCRATCH_REG_OFFSET); 1186 1187 dev_priv->scratch = ((__volatile__ u32 *) 1188 dev_priv->ring_rptr->handle + 1189 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); 1190 1191 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); 1192 1193 /* Writeback doesn't seem to work everywhere, test it first */ 1194 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0); 1195 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); 1196 1197 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 1198 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) == 1199 0xdeadbeef) 1200 break; 1201 DRM_UDELAY(1); 1202 } 1203 1204 if (tmp < dev_priv->usec_timeout) { 1205 dev_priv->writeback_works = 1; 1206 DRM_DEBUG("writeback test succeeded, tmp=%d\n", tmp); 1207 } else { 1208 dev_priv->writeback_works = 0; 1209 DRM_DEBUG("writeback test failed\n"); 1210 } 1211 1212 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; 1213 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); 1214 1215 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; 1216 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 1217 dev_priv->sarea_priv->last_dispatch); 1218 1219 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; 1220 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear); 1221 1222 /* Set ring buffer size */ 1223#ifdef __BIG_ENDIAN 1224 RADEON_WRITE(RADEON_CP_RB_CNTL, 1225 dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT); 1226#else 1227 RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw); 1228#endif 1229 1230 radeon_do_wait_for_idle(dev_priv); 1231 1232 /* Turn on bus mastering */ 1233 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 1234 RADEON_WRITE(RADEON_BUS_CNTL, tmp); 1235 1236 /* Sync everything up */ 1237 RADEON_WRITE(RADEON_ISYNC_CNTL, 1238 (RADEON_ISYNC_ANY2D_IDLE3D | 1239 RADEON_ISYNC_ANY3D_IDLE2D | 1240 RADEON_ISYNC_WAIT_IDLEGUI | 1241 RADEON_ISYNC_CPSCRATCH_IDLEGUI)); 1242} 1243 1244/* Enable or disable PCI-E GART on the chip */ 1245static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) 1246{ 1247 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); 1248 if (on) { 1249 1250 DRM_DEBUG("programming pcie %08X %08lX %08X\n", dev_priv->gart_vm_start, dev_priv->bus_pci_gart,dev_priv->gart_size); 1251 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, dev_priv->gart_vm_start); 1252 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, dev_priv->bus_pci_gart); 1253 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, dev_priv->gart_vm_start); 1254 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, dev_priv->gart_vm_start 1255 + dev_priv->gart_size - 1); 1256 1257 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */ 1258 1259 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, RADEON_PCIE_TX_GART_EN | RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD | RADEON_PCIE_TX_GART_CHK_RW_VALID_EN); 1260 } else { 1261 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 1262 } 1263} 1264 1265/* Enable or disable PCI GART on the chip */ 1266static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) 1267{ 1268 u32 tmp = RADEON_READ(RADEON_AIC_CNTL); 1269 1270 if (dev_priv->flags & CHIP_IS_PCIE) 1271 { 1272 radeon_set_pciegart(dev_priv, on); 1273 return; 1274 } 1275 1276 if (on) { 1277 RADEON_WRITE(RADEON_AIC_CNTL, 1278 tmp | RADEON_PCIGART_TRANSLATE_EN); 1279 1280 /* set PCI GART page-table base address 1281 */ 1282 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart); 1283 1284 /* set address range for PCI address translate 1285 */ 1286 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); 1287 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start 1288 + dev_priv->gart_size - 1); 1289 1290 /* Turn off AGP aperture -- is this required for PCI GART? 1291 */ 1292 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */ 1293 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ 1294 } else { 1295 RADEON_WRITE(RADEON_AIC_CNTL, 1296 tmp & ~RADEON_PCIGART_TRANSLATE_EN); 1297 } 1298} 1299 1300static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init) 1301{ 1302 drm_radeon_private_t *dev_priv = dev->dev_private; 1303 DRM_DEBUG("\n"); 1304 1305 if ((!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg) { 1306 DRM_ERROR("PCI GART memory not allocated!\n"); 1307 radeon_do_cleanup_cp(dev); 1308 return DRM_ERR(EINVAL); 1309 } 1310 1311 dev_priv->usec_timeout = init->usec_timeout; 1312 if (dev_priv->usec_timeout < 1 || 1313 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 1314 DRM_DEBUG("TIMEOUT problem!\n"); 1315 radeon_do_cleanup_cp(dev); 1316 return DRM_ERR(EINVAL); 1317 } 1318 1319 switch(init->func) { 1320 case RADEON_INIT_R200_CP: 1321 dev_priv->microcode_version=UCODE_R200; 1322 break; 1323 case RADEON_INIT_R300_CP: 1324 dev_priv->microcode_version=UCODE_R300; 1325 break; 1326 default: 1327 dev_priv->microcode_version=UCODE_R100; 1328 break; 1329 } 1330 1331 dev_priv->do_boxes = 0; 1332 dev_priv->cp_mode = init->cp_mode; 1333 1334 /* We don't support anything other than bus-mastering ring mode, 1335 * but the ring can be in either AGP or PCI space for the ring 1336 * read pointer. 1337 */ 1338 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 1339 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 1340 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 1341 radeon_do_cleanup_cp(dev); 1342 return DRM_ERR(EINVAL); 1343 } 1344 1345 switch (init->fb_bpp) { 1346 case 16: 1347 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 1348 break; 1349 case 32: 1350 default: 1351 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 1352 break; 1353 } 1354 dev_priv->front_offset = init->front_offset; 1355 dev_priv->front_pitch = init->front_pitch; 1356 dev_priv->back_offset = init->back_offset; 1357 dev_priv->back_pitch = init->back_pitch; 1358 1359 switch (init->depth_bpp) { 1360 case 16: 1361 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 1362 break; 1363 case 32: 1364 default: 1365 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 1366 break; 1367 } 1368 dev_priv->depth_offset = init->depth_offset; 1369 dev_priv->depth_pitch = init->depth_pitch; 1370 1371 /* Hardware state for depth clears. Remove this if/when we no 1372 * longer clear the depth buffer with a 3D rectangle. Hard-code 1373 * all values to prevent unwanted 3D state from slipping through 1374 * and screwing with the clear operation. 1375 */ 1376 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | 1377 (dev_priv->color_fmt << 10) | 1378 (dev_priv->microcode_version == UCODE_R100 ? 1379 RADEON_ZBLOCK16 : 0)); 1380 1381 dev_priv->depth_clear.rb3d_zstencilcntl = 1382 (dev_priv->depth_fmt | 1383 RADEON_Z_TEST_ALWAYS | 1384 RADEON_STENCIL_TEST_ALWAYS | 1385 RADEON_STENCIL_S_FAIL_REPLACE | 1386 RADEON_STENCIL_ZPASS_REPLACE | 1387 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); 1388 1389 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | 1390 RADEON_BFACE_SOLID | 1391 RADEON_FFACE_SOLID | 1392 RADEON_FLAT_SHADE_VTX_LAST | 1393 RADEON_DIFFUSE_SHADE_FLAT | 1394 RADEON_ALPHA_SHADE_FLAT | 1395 RADEON_SPECULAR_SHADE_FLAT | 1396 RADEON_FOG_SHADE_FLAT | 1397 RADEON_VTX_PIX_CENTER_OGL | 1398 RADEON_ROUND_MODE_TRUNC | 1399 RADEON_ROUND_PREC_8TH_PIX); 1400 1401 DRM_GETSAREA(); 1402 1403 dev_priv->fb_offset = init->fb_offset; 1404 dev_priv->mmio_offset = init->mmio_offset; 1405 dev_priv->ring_offset = init->ring_offset; 1406 dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1407 dev_priv->buffers_offset = init->buffers_offset; 1408 dev_priv->gart_textures_offset = init->gart_textures_offset; 1409 1410 if (!dev_priv->sarea) { 1411 DRM_ERROR("could not find sarea!\n"); 1412 radeon_do_cleanup_cp(dev); 1413 return DRM_ERR(EINVAL); 1414 } 1415 1416 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); 1417 if (!dev_priv->mmio) { 1418 DRM_ERROR("could not find mmio region!\n"); 1419 radeon_do_cleanup_cp(dev); 1420 return DRM_ERR(EINVAL); 1421 } 1422 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 1423 if (!dev_priv->cp_ring) { 1424 DRM_ERROR("could not find cp ring region!\n"); 1425 radeon_do_cleanup_cp(dev); 1426 return DRM_ERR(EINVAL); 1427 } 1428 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1429 if (!dev_priv->ring_rptr) { 1430 DRM_ERROR("could not find ring read pointer!\n"); 1431 radeon_do_cleanup_cp(dev); 1432 return DRM_ERR(EINVAL); 1433 } 1434 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1435 if (!dev->agp_buffer_map) { 1436 DRM_ERROR("could not find dma buffer region!\n"); 1437 radeon_do_cleanup_cp(dev); 1438 return DRM_ERR(EINVAL); 1439 } 1440 1441 if (init->gart_textures_offset) { 1442 dev_priv->gart_textures = 1443 drm_core_findmap(dev, init->gart_textures_offset); 1444 if (!dev_priv->gart_textures) { 1445 DRM_ERROR("could not find GART texture region!\n"); 1446 radeon_do_cleanup_cp(dev); 1447 return DRM_ERR(EINVAL); 1448 } 1449 } 1450 1451 dev_priv->sarea_priv = 1452 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + 1453 init->sarea_priv_offset); 1454 1455#if __OS_HAS_AGP 1456 if (dev_priv->flags & CHIP_IS_AGP) { 1457 drm_core_ioremap(dev_priv->cp_ring, dev); 1458 drm_core_ioremap(dev_priv->ring_rptr, dev); 1459 drm_core_ioremap(dev->agp_buffer_map, dev); 1460 if (!dev_priv->cp_ring->handle || 1461 !dev_priv->ring_rptr->handle || 1462 !dev->agp_buffer_map->handle) { 1463 DRM_ERROR("could not find ioremap agp regions!\n"); 1464 radeon_do_cleanup_cp(dev); 1465 return DRM_ERR(EINVAL); 1466 } 1467 } else 1468#endif 1469 { 1470 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; 1471 dev_priv->ring_rptr->handle = 1472 (void *)dev_priv->ring_rptr->offset; 1473 dev->agp_buffer_map->handle = 1474 (void *)dev->agp_buffer_map->offset; 1475 1476 DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 1477 dev_priv->cp_ring->handle); 1478 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 1479 dev_priv->ring_rptr->handle); 1480 DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 1481 dev->agp_buffer_map->handle); 1482 } 1483 1484 dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION) 1485 & 0xffff) << 16; 1486 1487 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 1488 ((dev_priv->front_offset 1489 + dev_priv->fb_location) >> 10)); 1490 1491 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 1492 ((dev_priv->back_offset 1493 + dev_priv->fb_location) >> 10)); 1494 1495 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 1496 ((dev_priv->depth_offset 1497 + dev_priv->fb_location) >> 10)); 1498 1499 dev_priv->gart_size = init->gart_size; 1500 dev_priv->gart_vm_start = dev_priv->fb_location 1501 + RADEON_READ(RADEON_CONFIG_APER_SIZE); 1502 1503#if __OS_HAS_AGP 1504 if (dev_priv->flags & CHIP_IS_AGP) 1505 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1506 - dev->agp->base 1507 + dev_priv->gart_vm_start); 1508 else 1509#endif 1510 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1511 - dev->sg->handle 1512 + dev_priv->gart_vm_start); 1513 1514 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 1515 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); 1516 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", 1517 dev_priv->gart_buffers_offset); 1518 1519 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 1520 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 1521 + init->ring_size / sizeof(u32)); 1522 dev_priv->ring.size = init->ring_size; 1523 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 1524 1525 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 1526 1527 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 1528 1529#if __OS_HAS_AGP 1530 if (dev_priv->flags & CHIP_IS_AGP) { 1531 /* Turn off PCI GART */ 1532 radeon_set_pcigart(dev_priv, 0); 1533 } else 1534#endif 1535 { 1536 if (!drm_ati_pcigart_init(dev, &dev_priv->phys_pci_gart, 1537 &dev_priv->bus_pci_gart, (dev_priv->flags & CHIP_IS_PCIE))) { 1538 DRM_ERROR("failed to init PCI GART!\n"); 1539 radeon_do_cleanup_cp(dev); 1540 return DRM_ERR(ENOMEM); 1541 } 1542 1543 /* Turn on PCI GART */ 1544 radeon_set_pcigart(dev_priv, 1); 1545 } 1546 1547 radeon_cp_load_microcode(dev_priv); 1548 radeon_cp_init_ring_buffer(dev, dev_priv); 1549 1550 dev_priv->last_buf = 0; 1551 1552 radeon_do_engine_reset(dev); 1553 1554 return 0; 1555} 1556 1557static int radeon_do_cleanup_cp(drm_device_t * dev) 1558{ 1559 drm_radeon_private_t *dev_priv = dev->dev_private; 1560 DRM_DEBUG("\n"); 1561 1562 /* Make sure interrupts are disabled here because the uninstall ioctl 1563 * may not have been called from userspace and after dev_private 1564 * is freed, it's too late. 1565 */ 1566 if (dev->irq_enabled) 1567 drm_irq_uninstall(dev); 1568 1569#if __OS_HAS_AGP 1570 if (dev_priv->flags & CHIP_IS_AGP) { 1571 if (dev_priv->cp_ring != NULL) { 1572 drm_core_ioremapfree(dev_priv->cp_ring, dev); 1573 dev_priv->cp_ring = NULL; 1574 } 1575 if (dev_priv->ring_rptr != NULL) { 1576 drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1577 dev_priv->ring_rptr = NULL; 1578 } 1579 if (dev->agp_buffer_map != NULL) { 1580 drm_core_ioremapfree(dev->agp_buffer_map, dev); 1581 dev->agp_buffer_map = NULL; 1582 } 1583 } else 1584#endif 1585 { 1586 if (!drm_ati_pcigart_cleanup(dev, 1587 dev_priv->phys_pci_gart, 1588 dev_priv->bus_pci_gart)) 1589 DRM_ERROR("failed to cleanup PCI GART!\n"); 1590 } 1591 /* only clear to the start of flags */ 1592 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1593 1594 return 0; 1595} 1596 1597/* This code will reinit the Radeon CP hardware after a resume from disc. 1598 * AFAIK, it would be very difficult to pickle the state at suspend time, so 1599 * here we make sure that all Radeon hardware initialisation is re-done without 1600 * affecting running applications. 1601 * 1602 * Charl P. Botha <http://cpbotha.net> 1603 */ 1604static int radeon_do_resume_cp(drm_device_t * dev) 1605{ 1606 drm_radeon_private_t *dev_priv = dev->dev_private; 1607 1608 if (!dev_priv) { 1609 DRM_ERROR("Called with no initialization\n"); 1610 return DRM_ERR(EINVAL); 1611 } 1612 1613 DRM_DEBUG("Starting radeon_do_resume_cp()\n"); 1614 1615#if __OS_HAS_AGP 1616 if (dev_priv->flags & CHIP_IS_AGP) { 1617 /* Turn off PCI GART */ 1618 radeon_set_pcigart(dev_priv, 0); 1619 } else 1620#endif 1621 { 1622 /* Turn on PCI GART */ 1623 radeon_set_pcigart(dev_priv, 1); 1624 } 1625 1626 radeon_cp_load_microcode(dev_priv); 1627 radeon_cp_init_ring_buffer(dev, dev_priv); 1628 1629 radeon_do_engine_reset(dev); 1630 1631 DRM_DEBUG("radeon_do_resume_cp() complete\n"); 1632 1633 return 0; 1634} 1635 1636int radeon_cp_init(DRM_IOCTL_ARGS) 1637{ 1638 DRM_DEVICE; 1639 drm_radeon_init_t init; 1640 1641 LOCK_TEST_WITH_RETURN(dev, filp); 1642 1643 DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data, 1644 sizeof(init)); 1645 1646 if(init.func == RADEON_INIT_R300_CP) 1647 r300_init_reg_flags(); 1648 1649 switch (init.func) { 1650 case RADEON_INIT_CP: 1651 case RADEON_INIT_R200_CP: 1652 case RADEON_INIT_R300_CP: 1653 return radeon_do_init_cp(dev, &init); 1654 case RADEON_CLEANUP_CP: 1655 return radeon_do_cleanup_cp(dev); 1656 } 1657 1658 return DRM_ERR(EINVAL); 1659} 1660 1661int radeon_cp_start(DRM_IOCTL_ARGS) 1662{ 1663 DRM_DEVICE; 1664 drm_radeon_private_t *dev_priv = dev->dev_private; 1665 DRM_DEBUG("\n"); 1666 1667 LOCK_TEST_WITH_RETURN(dev, filp); 1668 1669 if (dev_priv->cp_running) { 1670 DRM_DEBUG("%s while CP running\n", __FUNCTION__); 1671 return 0; 1672 } 1673 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { 1674 DRM_DEBUG("%s called with bogus CP mode (%d)\n", 1675 __FUNCTION__, dev_priv->cp_mode); 1676 return 0; 1677 } 1678 1679 radeon_do_cp_start(dev_priv); 1680 1681 return 0; 1682} 1683 1684/* Stop the CP. The engine must have been idled before calling this 1685 * routine. 1686 */ 1687int radeon_cp_stop(DRM_IOCTL_ARGS) 1688{ 1689 DRM_DEVICE; 1690 drm_radeon_private_t *dev_priv = dev->dev_private; 1691 drm_radeon_cp_stop_t stop; 1692 int ret; 1693 DRM_DEBUG("\n"); 1694 1695 LOCK_TEST_WITH_RETURN(dev, filp); 1696 1697 DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data, 1698 sizeof(stop)); 1699 1700 if (!dev_priv->cp_running) 1701 return 0; 1702 1703 /* Flush any pending CP commands. This ensures any outstanding 1704 * commands are exectuted by the engine before we turn it off. 1705 */ 1706 if (stop.flush) { 1707 radeon_do_cp_flush(dev_priv); 1708 } 1709 1710 /* If we fail to make the engine go idle, we return an error 1711 * code so that the DRM ioctl wrapper can try again. 1712 */ 1713 if (stop.idle) { 1714 ret = radeon_do_cp_idle(dev_priv); 1715 if (ret) 1716 return ret; 1717 } 1718 1719 /* Finally, we can turn off the CP. If the engine isn't idle, 1720 * we will get some dropped triangles as they won't be fully 1721 * rendered before the CP is shut down. 1722 */ 1723 radeon_do_cp_stop(dev_priv); 1724 1725 /* Reset the engine */ 1726 radeon_do_engine_reset(dev); 1727 1728 return 0; 1729} 1730 1731void radeon_do_release(drm_device_t * dev) 1732{ 1733 drm_radeon_private_t *dev_priv = dev->dev_private; 1734 int i, ret; 1735 1736 if (dev_priv) { 1737 1738 if (dev_priv->cp_running) { 1739 /* Stop the cp */ 1740 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { 1741 DRM_DEBUG("radeon_do_cp_idle %d\n", ret); 1742#ifdef __linux__ 1743 schedule(); 1744#else 1745 tsleep(&ret, PZERO, "rdnrel", 1); 1746#endif 1747 } 1748 radeon_do_cp_stop(dev_priv); 1749 radeon_do_engine_reset(dev); 1750 } 1751 1752 /* Disable *all* interrupts */ 1753 if (dev_priv->mmio) /* remove this after permanent addmaps */ 1754 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 1755 1756 if (dev_priv->mmio) {/* remove all surfaces */ 1757 for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1758 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0); 1759 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0); 1760 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0); 1761 } 1762 } 1763 1764 /* Free memory heap structures */ 1765 radeon_mem_takedown(&(dev_priv->gart_heap)); 1766 radeon_mem_takedown(&(dev_priv->fb_heap)); 1767 1768 /* deallocate kernel resources */ 1769 radeon_do_cleanup_cp(dev); 1770 } 1771} 1772 1773/* Just reset the CP ring. Called as part of an X Server engine reset. 1774 */ 1775int radeon_cp_reset(DRM_IOCTL_ARGS) 1776{ 1777 DRM_DEVICE; 1778 drm_radeon_private_t *dev_priv = dev->dev_private; 1779 DRM_DEBUG("\n"); 1780 1781 LOCK_TEST_WITH_RETURN(dev, filp); 1782 1783 if (!dev_priv) { 1784 DRM_DEBUG("%s called before init done\n", __FUNCTION__); 1785 return DRM_ERR(EINVAL); 1786 } 1787 1788 radeon_do_cp_reset(dev_priv); 1789 1790 /* The CP is no longer running after an engine reset */ 1791 dev_priv->cp_running = 0; 1792 1793 return 0; 1794} 1795 1796int radeon_cp_idle(DRM_IOCTL_ARGS) 1797{ 1798 DRM_DEVICE; 1799 drm_radeon_private_t *dev_priv = dev->dev_private; 1800 DRM_DEBUG("\n"); 1801 1802 LOCK_TEST_WITH_RETURN(dev, filp); 1803 1804 return radeon_do_cp_idle(dev_priv); 1805} 1806 1807/* Added by Charl P. Botha to call radeon_do_resume_cp(). 1808 */ 1809int radeon_cp_resume(DRM_IOCTL_ARGS) 1810{ 1811 DRM_DEVICE; 1812 1813 return radeon_do_resume_cp(dev); 1814} 1815 1816int radeon_engine_reset(DRM_IOCTL_ARGS) 1817{ 1818 DRM_DEVICE; 1819 DRM_DEBUG("\n"); 1820 1821 LOCK_TEST_WITH_RETURN(dev, filp); 1822 1823 return radeon_do_engine_reset(dev); 1824} 1825 1826/* ================================================================ 1827 * Fullscreen mode 1828 */ 1829 1830/* KW: Deprecated to say the least: 1831 */ 1832int radeon_fullscreen(DRM_IOCTL_ARGS) 1833{ 1834 return 0; 1835} 1836 1837/* ================================================================ 1838 * Freelist management 1839 */ 1840 1841/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through 1842 * bufs until freelist code is used. Note this hides a problem with 1843 * the scratch register * (used to keep track of last buffer 1844 * completed) being written to before * the last buffer has actually 1845 * completed rendering. 1846 * 1847 * KW: It's also a good way to find free buffers quickly. 1848 * 1849 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't 1850 * sleep. However, bugs in older versions of radeon_accel.c mean that 1851 * we essentially have to do this, else old clients will break. 1852 * 1853 * However, it does leave open a potential deadlock where all the 1854 * buffers are held by other clients, which can't release them because 1855 * they can't get the lock. 1856 */ 1857 1858drm_buf_t *radeon_freelist_get(drm_device_t * dev) 1859{ 1860 drm_device_dma_t *dma = dev->dma; 1861 drm_radeon_private_t *dev_priv = dev->dev_private; 1862 drm_radeon_buf_priv_t *buf_priv; 1863 drm_buf_t *buf; 1864 int i, t; 1865 int start; 1866 1867 if (++dev_priv->last_buf >= dma->buf_count) 1868 dev_priv->last_buf = 0; 1869 1870 start = dev_priv->last_buf; 1871 1872 for (t = 0; t < dev_priv->usec_timeout; t++) { 1873 u32 done_age = GET_SCRATCH(1); 1874 DRM_DEBUG("done_age = %d\n", done_age); 1875 for (i = start; i < dma->buf_count; i++) { 1876 buf = dma->buflist[i]; 1877 buf_priv = buf->dev_private; 1878 if (buf->filp == 0 || (buf->pending && 1879 buf_priv->age <= done_age)) { 1880 dev_priv->stats.requested_bufs++; 1881 buf->pending = 0; 1882 return buf; 1883 } 1884 start = 0; 1885 } 1886 1887 if (t) { 1888 DRM_UDELAY(1); 1889 dev_priv->stats.freelist_loops++; 1890 } 1891 } 1892 1893 DRM_DEBUG("returning NULL!\n"); 1894 return NULL; 1895} 1896 1897#if 0 1898drm_buf_t *radeon_freelist_get(drm_device_t * dev) 1899{ 1900 drm_device_dma_t *dma = dev->dma; 1901 drm_radeon_private_t *dev_priv = dev->dev_private; 1902 drm_radeon_buf_priv_t *buf_priv; 1903 drm_buf_t *buf; 1904 int i, t; 1905 int start; 1906 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); 1907 1908 if (++dev_priv->last_buf >= dma->buf_count) 1909 dev_priv->last_buf = 0; 1910 1911 start = dev_priv->last_buf; 1912 dev_priv->stats.freelist_loops++; 1913 1914 for (t = 0; t < 2; t++) { 1915 for (i = start; i < dma->buf_count; i++) { 1916 buf = dma->buflist[i]; 1917 buf_priv = buf->dev_private; 1918 if (buf->filp == 0 || (buf->pending && 1919 buf_priv->age <= done_age)) { 1920 dev_priv->stats.requested_bufs++; 1921 buf->pending = 0; 1922 return buf; 1923 } 1924 } 1925 start = 0; 1926 } 1927 1928 return NULL; 1929} 1930#endif 1931 1932void radeon_freelist_reset(drm_device_t * dev) 1933{ 1934 drm_device_dma_t *dma = dev->dma; 1935 drm_radeon_private_t *dev_priv = dev->dev_private; 1936 int i; 1937 1938 dev_priv->last_buf = 0; 1939 for (i = 0; i < dma->buf_count; i++) { 1940 drm_buf_t *buf = dma->buflist[i]; 1941 drm_radeon_buf_priv_t *buf_priv = buf->dev_private; 1942 buf_priv->age = 0; 1943 } 1944} 1945 1946/* ================================================================ 1947 * CP command submission 1948 */ 1949 1950int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) 1951{ 1952 drm_radeon_ring_buffer_t *ring = &dev_priv->ring; 1953 int i; 1954 u32 last_head = GET_RING_HEAD(dev_priv); 1955 1956 for (i = 0; i < dev_priv->usec_timeout; i++) { 1957 u32 head = GET_RING_HEAD(dev_priv); 1958 1959 ring->space = (head - ring->tail) * sizeof(u32); 1960 if (ring->space <= 0) 1961 ring->space += ring->size; 1962 if (ring->space > n) 1963 return 0; 1964 1965 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 1966 1967 if (head != last_head) 1968 i = 0; 1969 last_head = head; 1970 1971 DRM_UDELAY(1); 1972 } 1973 1974 /* FIXME: This return value is ignored in the BEGIN_RING macro! */ 1975#if RADEON_FIFO_DEBUG 1976 radeon_status(dev_priv); 1977 DRM_ERROR("failed!\n"); 1978#endif 1979 return DRM_ERR(EBUSY); 1980} 1981 1982static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev, 1983 drm_dma_t * d) 1984{ 1985 int i; 1986 drm_buf_t *buf; 1987 1988 for (i = d->granted_count; i < d->request_count; i++) { 1989 buf = radeon_freelist_get(dev); 1990 if (!buf) 1991 return DRM_ERR(EBUSY); /* NOTE: broken client */ 1992 1993 buf->filp = filp; 1994 1995 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, 1996 sizeof(buf->idx))) 1997 return DRM_ERR(EFAULT); 1998 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, 1999 sizeof(buf->total))) 2000 return DRM_ERR(EFAULT); 2001 2002 d->granted_count++; 2003 } 2004 return 0; 2005} 2006 2007int radeon_cp_buffers(DRM_IOCTL_ARGS) 2008{ 2009 DRM_DEVICE; 2010 drm_device_dma_t *dma = dev->dma; 2011 int ret = 0; 2012 drm_dma_t __user *argp = (void __user *)data; 2013 drm_dma_t d; 2014 2015 LOCK_TEST_WITH_RETURN(dev, filp); 2016 2017 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); 2018 2019 /* Please don't send us buffers. 2020 */ 2021 if (d.send_count != 0) { 2022 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", 2023 DRM_CURRENTPID, d.send_count); 2024 return DRM_ERR(EINVAL); 2025 } 2026 2027 /* We'll send you buffers. 2028 */ 2029 if (d.request_count < 0 || d.request_count > dma->buf_count) { 2030 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", 2031 DRM_CURRENTPID, d.request_count, dma->buf_count); 2032 return DRM_ERR(EINVAL); 2033 } 2034 2035 d.granted_count = 0; 2036 2037 if (d.request_count) { 2038 ret = radeon_cp_get_buffers(filp, dev, &d); 2039 } 2040 2041 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); 2042 2043 return ret; 2044} 2045 2046/* Always create a map record for MMIO and FB memory, done from DRIVER_POSTINIT */ 2047int radeon_preinit(struct drm_device *dev, unsigned long flags) 2048{ 2049 drm_radeon_private_t *dev_priv; 2050 int ret = 0; 2051 2052 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); 2053 if (dev_priv == NULL) 2054 return DRM_ERR(ENOMEM); 2055 2056 memset(dev_priv, 0, sizeof(drm_radeon_private_t)); 2057 dev->dev_private = (void *)dev_priv; 2058 dev_priv->flags = flags; 2059 2060 switch (flags & CHIP_FAMILY_MASK) { 2061 case CHIP_R100: 2062 case CHIP_RV200: 2063 case CHIP_R200: 2064 case CHIP_R300: 2065 case CHIP_R420: 2066 dev_priv->flags |= CHIP_HAS_HIERZ; 2067 break; 2068 default: 2069 /* all other chips have no hierarchical z buffer */ 2070 break; 2071 } 2072 2073 /* Disable initmaps because it is broken on FreeBSD, and results in 2074 * crashes on startup for some. The proper fix will involve being 2075 * smarter about allocating PCI resources. 2076 */ 2077 /* 2078 ret = drm_initmap(dev, drm_get_resource_start(dev, 2), 2079 drm_get_resource_len(dev, 2), 2, _DRM_REGISTERS, 2080 _DRM_READ_ONLY); 2081 if (ret != 0) 2082 return ret; 2083 2084 ret = drm_initmap(dev, drm_get_resource_start(dev, 0), 2085 drm_get_resource_len(dev, 0), 0, _DRM_FRAME_BUFFER, 2086 _DRM_WRITE_COMBINING); 2087 if (ret != 0) 2088 return ret; 2089 */ 2090 2091 /* The original method of detecting AGP is known to not work correctly, 2092 * according to Mike Harris. The solution is to walk the capabilities 2093 * list, which should be done in drm_device_is_agp(). 2094 */ 2095 if (drm_device_is_agp(dev)) 2096 dev_priv->flags |= CHIP_IS_AGP; 2097 2098 if (drm_device_is_pcie(dev)) 2099 dev_priv->flags |= CHIP_IS_PCIE; 2100 2101 DRM_DEBUG("%s card detected\n", 2102 ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : (((dev_priv->flags & CHIP_IS_PCIE) ? "PCIE" : "PCI")))); 2103 2104#if defined(__linux__) 2105 /* Check if we need a reset */ 2106 if (! 2107 (dev_priv->mmio = 2108 drm_core_findmap(dev, pci_resource_start(dev->pdev, 2)))) 2109 return DRM_ERR(ENOMEM); 2110 2111 ret = radeon_create_i2c_busses(dev); 2112#endif 2113 return ret; 2114} 2115 2116int radeon_postcleanup(struct drm_device *dev) 2117{ 2118 drm_radeon_private_t *dev_priv = dev->dev_private; 2119 2120 DRM_DEBUG("\n"); 2121#if defined(__linux__) 2122 radeon_delete_i2c_busses(dev); 2123#endif 2124 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); 2125 2126 dev->dev_private = NULL; 2127 return 0; 2128} 2129