r600_cp.c revision 190595
1/*- 2 * Copyright 2008-2009 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Dave Airlie <airlied@redhat.com> 26 * Alex Deucher <alexander.deucher@amd.com> 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/drm/r600_cp.c 190595 2009-03-31 17:52:05Z rnoland $"); 31 32#include "dev/drm/drmP.h" 33#include "dev/drm/drm.h" 34#include "dev/drm/radeon_drm.h" 35#include "dev/drm/radeon_drv.h" 36 37#include "dev/drm/r600_microcode.h" 38 39# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ 40# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) 41 42#define R600_PTE_VALID (1 << 0) 43#define R600_PTE_SYSTEM (1 << 1) 44#define R600_PTE_SNOOPED (1 << 2) 45#define R600_PTE_READABLE (1 << 5) 46#define R600_PTE_WRITEABLE (1 << 6) 47 48/* MAX values used for gfx init */ 49#define R6XX_MAX_SH_GPRS 256 50#define R6XX_MAX_TEMP_GPRS 16 51#define R6XX_MAX_SH_THREADS 256 52#define R6XX_MAX_SH_STACK_ENTRIES 4096 53#define R6XX_MAX_BACKENDS 8 54#define R6XX_MAX_BACKENDS_MASK 0xff 55#define R6XX_MAX_SIMDS 8 56#define R6XX_MAX_SIMDS_MASK 0xff 57#define R6XX_MAX_PIPES 8 58#define R6XX_MAX_PIPES_MASK 0xff 59 60#define R7XX_MAX_SH_GPRS 256 61#define R7XX_MAX_TEMP_GPRS 16 62#define R7XX_MAX_SH_THREADS 256 63#define R7XX_MAX_SH_STACK_ENTRIES 4096 64#define R7XX_MAX_BACKENDS 8 65#define R7XX_MAX_BACKENDS_MASK 0xff 66#define R7XX_MAX_SIMDS 16 67#define R7XX_MAX_SIMDS_MASK 0xffff 68#define R7XX_MAX_PIPES 8 69#define R7XX_MAX_PIPES_MASK 0xff 70 71static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) 72{ 73 int i; 74 75 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 76 77 for (i = 0; i < dev_priv->usec_timeout; i++) { 78 int slots; 79 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 80 slots = (RADEON_READ(R600_GRBM_STATUS) 81 & R700_CMDFIFO_AVAIL_MASK); 82 else 83 slots = (RADEON_READ(R600_GRBM_STATUS) 84 & R600_CMDFIFO_AVAIL_MASK); 85 if (slots >= entries) 86 return 0; 87 DRM_UDELAY(1); 88 } 89 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", 90 RADEON_READ(R600_GRBM_STATUS), 91 RADEON_READ(R600_GRBM_STATUS2)); 92 93 return -EBUSY; 94} 95 96static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) 97{ 98 int i, ret; 99 100 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 101 102 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 103 ret = r600_do_wait_for_fifo(dev_priv, 8); 104 else 105 ret = r600_do_wait_for_fifo(dev_priv, 16); 106 if (ret) 107 return ret; 108 for (i = 0; i < dev_priv->usec_timeout; i++) { 109 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) 110 return 0; 111 DRM_UDELAY(1); 112 } 113 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", 114 RADEON_READ(R600_GRBM_STATUS), 115 RADEON_READ(R600_GRBM_STATUS2)); 116 117 return -EBUSY; 118} 119 120void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) 121{ 122#ifdef __linux__ 123 struct drm_sg_mem *entry = dev->sg; 124 int max_pages; 125 int pages; 126 int i; 127#endif 128 if (gart_info->bus_addr) { 129#ifdef __linux__ 130 max_pages = (gart_info->table_size / sizeof(u32)); 131 pages = (entry->pages <= max_pages) 132 ? entry->pages : max_pages; 133 134 for (i = 0; i < pages; i++) { 135 if (!entry->busaddr[i]) 136 break; 137 pci_unmap_single(dev->pdev, entry->busaddr[i], 138 PAGE_SIZE, PCI_DMA_TODEVICE); 139 } 140#endif 141 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) 142 gart_info->bus_addr = 0; 143 } 144} 145 146/* R600 has page table setup */ 147int r600_page_table_init(struct drm_device *dev) 148{ 149 drm_radeon_private_t *dev_priv = dev->dev_private; 150 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; 151 struct drm_sg_mem *entry = dev->sg; 152 int ret = 0; 153 int i, j; 154 int max_pages, pages; 155 u64 *pci_gart, page_base; 156 dma_addr_t entry_addr; 157 158 /* okay page table is available - lets rock */ 159 160 /* PTEs are 64-bits */ 161 pci_gart = (u64 *)gart_info->addr; 162 163 max_pages = (gart_info->table_size / sizeof(u64)); 164 pages = (entry->pages <= max_pages) ? entry->pages : max_pages; 165 166 memset(pci_gart, 0, max_pages * sizeof(u64)); 167 168 for (i = 0; i < pages; i++) { 169#ifdef __linux__ 170 entry->busaddr[i] = pci_map_single(dev->pdev, 171 page_address(entry-> 172 pagelist[i]), 173 PAGE_SIZE, PCI_DMA_TODEVICE); 174 if (entry->busaddr[i] == 0) { 175 DRM_ERROR("unable to map PCIGART pages!\n"); 176 r600_page_table_cleanup(dev, gart_info); 177 goto done; 178 } 179#endif 180 entry_addr = entry->busaddr[i]; 181 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { 182 page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK; 183 page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 184 page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 185 186 *pci_gart = page_base; 187 188 if ((i % 128) == 0) 189 DRM_DEBUG("page entry %d: 0x%016llx\n", 190 i, (unsigned long long)page_base); 191 pci_gart++; 192 entry_addr += ATI_PCIGART_PAGE_SIZE; 193 } 194 } 195 ret = 1; 196#ifdef __linux__ 197done: 198#endif 199 return ret; 200} 201 202static void r600_vm_flush_gart_range(struct drm_device *dev) 203{ 204 drm_radeon_private_t *dev_priv = dev->dev_private; 205 u32 resp, countdown = 1000; 206 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); 207 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 208 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2); 209 210 do { 211 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE); 212 countdown--; 213 DRM_UDELAY(1); 214 } while (((resp & 0xf0) == 0) && countdown); 215} 216 217static void r600_vm_init(struct drm_device *dev) 218{ 219 drm_radeon_private_t *dev_priv = dev->dev_private; 220 /* initialise the VM to use the page table we constructed up there */ 221 u32 vm_c0, i; 222 u32 mc_rd_a; 223 u32 vm_l2_cntl, vm_l2_cntl3; 224 /* okay set up the PCIE aperture type thingo */ 225 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 226 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 227 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 228 229 /* setup MC RD a */ 230 mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS | 231 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) | 232 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY; 233 234 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a); 235 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a); 236 237 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a); 238 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a); 239 240 RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a); 241 RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a); 242 243 RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a); 244 RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a); 245 246 RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING); 247 RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/); 248 249 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a); 250 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a); 251 252 RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE); 253 RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a); 254 255 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 256 vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7); 257 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 258 259 RADEON_WRITE(R600_VM_L2_CNTL2, 0); 260 vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) | 261 R600_VM_L2_CNTL3_BANK_SELECT_1(1) | 262 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2)); 263 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 264 265 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 266 267 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 268 269 vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 270 271 /* disable all other contexts */ 272 for (i = 1; i < 8; i++) 273 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 274 275 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 276 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 277 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 278 279 r600_vm_flush_gart_range(dev); 280} 281 282/* load r600 microcode */ 283static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) 284{ 285 const u32 (*cp)[3]; 286 const u32 *pfp; 287 int i; 288 289 r600_do_cp_stop(dev_priv); 290 291 RADEON_WRITE(R600_CP_RB_CNTL, 292 R600_RB_NO_UPDATE | 293 R600_RB_BLKSZ(15) | 294 R600_RB_BUFSZ(3)); 295 296 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 297 RADEON_READ(R600_GRBM_SOFT_RESET); 298 DRM_UDELAY(15000); 299 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 300 301 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 302 303 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 304 case CHIP_R600: 305 DRM_INFO("Loading R600 Microcode\n"); 306 cp = R600_cp_microcode; 307 pfp = R600_pfp_microcode; 308 break; 309 case CHIP_RV610: 310 DRM_INFO("Loading RV610 Microcode\n"); 311 cp = RV610_cp_microcode; 312 pfp = RV610_pfp_microcode; 313 break; 314 case CHIP_RV630: 315 DRM_INFO("Loading RV630 Microcode\n"); 316 cp = RV630_cp_microcode; 317 pfp = RV630_pfp_microcode; 318 break; 319 case CHIP_RV620: 320 DRM_INFO("Loading RV620 Microcode\n"); 321 cp = RV620_cp_microcode; 322 pfp = RV620_pfp_microcode; 323 break; 324 case CHIP_RV635: 325 DRM_INFO("Loading RV635 Microcode\n"); 326 cp = RV635_cp_microcode; 327 pfp = RV635_pfp_microcode; 328 break; 329 case CHIP_RV670: 330 DRM_INFO("Loading RV670 Microcode\n"); 331 cp = RV670_cp_microcode; 332 pfp = RV670_pfp_microcode; 333 break; 334 case CHIP_RS780: 335 DRM_INFO("Loading RS780 Microcode\n"); 336 cp = RS780_cp_microcode; 337 pfp = RS780_pfp_microcode; 338 break; 339 default: 340 goto no_microcode; 341 } 342 343 for (i = 0; i != PM4_UCODE_SIZE; i++) { 344 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][0]); 345 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][1]); 346 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][2]); 347 } 348 349 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 350 for (i = 0; i != PFP_UCODE_SIZE; i++) 351 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]); 352no_microcode:; 353 354 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 355 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 356 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 357} 358 359static void r700_vm_init(struct drm_device *dev) 360{ 361 drm_radeon_private_t *dev_priv = dev->dev_private; 362 /* initialise the VM to use the page table we constructed up there */ 363 u32 vm_c0, i; 364 u32 mc_vm_md_l1; 365 u32 vm_l2_cntl, vm_l2_cntl3; 366 /* okay set up the PCIE aperture type thingo */ 367 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 368 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 369 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 370 371 mc_vm_md_l1 = R700_ENABLE_L1_TLB | 372 R700_ENABLE_L1_FRAGMENT_PROCESSING | 373 R700_SYSTEM_ACCESS_MODE_IN_SYS | 374 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 375 R700_EFFECTIVE_L1_TLB_SIZE(5) | 376 R700_EFFECTIVE_L1_QUEUE_SIZE(5); 377 378 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1); 379 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1); 380 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1); 381 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1); 382 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1); 383 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1); 384 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1); 385 386 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 387 vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7); 388 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 389 390 RADEON_WRITE(R600_VM_L2_CNTL2, 0); 391 vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2); 392 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 393 394 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 395 396 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 397 398 vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 399 400 /* disable all other contexts */ 401 for (i = 1; i < 8; i++) 402 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 403 404 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 405 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 406 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 407 408 r600_vm_flush_gart_range(dev); 409} 410 411/* load r600 microcode */ 412static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) 413{ 414 const u32 *pfp; 415 const u32 *cp; 416 int i; 417 418 r600_do_cp_stop(dev_priv); 419 420 RADEON_WRITE(R600_CP_RB_CNTL, 421 R600_RB_NO_UPDATE | 422 (15 << 8) | 423 (3 << 0)); 424 425 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 426 RADEON_READ(R600_GRBM_SOFT_RESET); 427 DRM_UDELAY(15000); 428 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 429 430 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 431 case CHIP_RV770: 432 DRM_INFO("Loading RV770 Microcode\n"); 433 pfp = RV770_pfp_microcode; 434 cp = RV770_cp_microcode; 435 break; 436 case CHIP_RV730: 437 DRM_INFO("Loading RV730 Microcode\n"); 438 pfp = RV730_pfp_microcode; 439 cp = RV730_cp_microcode; 440 break; 441 case CHIP_RV710: 442 DRM_INFO("Loading RV710 Microcode\n"); 443 pfp = RV710_pfp_microcode; 444 cp = RV710_cp_microcode; 445 break; 446 default: 447 goto no_microcode; 448 } 449 450 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 451 for (i = 0; i != R700_PFP_UCODE_SIZE; i++) 452 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]); 453 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 454 455 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 456 for (i = 0; i != R700_PM4_UCODE_SIZE; i++) 457 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i]); 458 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 459no_microcode:; 460 461 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 462 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 463 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 464} 465 466static void r600_test_writeback(drm_radeon_private_t *dev_priv) 467{ 468 u32 tmp; 469 470 /* Start with assuming that writeback doesn't work */ 471 dev_priv->writeback_works = 0; 472 473 /* Writeback doesn't seem to work everywhere, test it here and possibly 474 * enable it if it appears to work 475 */ 476 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 477 478 RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef); 479 480 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 481 u32 val; 482 483 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1)); 484 if (val == 0xdeadbeef) 485 break; 486 DRM_UDELAY(1); 487 } 488 489 if (tmp < dev_priv->usec_timeout) { 490 dev_priv->writeback_works = 1; 491 DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 492 } else { 493 dev_priv->writeback_works = 0; 494 DRM_INFO("writeback test failed\n"); 495 } 496 if (radeon_no_wb == 1) { 497 dev_priv->writeback_works = 0; 498 DRM_INFO("writeback forced off\n"); 499 } 500 501 if (!dev_priv->writeback_works) { 502 /* Disable writeback to avoid unnecessary bus master transfer */ 503 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) | 504 RADEON_RB_NO_UPDATE); 505 RADEON_WRITE(R600_SCRATCH_UMSK, 0); 506 } 507} 508 509int r600_do_engine_reset(struct drm_device *dev) 510{ 511 drm_radeon_private_t *dev_priv = dev->dev_private; 512 u32 cp_ptr, cp_me_cntl, cp_rb_cntl; 513 514 DRM_INFO("Resetting GPU\n"); 515 516 cp_ptr = RADEON_READ(R600_CP_RB_WPTR); 517 cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL); 518 RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT); 519 520 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff); 521 RADEON_READ(R600_GRBM_SOFT_RESET); 522 DRM_UDELAY(50); 523 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 524 RADEON_READ(R600_GRBM_SOFT_RESET); 525 526 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 527 cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL); 528 RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA); 529 530 RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); 531 RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); 532 RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl); 533 RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl); 534 535 /* Reset the CP ring */ 536 r600_do_cp_reset(dev_priv); 537 538 /* The CP is no longer running after an engine reset */ 539 dev_priv->cp_running = 0; 540 541 /* Reset any pending vertex, indirect buffers */ 542 radeon_freelist_reset(dev); 543 544 return 0; 545 546} 547 548static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 549 u32 num_backends, 550 u32 backend_disable_mask) 551{ 552 u32 backend_map = 0; 553 u32 enabled_backends_mask; 554 u32 enabled_backends_count; 555 u32 cur_pipe; 556 u32 swizzle_pipe[R6XX_MAX_PIPES]; 557 u32 cur_backend; 558 u32 i; 559 560 if (num_tile_pipes > R6XX_MAX_PIPES) 561 num_tile_pipes = R6XX_MAX_PIPES; 562 if (num_tile_pipes < 1) 563 num_tile_pipes = 1; 564 if (num_backends > R6XX_MAX_BACKENDS) 565 num_backends = R6XX_MAX_BACKENDS; 566 if (num_backends < 1) 567 num_backends = 1; 568 569 enabled_backends_mask = 0; 570 enabled_backends_count = 0; 571 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { 572 if (((backend_disable_mask >> i) & 1) == 0) { 573 enabled_backends_mask |= (1 << i); 574 ++enabled_backends_count; 575 } 576 if (enabled_backends_count == num_backends) 577 break; 578 } 579 580 if (enabled_backends_count == 0) { 581 enabled_backends_mask = 1; 582 enabled_backends_count = 1; 583 } 584 585 if (enabled_backends_count != num_backends) 586 num_backends = enabled_backends_count; 587 588 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); 589 switch (num_tile_pipes) { 590 case 1: 591 swizzle_pipe[0] = 0; 592 break; 593 case 2: 594 swizzle_pipe[0] = 0; 595 swizzle_pipe[1] = 1; 596 break; 597 case 3: 598 swizzle_pipe[0] = 0; 599 swizzle_pipe[1] = 1; 600 swizzle_pipe[2] = 2; 601 break; 602 case 4: 603 swizzle_pipe[0] = 0; 604 swizzle_pipe[1] = 1; 605 swizzle_pipe[2] = 2; 606 swizzle_pipe[3] = 3; 607 break; 608 case 5: 609 swizzle_pipe[0] = 0; 610 swizzle_pipe[1] = 1; 611 swizzle_pipe[2] = 2; 612 swizzle_pipe[3] = 3; 613 swizzle_pipe[4] = 4; 614 break; 615 case 6: 616 swizzle_pipe[0] = 0; 617 swizzle_pipe[1] = 2; 618 swizzle_pipe[2] = 4; 619 swizzle_pipe[3] = 5; 620 swizzle_pipe[4] = 1; 621 swizzle_pipe[5] = 3; 622 break; 623 case 7: 624 swizzle_pipe[0] = 0; 625 swizzle_pipe[1] = 2; 626 swizzle_pipe[2] = 4; 627 swizzle_pipe[3] = 6; 628 swizzle_pipe[4] = 1; 629 swizzle_pipe[5] = 3; 630 swizzle_pipe[6] = 5; 631 break; 632 case 8: 633 swizzle_pipe[0] = 0; 634 swizzle_pipe[1] = 2; 635 swizzle_pipe[2] = 4; 636 swizzle_pipe[3] = 6; 637 swizzle_pipe[4] = 1; 638 swizzle_pipe[5] = 3; 639 swizzle_pipe[6] = 5; 640 swizzle_pipe[7] = 7; 641 break; 642 } 643 644 cur_backend = 0; 645 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 646 while (((1 << cur_backend) & enabled_backends_mask) == 0) 647 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 648 649 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 650 651 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 652 } 653 654 return backend_map; 655} 656 657static int r600_count_pipe_bits(uint32_t val) 658{ 659 int i, ret = 0; 660 for (i = 0; i < 32; i++) { 661 ret += val & 1; 662 val >>= 1; 663 } 664 return ret; 665} 666 667static void r600_gfx_init(struct drm_device *dev, 668 drm_radeon_private_t *dev_priv) 669{ 670 int i, j, num_qd_pipes; 671 u32 sx_debug_1; 672 u32 tc_cntl; 673 u32 arb_pop; 674 u32 num_gs_verts_per_thread; 675 u32 vgt_gs_per_es; 676 u32 gs_prim_buffer_depth = 0; 677 u32 sq_ms_fifo_sizes; 678 u32 sq_config; 679 u32 sq_gpr_resource_mgmt_1 = 0; 680 u32 sq_gpr_resource_mgmt_2 = 0; 681 u32 sq_thread_resource_mgmt = 0; 682 u32 sq_stack_resource_mgmt_1 = 0; 683 u32 sq_stack_resource_mgmt_2 = 0; 684 u32 hdp_host_path_cntl; 685 u32 backend_map; 686 u32 gb_tiling_config = 0; 687 u32 cc_rb_backend_disable = 0; 688 u32 cc_gc_shader_pipe_config = 0; 689 u32 ramcfg; 690 691 /* setup chip specs */ 692 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 693 case CHIP_R600: 694 dev_priv->r600_max_pipes = 4; 695 dev_priv->r600_max_tile_pipes = 8; 696 dev_priv->r600_max_simds = 4; 697 dev_priv->r600_max_backends = 4; 698 dev_priv->r600_max_gprs = 256; 699 dev_priv->r600_max_threads = 192; 700 dev_priv->r600_max_stack_entries = 256; 701 dev_priv->r600_max_hw_contexts = 8; 702 dev_priv->r600_max_gs_threads = 16; 703 dev_priv->r600_sx_max_export_size = 128; 704 dev_priv->r600_sx_max_export_pos_size = 16; 705 dev_priv->r600_sx_max_export_smx_size = 128; 706 dev_priv->r600_sq_num_cf_insts = 2; 707 break; 708 case CHIP_RV630: 709 case CHIP_RV635: 710 dev_priv->r600_max_pipes = 2; 711 dev_priv->r600_max_tile_pipes = 2; 712 dev_priv->r600_max_simds = 3; 713 dev_priv->r600_max_backends = 1; 714 dev_priv->r600_max_gprs = 128; 715 dev_priv->r600_max_threads = 192; 716 dev_priv->r600_max_stack_entries = 128; 717 dev_priv->r600_max_hw_contexts = 8; 718 dev_priv->r600_max_gs_threads = 4; 719 dev_priv->r600_sx_max_export_size = 128; 720 dev_priv->r600_sx_max_export_pos_size = 16; 721 dev_priv->r600_sx_max_export_smx_size = 128; 722 dev_priv->r600_sq_num_cf_insts = 2; 723 break; 724 case CHIP_RV610: 725 case CHIP_RS780: 726 case CHIP_RV620: 727 dev_priv->r600_max_pipes = 1; 728 dev_priv->r600_max_tile_pipes = 1; 729 dev_priv->r600_max_simds = 2; 730 dev_priv->r600_max_backends = 1; 731 dev_priv->r600_max_gprs = 128; 732 dev_priv->r600_max_threads = 192; 733 dev_priv->r600_max_stack_entries = 128; 734 dev_priv->r600_max_hw_contexts = 4; 735 dev_priv->r600_max_gs_threads = 4; 736 dev_priv->r600_sx_max_export_size = 128; 737 dev_priv->r600_sx_max_export_pos_size = 16; 738 dev_priv->r600_sx_max_export_smx_size = 128; 739 dev_priv->r600_sq_num_cf_insts = 1; 740 break; 741 case CHIP_RV670: 742 dev_priv->r600_max_pipes = 4; 743 dev_priv->r600_max_tile_pipes = 4; 744 dev_priv->r600_max_simds = 4; 745 dev_priv->r600_max_backends = 4; 746 dev_priv->r600_max_gprs = 192; 747 dev_priv->r600_max_threads = 192; 748 dev_priv->r600_max_stack_entries = 256; 749 dev_priv->r600_max_hw_contexts = 8; 750 dev_priv->r600_max_gs_threads = 16; 751 dev_priv->r600_sx_max_export_size = 128; 752 dev_priv->r600_sx_max_export_pos_size = 16; 753 dev_priv->r600_sx_max_export_smx_size = 128; 754 dev_priv->r600_sq_num_cf_insts = 2; 755 break; 756 default: 757 break; 758 } 759 760 /* Initialize HDP */ 761 j = 0; 762 for (i = 0; i < 32; i++) { 763 RADEON_WRITE((0x2c14 + j), 0x00000000); 764 RADEON_WRITE((0x2c18 + j), 0x00000000); 765 RADEON_WRITE((0x2c1c + j), 0x00000000); 766 RADEON_WRITE((0x2c20 + j), 0x00000000); 767 RADEON_WRITE((0x2c24 + j), 0x00000000); 768 j += 0x18; 769 } 770 771 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 772 773 /* setup tiling, simd, pipe config */ 774 ramcfg = RADEON_READ(R600_RAMCFG); 775 776 switch (dev_priv->r600_max_tile_pipes) { 777 case 1: 778 gb_tiling_config |= R600_PIPE_TILING(0); 779 break; 780 case 2: 781 gb_tiling_config |= R600_PIPE_TILING(1); 782 break; 783 case 4: 784 gb_tiling_config |= R600_PIPE_TILING(2); 785 break; 786 case 8: 787 gb_tiling_config |= R600_PIPE_TILING(3); 788 break; 789 default: 790 break; 791 } 792 793 gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK); 794 795 gb_tiling_config |= R600_GROUP_SIZE(0); 796 797 if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) { 798 gb_tiling_config |= R600_ROW_TILING(3); 799 gb_tiling_config |= R600_SAMPLE_SPLIT(3); 800 } else { 801 gb_tiling_config |= 802 R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 803 gb_tiling_config |= 804 R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 805 } 806 807 gb_tiling_config |= R600_BANK_SWAPS(1); 808 809 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, 810 dev_priv->r600_max_backends, 811 (0xff << dev_priv->r600_max_backends) & 0xff); 812 gb_tiling_config |= R600_BACKEND_MAP(backend_map); 813 814 cc_gc_shader_pipe_config = 815 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); 816 cc_gc_shader_pipe_config |= 817 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); 818 819 cc_rb_backend_disable = 820 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK); 821 822 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 823 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 824 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 825 826 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 827 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 828 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 829 830 num_qd_pipes = 831 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK); 832 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 833 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 834 835 /* set HW defaults for 3D engine */ 836 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 837 R600_ROQ_IB2_START(0x2b))); 838 839 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) | 840 R600_ROQ_END(0x40))); 841 842 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | 843 R600_SYNC_GRADIENT | 844 R600_SYNC_WALKER | 845 R600_SYNC_ALIGNER)); 846 847 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) 848 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021); 849 850 sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1); 851 sx_debug_1 |= R600_SMX_EVENT_RELEASE; 852 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600)) 853 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS; 854 RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1); 855 856 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 857 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 858 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 859 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 860 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) 861 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE); 862 else 863 RADEON_WRITE(R600_DB_DEBUG, 0); 864 865 RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) | 866 R600_DEPTH_FLUSH(16) | 867 R600_DEPTH_PENDING_FREE(4) | 868 R600_DEPTH_CACHELINE_FREE(16))); 869 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 870 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0); 871 872 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 873 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0)); 874 875 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES); 876 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 877 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 878 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 879 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) | 880 R600_FETCH_FIFO_HIWATER(0xa) | 881 R600_DONE_FIFO_HIWATER(0xe0) | 882 R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 883 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 884 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { 885 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff); 886 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4); 887 } 888 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 889 890 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 891 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 892 */ 893 sq_config = RADEON_READ(R600_SQ_CONFIG); 894 sq_config &= ~(R600_PS_PRIO(3) | 895 R600_VS_PRIO(3) | 896 R600_GS_PRIO(3) | 897 R600_ES_PRIO(3)); 898 sq_config |= (R600_DX9_CONSTS | 899 R600_VC_ENABLE | 900 R600_PS_PRIO(0) | 901 R600_VS_PRIO(1) | 902 R600_GS_PRIO(2) | 903 R600_ES_PRIO(3)); 904 905 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) { 906 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) | 907 R600_NUM_VS_GPRS(124) | 908 R600_NUM_CLAUSE_TEMP_GPRS(4)); 909 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) | 910 R600_NUM_ES_GPRS(0)); 911 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) | 912 R600_NUM_VS_THREADS(48) | 913 R600_NUM_GS_THREADS(4) | 914 R600_NUM_ES_THREADS(4)); 915 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) | 916 R600_NUM_VS_STACK_ENTRIES(128)); 917 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) | 918 R600_NUM_ES_STACK_ENTRIES(0)); 919 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 920 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 921 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { 922 /* no vertex cache */ 923 sq_config &= ~R600_VC_ENABLE; 924 925 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 926 R600_NUM_VS_GPRS(44) | 927 R600_NUM_CLAUSE_TEMP_GPRS(2)); 928 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 929 R600_NUM_ES_GPRS(17)); 930 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 931 R600_NUM_VS_THREADS(78) | 932 R600_NUM_GS_THREADS(4) | 933 R600_NUM_ES_THREADS(31)); 934 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 935 R600_NUM_VS_STACK_ENTRIES(40)); 936 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 937 R600_NUM_ES_STACK_ENTRIES(16)); 938 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 939 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { 940 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 941 R600_NUM_VS_GPRS(44) | 942 R600_NUM_CLAUSE_TEMP_GPRS(2)); 943 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) | 944 R600_NUM_ES_GPRS(18)); 945 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 946 R600_NUM_VS_THREADS(78) | 947 R600_NUM_GS_THREADS(4) | 948 R600_NUM_ES_THREADS(31)); 949 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 950 R600_NUM_VS_STACK_ENTRIES(40)); 951 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 952 R600_NUM_ES_STACK_ENTRIES(16)); 953 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) { 954 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 955 R600_NUM_VS_GPRS(44) | 956 R600_NUM_CLAUSE_TEMP_GPRS(2)); 957 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 958 R600_NUM_ES_GPRS(17)); 959 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 960 R600_NUM_VS_THREADS(78) | 961 R600_NUM_GS_THREADS(4) | 962 R600_NUM_ES_THREADS(31)); 963 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) | 964 R600_NUM_VS_STACK_ENTRIES(64)); 965 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) | 966 R600_NUM_ES_STACK_ENTRIES(64)); 967 } 968 969 RADEON_WRITE(R600_SQ_CONFIG, sq_config); 970 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 971 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 972 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 973 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 974 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 975 976 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 977 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 978 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) 979 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY)); 980 else 981 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC)); 982 983 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) | 984 R600_S0_Y(0x4) | 985 R600_S1_X(0x4) | 986 R600_S1_Y(0xc))); 987 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) | 988 R600_S0_Y(0xe) | 989 R600_S1_X(0x2) | 990 R600_S1_Y(0x2) | 991 R600_S2_X(0xa) | 992 R600_S2_Y(0x6) | 993 R600_S3_X(0x6) | 994 R600_S3_Y(0xa))); 995 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) | 996 R600_S0_Y(0xb) | 997 R600_S1_X(0x4) | 998 R600_S1_Y(0xc) | 999 R600_S2_X(0x1) | 1000 R600_S2_Y(0x6) | 1001 R600_S3_X(0xa) | 1002 R600_S3_Y(0xe))); 1003 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) | 1004 R600_S4_Y(0x1) | 1005 R600_S5_X(0x0) | 1006 R600_S5_Y(0x0) | 1007 R600_S6_X(0xb) | 1008 R600_S6_Y(0x4) | 1009 R600_S7_X(0x7) | 1010 R600_S7_Y(0x8))); 1011 1012 1013 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1014 case CHIP_R600: 1015 case CHIP_RV630: 1016 case CHIP_RV635: 1017 gs_prim_buffer_depth = 0; 1018 break; 1019 case CHIP_RV610: 1020 case CHIP_RS780: 1021 case CHIP_RV620: 1022 gs_prim_buffer_depth = 32; 1023 break; 1024 case CHIP_RV670: 1025 gs_prim_buffer_depth = 128; 1026 break; 1027 default: 1028 break; 1029 } 1030 1031 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1032 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1033 /* Max value for this is 256 */ 1034 if (vgt_gs_per_es > 256) 1035 vgt_gs_per_es = 256; 1036 1037 RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1038 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1039 RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1040 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1041 1042 /* more default values. 2D/3D driver should adjust as needed */ 1043 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1044 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1045 RADEON_WRITE(R600_SX_MISC, 0); 1046 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1047 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1048 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1049 RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1050 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1051 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1052 1053 /* clear render buffer base addresses */ 1054 RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1055 RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1056 RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1057 RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1058 RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1059 RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1060 RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1061 RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1062 1063 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1064 case CHIP_RV610: 1065 case CHIP_RS780: 1066 case CHIP_RV620: 1067 tc_cntl = R600_TC_L2_SIZE(8); 1068 break; 1069 case CHIP_RV630: 1070 case CHIP_RV635: 1071 tc_cntl = R600_TC_L2_SIZE(4); 1072 break; 1073 case CHIP_R600: 1074 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT; 1075 break; 1076 default: 1077 tc_cntl = R600_TC_L2_SIZE(0); 1078 break; 1079 } 1080 1081 RADEON_WRITE(R600_TC_CNTL, tc_cntl); 1082 1083 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1084 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1085 1086 arb_pop = RADEON_READ(R600_ARB_POP); 1087 arb_pop |= R600_ENABLE_TC128; 1088 RADEON_WRITE(R600_ARB_POP, arb_pop); 1089 1090 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1091 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1092 R600_NUM_CLIP_SEQ(3))); 1093 RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095)); 1094 1095} 1096 1097static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 1098 u32 num_backends, 1099 u32 backend_disable_mask) 1100{ 1101 u32 backend_map = 0; 1102 u32 enabled_backends_mask; 1103 u32 enabled_backends_count; 1104 u32 cur_pipe; 1105 u32 swizzle_pipe[R7XX_MAX_PIPES]; 1106 u32 cur_backend; 1107 u32 i; 1108 1109 if (num_tile_pipes > R7XX_MAX_PIPES) 1110 num_tile_pipes = R7XX_MAX_PIPES; 1111 if (num_tile_pipes < 1) 1112 num_tile_pipes = 1; 1113 if (num_backends > R7XX_MAX_BACKENDS) 1114 num_backends = R7XX_MAX_BACKENDS; 1115 if (num_backends < 1) 1116 num_backends = 1; 1117 1118 enabled_backends_mask = 0; 1119 enabled_backends_count = 0; 1120 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 1121 if (((backend_disable_mask >> i) & 1) == 0) { 1122 enabled_backends_mask |= (1 << i); 1123 ++enabled_backends_count; 1124 } 1125 if (enabled_backends_count == num_backends) 1126 break; 1127 } 1128 1129 if (enabled_backends_count == 0) { 1130 enabled_backends_mask = 1; 1131 enabled_backends_count = 1; 1132 } 1133 1134 if (enabled_backends_count != num_backends) 1135 num_backends = enabled_backends_count; 1136 1137 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 1138 switch (num_tile_pipes) { 1139 case 1: 1140 swizzle_pipe[0] = 0; 1141 break; 1142 case 2: 1143 swizzle_pipe[0] = 0; 1144 swizzle_pipe[1] = 1; 1145 break; 1146 case 3: 1147 swizzle_pipe[0] = 0; 1148 swizzle_pipe[1] = 2; 1149 swizzle_pipe[2] = 1; 1150 break; 1151 case 4: 1152 swizzle_pipe[0] = 0; 1153 swizzle_pipe[1] = 2; 1154 swizzle_pipe[2] = 3; 1155 swizzle_pipe[3] = 1; 1156 break; 1157 case 5: 1158 swizzle_pipe[0] = 0; 1159 swizzle_pipe[1] = 2; 1160 swizzle_pipe[2] = 4; 1161 swizzle_pipe[3] = 1; 1162 swizzle_pipe[4] = 3; 1163 break; 1164 case 6: 1165 swizzle_pipe[0] = 0; 1166 swizzle_pipe[1] = 2; 1167 swizzle_pipe[2] = 4; 1168 swizzle_pipe[3] = 5; 1169 swizzle_pipe[4] = 3; 1170 swizzle_pipe[5] = 1; 1171 break; 1172 case 7: 1173 swizzle_pipe[0] = 0; 1174 swizzle_pipe[1] = 2; 1175 swizzle_pipe[2] = 4; 1176 swizzle_pipe[3] = 6; 1177 swizzle_pipe[4] = 3; 1178 swizzle_pipe[5] = 1; 1179 swizzle_pipe[6] = 5; 1180 break; 1181 case 8: 1182 swizzle_pipe[0] = 0; 1183 swizzle_pipe[1] = 2; 1184 swizzle_pipe[2] = 4; 1185 swizzle_pipe[3] = 6; 1186 swizzle_pipe[4] = 3; 1187 swizzle_pipe[5] = 1; 1188 swizzle_pipe[6] = 7; 1189 swizzle_pipe[7] = 5; 1190 break; 1191 } 1192 1193 cur_backend = 0; 1194 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 1195 while (((1 << cur_backend) & enabled_backends_mask) == 0) 1196 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1197 1198 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 1199 1200 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1201 } 1202 1203 return backend_map; 1204} 1205 1206static void r700_gfx_init(struct drm_device *dev, 1207 drm_radeon_private_t *dev_priv) 1208{ 1209 int i, j, num_qd_pipes; 1210 u32 sx_debug_1; 1211 u32 smx_dc_ctl0; 1212 u32 num_gs_verts_per_thread; 1213 u32 vgt_gs_per_es; 1214 u32 gs_prim_buffer_depth = 0; 1215 u32 sq_ms_fifo_sizes; 1216 u32 sq_config; 1217 u32 sq_thread_resource_mgmt; 1218 u32 hdp_host_path_cntl; 1219 u32 sq_dyn_gpr_size_simd_ab_0; 1220 u32 backend_map; 1221 u32 gb_tiling_config = 0; 1222 u32 cc_rb_backend_disable = 0; 1223 u32 cc_gc_shader_pipe_config = 0; 1224 u32 mc_arb_ramcfg; 1225 u32 db_debug4; 1226 1227 /* setup chip specs */ 1228 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1229 case CHIP_RV770: 1230 dev_priv->r600_max_pipes = 4; 1231 dev_priv->r600_max_tile_pipes = 8; 1232 dev_priv->r600_max_simds = 10; 1233 dev_priv->r600_max_backends = 4; 1234 dev_priv->r600_max_gprs = 256; 1235 dev_priv->r600_max_threads = 248; 1236 dev_priv->r600_max_stack_entries = 512; 1237 dev_priv->r600_max_hw_contexts = 8; 1238 dev_priv->r600_max_gs_threads = 16 * 2; 1239 dev_priv->r600_sx_max_export_size = 128; 1240 dev_priv->r600_sx_max_export_pos_size = 16; 1241 dev_priv->r600_sx_max_export_smx_size = 112; 1242 dev_priv->r600_sq_num_cf_insts = 2; 1243 1244 dev_priv->r700_sx_num_of_sets = 7; 1245 dev_priv->r700_sc_prim_fifo_size = 0xF9; 1246 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1247 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1248 break; 1249 case CHIP_RV730: 1250 dev_priv->r600_max_pipes = 2; 1251 dev_priv->r600_max_tile_pipes = 4; 1252 dev_priv->r600_max_simds = 8; 1253 dev_priv->r600_max_backends = 2; 1254 dev_priv->r600_max_gprs = 128; 1255 dev_priv->r600_max_threads = 248; 1256 dev_priv->r600_max_stack_entries = 256; 1257 dev_priv->r600_max_hw_contexts = 8; 1258 dev_priv->r600_max_gs_threads = 16 * 2; 1259 dev_priv->r600_sx_max_export_size = 256; 1260 dev_priv->r600_sx_max_export_pos_size = 32; 1261 dev_priv->r600_sx_max_export_smx_size = 224; 1262 dev_priv->r600_sq_num_cf_insts = 2; 1263 1264 dev_priv->r700_sx_num_of_sets = 7; 1265 dev_priv->r700_sc_prim_fifo_size = 0xf9; 1266 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1267 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1268 break; 1269 case CHIP_RV710: 1270 dev_priv->r600_max_pipes = 2; 1271 dev_priv->r600_max_tile_pipes = 2; 1272 dev_priv->r600_max_simds = 2; 1273 dev_priv->r600_max_backends = 1; 1274 dev_priv->r600_max_gprs = 256; 1275 dev_priv->r600_max_threads = 192; 1276 dev_priv->r600_max_stack_entries = 256; 1277 dev_priv->r600_max_hw_contexts = 4; 1278 dev_priv->r600_max_gs_threads = 8 * 2; 1279 dev_priv->r600_sx_max_export_size = 128; 1280 dev_priv->r600_sx_max_export_pos_size = 16; 1281 dev_priv->r600_sx_max_export_smx_size = 112; 1282 dev_priv->r600_sq_num_cf_insts = 1; 1283 1284 dev_priv->r700_sx_num_of_sets = 7; 1285 dev_priv->r700_sc_prim_fifo_size = 0x40; 1286 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1287 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1288 break; 1289 default: 1290 break; 1291 } 1292 1293 /* Initialize HDP */ 1294 j = 0; 1295 for (i = 0; i < 32; i++) { 1296 RADEON_WRITE((0x2c14 + j), 0x00000000); 1297 RADEON_WRITE((0x2c18 + j), 0x00000000); 1298 RADEON_WRITE((0x2c1c + j), 0x00000000); 1299 RADEON_WRITE((0x2c20 + j), 0x00000000); 1300 RADEON_WRITE((0x2c24 + j), 0x00000000); 1301 j += 0x18; 1302 } 1303 1304 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 1305 1306 /* setup tiling, simd, pipe config */ 1307 mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG); 1308 1309 switch (dev_priv->r600_max_tile_pipes) { 1310 case 1: 1311 gb_tiling_config |= R600_PIPE_TILING(0); 1312 break; 1313 case 2: 1314 gb_tiling_config |= R600_PIPE_TILING(1); 1315 break; 1316 case 4: 1317 gb_tiling_config |= R600_PIPE_TILING(2); 1318 break; 1319 case 8: 1320 gb_tiling_config |= R600_PIPE_TILING(3); 1321 break; 1322 default: 1323 break; 1324 } 1325 1326 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) 1327 gb_tiling_config |= R600_BANK_TILING(1); 1328 else 1329 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK); 1330 1331 gb_tiling_config |= R600_GROUP_SIZE(0); 1332 1333 if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) { 1334 gb_tiling_config |= R600_ROW_TILING(3); 1335 gb_tiling_config |= R600_SAMPLE_SPLIT(3); 1336 } else { 1337 gb_tiling_config |= 1338 R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1339 gb_tiling_config |= 1340 R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1341 } 1342 1343 gb_tiling_config |= R600_BANK_SWAPS(1); 1344 1345 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, 1346 dev_priv->r600_max_backends, 1347 (0xff << dev_priv->r600_max_backends) & 0xff); 1348 gb_tiling_config |= R600_BACKEND_MAP(backend_map); 1349 1350 cc_gc_shader_pipe_config = 1351 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); 1352 cc_gc_shader_pipe_config |= 1353 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); 1354 1355 cc_rb_backend_disable = 1356 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK); 1357 1358 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 1359 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1360 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1361 1362 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1363 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1364 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1365 1366 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1367 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); 1368 RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); 1369 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0); 1370 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0); 1371 1372 num_qd_pipes = 1373 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK); 1374 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 1375 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 1376 1377 /* set HW defaults for 3D engine */ 1378 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 1379 R600_ROQ_IB2_START(0x2b))); 1380 1381 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30)); 1382 1383 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | 1384 R600_SYNC_GRADIENT | 1385 R600_SYNC_WALKER | 1386 R600_SYNC_ALIGNER)); 1387 1388 sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1); 1389 sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS; 1390 RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1); 1391 1392 smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0); 1393 smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff); 1394 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); 1395 RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0); 1396 1397 RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) | 1398 R700_GS_FLUSH_CTL(4) | 1399 R700_ACK_FLUSH_CTL(3) | 1400 R700_SYNC_FLUSH_CTL)); 1401 1402 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) 1403 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f)); 1404 else { 1405 db_debug4 = RADEON_READ(RV700_DB_DEBUG4); 1406 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER; 1407 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4); 1408 } 1409 1410 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) | 1411 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) | 1412 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1))); 1413 1414 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | 1415 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) | 1416 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize))); 1417 1418 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1419 1420 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1); 1421 1422 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 1423 1424 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4)); 1425 1426 RADEON_WRITE(R600_CP_PERFMON_CNTL, 0); 1427 1428 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) | 1429 R600_DONE_FIFO_HIWATER(0xe0) | 1430 R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 1431 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1432 case CHIP_RV770: 1433 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1); 1434 break; 1435 case CHIP_RV730: 1436 case CHIP_RV710: 1437 default: 1438 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4); 1439 break; 1440 } 1441 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 1442 1443 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1444 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1445 */ 1446 sq_config = RADEON_READ(R600_SQ_CONFIG); 1447 sq_config &= ~(R600_PS_PRIO(3) | 1448 R600_VS_PRIO(3) | 1449 R600_GS_PRIO(3) | 1450 R600_ES_PRIO(3)); 1451 sq_config |= (R600_DX9_CONSTS | 1452 R600_VC_ENABLE | 1453 R600_EXPORT_SRC_C | 1454 R600_PS_PRIO(0) | 1455 R600_VS_PRIO(1) | 1456 R600_GS_PRIO(2) | 1457 R600_ES_PRIO(3)); 1458 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1459 /* no vertex cache */ 1460 sq_config &= ~R600_VC_ENABLE; 1461 1462 RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1463 1464 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1465 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1466 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2))); 1467 1468 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | 1469 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64))); 1470 1471 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) | 1472 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) | 1473 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8)); 1474 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads) 1475 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads); 1476 else 1477 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8); 1478 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1479 1480 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1481 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1482 1483 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1484 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1485 1486 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) | 1487 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) | 1488 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) | 1489 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64)); 1490 1491 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 1492 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 1493 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 1494 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 1495 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 1496 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 1497 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 1498 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 1499 1500 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) | 1501 R700_FORCE_EOV_MAX_REZ_CNT(255))); 1502 1503 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1504 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) | 1505 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1506 else 1507 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) | 1508 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1509 1510 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1511 case CHIP_RV770: 1512 case CHIP_RV730: 1513 gs_prim_buffer_depth = 384; 1514 break; 1515 case CHIP_RV710: 1516 gs_prim_buffer_depth = 128; 1517 break; 1518 default: 1519 break; 1520 } 1521 1522 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1523 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1524 /* Max value for this is 256 */ 1525 if (vgt_gs_per_es > 256) 1526 vgt_gs_per_es = 256; 1527 1528 RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1529 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1530 RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1531 1532 /* more default values. 2D/3D driver should adjust as needed */ 1533 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1534 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1535 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1536 RADEON_WRITE(R600_SX_MISC, 0); 1537 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1538 RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa); 1539 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1540 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff); 1541 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1542 RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1543 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1544 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1545 1546 /* clear render buffer base addresses */ 1547 RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1548 RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1549 RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1550 RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1551 RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1552 RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1553 RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1554 RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1555 1556 RADEON_WRITE(R700_TCP_CNTL, 0); 1557 1558 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1559 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1560 1561 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1562 1563 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1564 R600_NUM_CLIP_SEQ(3))); 1565 1566} 1567 1568static void r600_cp_init_ring_buffer(struct drm_device *dev, 1569 drm_radeon_private_t *dev_priv, 1570 struct drm_file *file_priv) 1571{ 1572 u32 ring_start; 1573 u64 rptr_addr; 1574 1575 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 1576 r700_gfx_init(dev, dev_priv); 1577 else 1578 r600_gfx_init(dev, dev_priv); 1579 1580 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 1581 RADEON_READ(R600_GRBM_SOFT_RESET); 1582 DRM_UDELAY(15000); 1583 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 1584 1585 1586 /* Set ring buffer size */ 1587#ifdef __BIG_ENDIAN 1588 RADEON_WRITE(R600_CP_RB_CNTL, 1589 RADEON_BUF_SWAP_32BIT | 1590 RADEON_RB_NO_UPDATE | 1591 (dev_priv->ring.rptr_update_l2qw << 8) | 1592 dev_priv->ring.size_l2qw); 1593#else 1594 RADEON_WRITE(R600_CP_RB_CNTL, 1595 RADEON_RB_NO_UPDATE | 1596 (dev_priv->ring.rptr_update_l2qw << 8) | 1597 dev_priv->ring.size_l2qw); 1598#endif 1599 1600 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4); 1601 1602 /* Set the write pointer delay */ 1603 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 1604 1605#ifdef __BIG_ENDIAN 1606 RADEON_WRITE(R600_CP_RB_CNTL, 1607 RADEON_BUF_SWAP_32BIT | 1608 RADEON_RB_NO_UPDATE | 1609 RADEON_RB_RPTR_WR_ENA | 1610 (dev_priv->ring.rptr_update_l2qw << 8) | 1611 dev_priv->ring.size_l2qw); 1612#else 1613 RADEON_WRITE(R600_CP_RB_CNTL, 1614 RADEON_RB_NO_UPDATE | 1615 RADEON_RB_RPTR_WR_ENA | 1616 (dev_priv->ring.rptr_update_l2qw << 8) | 1617 dev_priv->ring.size_l2qw); 1618#endif 1619 1620 /* Initialize the ring buffer's read and write pointers */ 1621 RADEON_WRITE(R600_CP_RB_RPTR_WR, 0); 1622 RADEON_WRITE(R600_CP_RB_WPTR, 0); 1623 SET_RING_HEAD(dev_priv, 0); 1624 dev_priv->ring.tail = 0; 1625 1626#if __OS_HAS_AGP 1627 if (dev_priv->flags & RADEON_IS_AGP) { 1628 rptr_addr = dev_priv->ring_rptr->offset 1629 - dev->agp->base + 1630 dev_priv->gart_vm_start; 1631 } else 1632#endif 1633 { 1634 rptr_addr = dev_priv->ring_rptr->offset 1635 - ((unsigned long) dev->sg->virtual) 1636 + dev_priv->gart_vm_start; 1637 } 1638 RADEON_WRITE(R600_CP_RB_RPTR_ADDR, 1639 rptr_addr & 0xffffffff); 1640 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, 1641 upper_32_bits(rptr_addr)); 1642 1643#ifdef __BIG_ENDIAN 1644 RADEON_WRITE(R600_CP_RB_CNTL, 1645 RADEON_BUF_SWAP_32BIT | 1646 (dev_priv->ring.rptr_update_l2qw << 8) | 1647 dev_priv->ring.size_l2qw); 1648#else 1649 RADEON_WRITE(R600_CP_RB_CNTL, 1650 (dev_priv->ring.rptr_update_l2qw << 8) | 1651 dev_priv->ring.size_l2qw); 1652#endif 1653 1654#if __OS_HAS_AGP 1655 if (dev_priv->flags & RADEON_IS_AGP) { 1656 /* XXX */ 1657 radeon_write_agp_base(dev_priv, dev->agp->base); 1658 1659 /* XXX */ 1660 radeon_write_agp_location(dev_priv, 1661 (((dev_priv->gart_vm_start - 1 + 1662 dev_priv->gart_size) & 0xffff0000) | 1663 (dev_priv->gart_vm_start >> 16))); 1664 1665 ring_start = (dev_priv->cp_ring->offset 1666 - dev->agp->base 1667 + dev_priv->gart_vm_start); 1668 } else 1669#endif 1670 ring_start = (dev_priv->cp_ring->offset 1671 - (unsigned long)dev->sg->virtual 1672 + dev_priv->gart_vm_start); 1673 1674 RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8); 1675 1676 RADEON_WRITE(R600_CP_ME_CNTL, 0xff); 1677 1678 RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28)); 1679 1680 /* Initialize the scratch register pointer. This will cause 1681 * the scratch register values to be written out to memory 1682 * whenever they are updated. 1683 * 1684 * We simply put this behind the ring read pointer, this works 1685 * with PCI GART as well as (whatever kind of) AGP GART 1686 */ 1687 { 1688 u64 scratch_addr; 1689 1690 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR); 1691 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32; 1692 scratch_addr += R600_SCRATCH_REG_OFFSET; 1693 scratch_addr >>= 8; 1694 scratch_addr &= 0xffffffff; 1695 1696 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr); 1697 } 1698 1699 RADEON_WRITE(R600_SCRATCH_UMSK, 0x7); 1700 1701 /* Turn on bus mastering */ 1702 radeon_enable_bm(dev_priv); 1703 1704 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0); 1705 RADEON_WRITE(R600_LAST_FRAME_REG, 0); 1706 1707 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 1708 RADEON_WRITE(R600_LAST_DISPATCH_REG, 0); 1709 1710 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0); 1711 RADEON_WRITE(R600_LAST_CLEAR_REG, 0); 1712 1713 /* reset sarea copies of these */ 1714 if (dev_priv->sarea_priv) { 1715 dev_priv->sarea_priv->last_frame = 0; 1716 dev_priv->sarea_priv->last_dispatch = 0; 1717 dev_priv->sarea_priv->last_clear = 0; 1718 } 1719 1720 r600_do_wait_for_idle(dev_priv); 1721 1722} 1723 1724int r600_do_cleanup_cp(struct drm_device *dev) 1725{ 1726 drm_radeon_private_t *dev_priv = dev->dev_private; 1727 DRM_DEBUG("\n"); 1728 1729 /* Make sure interrupts are disabled here because the uninstall ioctl 1730 * may not have been called from userspace and after dev_private 1731 * is freed, it's too late. 1732 */ 1733 if (dev->irq_enabled) 1734 drm_irq_uninstall(dev); 1735 1736#if __OS_HAS_AGP 1737 if (dev_priv->flags & RADEON_IS_AGP) { 1738 if (dev_priv->cp_ring != NULL) { 1739 drm_core_ioremapfree(dev_priv->cp_ring, dev); 1740 dev_priv->cp_ring = NULL; 1741 } 1742 if (dev_priv->ring_rptr != NULL) { 1743 drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1744 dev_priv->ring_rptr = NULL; 1745 } 1746 if (dev->agp_buffer_map != NULL) { 1747 drm_core_ioremapfree(dev->agp_buffer_map, dev); 1748 dev->agp_buffer_map = NULL; 1749 } 1750 } else 1751#endif 1752 { 1753 1754 if (dev_priv->gart_info.bus_addr) 1755 r600_page_table_cleanup(dev, &dev_priv->gart_info); 1756 1757 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { 1758 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 1759 dev_priv->gart_info.addr = 0; 1760 } 1761 } 1762 /* only clear to the start of flags */ 1763 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1764 1765 return 0; 1766} 1767 1768int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 1769 struct drm_file *file_priv) 1770{ 1771 drm_radeon_private_t *dev_priv = dev->dev_private; 1772 1773 DRM_DEBUG("\n"); 1774 1775 /* if we require new memory map but we don't have it fail */ 1776 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 1777 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 1778 r600_do_cleanup_cp(dev); 1779 return -EINVAL; 1780 } 1781 1782 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { 1783 DRM_DEBUG("Forcing AGP card to PCI mode\n"); 1784 dev_priv->flags &= ~RADEON_IS_AGP; 1785 /* The writeback test succeeds, but when writeback is enabled, 1786 * the ring buffer read ptr update fails after first 128 bytes. 1787 */ 1788 radeon_no_wb = 1; 1789 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) 1790 && !init->is_pci) { 1791 DRM_DEBUG("Restoring AGP flag\n"); 1792 dev_priv->flags |= RADEON_IS_AGP; 1793 } 1794 1795 dev_priv->usec_timeout = init->usec_timeout; 1796 if (dev_priv->usec_timeout < 1 || 1797 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 1798 DRM_DEBUG("TIMEOUT problem!\n"); 1799 r600_do_cleanup_cp(dev); 1800 return -EINVAL; 1801 } 1802 1803 /* Enable vblank on CRTC1 for older X servers 1804 */ 1805 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 1806 1807 dev_priv->cp_mode = init->cp_mode; 1808 1809 /* We don't support anything other than bus-mastering ring mode, 1810 * but the ring can be in either AGP or PCI space for the ring 1811 * read pointer. 1812 */ 1813 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 1814 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 1815 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 1816 r600_do_cleanup_cp(dev); 1817 return -EINVAL; 1818 } 1819 1820 switch (init->fb_bpp) { 1821 case 16: 1822 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 1823 break; 1824 case 32: 1825 default: 1826 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 1827 break; 1828 } 1829 dev_priv->front_offset = init->front_offset; 1830 dev_priv->front_pitch = init->front_pitch; 1831 dev_priv->back_offset = init->back_offset; 1832 dev_priv->back_pitch = init->back_pitch; 1833 1834 dev_priv->ring_offset = init->ring_offset; 1835 dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1836 dev_priv->buffers_offset = init->buffers_offset; 1837 dev_priv->gart_textures_offset = init->gart_textures_offset; 1838 1839 dev_priv->sarea = drm_getsarea(dev); 1840 if (!dev_priv->sarea) { 1841 DRM_ERROR("could not find sarea!\n"); 1842 r600_do_cleanup_cp(dev); 1843 return -EINVAL; 1844 } 1845 1846 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 1847 if (!dev_priv->cp_ring) { 1848 DRM_ERROR("could not find cp ring region!\n"); 1849 r600_do_cleanup_cp(dev); 1850 return -EINVAL; 1851 } 1852 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1853 if (!dev_priv->ring_rptr) { 1854 DRM_ERROR("could not find ring read pointer!\n"); 1855 r600_do_cleanup_cp(dev); 1856 return -EINVAL; 1857 } 1858 dev->agp_buffer_token = init->buffers_offset; 1859 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1860 if (!dev->agp_buffer_map) { 1861 DRM_ERROR("could not find dma buffer region!\n"); 1862 r600_do_cleanup_cp(dev); 1863 return -EINVAL; 1864 } 1865 1866 if (init->gart_textures_offset) { 1867 dev_priv->gart_textures = 1868 drm_core_findmap(dev, init->gart_textures_offset); 1869 if (!dev_priv->gart_textures) { 1870 DRM_ERROR("could not find GART texture region!\n"); 1871 r600_do_cleanup_cp(dev); 1872 return -EINVAL; 1873 } 1874 } 1875 1876 dev_priv->sarea_priv = 1877 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + 1878 init->sarea_priv_offset); 1879 1880#if __OS_HAS_AGP 1881 /* XXX */ 1882 if (dev_priv->flags & RADEON_IS_AGP) { 1883 drm_core_ioremap_wc(dev_priv->cp_ring, dev); 1884 drm_core_ioremap_wc(dev_priv->ring_rptr, dev); 1885 drm_core_ioremap_wc(dev->agp_buffer_map, dev); 1886 if (!dev_priv->cp_ring->handle || 1887 !dev_priv->ring_rptr->handle || 1888 !dev->agp_buffer_map->handle) { 1889 DRM_ERROR("could not find ioremap agp regions!\n"); 1890 r600_do_cleanup_cp(dev); 1891 return -EINVAL; 1892 } 1893 } else 1894#endif 1895 { 1896 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; 1897 dev_priv->ring_rptr->handle = 1898 (void *)dev_priv->ring_rptr->offset; 1899 dev->agp_buffer_map->handle = 1900 (void *)dev->agp_buffer_map->offset; 1901 1902 DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 1903 dev_priv->cp_ring->handle); 1904 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 1905 dev_priv->ring_rptr->handle); 1906 DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 1907 dev->agp_buffer_map->handle); 1908 } 1909 1910 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24; 1911 dev_priv->fb_size = 1912 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000) 1913 - dev_priv->fb_location; 1914 1915 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 1916 ((dev_priv->front_offset 1917 + dev_priv->fb_location) >> 10)); 1918 1919 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 1920 ((dev_priv->back_offset 1921 + dev_priv->fb_location) >> 10)); 1922 1923 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 1924 ((dev_priv->depth_offset 1925 + dev_priv->fb_location) >> 10)); 1926 1927 dev_priv->gart_size = init->gart_size; 1928 1929 /* New let's set the memory map ... */ 1930 if (dev_priv->new_memmap) { 1931 u32 base = 0; 1932 1933 DRM_INFO("Setting GART location based on new memory map\n"); 1934 1935 /* If using AGP, try to locate the AGP aperture at the same 1936 * location in the card and on the bus, though we have to 1937 * align it down. 1938 */ 1939#if __OS_HAS_AGP 1940 /* XXX */ 1941 if (dev_priv->flags & RADEON_IS_AGP) { 1942 base = dev->agp->base; 1943 /* Check if valid */ 1944 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && 1945 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { 1946 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 1947 dev->agp->base); 1948 base = 0; 1949 } 1950 } 1951#endif 1952 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 1953 if (base == 0) { 1954 base = dev_priv->fb_location + dev_priv->fb_size; 1955 if (base < dev_priv->fb_location || 1956 ((base + dev_priv->gart_size) & 0xfffffffful) < base) 1957 base = dev_priv->fb_location 1958 - dev_priv->gart_size; 1959 } 1960 dev_priv->gart_vm_start = base & 0xffc00000u; 1961 if (dev_priv->gart_vm_start != base) 1962 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 1963 base, dev_priv->gart_vm_start); 1964 } 1965 1966#if __OS_HAS_AGP 1967 /* XXX */ 1968 if (dev_priv->flags & RADEON_IS_AGP) 1969 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1970 - dev->agp->base 1971 + dev_priv->gart_vm_start); 1972 else 1973#endif 1974 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1975 - (unsigned long)dev->sg->virtual 1976 + dev_priv->gart_vm_start); 1977 1978 DRM_DEBUG("fb 0x%08x size %d\n", 1979 (unsigned int) dev_priv->fb_location, 1980 (unsigned int) dev_priv->fb_size); 1981 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 1982 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n", 1983 (unsigned int) dev_priv->gart_vm_start); 1984 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n", 1985 dev_priv->gart_buffers_offset); 1986 1987 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 1988 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 1989 + init->ring_size / sizeof(u32)); 1990 dev_priv->ring.size = init->ring_size; 1991 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 1992 1993 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; 1994 dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8); 1995 1996 dev_priv->ring.fetch_size = /* init->fetch_size */ 32; 1997 dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16); 1998 1999 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 2000 2001 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 2002 2003#if __OS_HAS_AGP 2004 if (dev_priv->flags & RADEON_IS_AGP) { 2005 /* XXX turn off pcie gart */ 2006 } else 2007#endif 2008 { 2009 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); 2010 /* if we have an offset set from userspace */ 2011 if (!dev_priv->pcigart_offset_set) { 2012 DRM_ERROR("Need gart offset from userspace\n"); 2013 r600_do_cleanup_cp(dev); 2014 return -EINVAL; 2015 } 2016 2017 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset); 2018 2019 dev_priv->gart_info.bus_addr = 2020 dev_priv->pcigart_offset + dev_priv->fb_location; 2021 dev_priv->gart_info.mapping.offset = 2022 dev_priv->pcigart_offset + dev_priv->fb_aper_offset; 2023 dev_priv->gart_info.mapping.size = 2024 dev_priv->gart_info.table_size; 2025 2026 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); 2027 if (!dev_priv->gart_info.mapping.handle) { 2028 DRM_ERROR("ioremap failed.\n"); 2029 r600_do_cleanup_cp(dev); 2030 return -EINVAL; 2031 } 2032 2033 dev_priv->gart_info.addr = 2034 dev_priv->gart_info.mapping.handle; 2035 2036 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 2037 dev_priv->gart_info.addr, 2038 dev_priv->pcigart_offset); 2039 2040 if (!r600_page_table_init(dev)) { 2041 DRM_ERROR("Failed to init GART table\n"); 2042 r600_do_cleanup_cp(dev); 2043 return -EINVAL; 2044 } 2045 2046 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2047 r700_vm_init(dev); 2048 else 2049 r600_vm_init(dev); 2050 } 2051 2052 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2053 r700_cp_load_microcode(dev_priv); 2054 else 2055 r600_cp_load_microcode(dev_priv); 2056 2057 r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2058 2059 dev_priv->last_buf = 0; 2060 2061 r600_do_engine_reset(dev); 2062 r600_test_writeback(dev_priv); 2063 2064 return 0; 2065} 2066 2067int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) 2068{ 2069 drm_radeon_private_t *dev_priv = dev->dev_private; 2070 2071 DRM_DEBUG("\n"); 2072 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) { 2073 r700_vm_init(dev); 2074 r700_cp_load_microcode(dev_priv); 2075 } else { 2076 r600_vm_init(dev); 2077 r600_cp_load_microcode(dev_priv); 2078 } 2079 r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2080 r600_do_engine_reset(dev); 2081 2082 return 0; 2083} 2084 2085/* Wait for the CP to go idle. 2086 */ 2087int r600_do_cp_idle(drm_radeon_private_t *dev_priv) 2088{ 2089 RING_LOCALS; 2090 DRM_DEBUG("\n"); 2091 2092 BEGIN_RING(5); 2093 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 2094 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); 2095 /* wait for 3D idle clean */ 2096 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); 2097 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); 2098 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); 2099 2100 ADVANCE_RING(); 2101 COMMIT_RING(); 2102 2103 return r600_do_wait_for_idle(dev_priv); 2104} 2105 2106/* Start the Command Processor. 2107 */ 2108void r600_do_cp_start(drm_radeon_private_t *dev_priv) 2109{ 2110 u32 cp_me; 2111 RING_LOCALS; 2112 DRM_DEBUG("\n"); 2113 2114 BEGIN_RING(7); 2115 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); 2116 OUT_RING(0x00000001); 2117 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) 2118 OUT_RING(0x00000003); 2119 else 2120 OUT_RING(0x00000000); 2121 OUT_RING((dev_priv->r600_max_hw_contexts - 1)); 2122 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1)); 2123 OUT_RING(0x00000000); 2124 OUT_RING(0x00000000); 2125 ADVANCE_RING(); 2126 COMMIT_RING(); 2127 2128 /* set the mux and reset the halt bit */ 2129 cp_me = 0xff; 2130 RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2131 2132 dev_priv->cp_running = 1; 2133 2134} 2135 2136void r600_do_cp_reset(drm_radeon_private_t *dev_priv) 2137{ 2138 u32 cur_read_ptr; 2139 DRM_DEBUG("\n"); 2140 2141 cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR); 2142 RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr); 2143 SET_RING_HEAD(dev_priv, cur_read_ptr); 2144 dev_priv->ring.tail = cur_read_ptr; 2145} 2146 2147void r600_do_cp_stop(drm_radeon_private_t *dev_priv) 2148{ 2149 uint32_t cp_me; 2150 2151 DRM_DEBUG("\n"); 2152 2153 cp_me = 0xff | R600_CP_ME_HALT; 2154 2155 RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2156 2157 dev_priv->cp_running = 0; 2158} 2159 2160int r600_cp_dispatch_indirect(struct drm_device *dev, 2161 struct drm_buf *buf, int start, int end) 2162{ 2163 drm_radeon_private_t *dev_priv = dev->dev_private; 2164 RING_LOCALS; 2165 2166 if (start != end) { 2167 unsigned long offset = (dev_priv->gart_buffers_offset 2168 + buf->offset + start); 2169 int dwords = (end - start + 3) / sizeof(u32); 2170 2171 DRM_DEBUG("dwords:%d\n", dwords); 2172 DRM_DEBUG("offset 0x%lx\n", offset); 2173 2174 2175 /* Indirect buffer data must be a multiple of 16 dwords. 2176 * pad the data with a Type-2 CP packet. 2177 */ 2178 while (dwords & 0xf) { 2179 u32 *data = (u32 *) 2180 ((char *)dev->agp_buffer_map->handle 2181 + buf->offset + start); 2182 data[dwords++] = RADEON_CP_PACKET2; 2183 } 2184 2185 /* Fire off the indirect buffer */ 2186 BEGIN_RING(4); 2187 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2)); 2188 OUT_RING((offset & 0xfffffffc)); 2189 OUT_RING((upper_32_bits(offset) & 0xff)); 2190 OUT_RING(dwords); 2191 ADVANCE_RING(); 2192 } 2193 2194 return 0; 2195} 2196