r128_cce.c revision 119098
1/* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*- 2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com 3 * 4 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Gareth Hughes <gareth@valinux.com> 29 * 30 * $FreeBSD: head/sys/dev/drm/r128_cce.c 119098 2003-08-19 02:57:31Z anholt $ 31 */ 32 33#include "dev/drm/r128.h" 34#include "dev/drm/drmP.h" 35#include "dev/drm/drm.h" 36#include "dev/drm/r128_drm.h" 37#include "dev/drm/r128_drv.h" 38 39#define R128_FIFO_DEBUG 0 40 41/* CCE microcode (from ATI) */ 42static u32 r128_cce_microcode[] = { 43 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, 44 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0, 45 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1, 46 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11, 47 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28, 48 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9, 49 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656, 50 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1, 51 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071, 52 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2, 53 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1, 54 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1, 55 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1, 56 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2, 57 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1, 58 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82, 59 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729, 60 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008, 61 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0, 62 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1, 63 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1, 64 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0, 65 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370, 66 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1, 67 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793, 68 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1, 69 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1, 70 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1, 71 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1, 72 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894, 73 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14, 74 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1, 75 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1, 76 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1, 77 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 78 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 82 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 83 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 84}; 85 86int R128_READ_PLL(drm_device_t *dev, int addr) 87{ 88 drm_r128_private_t *dev_priv = dev->dev_private; 89 90 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f); 91 return R128_READ(R128_CLOCK_CNTL_DATA); 92} 93 94#if R128_FIFO_DEBUG 95static void r128_status( drm_r128_private_t *dev_priv ) 96{ 97 printk( "GUI_STAT = 0x%08x\n", 98 (unsigned int)R128_READ( R128_GUI_STAT ) ); 99 printk( "PM4_STAT = 0x%08x\n", 100 (unsigned int)R128_READ( R128_PM4_STAT ) ); 101 printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n", 102 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) ); 103 printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n", 104 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) ); 105 printk( "PM4_MICRO_CNTL = 0x%08x\n", 106 (unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) ); 107 printk( "PM4_BUFFER_CNTL = 0x%08x\n", 108 (unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) ); 109} 110#endif 111 112 113/* ================================================================ 114 * Engine, FIFO control 115 */ 116 117static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv ) 118{ 119 u32 tmp; 120 int i; 121 122 tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL; 123 R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp ); 124 125 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 126 if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) { 127 return 0; 128 } 129 DRM_UDELAY( 1 ); 130 } 131 132#if R128_FIFO_DEBUG 133 DRM_ERROR( "failed!\n" ); 134#endif 135 return DRM_ERR(EBUSY); 136} 137 138static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries ) 139{ 140 int i; 141 142 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 143 int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK; 144 if ( slots >= entries ) return 0; 145 DRM_UDELAY( 1 ); 146 } 147 148#if R128_FIFO_DEBUG 149 DRM_ERROR( "failed!\n" ); 150#endif 151 return DRM_ERR(EBUSY); 152} 153 154static int r128_do_wait_for_idle( drm_r128_private_t *dev_priv ) 155{ 156 int i, ret; 157 158 ret = r128_do_wait_for_fifo( dev_priv, 64 ); 159 if ( ret ) return ret; 160 161 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 162 if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) { 163 r128_do_pixcache_flush( dev_priv ); 164 return 0; 165 } 166 DRM_UDELAY( 1 ); 167 } 168 169#if R128_FIFO_DEBUG 170 DRM_ERROR( "failed!\n" ); 171#endif 172 return DRM_ERR(EBUSY); 173} 174 175 176/* ================================================================ 177 * CCE control, initialization 178 */ 179 180/* Load the microcode for the CCE */ 181static void r128_cce_load_microcode( drm_r128_private_t *dev_priv ) 182{ 183 int i; 184 185 DRM_DEBUG( "\n" ); 186 187 r128_do_wait_for_idle( dev_priv ); 188 189 R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 ); 190 for ( i = 0 ; i < 256 ; i++ ) { 191 R128_WRITE( R128_PM4_MICROCODE_DATAH, 192 r128_cce_microcode[i * 2] ); 193 R128_WRITE( R128_PM4_MICROCODE_DATAL, 194 r128_cce_microcode[i * 2 + 1] ); 195 } 196} 197 198/* Flush any pending commands to the CCE. This should only be used just 199 * prior to a wait for idle, as it informs the engine that the command 200 * stream is ending. 201 */ 202static void r128_do_cce_flush( drm_r128_private_t *dev_priv ) 203{ 204 u32 tmp; 205 206 tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE; 207 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp ); 208} 209 210/* Wait for the CCE to go idle. 211 */ 212int r128_do_cce_idle( drm_r128_private_t *dev_priv ) 213{ 214 int i; 215 216 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 217 if ( GET_RING_HEAD( &dev_priv->ring ) == dev_priv->ring.tail ) { 218 int pm4stat = R128_READ( R128_PM4_STAT ); 219 if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >= 220 dev_priv->cce_fifo_size ) && 221 !(pm4stat & (R128_PM4_BUSY | 222 R128_PM4_GUI_ACTIVE)) ) { 223 return r128_do_pixcache_flush( dev_priv ); 224 } 225 } 226 DRM_UDELAY( 1 ); 227 } 228 229#if R128_FIFO_DEBUG 230 DRM_ERROR( "failed!\n" ); 231 r128_status( dev_priv ); 232#endif 233 return DRM_ERR(EBUSY); 234} 235 236/* Start the Concurrent Command Engine. 237 */ 238static void r128_do_cce_start( drm_r128_private_t *dev_priv ) 239{ 240 r128_do_wait_for_idle( dev_priv ); 241 242 R128_WRITE( R128_PM4_BUFFER_CNTL, 243 dev_priv->cce_mode | dev_priv->ring.size_l2qw ); 244 R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */ 245 R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN ); 246 247 dev_priv->cce_running = 1; 248} 249 250/* Reset the Concurrent Command Engine. This will not flush any pending 251 * commands, so you must wait for the CCE command stream to complete 252 * before calling this routine. 253 */ 254static void r128_do_cce_reset( drm_r128_private_t *dev_priv ) 255{ 256 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); 257 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); 258 SET_RING_HEAD( &dev_priv->ring, 0 ); 259 dev_priv->ring.tail = 0; 260} 261 262/* Stop the Concurrent Command Engine. This will not flush any pending 263 * commands, so you must flush the command stream and wait for the CCE 264 * to go idle before calling this routine. 265 */ 266static void r128_do_cce_stop( drm_r128_private_t *dev_priv ) 267{ 268 R128_WRITE( R128_PM4_MICRO_CNTL, 0 ); 269 R128_WRITE( R128_PM4_BUFFER_CNTL, R128_PM4_NONPM4 ); 270 271 dev_priv->cce_running = 0; 272} 273 274/* Reset the engine. This will stop the CCE if it is running. 275 */ 276static int r128_do_engine_reset( drm_device_t *dev ) 277{ 278 drm_r128_private_t *dev_priv = dev->dev_private; 279 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl; 280 281 r128_do_pixcache_flush( dev_priv ); 282 283 clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX ); 284 mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL ); 285 286 R128_WRITE_PLL( R128_MCLK_CNTL, 287 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP ); 288 289 gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL ); 290 291 /* Taken from the sample code - do not change */ 292 R128_WRITE( R128_GEN_RESET_CNTL, 293 gen_reset_cntl | R128_SOFT_RESET_GUI ); 294 R128_READ( R128_GEN_RESET_CNTL ); 295 R128_WRITE( R128_GEN_RESET_CNTL, 296 gen_reset_cntl & ~R128_SOFT_RESET_GUI ); 297 R128_READ( R128_GEN_RESET_CNTL ); 298 299 R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl ); 300 R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index ); 301 R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl ); 302 303 /* Reset the CCE ring */ 304 r128_do_cce_reset( dev_priv ); 305 306 /* The CCE is no longer running after an engine reset */ 307 dev_priv->cce_running = 0; 308 309 /* Reset any pending vertex, indirect buffers */ 310 r128_freelist_reset( dev ); 311 312 return 0; 313} 314 315static void r128_cce_init_ring_buffer( drm_device_t *dev, 316 drm_r128_private_t *dev_priv ) 317{ 318 u32 ring_start; 319 u32 tmp; 320 321 DRM_DEBUG( "\n" ); 322 323 /* The manual (p. 2) says this address is in "VM space". This 324 * means it's an offset from the start of AGP space. 325 */ 326#if __REALLY_HAVE_AGP 327 if ( !dev_priv->is_pci ) 328 ring_start = dev_priv->cce_ring->offset - dev->agp->base; 329 else 330#endif 331 ring_start = dev_priv->cce_ring->offset - dev->sg->handle; 332 333 R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET ); 334 335 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); 336 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); 337 338 /* DL_RPTR_ADDR is a physical address in AGP space. */ 339 SET_RING_HEAD( &dev_priv->ring, 0 ); 340 341 if ( !dev_priv->is_pci ) { 342 R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR, 343 dev_priv->ring_rptr->offset ); 344 } else { 345 drm_sg_mem_t *entry = dev->sg; 346 unsigned long tmp_ofs, page_ofs; 347 348 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; 349 page_ofs = tmp_ofs >> PAGE_SHIFT; 350 351 R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR, 352 entry->busaddr[page_ofs]); 353 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n", 354 (unsigned long) entry->busaddr[page_ofs], 355 entry->handle + tmp_ofs ); 356 } 357 358 /* Set watermark control */ 359 R128_WRITE( R128_PM4_BUFFER_WM_CNTL, 360 ((R128_WATERMARK_L/4) << R128_WMA_SHIFT) 361 | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT) 362 | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT) 363 | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) ); 364 365 /* Force read. Why? Because it's in the examples... */ 366 R128_READ( R128_PM4_BUFFER_ADDR ); 367 368 /* Turn on bus mastering */ 369 tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS; 370 R128_WRITE( R128_BUS_CNTL, tmp ); 371} 372 373static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) 374{ 375 drm_r128_private_t *dev_priv; 376 377 DRM_DEBUG( "\n" ); 378 379 dev_priv = DRM(alloc)( sizeof(drm_r128_private_t), DRM_MEM_DRIVER ); 380 if ( dev_priv == NULL ) 381 return DRM_ERR(ENOMEM); 382 383 memset( dev_priv, 0, sizeof(drm_r128_private_t) ); 384 385 dev_priv->is_pci = init->is_pci; 386 387 if ( dev_priv->is_pci && !dev->sg ) { 388 DRM_ERROR( "PCI GART memory not allocated!\n" ); 389 dev->dev_private = (void *)dev_priv; 390 r128_do_cleanup_cce( dev ); 391 return DRM_ERR(EINVAL); 392 } 393 394 dev_priv->usec_timeout = init->usec_timeout; 395 if ( dev_priv->usec_timeout < 1 || 396 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) { 397 DRM_DEBUG( "TIMEOUT problem!\n" ); 398 dev->dev_private = (void *)dev_priv; 399 r128_do_cleanup_cce( dev ); 400 return DRM_ERR(EINVAL); 401 } 402 403 dev_priv->cce_mode = init->cce_mode; 404 405 /* GH: Simple idle check. 406 */ 407 atomic_set( &dev_priv->idle_count, 0 ); 408 409 /* We don't support anything other than bus-mastering ring mode, 410 * but the ring can be in either AGP or PCI space for the ring 411 * read pointer. 412 */ 413 if ( ( init->cce_mode != R128_PM4_192BM ) && 414 ( init->cce_mode != R128_PM4_128BM_64INDBM ) && 415 ( init->cce_mode != R128_PM4_64BM_128INDBM ) && 416 ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) { 417 DRM_DEBUG( "Bad cce_mode!\n" ); 418 dev->dev_private = (void *)dev_priv; 419 r128_do_cleanup_cce( dev ); 420 return DRM_ERR(EINVAL); 421 } 422 423 switch ( init->cce_mode ) { 424 case R128_PM4_NONPM4: 425 dev_priv->cce_fifo_size = 0; 426 break; 427 case R128_PM4_192PIO: 428 case R128_PM4_192BM: 429 dev_priv->cce_fifo_size = 192; 430 break; 431 case R128_PM4_128PIO_64INDBM: 432 case R128_PM4_128BM_64INDBM: 433 dev_priv->cce_fifo_size = 128; 434 break; 435 case R128_PM4_64PIO_128INDBM: 436 case R128_PM4_64BM_128INDBM: 437 case R128_PM4_64PIO_64VCBM_64INDBM: 438 case R128_PM4_64BM_64VCBM_64INDBM: 439 case R128_PM4_64PIO_64VCPIO_64INDPIO: 440 dev_priv->cce_fifo_size = 64; 441 break; 442 } 443 444 switch ( init->fb_bpp ) { 445 case 16: 446 dev_priv->color_fmt = R128_DATATYPE_RGB565; 447 break; 448 case 32: 449 default: 450 dev_priv->color_fmt = R128_DATATYPE_ARGB8888; 451 break; 452 } 453 dev_priv->front_offset = init->front_offset; 454 dev_priv->front_pitch = init->front_pitch; 455 dev_priv->back_offset = init->back_offset; 456 dev_priv->back_pitch = init->back_pitch; 457 458 switch ( init->depth_bpp ) { 459 case 16: 460 dev_priv->depth_fmt = R128_DATATYPE_RGB565; 461 break; 462 case 24: 463 case 32: 464 default: 465 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888; 466 break; 467 } 468 dev_priv->depth_offset = init->depth_offset; 469 dev_priv->depth_pitch = init->depth_pitch; 470 dev_priv->span_offset = init->span_offset; 471 472 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) | 473 (dev_priv->front_offset >> 5)); 474 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) | 475 (dev_priv->back_offset >> 5)); 476 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | 477 (dev_priv->depth_offset >> 5) | 478 R128_DST_TILE); 479 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | 480 (dev_priv->span_offset >> 5)); 481 482 DRM_GETSAREA(); 483 484 if(!dev_priv->sarea) { 485 DRM_ERROR("could not find sarea!\n"); 486 dev->dev_private = (void *)dev_priv; 487 r128_do_cleanup_cce( dev ); 488 return DRM_ERR(EINVAL); 489 } 490 491 DRM_FIND_MAP( dev_priv->fb, init->fb_offset ); 492 if(!dev_priv->fb) { 493 DRM_ERROR("could not find framebuffer!\n"); 494 dev->dev_private = (void *)dev_priv; 495 r128_do_cleanup_cce( dev ); 496 return DRM_ERR(EINVAL); 497 } 498 DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset ); 499 if(!dev_priv->mmio) { 500 DRM_ERROR("could not find mmio region!\n"); 501 dev->dev_private = (void *)dev_priv; 502 r128_do_cleanup_cce( dev ); 503 return DRM_ERR(EINVAL); 504 } 505 DRM_FIND_MAP( dev_priv->cce_ring, init->ring_offset ); 506 if(!dev_priv->cce_ring) { 507 DRM_ERROR("could not find cce ring region!\n"); 508 dev->dev_private = (void *)dev_priv; 509 r128_do_cleanup_cce( dev ); 510 return DRM_ERR(EINVAL); 511 } 512 DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset ); 513 if(!dev_priv->ring_rptr) { 514 DRM_ERROR("could not find ring read pointer!\n"); 515 dev->dev_private = (void *)dev_priv; 516 r128_do_cleanup_cce( dev ); 517 return DRM_ERR(EINVAL); 518 } 519 DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset ); 520 if(!dev_priv->buffers) { 521 DRM_ERROR("could not find dma buffer region!\n"); 522 dev->dev_private = (void *)dev_priv; 523 r128_do_cleanup_cce( dev ); 524 return DRM_ERR(EINVAL); 525 } 526 527 if ( !dev_priv->is_pci ) { 528 DRM_FIND_MAP( dev_priv->agp_textures, 529 init->agp_textures_offset ); 530 if(!dev_priv->agp_textures) { 531 DRM_ERROR("could not find agp texture region!\n"); 532 dev->dev_private = (void *)dev_priv; 533 r128_do_cleanup_cce( dev ); 534 return DRM_ERR(EINVAL); 535 } 536 } 537 538 dev_priv->sarea_priv = 539 (drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle + 540 init->sarea_priv_offset); 541 542#if __REALLY_HAVE_AGP 543 if ( !dev_priv->is_pci ) { 544 DRM_IOREMAP( dev_priv->cce_ring, dev ); 545 DRM_IOREMAP( dev_priv->ring_rptr, dev ); 546 DRM_IOREMAP( dev_priv->buffers, dev ); 547 if(!dev_priv->cce_ring->handle || 548 !dev_priv->ring_rptr->handle || 549 !dev_priv->buffers->handle) { 550 DRM_ERROR("Could not ioremap agp regions!\n"); 551 dev->dev_private = (void *)dev_priv; 552 r128_do_cleanup_cce( dev ); 553 return DRM_ERR(ENOMEM); 554 } 555 } else 556#endif 557 { 558 dev_priv->cce_ring->handle = 559 (void *)dev_priv->cce_ring->offset; 560 dev_priv->ring_rptr->handle = 561 (void *)dev_priv->ring_rptr->offset; 562 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset; 563 } 564 565#if __REALLY_HAVE_AGP 566 if ( !dev_priv->is_pci ) 567 dev_priv->cce_buffers_offset = dev->agp->base; 568 else 569#endif 570 dev_priv->cce_buffers_offset = dev->sg->handle; 571 572 dev_priv->ring.head = ((__volatile__ u32 *) 573 dev_priv->ring_rptr->handle); 574 575 dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle; 576 dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle 577 + init->ring_size / sizeof(u32)); 578 dev_priv->ring.size = init->ring_size; 579 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 ); 580 581 dev_priv->ring.tail_mask = 582 (dev_priv->ring.size / sizeof(u32)) - 1; 583 584 dev_priv->ring.high_mark = 128; 585 dev_priv->ring.ring_rptr = dev_priv->ring_rptr; 586 587 dev_priv->sarea_priv->last_frame = 0; 588 R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame ); 589 590 dev_priv->sarea_priv->last_dispatch = 0; 591 R128_WRITE( R128_LAST_DISPATCH_REG, 592 dev_priv->sarea_priv->last_dispatch ); 593 594#if __REALLY_HAVE_SG 595 if ( dev_priv->is_pci ) { 596 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart, 597 &dev_priv->bus_pci_gart) ) { 598 DRM_ERROR( "failed to init PCI GART!\n" ); 599 dev->dev_private = (void *)dev_priv; 600 r128_do_cleanup_cce( dev ); 601 return DRM_ERR(ENOMEM); 602 } 603 R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart ); 604 } 605#endif 606 607 r128_cce_init_ring_buffer( dev, dev_priv ); 608 r128_cce_load_microcode( dev_priv ); 609 610 dev->dev_private = (void *)dev_priv; 611 612 r128_do_engine_reset( dev ); 613 614 return 0; 615} 616 617int r128_do_cleanup_cce( drm_device_t *dev ) 618{ 619 620#if _HAVE_DMA_IRQ 621 /* Make sure interrupts are disabled here because the uninstall ioctl 622 * may not have been called from userspace and after dev_private 623 * is freed, it's too late. 624 */ 625 if ( dev->irq ) DRM(irq_uninstall)(dev); 626#endif 627 628 if ( dev->dev_private ) { 629 drm_r128_private_t *dev_priv = dev->dev_private; 630 631#if __REALLY_HAVE_AGP 632 if ( !dev_priv->is_pci ) { 633 if ( dev_priv->cce_ring != NULL ) 634 DRM_IOREMAPFREE( dev_priv->cce_ring, dev ); 635 if ( dev_priv->ring_rptr != NULL ) 636 DRM_IOREMAPFREE( dev_priv->ring_rptr, dev ); 637 if ( dev_priv->buffers != NULL ) 638 DRM_IOREMAPFREE( dev_priv->buffers, dev ); 639 } else 640#endif 641 { 642 if (!DRM(ati_pcigart_cleanup)( dev, 643 dev_priv->phys_pci_gart, 644 dev_priv->bus_pci_gart )) 645 DRM_ERROR( "failed to cleanup PCI GART!\n" ); 646 } 647 648 DRM(free)( dev->dev_private, sizeof(drm_r128_private_t), 649 DRM_MEM_DRIVER ); 650 dev->dev_private = NULL; 651 } 652 653 return 0; 654} 655 656int r128_cce_init( DRM_IOCTL_ARGS ) 657{ 658 DRM_DEVICE; 659 drm_r128_init_t init; 660 661 DRM_DEBUG( "\n" ); 662 663 LOCK_TEST_WITH_RETURN( dev, filp ); 664 665 DRM_COPY_FROM_USER_IOCTL( init, (drm_r128_init_t *)data, sizeof(init) ); 666 667 switch ( init.func ) { 668 case R128_INIT_CCE: 669 return r128_do_init_cce( dev, &init ); 670 case R128_CLEANUP_CCE: 671 return r128_do_cleanup_cce( dev ); 672 } 673 674 return DRM_ERR(EINVAL); 675} 676 677int r128_cce_start( DRM_IOCTL_ARGS ) 678{ 679 DRM_DEVICE; 680 drm_r128_private_t *dev_priv = dev->dev_private; 681 DRM_DEBUG( "\n" ); 682 683 LOCK_TEST_WITH_RETURN( dev, filp ); 684 685 if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) { 686 DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ ); 687 return 0; 688 } 689 690 r128_do_cce_start( dev_priv ); 691 692 return 0; 693} 694 695/* Stop the CCE. The engine must have been idled before calling this 696 * routine. 697 */ 698int r128_cce_stop( DRM_IOCTL_ARGS ) 699{ 700 DRM_DEVICE; 701 drm_r128_private_t *dev_priv = dev->dev_private; 702 drm_r128_cce_stop_t stop; 703 int ret; 704 DRM_DEBUG( "\n" ); 705 706 LOCK_TEST_WITH_RETURN( dev, filp ); 707 708 DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t *)data, sizeof(stop) ); 709 710 /* Flush any pending CCE commands. This ensures any outstanding 711 * commands are exectuted by the engine before we turn it off. 712 */ 713 if ( stop.flush ) { 714 r128_do_cce_flush( dev_priv ); 715 } 716 717 /* If we fail to make the engine go idle, we return an error 718 * code so that the DRM ioctl wrapper can try again. 719 */ 720 if ( stop.idle ) { 721 ret = r128_do_cce_idle( dev_priv ); 722 if ( ret ) return ret; 723 } 724 725 /* Finally, we can turn off the CCE. If the engine isn't idle, 726 * we will get some dropped triangles as they won't be fully 727 * rendered before the CCE is shut down. 728 */ 729 r128_do_cce_stop( dev_priv ); 730 731 /* Reset the engine */ 732 r128_do_engine_reset( dev ); 733 734 return 0; 735} 736 737/* Just reset the CCE ring. Called as part of an X Server engine reset. 738 */ 739int r128_cce_reset( DRM_IOCTL_ARGS ) 740{ 741 DRM_DEVICE; 742 drm_r128_private_t *dev_priv = dev->dev_private; 743 DRM_DEBUG( "\n" ); 744 745 LOCK_TEST_WITH_RETURN( dev, filp ); 746 747 if ( !dev_priv ) { 748 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); 749 return DRM_ERR(EINVAL); 750 } 751 752 r128_do_cce_reset( dev_priv ); 753 754 /* The CCE is no longer running after an engine reset */ 755 dev_priv->cce_running = 0; 756 757 return 0; 758} 759 760int r128_cce_idle( DRM_IOCTL_ARGS ) 761{ 762 DRM_DEVICE; 763 drm_r128_private_t *dev_priv = dev->dev_private; 764 DRM_DEBUG( "\n" ); 765 766 LOCK_TEST_WITH_RETURN( dev, filp ); 767 768 if ( dev_priv->cce_running ) { 769 r128_do_cce_flush( dev_priv ); 770 } 771 772 return r128_do_cce_idle( dev_priv ); 773} 774 775int r128_engine_reset( DRM_IOCTL_ARGS ) 776{ 777 DRM_DEVICE; 778 DRM_DEBUG( "\n" ); 779 780 LOCK_TEST_WITH_RETURN( dev, filp ); 781 782 return r128_do_engine_reset( dev ); 783} 784 785int r128_fullscreen( DRM_IOCTL_ARGS ) 786{ 787 return DRM_ERR(EINVAL); 788} 789 790 791/* ================================================================ 792 * Freelist management 793 */ 794#define R128_BUFFER_USED 0xffffffff 795#define R128_BUFFER_FREE 0 796 797#if 0 798static int r128_freelist_init( drm_device_t *dev ) 799{ 800 drm_device_dma_t *dma = dev->dma; 801 drm_r128_private_t *dev_priv = dev->dev_private; 802 drm_buf_t *buf; 803 drm_r128_buf_priv_t *buf_priv; 804 drm_r128_freelist_t *entry; 805 int i; 806 807 dev_priv->head = DRM(alloc)( sizeof(drm_r128_freelist_t), 808 DRM_MEM_DRIVER ); 809 if ( dev_priv->head == NULL ) 810 return DRM_ERR(ENOMEM); 811 812 memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) ); 813 dev_priv->head->age = R128_BUFFER_USED; 814 815 for ( i = 0 ; i < dma->buf_count ; i++ ) { 816 buf = dma->buflist[i]; 817 buf_priv = buf->dev_private; 818 819 entry = DRM(alloc)( sizeof(drm_r128_freelist_t), 820 DRM_MEM_DRIVER ); 821 if ( !entry ) return DRM_ERR(ENOMEM); 822 823 entry->age = R128_BUFFER_FREE; 824 entry->buf = buf; 825 entry->prev = dev_priv->head; 826 entry->next = dev_priv->head->next; 827 if ( !entry->next ) 828 dev_priv->tail = entry; 829 830 buf_priv->discard = 0; 831 buf_priv->dispatched = 0; 832 buf_priv->list_entry = entry; 833 834 dev_priv->head->next = entry; 835 836 if ( dev_priv->head->next ) 837 dev_priv->head->next->prev = entry; 838 } 839 840 return 0; 841 842} 843#endif 844 845drm_buf_t *r128_freelist_get( drm_device_t *dev ) 846{ 847 drm_device_dma_t *dma = dev->dma; 848 drm_r128_private_t *dev_priv = dev->dev_private; 849 drm_r128_buf_priv_t *buf_priv; 850 drm_buf_t *buf; 851 int i, t; 852 853 /* FIXME: Optimize -- use freelist code */ 854 855 for ( i = 0 ; i < dma->buf_count ; i++ ) { 856 buf = dma->buflist[i]; 857 buf_priv = buf->dev_private; 858 if ( buf->filp == 0 ) 859 return buf; 860 } 861 862 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { 863 u32 done_age = R128_READ( R128_LAST_DISPATCH_REG ); 864 865 for ( i = 0 ; i < dma->buf_count ; i++ ) { 866 buf = dma->buflist[i]; 867 buf_priv = buf->dev_private; 868 if ( buf->pending && buf_priv->age <= done_age ) { 869 /* The buffer has been processed, so it 870 * can now be used. 871 */ 872 buf->pending = 0; 873 return buf; 874 } 875 } 876 DRM_UDELAY( 1 ); 877 } 878 879 DRM_DEBUG( "returning NULL!\n" ); 880 return NULL; 881} 882 883void r128_freelist_reset( drm_device_t *dev ) 884{ 885 drm_device_dma_t *dma = dev->dma; 886 int i; 887 888 for ( i = 0 ; i < dma->buf_count ; i++ ) { 889 drm_buf_t *buf = dma->buflist[i]; 890 drm_r128_buf_priv_t *buf_priv = buf->dev_private; 891 buf_priv->age = 0; 892 } 893} 894 895 896/* ================================================================ 897 * CCE command submission 898 */ 899 900int r128_wait_ring( drm_r128_private_t *dev_priv, int n ) 901{ 902 drm_r128_ring_buffer_t *ring = &dev_priv->ring; 903 int i; 904 905 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 906 r128_update_ring_snapshot( ring ); 907 if ( ring->space >= n ) 908 return 0; 909 DRM_UDELAY( 1 ); 910 } 911 912 /* FIXME: This is being ignored... */ 913 DRM_ERROR( "failed!\n" ); 914 return DRM_ERR(EBUSY); 915} 916 917static int r128_cce_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) 918{ 919 int i; 920 drm_buf_t *buf; 921 922 for ( i = d->granted_count ; i < d->request_count ; i++ ) { 923 buf = r128_freelist_get( dev ); 924 if ( !buf ) return DRM_ERR(EAGAIN); 925 926 buf->filp = filp; 927 928 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, 929 sizeof(buf->idx) ) ) 930 return DRM_ERR(EFAULT); 931 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, 932 sizeof(buf->total) ) ) 933 return DRM_ERR(EFAULT); 934 935 d->granted_count++; 936 } 937 return 0; 938} 939 940int r128_cce_buffers( DRM_IOCTL_ARGS ) 941{ 942 DRM_DEVICE; 943 drm_device_dma_t *dma = dev->dma; 944 int ret = 0; 945 drm_dma_t d; 946 947 LOCK_TEST_WITH_RETURN( dev, filp ); 948 949 DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *) data, sizeof(d) ); 950 951 /* Please don't send us buffers. 952 */ 953 if ( d.send_count != 0 ) { 954 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", 955 DRM_CURRENTPID, d.send_count ); 956 return DRM_ERR(EINVAL); 957 } 958 959 /* We'll send you buffers. 960 */ 961 if ( d.request_count < 0 || d.request_count > dma->buf_count ) { 962 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", 963 DRM_CURRENTPID, d.request_count, dma->buf_count ); 964 return DRM_ERR(EINVAL); 965 } 966 967 d.granted_count = 0; 968 969 if ( d.request_count ) { 970 ret = r128_cce_get_buffers( filp, dev, &d ); 971 } 972 973 DRM_COPY_TO_USER_IOCTL((drm_dma_t *) data, d, sizeof(d) ); 974 975 return ret; 976} 977