mga_drm.h revision 95746
195584Sanholt/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*- 295584Sanholt * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com 395584Sanholt * 495584Sanholt * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 595584Sanholt * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 695584Sanholt * All rights reserved. 795584Sanholt * 895584Sanholt * Permission is hereby granted, free of charge, to any person obtaining a 995584Sanholt * copy of this software and associated documentation files (the "Software"), 1095584Sanholt * to deal in the Software without restriction, including without limitation 1195584Sanholt * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1295584Sanholt * and/or sell copies of the Software, and to permit persons to whom the 1395584Sanholt * Software is furnished to do so, subject to the following conditions: 1495584Sanholt * 1595584Sanholt * The above copyright notice and this permission notice (including the next 1695584Sanholt * paragraph) shall be included in all copies or substantial portions of the 1795584Sanholt * Software. 1895584Sanholt * 1995584Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 2095584Sanholt * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2195584Sanholt * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2295584Sanholt * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 2395584Sanholt * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2495584Sanholt * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2595584Sanholt * OTHER DEALINGS IN THE SOFTWARE. 2695584Sanholt * 2795584Sanholt * Authors: 2895584Sanholt * Jeff Hartmann <jhartmann@valinux.com> 2995584Sanholt * Keith Whitwell <keithw@valinux.com> 3095584Sanholt * 3195584Sanholt * Rewritten by: 3295584Sanholt * Gareth Hughes <gareth@valinux.com> 3395584Sanholt * 3495584Sanholt * $FreeBSD: head/sys/dev/drm/mga_drm.h 95746 2002-04-29 18:18:42Z anholt $ 3595584Sanholt */ 3695584Sanholt 3795584Sanholt#ifndef __MGA_DRM_H__ 3895584Sanholt#define __MGA_DRM_H__ 3995584Sanholt 4095584Sanholt/* WARNING: If you change any of these defines, make sure to change the 4195584Sanholt * defines in the Xserver file (mga_sarea.h) 4295584Sanholt */ 4395584Sanholt#ifndef __MGA_SAREA_DEFINES__ 4495584Sanholt#define __MGA_SAREA_DEFINES__ 4595584Sanholt 4695584Sanholt/* WARP pipe flags 4795584Sanholt */ 4895584Sanholt#define MGA_F 0x1 /* fog */ 4995584Sanholt#define MGA_A 0x2 /* alpha */ 5095584Sanholt#define MGA_S 0x4 /* specular */ 5195584Sanholt#define MGA_T2 0x8 /* multitexture */ 5295584Sanholt 5395584Sanholt#define MGA_WARP_TGZ 0 5495584Sanholt#define MGA_WARP_TGZF (MGA_F) 5595584Sanholt#define MGA_WARP_TGZA (MGA_A) 5695584Sanholt#define MGA_WARP_TGZAF (MGA_F|MGA_A) 5795584Sanholt#define MGA_WARP_TGZS (MGA_S) 5895584Sanholt#define MGA_WARP_TGZSF (MGA_S|MGA_F) 5995584Sanholt#define MGA_WARP_TGZSA (MGA_S|MGA_A) 6095584Sanholt#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A) 6195584Sanholt#define MGA_WARP_T2GZ (MGA_T2) 6295584Sanholt#define MGA_WARP_T2GZF (MGA_T2|MGA_F) 6395584Sanholt#define MGA_WARP_T2GZA (MGA_T2|MGA_A) 6495584Sanholt#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F) 6595584Sanholt#define MGA_WARP_T2GZS (MGA_T2|MGA_S) 6695584Sanholt#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F) 6795584Sanholt#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) 6895584Sanholt#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) 6995584Sanholt 7095584Sanholt#define MGA_MAX_G200_PIPES 8 /* no multitex */ 7195584Sanholt#define MGA_MAX_G400_PIPES 16 7295584Sanholt#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES 7395584Sanholt#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ 7495584Sanholt 7595584Sanholt#define MGA_CARD_TYPE_G200 1 7695584Sanholt#define MGA_CARD_TYPE_G400 2 7795584Sanholt 7895584Sanholt 7995584Sanholt#define MGA_FRONT 0x1 8095584Sanholt#define MGA_BACK 0x2 8195584Sanholt#define MGA_DEPTH 0x4 8295584Sanholt 8395584Sanholt/* What needs to be changed for the current vertex dma buffer? 8495584Sanholt */ 8595584Sanholt#define MGA_UPLOAD_CONTEXT 0x1 8695584Sanholt#define MGA_UPLOAD_TEX0 0x2 8795584Sanholt#define MGA_UPLOAD_TEX1 0x4 8895584Sanholt#define MGA_UPLOAD_PIPE 0x8 8995584Sanholt#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ 9095584Sanholt#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ 9195584Sanholt#define MGA_UPLOAD_2D 0x40 9295584Sanholt#define MGA_WAIT_AGE 0x80 /* handled client-side */ 9395584Sanholt#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ 9495584Sanholt#if 0 9595584Sanholt#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock 9695584Sanholt quiescent */ 9795584Sanholt#endif 9895584Sanholt 9995584Sanholt/* 32 buffers of 64k each, total 2 meg. 10095584Sanholt */ 10195584Sanholt#define MGA_BUFFER_SIZE (1 << 16) 10295584Sanholt#define MGA_NUM_BUFFERS 128 10395584Sanholt 10495584Sanholt/* Keep these small for testing. 10595584Sanholt */ 10695584Sanholt#define MGA_NR_SAREA_CLIPRECTS 8 10795584Sanholt 10895584Sanholt/* 2 heaps (1 for card, 1 for agp), each divided into upto 128 10995584Sanholt * regions, subject to a minimum region size of (1<<16) == 64k. 11095584Sanholt * 11195584Sanholt * Clients may subdivide regions internally, but when sharing between 11295584Sanholt * clients, the region size is the minimum granularity. 11395584Sanholt */ 11495584Sanholt 11595584Sanholt#define MGA_CARD_HEAP 0 11695584Sanholt#define MGA_AGP_HEAP 1 11795584Sanholt#define MGA_NR_TEX_HEAPS 2 11895584Sanholt#define MGA_NR_TEX_REGIONS 16 11995584Sanholt#define MGA_LOG_MIN_TEX_REGION_SIZE 16 12095584Sanholt 12195584Sanholt#endif /* __MGA_SAREA_DEFINES__ */ 12295584Sanholt 12395584Sanholt 12495584Sanholt/* Setup registers for 3D context 12595584Sanholt */ 12695584Sanholttypedef struct { 12795584Sanholt unsigned int dstorg; 12895584Sanholt unsigned int maccess; 12995584Sanholt unsigned int plnwt; 13095584Sanholt unsigned int dwgctl; 13195584Sanholt unsigned int alphactrl; 13295584Sanholt unsigned int fogcolor; 13395584Sanholt unsigned int wflag; 13495584Sanholt unsigned int tdualstage0; 13595584Sanholt unsigned int tdualstage1; 13695584Sanholt unsigned int fcol; 13795584Sanholt unsigned int stencil; 13895584Sanholt unsigned int stencilctl; 13995584Sanholt} drm_mga_context_regs_t; 14095584Sanholt 14195584Sanholt/* Setup registers for 2D, X server 14295584Sanholt */ 14395584Sanholttypedef struct { 14495584Sanholt unsigned int pitch; 14595584Sanholt} drm_mga_server_regs_t; 14695584Sanholt 14795584Sanholt/* Setup registers for each texture unit 14895584Sanholt */ 14995584Sanholttypedef struct { 15095584Sanholt unsigned int texctl; 15195584Sanholt unsigned int texctl2; 15295584Sanholt unsigned int texfilter; 15395584Sanholt unsigned int texbordercol; 15495584Sanholt unsigned int texorg; 15595584Sanholt unsigned int texwidth; 15695584Sanholt unsigned int texheight; 15795584Sanholt unsigned int texorg1; 15895584Sanholt unsigned int texorg2; 15995584Sanholt unsigned int texorg3; 16095584Sanholt unsigned int texorg4; 16195584Sanholt} drm_mga_texture_regs_t; 16295584Sanholt 16395584Sanholt/* General aging mechanism 16495584Sanholt */ 16595584Sanholttypedef struct { 16695584Sanholt unsigned int head; /* Position of head pointer */ 16795584Sanholt unsigned int wrap; /* Primary DMA wrap count */ 16895584Sanholt} drm_mga_age_t; 16995584Sanholt 17095584Sanholttypedef struct _drm_mga_sarea { 17195584Sanholt /* The channel for communication of state information to the kernel 17295584Sanholt * on firing a vertex dma buffer. 17395584Sanholt */ 17495584Sanholt drm_mga_context_regs_t context_state; 17595584Sanholt drm_mga_server_regs_t server_state; 17695584Sanholt drm_mga_texture_regs_t tex_state[2]; 17795584Sanholt unsigned int warp_pipe; 17895584Sanholt unsigned int dirty; 17995584Sanholt unsigned int vertsize; 18095584Sanholt 18195584Sanholt /* The current cliprects, or a subset thereof. 18295584Sanholt */ 18395584Sanholt drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS]; 18495584Sanholt unsigned int nbox; 18595584Sanholt 18695584Sanholt /* Information about the most recently used 3d drawable. The 18795584Sanholt * client fills in the req_* fields, the server fills in the 18895584Sanholt * exported_ fields and puts the cliprects into boxes, above. 18995584Sanholt * 19095584Sanholt * The client clears the exported_drawable field before 19195584Sanholt * clobbering the boxes data. 19295584Sanholt */ 19395584Sanholt unsigned int req_drawable; /* the X drawable id */ 19495584Sanholt unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ 19595584Sanholt 19695584Sanholt unsigned int exported_drawable; 19795584Sanholt unsigned int exported_index; 19895584Sanholt unsigned int exported_stamp; 19995584Sanholt unsigned int exported_buffers; 20095584Sanholt unsigned int exported_nfront; 20195584Sanholt unsigned int exported_nback; 20295584Sanholt int exported_back_x, exported_front_x, exported_w; 20395584Sanholt int exported_back_y, exported_front_y, exported_h; 20495584Sanholt drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS]; 20595584Sanholt 20695584Sanholt /* Counters for aging textures and for client-side throttling. 20795584Sanholt */ 20895584Sanholt unsigned int status[4]; 20995584Sanholt unsigned int last_wrap; 21095584Sanholt 21195584Sanholt drm_mga_age_t last_frame; 21295584Sanholt unsigned int last_enqueue; /* last time a buffer was enqueued */ 21395584Sanholt unsigned int last_dispatch; /* age of the most recently dispatched buffer */ 21495584Sanholt unsigned int last_quiescent; /* */ 21595584Sanholt 21695584Sanholt /* LRU lists for texture memory in agp space and on the card. 21795584Sanholt */ 21895584Sanholt drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1]; 21995584Sanholt unsigned int texAge[MGA_NR_TEX_HEAPS]; 22095584Sanholt 22195584Sanholt /* Mechanism to validate card state. 22295584Sanholt */ 22395584Sanholt int ctxOwner; 22495584Sanholt} drm_mga_sarea_t; 22595584Sanholt 22695746Sanholt/* MGA specific ioctls */ 22795746Sanholt#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t) 22895746Sanholt#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x41, drm_lock_t) 22995746Sanholt#define DRM_IOCTL_MGA_RESET DRM_IO( 0x42) 23095746Sanholt#define DRM_IOCTL_MGA_SWAP DRM_IO( 0x43) 23195746Sanholt#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x44, drm_mga_clear_t) 23295746Sanholt#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x45, drm_mga_vertex_t) 23395746Sanholt#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t) 23495746Sanholt#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x47, drm_mga_iload_t) 23595746Sanholt#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x48, drm_mga_blit_t) 23695584Sanholt 23795746Sanholt 23895584Sanholt/* WARNING: If you change any of these defines, make sure to change the 23995584Sanholt * defines in the Xserver file (xf86drmMga.h) 24095584Sanholt */ 24195584Sanholttypedef struct _drm_mga_warp_index { 24295584Sanholt int installed; 24395584Sanholt unsigned long phys_addr; 24495584Sanholt int size; 24595584Sanholt} drm_mga_warp_index_t; 24695584Sanholt 24795584Sanholttypedef struct drm_mga_init { 24895584Sanholt enum { 24995584Sanholt MGA_INIT_DMA = 0x01, 25095584Sanholt MGA_CLEANUP_DMA = 0x02 25195584Sanholt } func; 25295584Sanholt 25395584Sanholt unsigned long sarea_priv_offset; 25495584Sanholt 25595584Sanholt int chipset; 25695584Sanholt int sgram; 25795584Sanholt 25895584Sanholt unsigned int maccess; 25995584Sanholt 26095584Sanholt unsigned int fb_cpp; 26195584Sanholt unsigned int front_offset, front_pitch; 26295584Sanholt unsigned int back_offset, back_pitch; 26395584Sanholt 26495584Sanholt unsigned int depth_cpp; 26595584Sanholt unsigned int depth_offset, depth_pitch; 26695584Sanholt 26795584Sanholt unsigned int texture_offset[MGA_NR_TEX_HEAPS]; 26895584Sanholt unsigned int texture_size[MGA_NR_TEX_HEAPS]; 26995584Sanholt 27095584Sanholt unsigned long fb_offset; 27195584Sanholt unsigned long mmio_offset; 27295584Sanholt unsigned long status_offset; 27395584Sanholt unsigned long warp_offset; 27495584Sanholt unsigned long primary_offset; 27595584Sanholt unsigned long buffers_offset; 27695584Sanholt} drm_mga_init_t; 27795584Sanholt 27895584Sanholttypedef struct drm_mga_fullscreen { 27995584Sanholt enum { 28095584Sanholt MGA_INIT_FULLSCREEN = 0x01, 28195584Sanholt MGA_CLEANUP_FULLSCREEN = 0x02 28295584Sanholt } func; 28395584Sanholt} drm_mga_fullscreen_t; 28495584Sanholt 28595584Sanholttypedef struct drm_mga_clear { 28695584Sanholt unsigned int flags; 28795584Sanholt unsigned int clear_color; 28895584Sanholt unsigned int clear_depth; 28995584Sanholt unsigned int color_mask; 29095584Sanholt unsigned int depth_mask; 29195584Sanholt} drm_mga_clear_t; 29295584Sanholt 29395584Sanholttypedef struct drm_mga_vertex { 29495584Sanholt int idx; /* buffer to queue */ 29595584Sanholt int used; /* bytes in use */ 29695584Sanholt int discard; /* client finished with buffer? */ 29795584Sanholt} drm_mga_vertex_t; 29895584Sanholt 29995584Sanholttypedef struct drm_mga_indices { 30095584Sanholt int idx; /* buffer to queue */ 30195584Sanholt unsigned int start; 30295584Sanholt unsigned int end; 30395584Sanholt int discard; /* client finished with buffer? */ 30495584Sanholt} drm_mga_indices_t; 30595584Sanholt 30695584Sanholttypedef struct drm_mga_iload { 30795584Sanholt int idx; 30895584Sanholt unsigned int dstorg; 30995584Sanholt unsigned int length; 31095584Sanholt} drm_mga_iload_t; 31195584Sanholt 31295584Sanholttypedef struct _drm_mga_blit { 31395584Sanholt unsigned int planemask; 31495584Sanholt unsigned int srcorg; 31595584Sanholt unsigned int dstorg; 31695584Sanholt int src_pitch, dst_pitch; 31795584Sanholt int delta_sx, delta_sy; 31895584Sanholt int delta_dx, delta_dy; 31995584Sanholt int height, ydir; /* flip image vertically */ 32095584Sanholt int source_pitch, dest_pitch; 32195584Sanholt} drm_mga_blit_t; 32295584Sanholt 32395584Sanholt#endif 324