mga_drm.h revision 145132
195584Sanholt/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
2139749Simp * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com */
3139749Simp/*-
495584Sanholt * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
595584Sanholt * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
695584Sanholt * All rights reserved.
795584Sanholt *
895584Sanholt * Permission is hereby granted, free of charge, to any person obtaining a
995584Sanholt * copy of this software and associated documentation files (the "Software"),
1095584Sanholt * to deal in the Software without restriction, including without limitation
1195584Sanholt * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1295584Sanholt * and/or sell copies of the Software, and to permit persons to whom the
1395584Sanholt * Software is furnished to do so, subject to the following conditions:
1495584Sanholt *
1595584Sanholt * The above copyright notice and this permission notice (including the next
1695584Sanholt * paragraph) shall be included in all copies or substantial portions of the
1795584Sanholt * Software.
1895584Sanholt *
1995584Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
2095584Sanholt * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2195584Sanholt * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
2295584Sanholt * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
2395584Sanholt * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
2495584Sanholt * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2595584Sanholt * OTHER DEALINGS IN THE SOFTWARE.
2695584Sanholt *
2795584Sanholt * Authors:
2895584Sanholt *    Jeff Hartmann <jhartmann@valinux.com>
29112015Sanholt *    Keith Whitwell <keith@tungstengraphics.com>
3095584Sanholt *
3195584Sanholt * Rewritten by:
3295584Sanholt *    Gareth Hughes <gareth@valinux.com>
3395584Sanholt *
3495584Sanholt * $FreeBSD: head/sys/dev/drm/mga_drm.h 145132 2005-04-16 03:44:47Z anholt $
3595584Sanholt */
3695584Sanholt
3795584Sanholt#ifndef __MGA_DRM_H__
3895584Sanholt#define __MGA_DRM_H__
3995584Sanholt
4095584Sanholt/* WARNING: If you change any of these defines, make sure to change the
4195584Sanholt * defines in the Xserver file (mga_sarea.h)
4295584Sanholt */
43112015Sanholt
4495584Sanholt#ifndef __MGA_SAREA_DEFINES__
4595584Sanholt#define __MGA_SAREA_DEFINES__
4695584Sanholt
4795584Sanholt/* WARP pipe flags
4895584Sanholt */
49145132Sanholt#define MGA_F			0x1	/* fog */
50145132Sanholt#define MGA_A			0x2	/* alpha */
51145132Sanholt#define MGA_S			0x4	/* specular */
52145132Sanholt#define MGA_T2			0x8	/* multitexture */
5395584Sanholt
5495584Sanholt#define MGA_WARP_TGZ		0
5595584Sanholt#define MGA_WARP_TGZF		(MGA_F)
5695584Sanholt#define MGA_WARP_TGZA		(MGA_A)
5795584Sanholt#define MGA_WARP_TGZAF		(MGA_F|MGA_A)
5895584Sanholt#define MGA_WARP_TGZS		(MGA_S)
5995584Sanholt#define MGA_WARP_TGZSF		(MGA_S|MGA_F)
6095584Sanholt#define MGA_WARP_TGZSA		(MGA_S|MGA_A)
6195584Sanholt#define MGA_WARP_TGZSAF		(MGA_S|MGA_F|MGA_A)
6295584Sanholt#define MGA_WARP_T2GZ		(MGA_T2)
6395584Sanholt#define MGA_WARP_T2GZF		(MGA_T2|MGA_F)
6495584Sanholt#define MGA_WARP_T2GZA		(MGA_T2|MGA_A)
6595584Sanholt#define MGA_WARP_T2GZAF		(MGA_T2|MGA_A|MGA_F)
6695584Sanholt#define MGA_WARP_T2GZS		(MGA_T2|MGA_S)
6795584Sanholt#define MGA_WARP_T2GZSF		(MGA_T2|MGA_S|MGA_F)
6895584Sanholt#define MGA_WARP_T2GZSA		(MGA_T2|MGA_S|MGA_A)
6995584Sanholt#define MGA_WARP_T2GZSAF	(MGA_T2|MGA_S|MGA_F|MGA_A)
7095584Sanholt
71145132Sanholt#define MGA_MAX_G200_PIPES	8	/* no multitex */
7295584Sanholt#define MGA_MAX_G400_PIPES	16
7395584Sanholt#define MGA_MAX_WARP_PIPES	MGA_MAX_G400_PIPES
74145132Sanholt#define MGA_WARP_UCODE_SIZE	32768	/* in bytes */
7595584Sanholt
7695584Sanholt#define MGA_CARD_TYPE_G200	1
7795584Sanholt#define MGA_CARD_TYPE_G400	2
7895584Sanholt
7995584Sanholt#define MGA_FRONT		0x1
8095584Sanholt#define MGA_BACK		0x2
8195584Sanholt#define MGA_DEPTH		0x4
8295584Sanholt
8395584Sanholt/* What needs to be changed for the current vertex dma buffer?
8495584Sanholt */
8595584Sanholt#define MGA_UPLOAD_CONTEXT	0x1
8695584Sanholt#define MGA_UPLOAD_TEX0		0x2
8795584Sanholt#define MGA_UPLOAD_TEX1		0x4
8895584Sanholt#define MGA_UPLOAD_PIPE		0x8
89145132Sanholt#define MGA_UPLOAD_TEX0IMAGE	0x10	/* handled client-side */
90145132Sanholt#define MGA_UPLOAD_TEX1IMAGE	0x20	/* handled client-side */
9195584Sanholt#define MGA_UPLOAD_2D		0x40
92145132Sanholt#define MGA_WAIT_AGE		0x80	/* handled client-side */
93145132Sanholt#define MGA_UPLOAD_CLIPRECTS	0x100	/* handled client-side */
9495584Sanholt#if 0
95145132Sanholt#define MGA_DMA_FLUSH		0x200	/* set when someone gets the lock
96145132Sanholt					   quiescent */
9795584Sanholt#endif
9895584Sanholt
9995584Sanholt/* 32 buffers of 64k each, total 2 meg.
10095584Sanholt */
10195584Sanholt#define MGA_BUFFER_SIZE		(1 << 16)
10295584Sanholt#define MGA_NUM_BUFFERS		128
10395584Sanholt
10495584Sanholt/* Keep these small for testing.
10595584Sanholt */
10695584Sanholt#define MGA_NR_SAREA_CLIPRECTS	8
10795584Sanholt
10895584Sanholt/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
10995584Sanholt * regions, subject to a minimum region size of (1<<16) == 64k.
11095584Sanholt *
11195584Sanholt * Clients may subdivide regions internally, but when sharing between
11295584Sanholt * clients, the region size is the minimum granularity.
11395584Sanholt */
11495584Sanholt
11595584Sanholt#define MGA_CARD_HEAP			0
11695584Sanholt#define MGA_AGP_HEAP			1
11795584Sanholt#define MGA_NR_TEX_HEAPS		2
11895584Sanholt#define MGA_NR_TEX_REGIONS		16
11995584Sanholt#define MGA_LOG_MIN_TEX_REGION_SIZE	16
12095584Sanholt
121130331Sanholt#define  DRM_MGA_IDLE_RETRY          2048
122130331Sanholt
123145132Sanholt#endif				/* __MGA_SAREA_DEFINES__ */
12495584Sanholt
12595584Sanholt/* Setup registers for 3D context
12695584Sanholt */
12795584Sanholttypedef struct {
12895584Sanholt	unsigned int dstorg;
12995584Sanholt	unsigned int maccess;
13095584Sanholt	unsigned int plnwt;
13195584Sanholt	unsigned int dwgctl;
13295584Sanholt	unsigned int alphactrl;
13395584Sanholt	unsigned int fogcolor;
13495584Sanholt	unsigned int wflag;
13595584Sanholt	unsigned int tdualstage0;
13695584Sanholt	unsigned int tdualstage1;
13795584Sanholt	unsigned int fcol;
13895584Sanholt	unsigned int stencil;
13995584Sanholt	unsigned int stencilctl;
14095584Sanholt} drm_mga_context_regs_t;
14195584Sanholt
14295584Sanholt/* Setup registers for 2D, X server
14395584Sanholt */
14495584Sanholttypedef struct {
14595584Sanholt	unsigned int pitch;
14695584Sanholt} drm_mga_server_regs_t;
14795584Sanholt
14895584Sanholt/* Setup registers for each texture unit
14995584Sanholt */
15095584Sanholttypedef struct {
15195584Sanholt	unsigned int texctl;
15295584Sanholt	unsigned int texctl2;
15395584Sanholt	unsigned int texfilter;
15495584Sanholt	unsigned int texbordercol;
15595584Sanholt	unsigned int texorg;
15695584Sanholt	unsigned int texwidth;
15795584Sanholt	unsigned int texheight;
15895584Sanholt	unsigned int texorg1;
15995584Sanholt	unsigned int texorg2;
16095584Sanholt	unsigned int texorg3;
16195584Sanholt	unsigned int texorg4;
16295584Sanholt} drm_mga_texture_regs_t;
16395584Sanholt
16495584Sanholt/* General aging mechanism
16595584Sanholt */
16695584Sanholttypedef struct {
167145132Sanholt	unsigned int head;	/* Position of head pointer          */
168145132Sanholt	unsigned int wrap;	/* Primary DMA wrap count            */
16995584Sanholt} drm_mga_age_t;
17095584Sanholt
17195584Sanholttypedef struct _drm_mga_sarea {
17295584Sanholt	/* The channel for communication of state information to the kernel
17395584Sanholt	 * on firing a vertex dma buffer.
17495584Sanholt	 */
175145132Sanholt	drm_mga_context_regs_t context_state;
176145132Sanholt	drm_mga_server_regs_t server_state;
177145132Sanholt	drm_mga_texture_regs_t tex_state[2];
178145132Sanholt	unsigned int warp_pipe;
179145132Sanholt	unsigned int dirty;
180145132Sanholt	unsigned int vertsize;
18195584Sanholt
18295584Sanholt	/* The current cliprects, or a subset thereof.
18395584Sanholt	 */
184145132Sanholt	drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
185145132Sanholt	unsigned int nbox;
18695584Sanholt
18795584Sanholt	/* Information about the most recently used 3d drawable.  The
18895584Sanholt	 * client fills in the req_* fields, the server fills in the
18995584Sanholt	 * exported_ fields and puts the cliprects into boxes, above.
19095584Sanholt	 *
19195584Sanholt	 * The client clears the exported_drawable field before
19295584Sanholt	 * clobbering the boxes data.
19395584Sanholt	 */
194145132Sanholt	unsigned int req_drawable;	/* the X drawable id */
195145132Sanholt	unsigned int req_draw_buffer;	/* MGA_FRONT or MGA_BACK */
19695584Sanholt
197145132Sanholt	unsigned int exported_drawable;
19895584Sanholt	unsigned int exported_index;
199145132Sanholt	unsigned int exported_stamp;
200145132Sanholt	unsigned int exported_buffers;
201145132Sanholt	unsigned int exported_nfront;
202145132Sanholt	unsigned int exported_nback;
20395584Sanholt	int exported_back_x, exported_front_x, exported_w;
20495584Sanholt	int exported_back_y, exported_front_y, exported_h;
205145132Sanholt	drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
20695584Sanholt
20795584Sanholt	/* Counters for aging textures and for client-side throttling.
20895584Sanholt	 */
20995584Sanholt	unsigned int status[4];
21095584Sanholt	unsigned int last_wrap;
21195584Sanholt
21295584Sanholt	drm_mga_age_t last_frame;
213145132Sanholt	unsigned int last_enqueue;	/* last time a buffer was enqueued */
21495584Sanholt	unsigned int last_dispatch;	/* age of the most recently dispatched buffer */
215145132Sanholt	unsigned int last_quiescent;	/*  */
21695584Sanholt
21795584Sanholt	/* LRU lists for texture memory in agp space and on the card.
21895584Sanholt	 */
219145132Sanholt	drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
22095584Sanholt	unsigned int texAge[MGA_NR_TEX_HEAPS];
22195584Sanholt
22295584Sanholt	/* Mechanism to validate card state.
22395584Sanholt	 */
224145132Sanholt	int ctxOwner;
22595584Sanholt} drm_mga_sarea_t;
22695584Sanholt
227112015Sanholt/* WARNING: If you change any of these defines, make sure to change the
228112015Sanholt * defines in the Xserver file (xf86drmMga.h)
229112015Sanholt */
230112015Sanholt
231112015Sanholt/* MGA specific ioctls
232112015Sanholt * The device specific ioctl range is 0x40 to 0x79.
233112015Sanholt */
234130331Sanholt#define DRM_MGA_INIT     0x00
235130331Sanholt#define DRM_MGA_FLUSH    0x01
236130331Sanholt#define DRM_MGA_RESET    0x02
237130331Sanholt#define DRM_MGA_SWAP     0x03
238130331Sanholt#define DRM_MGA_CLEAR    0x04
239130331Sanholt#define DRM_MGA_VERTEX   0x05
240130331Sanholt#define DRM_MGA_INDICES  0x06
241130331Sanholt#define DRM_MGA_ILOAD    0x07
242130331Sanholt#define DRM_MGA_BLIT     0x08
243130331Sanholt#define DRM_MGA_GETPARAM 0x09
24495584Sanholt
245130331Sanholt#define DRM_IOCTL_MGA_INIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
246130331Sanholt#define DRM_IOCTL_MGA_FLUSH    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t)
247130331Sanholt#define DRM_IOCTL_MGA_RESET    DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_RESET)
248130331Sanholt#define DRM_IOCTL_MGA_SWAP     DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_SWAP)
249130331Sanholt#define DRM_IOCTL_MGA_CLEAR    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
250130331Sanholt#define DRM_IOCTL_MGA_VERTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
251130331Sanholt#define DRM_IOCTL_MGA_INDICES  DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
252130331Sanholt#define DRM_IOCTL_MGA_ILOAD    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
253130331Sanholt#define DRM_IOCTL_MGA_BLIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
254130331Sanholt#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
255130331Sanholt
25695584Sanholttypedef struct _drm_mga_warp_index {
257145132Sanholt	int installed;
258145132Sanholt	unsigned long phys_addr;
259145132Sanholt	int size;
26095584Sanholt} drm_mga_warp_index_t;
26195584Sanholt
26295584Sanholttypedef struct drm_mga_init {
263145132Sanholt	enum {
264145132Sanholt		MGA_INIT_DMA = 0x01,
265145132Sanholt		MGA_CLEANUP_DMA = 0x02
26695584Sanholt	} func;
26795584Sanholt
268145132Sanholt	unsigned long sarea_priv_offset;
26995584Sanholt
27095584Sanholt	int chipset;
271145132Sanholt	int sgram;
27295584Sanholt
27395584Sanholt	unsigned int maccess;
27495584Sanholt
275145132Sanholt	unsigned int fb_cpp;
27695584Sanholt	unsigned int front_offset, front_pitch;
277145132Sanholt	unsigned int back_offset, back_pitch;
27895584Sanholt
279145132Sanholt	unsigned int depth_cpp;
280145132Sanholt	unsigned int depth_offset, depth_pitch;
28195584Sanholt
282145132Sanholt	unsigned int texture_offset[MGA_NR_TEX_HEAPS];
283145132Sanholt	unsigned int texture_size[MGA_NR_TEX_HEAPS];
28495584Sanholt
28595584Sanholt	unsigned long fb_offset;
28695584Sanholt	unsigned long mmio_offset;
28795584Sanholt	unsigned long status_offset;
28895584Sanholt	unsigned long warp_offset;
28995584Sanholt	unsigned long primary_offset;
29095584Sanholt	unsigned long buffers_offset;
29195584Sanholt} drm_mga_init_t;
29295584Sanholt
29395584Sanholttypedef struct drm_mga_fullscreen {
29495584Sanholt	enum {
295145132Sanholt		MGA_INIT_FULLSCREEN = 0x01,
29695584Sanholt		MGA_CLEANUP_FULLSCREEN = 0x02
29795584Sanholt	} func;
29895584Sanholt} drm_mga_fullscreen_t;
29995584Sanholt
30095584Sanholttypedef struct drm_mga_clear {
30195584Sanholt	unsigned int flags;
30295584Sanholt	unsigned int clear_color;
30395584Sanholt	unsigned int clear_depth;
30495584Sanholt	unsigned int color_mask;
30595584Sanholt	unsigned int depth_mask;
30695584Sanholt} drm_mga_clear_t;
30795584Sanholt
30895584Sanholttypedef struct drm_mga_vertex {
309145132Sanholt	int idx;		/* buffer to queue */
310145132Sanholt	int used;		/* bytes in use */
311145132Sanholt	int discard;		/* client finished with buffer?  */
31295584Sanholt} drm_mga_vertex_t;
31395584Sanholt
31495584Sanholttypedef struct drm_mga_indices {
315145132Sanholt	int idx;		/* buffer to queue */
31695584Sanholt	unsigned int start;
31795584Sanholt	unsigned int end;
318145132Sanholt	int discard;		/* client finished with buffer?  */
31995584Sanholt} drm_mga_indices_t;
32095584Sanholt
32195584Sanholttypedef struct drm_mga_iload {
32295584Sanholt	int idx;
32395584Sanholt	unsigned int dstorg;
32495584Sanholt	unsigned int length;
32595584Sanholt} drm_mga_iload_t;
32695584Sanholt
32795584Sanholttypedef struct _drm_mga_blit {
32895584Sanholt	unsigned int planemask;
32995584Sanholt	unsigned int srcorg;
33095584Sanholt	unsigned int dstorg;
33195584Sanholt	int src_pitch, dst_pitch;
33295584Sanholt	int delta_sx, delta_sy;
33395584Sanholt	int delta_dx, delta_dy;
334145132Sanholt	int height, ydir;	/* flip image vertically */
33595584Sanholt	int source_pitch, dest_pitch;
33695584Sanholt} drm_mga_blit_t;
33795584Sanholt
338112015Sanholt/* 3.1: An ioctl to get parameters that aren't available to the 3d
339145132Sanholt * client any other way.
340112015Sanholt */
341112015Sanholt#define MGA_PARAM_IRQ_NR            1
342112015Sanholt
343112015Sanholttypedef struct drm_mga_getparam {
344112015Sanholt	int param;
345145132Sanholt	void __user *value;
346112015Sanholt} drm_mga_getparam_t;
347112015Sanholt
34895584Sanholt#endif
349