mga_drm.h revision 130331
137535Sdes/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
263012Sdes * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
337535Sdes *
437535Sdes * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
537535Sdes * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
637535Sdes * All rights reserved.
737535Sdes *
837535Sdes * Permission is hereby granted, free of charge, to any person obtaining a
937535Sdes * copy of this software and associated documentation files (the "Software"),
1037535Sdes * to deal in the Software without restriction, including without limitation
1137535Sdes * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1237535Sdes * and/or sell copies of the Software, and to permit persons to whom the
1337535Sdes * Software is furnished to do so, subject to the following conditions:
1437535Sdes *
1563012Sdes * The above copyright notice and this permission notice (including the next
1637535Sdes * paragraph) shall be included in all copies or substantial portions of the
1737535Sdes * Software.
1837535Sdes *
1937535Sdes * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
2037535Sdes * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2137535Sdes * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
2237535Sdes * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
2337535Sdes * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
2437535Sdes * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2537535Sdes * OTHER DEALINGS IN THE SOFTWARE.
2637535Sdes *
2737535Sdes * Authors:
2863012Sdes *    Jeff Hartmann <jhartmann@valinux.com>
2937535Sdes *    Keith Whitwell <keith@tungstengraphics.com>
3037535Sdes *
3163236Sdes * Rewritten by:
3263236Sdes *    Gareth Hughes <gareth@valinux.com>
3363236Sdes *
3463236Sdes * $FreeBSD: head/sys/dev/drm/mga_drm.h 130331 2004-06-11 03:26:59Z anholt $
3563236Sdes */
3663236Sdes
3763236Sdes#ifndef __MGA_DRM_H__
3863236Sdes#define __MGA_DRM_H__
3963236Sdes
4063236Sdes/* WARNING: If you change any of these defines, make sure to change the
4163236Sdes * defines in the Xserver file (mga_sarea.h)
4263236Sdes */
4363236Sdes
4463236Sdes#ifndef __MGA_SAREA_DEFINES__
4563236Sdes#define __MGA_SAREA_DEFINES__
4663236Sdes
4763236Sdes/* WARP pipe flags
4863236Sdes */
4963236Sdes#define MGA_F			0x1		/* fog */
5063236Sdes#define MGA_A			0x2		/* alpha */
5163236Sdes#define MGA_S			0x4		/* specular */
5263236Sdes#define MGA_T2			0x8		/* multitexture */
5363236Sdes
5463236Sdes#define MGA_WARP_TGZ		0
5563236Sdes#define MGA_WARP_TGZF		(MGA_F)
5663236Sdes#define MGA_WARP_TGZA		(MGA_A)
5763236Sdes#define MGA_WARP_TGZAF		(MGA_F|MGA_A)
5863236Sdes#define MGA_WARP_TGZS		(MGA_S)
5963236Sdes#define MGA_WARP_TGZSF		(MGA_S|MGA_F)
6063236Sdes#define MGA_WARP_TGZSA		(MGA_S|MGA_A)
6163236Sdes#define MGA_WARP_TGZSAF		(MGA_S|MGA_F|MGA_A)
6263236Sdes#define MGA_WARP_T2GZ		(MGA_T2)
6337535Sdes#define MGA_WARP_T2GZF		(MGA_T2|MGA_F)
6460737Sume#define MGA_WARP_T2GZA		(MGA_T2|MGA_A)
6537535Sdes#define MGA_WARP_T2GZAF		(MGA_T2|MGA_A|MGA_F)
6663012Sdes#define MGA_WARP_T2GZS		(MGA_T2|MGA_S)
6737535Sdes#define MGA_WARP_T2GZSF		(MGA_T2|MGA_S|MGA_F)
6863012Sdes#define MGA_WARP_T2GZSA		(MGA_T2|MGA_S|MGA_A)
6960376Sdes#define MGA_WARP_T2GZSAF	(MGA_T2|MGA_S|MGA_F|MGA_A)
7060189Sdes
7137608Sdes#define MGA_MAX_G200_PIPES	8		/* no multitex */
7237535Sdes#define MGA_MAX_G400_PIPES	16
7337535Sdes#define MGA_MAX_WARP_PIPES	MGA_MAX_G400_PIPES
7437535Sdes#define MGA_WARP_UCODE_SIZE	32768		/* in bytes */
7560376Sdes
7637535Sdes#define MGA_CARD_TYPE_G200	1
7737535Sdes#define MGA_CARD_TYPE_G400	2
7837535Sdes
7940939Sdes
8041862Sdes#define MGA_FRONT		0x1
8137535Sdes#define MGA_BACK		0x2
8263012Sdes#define MGA_DEPTH		0x4
8337535Sdes
8463012Sdes/* What needs to be changed for the current vertex dma buffer?
8563012Sdes */
8637535Sdes#define MGA_UPLOAD_CONTEXT	0x1
8763012Sdes#define MGA_UPLOAD_TEX0		0x2
8863012Sdes#define MGA_UPLOAD_TEX1		0x4
8963012Sdes#define MGA_UPLOAD_PIPE		0x8
9063012Sdes#define MGA_UPLOAD_TEX0IMAGE	0x10 /* handled client-side */
9163012Sdes#define MGA_UPLOAD_TEX1IMAGE	0x20 /* handled client-side */
9263012Sdes#define MGA_UPLOAD_2D		0x40
9363012Sdes#define MGA_WAIT_AGE		0x80 /* handled client-side */
9463012Sdes#define MGA_UPLOAD_CLIPRECTS	0x100 /* handled client-side */
9563012Sdes#if 0
9660196Sdes#define MGA_DMA_FLUSH		0x200 /* set when someone gets the lock
9763012Sdes					 quiescent */
9863012Sdes#endif
9963012Sdes
10063012Sdes/* 32 buffers of 64k each, total 2 meg.
10163012Sdes */
10263012Sdes#define MGA_BUFFER_SIZE		(1 << 16)
10363012Sdes#define MGA_NUM_BUFFERS		128
10463012Sdes
10563012Sdes/* Keep these small for testing.
10663012Sdes */
10737535Sdes#define MGA_NR_SAREA_CLIPRECTS	8
10837535Sdes
10963012Sdes/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
11063012Sdes * regions, subject to a minimum region size of (1<<16) == 64k.
11163012Sdes *
11263012Sdes * Clients may subdivide regions internally, but when sharing between
11363012Sdes * clients, the region size is the minimum granularity.
11463012Sdes */
11563012Sdes
11663012Sdes#define MGA_CARD_HEAP			0
11763281Sdes#define MGA_AGP_HEAP			1
11863012Sdes#define MGA_NR_TEX_HEAPS		2
11963012Sdes#define MGA_NR_TEX_REGIONS		16
12037535Sdes#define MGA_LOG_MIN_TEX_REGION_SIZE	16
12137535Sdes
12237608Sdes#define  DRM_MGA_IDLE_RETRY          2048
12363012Sdes
12437608Sdes#endif /* __MGA_SAREA_DEFINES__ */
12537608Sdes
12663012Sdes
12737608Sdes/* Setup registers for 3D context
12863012Sdes */
12937608Sdestypedef struct {
13063012Sdes	unsigned int dstorg;
13163012Sdes	unsigned int maccess;
13263012Sdes	unsigned int plnwt;
13363012Sdes	unsigned int dwgctl;
13463012Sdes	unsigned int alphactrl;
13563012Sdes	unsigned int fogcolor;
13663012Sdes	unsigned int wflag;
13763012Sdes	unsigned int tdualstage0;
13863012Sdes	unsigned int tdualstage1;
13963012Sdes	unsigned int fcol;
14063012Sdes	unsigned int stencil;
14163012Sdes	unsigned int stencilctl;
14263012Sdes} drm_mga_context_regs_t;
14363012Sdes
14463281Sdes/* Setup registers for 2D, X server
14563012Sdes */
14663012Sdestypedef struct {
14763012Sdes	unsigned int pitch;
14863012Sdes} drm_mga_server_regs_t;
14963012Sdes
15063012Sdes/* Setup registers for each texture unit
15163012Sdes */
15263012Sdestypedef struct {
15363012Sdes	unsigned int texctl;
15463012Sdes	unsigned int texctl2;
15537608Sdes	unsigned int texfilter;
15637608Sdes	unsigned int texbordercol;
15737608Sdes	unsigned int texorg;
15837608Sdes	unsigned int texwidth;
15937608Sdes	unsigned int texheight;
16063012Sdes	unsigned int texorg1;
16137535Sdes	unsigned int texorg2;
16237535Sdes	unsigned int texorg3;
16363012Sdes	unsigned int texorg4;
16463012Sdes} drm_mga_texture_regs_t;
16537535Sdes
16663012Sdes/* General aging mechanism
16763012Sdes */
16863012Sdestypedef struct {
16963012Sdes	unsigned int head;		/* Position of head pointer          */
17063012Sdes	unsigned int wrap;		/* Primary DMA wrap count            */
17163012Sdes} drm_mga_age_t;
17263012Sdes
17363012Sdestypedef struct _drm_mga_sarea {
17463012Sdes	/* The channel for communication of state information to the kernel
17563012Sdes	 * on firing a vertex dma buffer.
17637535Sdes	 */
17737535Sdes   	drm_mga_context_regs_t context_state;
17863012Sdes   	drm_mga_server_regs_t server_state;
17963012Sdes   	drm_mga_texture_regs_t tex_state[2];
18063012Sdes   	unsigned int warp_pipe;
18163012Sdes   	unsigned int dirty;
18263012Sdes   	unsigned int vertsize;
18363012Sdes
18463012Sdes	/* The current cliprects, or a subset thereof.
18563012Sdes	 */
18663012Sdes   	drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
18763012Sdes   	unsigned int nbox;
18863012Sdes
18963012Sdes	/* Information about the most recently used 3d drawable.  The
19063012Sdes	 * client fills in the req_* fields, the server fills in the
19163012Sdes	 * exported_ fields and puts the cliprects into boxes, above.
19263012Sdes	 *
19363012Sdes	 * The client clears the exported_drawable field before
19463012Sdes	 * clobbering the boxes data.
19563012Sdes	 */
19663012Sdes        unsigned int req_drawable;	 /* the X drawable id */
19763012Sdes	unsigned int req_draw_buffer;	 /* MGA_FRONT or MGA_BACK */
19863012Sdes
19963012Sdes        unsigned int exported_drawable;
20037535Sdes	unsigned int exported_index;
20137535Sdes        unsigned int exported_stamp;
20237608Sdes        unsigned int exported_buffers;
20337608Sdes        unsigned int exported_nfront;
20437608Sdes        unsigned int exported_nback;
20537535Sdes	int exported_back_x, exported_front_x, exported_w;
20663012Sdes	int exported_back_y, exported_front_y, exported_h;
20737535Sdes   	drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
20863012Sdes
20963012Sdes	/* Counters for aging textures and for client-side throttling.
21063012Sdes	 */
21163012Sdes	unsigned int status[4];
21263012Sdes	unsigned int last_wrap;
21363012Sdes
21463012Sdes	drm_mga_age_t last_frame;
21563012Sdes        unsigned int last_enqueue;	/* last time a buffer was enqueued */
21663012Sdes	unsigned int last_dispatch;	/* age of the most recently dispatched buffer */
21737535Sdes	unsigned int last_quiescent;     /*  */
21863012Sdes
21963012Sdes	/* LRU lists for texture memory in agp space and on the card.
22037535Sdes	 */
22163012Sdes	drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1];
22263012Sdes	unsigned int texAge[MGA_NR_TEX_HEAPS];
22363012Sdes
22463012Sdes	/* Mechanism to validate card state.
22563012Sdes	 */
22663012Sdes   	int ctxOwner;
22737535Sdes} drm_mga_sarea_t;
22863012Sdes
22937535Sdes
23063012Sdes/* WARNING: If you change any of these defines, make sure to change the
23137535Sdes * defines in the Xserver file (xf86drmMga.h)
23237535Sdes */
23337608Sdes
23437608Sdes/* MGA specific ioctls
23537608Sdes * The device specific ioctl range is 0x40 to 0x79.
23637535Sdes */
23763012Sdes#define DRM_MGA_INIT     0x00
23837535Sdes#define DRM_MGA_FLUSH    0x01
23963012Sdes#define DRM_MGA_RESET    0x02
24063012Sdes#define DRM_MGA_SWAP     0x03
24163012Sdes#define DRM_MGA_CLEAR    0x04
24237535Sdes#define DRM_MGA_VERTEX   0x05
24337535Sdes#define DRM_MGA_INDICES  0x06
24437608Sdes#define DRM_MGA_ILOAD    0x07
24537608Sdes#define DRM_MGA_BLIT     0x08
24637608Sdes#define DRM_MGA_GETPARAM 0x09
24737535Sdes
24863012Sdes#define DRM_IOCTL_MGA_INIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
24937535Sdes#define DRM_IOCTL_MGA_FLUSH    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t)
25063012Sdes#define DRM_IOCTL_MGA_RESET    DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_RESET)
25163012Sdes#define DRM_IOCTL_MGA_SWAP     DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_SWAP)
25263012Sdes#define DRM_IOCTL_MGA_CLEAR    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
25363012Sdes#define DRM_IOCTL_MGA_VERTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
25463012Sdes#define DRM_IOCTL_MGA_INDICES  DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
25563012Sdes#define DRM_IOCTL_MGA_ILOAD    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
25637535Sdes#define DRM_IOCTL_MGA_BLIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
25763012Sdes#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
25837535Sdes
25937535Sdestypedef struct _drm_mga_warp_index {
26037608Sdes   	int installed;
26163012Sdes   	unsigned long phys_addr;
26237608Sdes   	int size;
26363012Sdes} drm_mga_warp_index_t;
26463012Sdes
26537535Sdestypedef struct drm_mga_init {
26663012Sdes   	enum {
26763012Sdes	   	MGA_INIT_DMA    = 0x01,
26863012Sdes	       	MGA_CLEANUP_DMA = 0x02
26963012Sdes	} func;
27063012Sdes
27163012Sdes   	unsigned long sarea_priv_offset;
27263012Sdes
27363012Sdes	int chipset;
27463012Sdes   	int sgram;
27563012Sdes
27663012Sdes	unsigned int maccess;
27763012Sdes
27863012Sdes   	unsigned int fb_cpp;
27963012Sdes	unsigned int front_offset, front_pitch;
28063012Sdes   	unsigned int back_offset, back_pitch;
28163012Sdes
28263012Sdes   	unsigned int depth_cpp;
28363012Sdes   	unsigned int depth_offset, depth_pitch;
28463012Sdes
28563012Sdes   	unsigned int texture_offset[MGA_NR_TEX_HEAPS];
28663012Sdes   	unsigned int texture_size[MGA_NR_TEX_HEAPS];
28763012Sdes
28863012Sdes	unsigned long fb_offset;
28963012Sdes	unsigned long mmio_offset;
29063012Sdes	unsigned long status_offset;
29163012Sdes	unsigned long warp_offset;
29263012Sdes	unsigned long primary_offset;
29363012Sdes	unsigned long buffers_offset;
29463012Sdes} drm_mga_init_t;
29563012Sdes
29663012Sdestypedef struct drm_mga_fullscreen {
29763012Sdes	enum {
29863012Sdes		MGA_INIT_FULLSCREEN    = 0x01,
29963012Sdes		MGA_CLEANUP_FULLSCREEN = 0x02
30063012Sdes	} func;
30163012Sdes} drm_mga_fullscreen_t;
30263012Sdes
30363012Sdestypedef struct drm_mga_clear {
30463012Sdes	unsigned int flags;
30563012Sdes	unsigned int clear_color;
30663012Sdes	unsigned int clear_depth;
30763012Sdes	unsigned int color_mask;
30863012Sdes	unsigned int depth_mask;
30963012Sdes} drm_mga_clear_t;
31063012Sdes
31163012Sdestypedef struct drm_mga_vertex {
31263012Sdes   	int idx;			/* buffer to queue */
31363012Sdes	int used;			/* bytes in use */
31463012Sdes	int discard;			/* client finished with buffer?  */
31563012Sdes} drm_mga_vertex_t;
31663012Sdes
31763012Sdestypedef struct drm_mga_indices {
31863012Sdes   	int idx;			/* buffer to queue */
31963012Sdes	unsigned int start;
32063012Sdes	unsigned int end;
32163012Sdes	int discard;			/* client finished with buffer?  */
32263012Sdes} drm_mga_indices_t;
32363012Sdes
32463012Sdestypedef struct drm_mga_iload {
32563012Sdes	int idx;
32663012Sdes	unsigned int dstorg;
32763012Sdes	unsigned int length;
32863012Sdes} drm_mga_iload_t;
32963012Sdes
33063012Sdestypedef struct _drm_mga_blit {
33163012Sdes	unsigned int planemask;
33263012Sdes	unsigned int srcorg;
33363012Sdes	unsigned int dstorg;
33463012Sdes	int src_pitch, dst_pitch;
33563012Sdes	int delta_sx, delta_sy;
33663012Sdes	int delta_dx, delta_dy;
33763012Sdes	int height, ydir;		/* flip image vertically */
33863012Sdes	int source_pitch, dest_pitch;
33963012Sdes} drm_mga_blit_t;
34063012Sdes
34163012Sdes/* 3.1: An ioctl to get parameters that aren't available to the 3d
34263012Sdes * client any other way.
34363012Sdes */
34463012Sdes#define MGA_PARAM_IRQ_NR            1
34563012Sdes
34663012Sdestypedef struct drm_mga_getparam {
34763012Sdes	int param;
34863012Sdes	void *value;
34963012Sdes} drm_mga_getparam_t;
35063012Sdes
35163012Sdes#endif
35263012Sdes