mga_drm.h revision 112015
195584Sanholt/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
295584Sanholt * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
395584Sanholt *
495584Sanholt * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
595584Sanholt * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
695584Sanholt * All rights reserved.
795584Sanholt *
895584Sanholt * Permission is hereby granted, free of charge, to any person obtaining a
995584Sanholt * copy of this software and associated documentation files (the "Software"),
1095584Sanholt * to deal in the Software without restriction, including without limitation
1195584Sanholt * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1295584Sanholt * and/or sell copies of the Software, and to permit persons to whom the
1395584Sanholt * Software is furnished to do so, subject to the following conditions:
1495584Sanholt *
1595584Sanholt * The above copyright notice and this permission notice (including the next
1695584Sanholt * paragraph) shall be included in all copies or substantial portions of the
1795584Sanholt * Software.
1895584Sanholt *
1995584Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
2095584Sanholt * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2195584Sanholt * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
2295584Sanholt * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
2395584Sanholt * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
2495584Sanholt * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2595584Sanholt * OTHER DEALINGS IN THE SOFTWARE.
2695584Sanholt *
2795584Sanholt * Authors:
2895584Sanholt *    Jeff Hartmann <jhartmann@valinux.com>
29112015Sanholt *    Keith Whitwell <keith@tungstengraphics.com>
3095584Sanholt *
3195584Sanholt * Rewritten by:
3295584Sanholt *    Gareth Hughes <gareth@valinux.com>
3395584Sanholt *
3495584Sanholt * $FreeBSD: head/sys/dev/drm/mga_drm.h 112015 2003-03-09 02:08:30Z anholt $
3595584Sanholt */
3695584Sanholt
3795584Sanholt#ifndef __MGA_DRM_H__
3895584Sanholt#define __MGA_DRM_H__
3995584Sanholt
4095584Sanholt/* WARNING: If you change any of these defines, make sure to change the
4195584Sanholt * defines in the Xserver file (mga_sarea.h)
4295584Sanholt */
43112015Sanholt
4495584Sanholt#ifndef __MGA_SAREA_DEFINES__
4595584Sanholt#define __MGA_SAREA_DEFINES__
4695584Sanholt
4795584Sanholt/* WARP pipe flags
4895584Sanholt */
4995584Sanholt#define MGA_F			0x1		/* fog */
5095584Sanholt#define MGA_A			0x2		/* alpha */
5195584Sanholt#define MGA_S			0x4		/* specular */
5295584Sanholt#define MGA_T2			0x8		/* multitexture */
5395584Sanholt
5495584Sanholt#define MGA_WARP_TGZ		0
5595584Sanholt#define MGA_WARP_TGZF		(MGA_F)
5695584Sanholt#define MGA_WARP_TGZA		(MGA_A)
5795584Sanholt#define MGA_WARP_TGZAF		(MGA_F|MGA_A)
5895584Sanholt#define MGA_WARP_TGZS		(MGA_S)
5995584Sanholt#define MGA_WARP_TGZSF		(MGA_S|MGA_F)
6095584Sanholt#define MGA_WARP_TGZSA		(MGA_S|MGA_A)
6195584Sanholt#define MGA_WARP_TGZSAF		(MGA_S|MGA_F|MGA_A)
6295584Sanholt#define MGA_WARP_T2GZ		(MGA_T2)
6395584Sanholt#define MGA_WARP_T2GZF		(MGA_T2|MGA_F)
6495584Sanholt#define MGA_WARP_T2GZA		(MGA_T2|MGA_A)
6595584Sanholt#define MGA_WARP_T2GZAF		(MGA_T2|MGA_A|MGA_F)
6695584Sanholt#define MGA_WARP_T2GZS		(MGA_T2|MGA_S)
6795584Sanholt#define MGA_WARP_T2GZSF		(MGA_T2|MGA_S|MGA_F)
6895584Sanholt#define MGA_WARP_T2GZSA		(MGA_T2|MGA_S|MGA_A)
6995584Sanholt#define MGA_WARP_T2GZSAF	(MGA_T2|MGA_S|MGA_F|MGA_A)
7095584Sanholt
7195584Sanholt#define MGA_MAX_G200_PIPES	8		/* no multitex */
7295584Sanholt#define MGA_MAX_G400_PIPES	16
7395584Sanholt#define MGA_MAX_WARP_PIPES	MGA_MAX_G400_PIPES
7495584Sanholt#define MGA_WARP_UCODE_SIZE	32768		/* in bytes */
7595584Sanholt
7695584Sanholt#define MGA_CARD_TYPE_G200	1
7795584Sanholt#define MGA_CARD_TYPE_G400	2
7895584Sanholt
7995584Sanholt
8095584Sanholt#define MGA_FRONT		0x1
8195584Sanholt#define MGA_BACK		0x2
8295584Sanholt#define MGA_DEPTH		0x4
8395584Sanholt
8495584Sanholt/* What needs to be changed for the current vertex dma buffer?
8595584Sanholt */
8695584Sanholt#define MGA_UPLOAD_CONTEXT	0x1
8795584Sanholt#define MGA_UPLOAD_TEX0		0x2
8895584Sanholt#define MGA_UPLOAD_TEX1		0x4
8995584Sanholt#define MGA_UPLOAD_PIPE		0x8
9095584Sanholt#define MGA_UPLOAD_TEX0IMAGE	0x10 /* handled client-side */
9195584Sanholt#define MGA_UPLOAD_TEX1IMAGE	0x20 /* handled client-side */
9295584Sanholt#define MGA_UPLOAD_2D		0x40
9395584Sanholt#define MGA_WAIT_AGE		0x80 /* handled client-side */
9495584Sanholt#define MGA_UPLOAD_CLIPRECTS	0x100 /* handled client-side */
9595584Sanholt#if 0
9695584Sanholt#define MGA_DMA_FLUSH		0x200 /* set when someone gets the lock
9795584Sanholt					 quiescent */
9895584Sanholt#endif
9995584Sanholt
10095584Sanholt/* 32 buffers of 64k each, total 2 meg.
10195584Sanholt */
10295584Sanholt#define MGA_BUFFER_SIZE		(1 << 16)
10395584Sanholt#define MGA_NUM_BUFFERS		128
10495584Sanholt
10595584Sanholt/* Keep these small for testing.
10695584Sanholt */
10795584Sanholt#define MGA_NR_SAREA_CLIPRECTS	8
10895584Sanholt
10995584Sanholt/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
11095584Sanholt * regions, subject to a minimum region size of (1<<16) == 64k.
11195584Sanholt *
11295584Sanholt * Clients may subdivide regions internally, but when sharing between
11395584Sanholt * clients, the region size is the minimum granularity.
11495584Sanholt */
11595584Sanholt
11695584Sanholt#define MGA_CARD_HEAP			0
11795584Sanholt#define MGA_AGP_HEAP			1
11895584Sanholt#define MGA_NR_TEX_HEAPS		2
11995584Sanholt#define MGA_NR_TEX_REGIONS		16
12095584Sanholt#define MGA_LOG_MIN_TEX_REGION_SIZE	16
12195584Sanholt
12295584Sanholt#endif /* __MGA_SAREA_DEFINES__ */
12395584Sanholt
12495584Sanholt
12595584Sanholt/* Setup registers for 3D context
12695584Sanholt */
12795584Sanholttypedef struct {
12895584Sanholt	unsigned int dstorg;
12995584Sanholt	unsigned int maccess;
13095584Sanholt	unsigned int plnwt;
13195584Sanholt	unsigned int dwgctl;
13295584Sanholt	unsigned int alphactrl;
13395584Sanholt	unsigned int fogcolor;
13495584Sanholt	unsigned int wflag;
13595584Sanholt	unsigned int tdualstage0;
13695584Sanholt	unsigned int tdualstage1;
13795584Sanholt	unsigned int fcol;
13895584Sanholt	unsigned int stencil;
13995584Sanholt	unsigned int stencilctl;
14095584Sanholt} drm_mga_context_regs_t;
14195584Sanholt
14295584Sanholt/* Setup registers for 2D, X server
14395584Sanholt */
14495584Sanholttypedef struct {
14595584Sanholt	unsigned int pitch;
14695584Sanholt} drm_mga_server_regs_t;
14795584Sanholt
14895584Sanholt/* Setup registers for each texture unit
14995584Sanholt */
15095584Sanholttypedef struct {
15195584Sanholt	unsigned int texctl;
15295584Sanholt	unsigned int texctl2;
15395584Sanholt	unsigned int texfilter;
15495584Sanholt	unsigned int texbordercol;
15595584Sanholt	unsigned int texorg;
15695584Sanholt	unsigned int texwidth;
15795584Sanholt	unsigned int texheight;
15895584Sanholt	unsigned int texorg1;
15995584Sanholt	unsigned int texorg2;
16095584Sanholt	unsigned int texorg3;
16195584Sanholt	unsigned int texorg4;
16295584Sanholt} drm_mga_texture_regs_t;
16395584Sanholt
16495584Sanholt/* General aging mechanism
16595584Sanholt */
16695584Sanholttypedef struct {
16795584Sanholt	unsigned int head;		/* Position of head pointer          */
16895584Sanholt	unsigned int wrap;		/* Primary DMA wrap count            */
16995584Sanholt} drm_mga_age_t;
17095584Sanholt
17195584Sanholttypedef struct _drm_mga_sarea {
17295584Sanholt	/* The channel for communication of state information to the kernel
17395584Sanholt	 * on firing a vertex dma buffer.
17495584Sanholt	 */
17595584Sanholt   	drm_mga_context_regs_t context_state;
17695584Sanholt   	drm_mga_server_regs_t server_state;
17795584Sanholt   	drm_mga_texture_regs_t tex_state[2];
17895584Sanholt   	unsigned int warp_pipe;
17995584Sanholt   	unsigned int dirty;
18095584Sanholt   	unsigned int vertsize;
18195584Sanholt
18295584Sanholt	/* The current cliprects, or a subset thereof.
18395584Sanholt	 */
18495584Sanholt   	drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
18595584Sanholt   	unsigned int nbox;
18695584Sanholt
18795584Sanholt	/* Information about the most recently used 3d drawable.  The
18895584Sanholt	 * client fills in the req_* fields, the server fills in the
18995584Sanholt	 * exported_ fields and puts the cliprects into boxes, above.
19095584Sanholt	 *
19195584Sanholt	 * The client clears the exported_drawable field before
19295584Sanholt	 * clobbering the boxes data.
19395584Sanholt	 */
19495584Sanholt        unsigned int req_drawable;	 /* the X drawable id */
19595584Sanholt	unsigned int req_draw_buffer;	 /* MGA_FRONT or MGA_BACK */
19695584Sanholt
19795584Sanholt        unsigned int exported_drawable;
19895584Sanholt	unsigned int exported_index;
19995584Sanholt        unsigned int exported_stamp;
20095584Sanholt        unsigned int exported_buffers;
20195584Sanholt        unsigned int exported_nfront;
20295584Sanholt        unsigned int exported_nback;
20395584Sanholt	int exported_back_x, exported_front_x, exported_w;
20495584Sanholt	int exported_back_y, exported_front_y, exported_h;
20595584Sanholt   	drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
20695584Sanholt
20795584Sanholt	/* Counters for aging textures and for client-side throttling.
20895584Sanholt	 */
20995584Sanholt	unsigned int status[4];
21095584Sanholt	unsigned int last_wrap;
21195584Sanholt
21295584Sanholt	drm_mga_age_t last_frame;
21395584Sanholt        unsigned int last_enqueue;	/* last time a buffer was enqueued */
21495584Sanholt	unsigned int last_dispatch;	/* age of the most recently dispatched buffer */
21595584Sanholt	unsigned int last_quiescent;     /*  */
21695584Sanholt
21795584Sanholt	/* LRU lists for texture memory in agp space and on the card.
21895584Sanholt	 */
21995584Sanholt	drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1];
22095584Sanholt	unsigned int texAge[MGA_NR_TEX_HEAPS];
22195584Sanholt
22295584Sanholt	/* Mechanism to validate card state.
22395584Sanholt	 */
22495584Sanholt   	int ctxOwner;
22595584Sanholt} drm_mga_sarea_t;
22695584Sanholt
227112015Sanholt
228112015Sanholt/* WARNING: If you change any of these defines, make sure to change the
229112015Sanholt * defines in the Xserver file (xf86drmMga.h)
230112015Sanholt */
231112015Sanholt
232112015Sanholt/* MGA specific ioctls
233112015Sanholt * The device specific ioctl range is 0x40 to 0x79.
234112015Sanholt */
23595746Sanholt#define DRM_IOCTL_MGA_INIT		DRM_IOW( 0x40, drm_mga_init_t)
23695746Sanholt#define DRM_IOCTL_MGA_FLUSH		DRM_IOW( 0x41, drm_lock_t)
23795746Sanholt#define DRM_IOCTL_MGA_RESET		DRM_IO(  0x42)
23895746Sanholt#define DRM_IOCTL_MGA_SWAP		DRM_IO(  0x43)
23995746Sanholt#define DRM_IOCTL_MGA_CLEAR		DRM_IOW( 0x44, drm_mga_clear_t)
24095746Sanholt#define DRM_IOCTL_MGA_VERTEX		DRM_IOW( 0x45, drm_mga_vertex_t)
24195746Sanholt#define DRM_IOCTL_MGA_INDICES		DRM_IOW( 0x46, drm_mga_indices_t)
24295746Sanholt#define DRM_IOCTL_MGA_ILOAD		DRM_IOW( 0x47, drm_mga_iload_t)
24395746Sanholt#define DRM_IOCTL_MGA_BLIT		DRM_IOW( 0x48, drm_mga_blit_t)
244112015Sanholt#define DRM_IOCTL_MGA_GETPARAM		DRM_IOWR(0x49, drm_mga_getparam_t)
24595584Sanholt
24695584Sanholttypedef struct _drm_mga_warp_index {
24795584Sanholt   	int installed;
24895584Sanholt   	unsigned long phys_addr;
24995584Sanholt   	int size;
25095584Sanholt} drm_mga_warp_index_t;
25195584Sanholt
25295584Sanholttypedef struct drm_mga_init {
25395584Sanholt   	enum {
25495584Sanholt	   	MGA_INIT_DMA    = 0x01,
25595584Sanholt	       	MGA_CLEANUP_DMA = 0x02
25695584Sanholt	} func;
25795584Sanholt
25895584Sanholt   	unsigned long sarea_priv_offset;
25995584Sanholt
26095584Sanholt	int chipset;
26195584Sanholt   	int sgram;
26295584Sanholt
26395584Sanholt	unsigned int maccess;
26495584Sanholt
26595584Sanholt   	unsigned int fb_cpp;
26695584Sanholt	unsigned int front_offset, front_pitch;
26795584Sanholt   	unsigned int back_offset, back_pitch;
26895584Sanholt
26995584Sanholt   	unsigned int depth_cpp;
27095584Sanholt   	unsigned int depth_offset, depth_pitch;
27195584Sanholt
27295584Sanholt   	unsigned int texture_offset[MGA_NR_TEX_HEAPS];
27395584Sanholt   	unsigned int texture_size[MGA_NR_TEX_HEAPS];
27495584Sanholt
27595584Sanholt	unsigned long fb_offset;
27695584Sanholt	unsigned long mmio_offset;
27795584Sanholt	unsigned long status_offset;
27895584Sanholt	unsigned long warp_offset;
27995584Sanholt	unsigned long primary_offset;
28095584Sanholt	unsigned long buffers_offset;
28195584Sanholt} drm_mga_init_t;
28295584Sanholt
28395584Sanholttypedef struct drm_mga_fullscreen {
28495584Sanholt	enum {
28595584Sanholt		MGA_INIT_FULLSCREEN    = 0x01,
28695584Sanholt		MGA_CLEANUP_FULLSCREEN = 0x02
28795584Sanholt	} func;
28895584Sanholt} drm_mga_fullscreen_t;
28995584Sanholt
29095584Sanholttypedef struct drm_mga_clear {
29195584Sanholt	unsigned int flags;
29295584Sanholt	unsigned int clear_color;
29395584Sanholt	unsigned int clear_depth;
29495584Sanholt	unsigned int color_mask;
29595584Sanholt	unsigned int depth_mask;
29695584Sanholt} drm_mga_clear_t;
29795584Sanholt
29895584Sanholttypedef struct drm_mga_vertex {
29995584Sanholt   	int idx;			/* buffer to queue */
30095584Sanholt	int used;			/* bytes in use */
30195584Sanholt	int discard;			/* client finished with buffer?  */
30295584Sanholt} drm_mga_vertex_t;
30395584Sanholt
30495584Sanholttypedef struct drm_mga_indices {
30595584Sanholt   	int idx;			/* buffer to queue */
30695584Sanholt	unsigned int start;
30795584Sanholt	unsigned int end;
30895584Sanholt	int discard;			/* client finished with buffer?  */
30995584Sanholt} drm_mga_indices_t;
31095584Sanholt
31195584Sanholttypedef struct drm_mga_iload {
31295584Sanholt	int idx;
31395584Sanholt	unsigned int dstorg;
31495584Sanholt	unsigned int length;
31595584Sanholt} drm_mga_iload_t;
31695584Sanholt
31795584Sanholttypedef struct _drm_mga_blit {
31895584Sanholt	unsigned int planemask;
31995584Sanholt	unsigned int srcorg;
32095584Sanholt	unsigned int dstorg;
32195584Sanholt	int src_pitch, dst_pitch;
32295584Sanholt	int delta_sx, delta_sy;
32395584Sanholt	int delta_dx, delta_dy;
32495584Sanholt	int height, ydir;		/* flip image vertically */
32595584Sanholt	int source_pitch, dest_pitch;
32695584Sanholt} drm_mga_blit_t;
32795584Sanholt
328112015Sanholt/* 3.1: An ioctl to get parameters that aren't available to the 3d
329112015Sanholt * client any other way.
330112015Sanholt */
331112015Sanholt#define MGA_PARAM_IRQ_NR            1
332112015Sanholt
333112015Sanholttypedef struct drm_mga_getparam {
334112015Sanholt	int param;
335112015Sanholt	int *value;
336112015Sanholt} drm_mga_getparam_t;
337112015Sanholt
33895584Sanholt#endif
339