195584Sanholt/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*- 2152909Sanholt * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com 3152909Sanholt * 495584Sanholt * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 595584Sanholt * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 695584Sanholt * All rights reserved. 795584Sanholt * 895584Sanholt * Permission is hereby granted, free of charge, to any person obtaining a 995584Sanholt * copy of this software and associated documentation files (the "Software"), 1095584Sanholt * to deal in the Software without restriction, including without limitation 1195584Sanholt * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1295584Sanholt * and/or sell copies of the Software, and to permit persons to whom the 1395584Sanholt * Software is furnished to do so, subject to the following conditions: 1495584Sanholt * 1595584Sanholt * The above copyright notice and this permission notice (including the next 1695584Sanholt * paragraph) shall be included in all copies or substantial portions of the 1795584Sanholt * Software. 1895584Sanholt * 1995584Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 2095584Sanholt * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2195584Sanholt * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2295584Sanholt * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 2395584Sanholt * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2495584Sanholt * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2595584Sanholt * OTHER DEALINGS IN THE SOFTWARE. 2695584Sanholt * 2795584Sanholt * Authors: 2895584Sanholt * Jeff Hartmann <jhartmann@valinux.com> 29112015Sanholt * Keith Whitwell <keith@tungstengraphics.com> 3095584Sanholt * 3195584Sanholt * Rewritten by: 3295584Sanholt * Gareth Hughes <gareth@valinux.com> 3395584Sanholt */ 3495584Sanholt 35152909Sanholt#include <sys/cdefs.h> 36152909Sanholt__FBSDID("$FreeBSD$"); 37152909Sanholt 3895584Sanholt#ifndef __MGA_DRM_H__ 3995584Sanholt#define __MGA_DRM_H__ 4095584Sanholt 4195584Sanholt/* WARNING: If you change any of these defines, make sure to change the 4295584Sanholt * defines in the Xserver file (mga_sarea.h) 4395584Sanholt */ 44112015Sanholt 4595584Sanholt#ifndef __MGA_SAREA_DEFINES__ 4695584Sanholt#define __MGA_SAREA_DEFINES__ 4795584Sanholt 4895584Sanholt/* WARP pipe flags 4995584Sanholt */ 50145132Sanholt#define MGA_F 0x1 /* fog */ 51145132Sanholt#define MGA_A 0x2 /* alpha */ 52145132Sanholt#define MGA_S 0x4 /* specular */ 53145132Sanholt#define MGA_T2 0x8 /* multitexture */ 5495584Sanholt 5595584Sanholt#define MGA_WARP_TGZ 0 5695584Sanholt#define MGA_WARP_TGZF (MGA_F) 5795584Sanholt#define MGA_WARP_TGZA (MGA_A) 5895584Sanholt#define MGA_WARP_TGZAF (MGA_F|MGA_A) 5995584Sanholt#define MGA_WARP_TGZS (MGA_S) 6095584Sanholt#define MGA_WARP_TGZSF (MGA_S|MGA_F) 6195584Sanholt#define MGA_WARP_TGZSA (MGA_S|MGA_A) 6295584Sanholt#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A) 6395584Sanholt#define MGA_WARP_T2GZ (MGA_T2) 6495584Sanholt#define MGA_WARP_T2GZF (MGA_T2|MGA_F) 6595584Sanholt#define MGA_WARP_T2GZA (MGA_T2|MGA_A) 6695584Sanholt#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F) 6795584Sanholt#define MGA_WARP_T2GZS (MGA_T2|MGA_S) 6895584Sanholt#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F) 6995584Sanholt#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) 7095584Sanholt#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) 7195584Sanholt 72145132Sanholt#define MGA_MAX_G200_PIPES 8 /* no multitex */ 7395584Sanholt#define MGA_MAX_G400_PIPES 16 7495584Sanholt#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES 75145132Sanholt#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ 7695584Sanholt 7795584Sanholt#define MGA_CARD_TYPE_G200 1 7895584Sanholt#define MGA_CARD_TYPE_G400 2 79152909Sanholt#define MGA_CARD_TYPE_G450 3 /* not currently used */ 80152909Sanholt#define MGA_CARD_TYPE_G550 4 8195584Sanholt 8295584Sanholt#define MGA_FRONT 0x1 8395584Sanholt#define MGA_BACK 0x2 8495584Sanholt#define MGA_DEPTH 0x4 8595584Sanholt 8695584Sanholt/* What needs to be changed for the current vertex dma buffer? 8795584Sanholt */ 8895584Sanholt#define MGA_UPLOAD_CONTEXT 0x1 8995584Sanholt#define MGA_UPLOAD_TEX0 0x2 9095584Sanholt#define MGA_UPLOAD_TEX1 0x4 9195584Sanholt#define MGA_UPLOAD_PIPE 0x8 92145132Sanholt#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ 93145132Sanholt#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ 9495584Sanholt#define MGA_UPLOAD_2D 0x40 95145132Sanholt#define MGA_WAIT_AGE 0x80 /* handled client-side */ 96145132Sanholt#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ 9795584Sanholt#if 0 98145132Sanholt#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock 99145132Sanholt quiescent */ 10095584Sanholt#endif 10195584Sanholt 10295584Sanholt/* 32 buffers of 64k each, total 2 meg. 10395584Sanholt */ 10495584Sanholt#define MGA_BUFFER_SIZE (1 << 16) 10595584Sanholt#define MGA_NUM_BUFFERS 128 10695584Sanholt 10795584Sanholt/* Keep these small for testing. 10895584Sanholt */ 10995584Sanholt#define MGA_NR_SAREA_CLIPRECTS 8 11095584Sanholt 111298955Spfg/* 2 heaps (1 for card, 1 for agp), each divided into up to 128 11295584Sanholt * regions, subject to a minimum region size of (1<<16) == 64k. 11395584Sanholt * 11495584Sanholt * Clients may subdivide regions internally, but when sharing between 11595584Sanholt * clients, the region size is the minimum granularity. 11695584Sanholt */ 11795584Sanholt 11895584Sanholt#define MGA_CARD_HEAP 0 11995584Sanholt#define MGA_AGP_HEAP 1 12095584Sanholt#define MGA_NR_TEX_HEAPS 2 12195584Sanholt#define MGA_NR_TEX_REGIONS 16 12295584Sanholt#define MGA_LOG_MIN_TEX_REGION_SIZE 16 12395584Sanholt 124130331Sanholt#define DRM_MGA_IDLE_RETRY 2048 125130331Sanholt 126145132Sanholt#endif /* __MGA_SAREA_DEFINES__ */ 12795584Sanholt 12895584Sanholt/* Setup registers for 3D context 12995584Sanholt */ 13095584Sanholttypedef struct { 13195584Sanholt unsigned int dstorg; 13295584Sanholt unsigned int maccess; 13395584Sanholt unsigned int plnwt; 13495584Sanholt unsigned int dwgctl; 13595584Sanholt unsigned int alphactrl; 13695584Sanholt unsigned int fogcolor; 13795584Sanholt unsigned int wflag; 13895584Sanholt unsigned int tdualstage0; 13995584Sanholt unsigned int tdualstage1; 14095584Sanholt unsigned int fcol; 14195584Sanholt unsigned int stencil; 14295584Sanholt unsigned int stencilctl; 14395584Sanholt} drm_mga_context_regs_t; 14495584Sanholt 14595584Sanholt/* Setup registers for 2D, X server 14695584Sanholt */ 14795584Sanholttypedef struct { 14895584Sanholt unsigned int pitch; 14995584Sanholt} drm_mga_server_regs_t; 15095584Sanholt 15195584Sanholt/* Setup registers for each texture unit 15295584Sanholt */ 15395584Sanholttypedef struct { 15495584Sanholt unsigned int texctl; 15595584Sanholt unsigned int texctl2; 15695584Sanholt unsigned int texfilter; 15795584Sanholt unsigned int texbordercol; 15895584Sanholt unsigned int texorg; 15995584Sanholt unsigned int texwidth; 16095584Sanholt unsigned int texheight; 16195584Sanholt unsigned int texorg1; 16295584Sanholt unsigned int texorg2; 16395584Sanholt unsigned int texorg3; 16495584Sanholt unsigned int texorg4; 16595584Sanholt} drm_mga_texture_regs_t; 16695584Sanholt 16795584Sanholt/* General aging mechanism 16895584Sanholt */ 16995584Sanholttypedef struct { 170145132Sanholt unsigned int head; /* Position of head pointer */ 171145132Sanholt unsigned int wrap; /* Primary DMA wrap count */ 17295584Sanholt} drm_mga_age_t; 17395584Sanholt 17495584Sanholttypedef struct _drm_mga_sarea { 17595584Sanholt /* The channel for communication of state information to the kernel 17695584Sanholt * on firing a vertex dma buffer. 17795584Sanholt */ 178145132Sanholt drm_mga_context_regs_t context_state; 179145132Sanholt drm_mga_server_regs_t server_state; 180145132Sanholt drm_mga_texture_regs_t tex_state[2]; 181145132Sanholt unsigned int warp_pipe; 182145132Sanholt unsigned int dirty; 183145132Sanholt unsigned int vertsize; 18495584Sanholt 18595584Sanholt /* The current cliprects, or a subset thereof. 18695584Sanholt */ 187182080Srnoland struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS]; 188145132Sanholt unsigned int nbox; 18995584Sanholt 19095584Sanholt /* Information about the most recently used 3d drawable. The 19195584Sanholt * client fills in the req_* fields, the server fills in the 19295584Sanholt * exported_ fields and puts the cliprects into boxes, above. 19395584Sanholt * 19495584Sanholt * The client clears the exported_drawable field before 19595584Sanholt * clobbering the boxes data. 19695584Sanholt */ 197145132Sanholt unsigned int req_drawable; /* the X drawable id */ 198145132Sanholt unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ 19995584Sanholt 200145132Sanholt unsigned int exported_drawable; 20195584Sanholt unsigned int exported_index; 202145132Sanholt unsigned int exported_stamp; 203145132Sanholt unsigned int exported_buffers; 204145132Sanholt unsigned int exported_nfront; 205145132Sanholt unsigned int exported_nback; 20695584Sanholt int exported_back_x, exported_front_x, exported_w; 20795584Sanholt int exported_back_y, exported_front_y, exported_h; 208182080Srnoland struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS]; 20995584Sanholt 21095584Sanholt /* Counters for aging textures and for client-side throttling. 21195584Sanholt */ 21295584Sanholt unsigned int status[4]; 21395584Sanholt unsigned int last_wrap; 21495584Sanholt 21595584Sanholt drm_mga_age_t last_frame; 216145132Sanholt unsigned int last_enqueue; /* last time a buffer was enqueued */ 21795584Sanholt unsigned int last_dispatch; /* age of the most recently dispatched buffer */ 218145132Sanholt unsigned int last_quiescent; /* */ 21995584Sanholt 22095584Sanholt /* LRU lists for texture memory in agp space and on the card. 22195584Sanholt */ 222182080Srnoland struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; 22395584Sanholt unsigned int texAge[MGA_NR_TEX_HEAPS]; 22495584Sanholt 22595584Sanholt /* Mechanism to validate card state. 22695584Sanholt */ 227145132Sanholt int ctxOwner; 22895584Sanholt} drm_mga_sarea_t; 22995584Sanholt 230112015Sanholt 231112015Sanholt/* MGA specific ioctls 232112015Sanholt * The device specific ioctl range is 0x40 to 0x79. 233112015Sanholt */ 234130331Sanholt#define DRM_MGA_INIT 0x00 235130331Sanholt#define DRM_MGA_FLUSH 0x01 236130331Sanholt#define DRM_MGA_RESET 0x02 237130331Sanholt#define DRM_MGA_SWAP 0x03 238130331Sanholt#define DRM_MGA_CLEAR 0x04 239130331Sanholt#define DRM_MGA_VERTEX 0x05 240130331Sanholt#define DRM_MGA_INDICES 0x06 241130331Sanholt#define DRM_MGA_ILOAD 0x07 242130331Sanholt#define DRM_MGA_BLIT 0x08 243130331Sanholt#define DRM_MGA_GETPARAM 0x09 24495584Sanholt 245152909Sanholt/* 3.2: 246152909Sanholt * ioctls for operating on fences. 247152909Sanholt */ 248152909Sanholt#define DRM_MGA_SET_FENCE 0x0a 249152909Sanholt#define DRM_MGA_WAIT_FENCE 0x0b 250152909Sanholt#define DRM_MGA_DMA_BOOTSTRAP 0x0c 251152909Sanholt 252152909Sanholt 253130331Sanholt#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) 254130331Sanholt#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t) 255130331Sanholt#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) 256130331Sanholt#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP) 257130331Sanholt#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) 258130331Sanholt#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t) 259130331Sanholt#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t) 260130331Sanholt#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) 261130331Sanholt#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) 262130331Sanholt#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) 263152909Sanholt#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t) 264152909Sanholt#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t) 265152909Sanholt#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) 266130331Sanholt 26795584Sanholttypedef struct _drm_mga_warp_index { 268145132Sanholt int installed; 269145132Sanholt unsigned long phys_addr; 270145132Sanholt int size; 27195584Sanholt} drm_mga_warp_index_t; 27295584Sanholt 27395584Sanholttypedef struct drm_mga_init { 274145132Sanholt enum { 275145132Sanholt MGA_INIT_DMA = 0x01, 276145132Sanholt MGA_CLEANUP_DMA = 0x02 27795584Sanholt } func; 27895584Sanholt 279145132Sanholt unsigned long sarea_priv_offset; 28095584Sanholt 28195584Sanholt int chipset; 282145132Sanholt int sgram; 28395584Sanholt 28495584Sanholt unsigned int maccess; 28595584Sanholt 286145132Sanholt unsigned int fb_cpp; 28795584Sanholt unsigned int front_offset, front_pitch; 288145132Sanholt unsigned int back_offset, back_pitch; 28995584Sanholt 290145132Sanholt unsigned int depth_cpp; 291145132Sanholt unsigned int depth_offset, depth_pitch; 29295584Sanholt 293145132Sanholt unsigned int texture_offset[MGA_NR_TEX_HEAPS]; 294145132Sanholt unsigned int texture_size[MGA_NR_TEX_HEAPS]; 29595584Sanholt 29695584Sanholt unsigned long fb_offset; 29795584Sanholt unsigned long mmio_offset; 29895584Sanholt unsigned long status_offset; 29995584Sanholt unsigned long warp_offset; 30095584Sanholt unsigned long primary_offset; 30195584Sanholt unsigned long buffers_offset; 30295584Sanholt} drm_mga_init_t; 30395584Sanholt 30495584Sanholt 305152909Sanholttypedef struct drm_mga_dma_bootstrap { 306152909Sanholt /** 307152909Sanholt * \name AGP texture region 308182080Srnoland * 309152909Sanholt * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will 310152909Sanholt * be filled in with the actual AGP texture settings. 311182080Srnoland * 312152909Sanholt * \warning 313152909Sanholt * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode 314152909Sanholt * is zero, it means that PCI memory (most likely through the use of 315152909Sanholt * an IOMMU) is being used for "AGP" textures. 316152909Sanholt */ 317152909Sanholt /*@{*/ 318152909Sanholt unsigned long texture_handle; /**< Handle used to map AGP textures. */ 319152909Sanholt uint32_t texture_size; /**< Size of the AGP texture region. */ 320152909Sanholt /*@}*/ 321152909Sanholt 322152909Sanholt 323152909Sanholt /** 324152909Sanholt * Requested size of the primary DMA region. 325182080Srnoland * 326152909Sanholt * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 327152909Sanholt * filled in with the actual AGP mode. If AGP was not available 328152909Sanholt */ 329152909Sanholt uint32_t primary_size; 330152909Sanholt 331152909Sanholt 332152909Sanholt /** 333152909Sanholt * Requested number of secondary DMA buffers. 334182080Srnoland * 335152909Sanholt * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 336152909Sanholt * filled in with the actual number of secondary DMA buffers 337152909Sanholt * allocated. Particularly when PCI DMA is used, this may be 338152909Sanholt * (subtantially) less than the number requested. 339152909Sanholt */ 340152909Sanholt uint32_t secondary_bin_count; 341182080Srnoland 342182080Srnoland 343152909Sanholt /** 344152909Sanholt * Requested size of each secondary DMA buffer. 345182080Srnoland * 346152909Sanholt * While the kernel \b is free to reduce 347152909Sanholt * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed 348152909Sanholt * to reduce dma_mga_dma_bootstrap::secondary_bin_size. 349152909Sanholt */ 350152909Sanholt uint32_t secondary_bin_size; 351152909Sanholt 352152909Sanholt 353152909Sanholt /** 354152909Sanholt * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, 355152909Sanholt * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is 356152909Sanholt * zero, it means that PCI DMA should be used, even if AGP is 357152909Sanholt * possible. 358182080Srnoland * 359152909Sanholt * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 360152909Sanholt * filled in with the actual AGP mode. If AGP was not available 361152909Sanholt * (i.e., PCI DMA was used), this value will be zero. 362152909Sanholt */ 363152909Sanholt uint32_t agp_mode; 364152909Sanholt 365152909Sanholt 366152909Sanholt /** 367152909Sanholt * Desired AGP GART size, measured in megabytes. 368152909Sanholt */ 369152909Sanholt uint8_t agp_size; 370152909Sanholt} drm_mga_dma_bootstrap_t; 371152909Sanholt 37295584Sanholttypedef struct drm_mga_clear { 37395584Sanholt unsigned int flags; 37495584Sanholt unsigned int clear_color; 37595584Sanholt unsigned int clear_depth; 37695584Sanholt unsigned int color_mask; 37795584Sanholt unsigned int depth_mask; 37895584Sanholt} drm_mga_clear_t; 37995584Sanholt 38095584Sanholttypedef struct drm_mga_vertex { 381145132Sanholt int idx; /* buffer to queue */ 382145132Sanholt int used; /* bytes in use */ 383145132Sanholt int discard; /* client finished with buffer? */ 38495584Sanholt} drm_mga_vertex_t; 38595584Sanholt 38695584Sanholttypedef struct drm_mga_indices { 387145132Sanholt int idx; /* buffer to queue */ 38895584Sanholt unsigned int start; 38995584Sanholt unsigned int end; 390145132Sanholt int discard; /* client finished with buffer? */ 39195584Sanholt} drm_mga_indices_t; 39295584Sanholt 39395584Sanholttypedef struct drm_mga_iload { 39495584Sanholt int idx; 39595584Sanholt unsigned int dstorg; 39695584Sanholt unsigned int length; 39795584Sanholt} drm_mga_iload_t; 39895584Sanholt 39995584Sanholttypedef struct _drm_mga_blit { 40095584Sanholt unsigned int planemask; 40195584Sanholt unsigned int srcorg; 40295584Sanholt unsigned int dstorg; 40395584Sanholt int src_pitch, dst_pitch; 40495584Sanholt int delta_sx, delta_sy; 40595584Sanholt int delta_dx, delta_dy; 406145132Sanholt int height, ydir; /* flip image vertically */ 40795584Sanholt int source_pitch, dest_pitch; 40895584Sanholt} drm_mga_blit_t; 40995584Sanholt 410112015Sanholt/* 3.1: An ioctl to get parameters that aren't available to the 3d 411145132Sanholt * client any other way. 412112015Sanholt */ 413112015Sanholt#define MGA_PARAM_IRQ_NR 1 414112015Sanholt 415152909Sanholt/* 3.2: Query the actual card type. The DDX only distinguishes between 416152909Sanholt * G200 chips and non-G200 chips, which it calls G400. It turns out that 417152909Sanholt * there are some very sublte differences between the G4x0 chips and the G550 418152909Sanholt * chips. Using this parameter query, a client-side driver can detect the 419152909Sanholt * difference between a G4x0 and a G550. 420152909Sanholt */ 421152909Sanholt#define MGA_PARAM_CARD_TYPE 2 422152909Sanholt 423112015Sanholttypedef struct drm_mga_getparam { 424112015Sanholt int param; 425145132Sanholt void __user *value; 426112015Sanholt} drm_mga_getparam_t; 427112015Sanholt 42895584Sanholt#endif 429