i915_suspend.c revision 302408
1/* i915_suspend.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3/* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/11/sys/dev/drm/i915_suspend.c 190164 2009-03-20 17:51:26Z rnoland $"); 32 33#include "dev/drm/drmP.h" 34#include "dev/drm/drm.h" 35#include "dev/drm/i915_drm.h" 36#include "dev/drm/i915_drv.h" 37 38static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe) 39{ 40 struct drm_i915_private *dev_priv = dev->dev_private; 41 42 if (pipe == PIPE_A) 43 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE); 44 else 45 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE); 46} 47 48static void i915_save_palette(struct drm_device *dev, enum pipe pipe) 49{ 50 struct drm_i915_private *dev_priv = dev->dev_private; 51 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); 52 u32 *array; 53 int i; 54 55 if (!i915_pipe_enabled(dev, pipe)) 56 return; 57 58 if (pipe == PIPE_A) 59 array = dev_priv->save_palette_a; 60 else 61 array = dev_priv->save_palette_b; 62 63 for(i = 0; i < 256; i++) 64 array[i] = I915_READ(reg + (i << 2)); 65} 66 67static void i915_restore_palette(struct drm_device *dev, enum pipe pipe) 68{ 69 struct drm_i915_private *dev_priv = dev->dev_private; 70 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); 71 u32 *array; 72 int i; 73 74 if (!i915_pipe_enabled(dev, pipe)) 75 return; 76 77 if (pipe == PIPE_A) 78 array = dev_priv->save_palette_a; 79 else 80 array = dev_priv->save_palette_b; 81 82 for(i = 0; i < 256; i++) 83 I915_WRITE(reg + (i << 2), array[i]); 84} 85 86static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg) 87{ 88 struct drm_i915_private *dev_priv = dev->dev_private; 89 90 I915_WRITE8(index_port, reg); 91 return I915_READ8(data_port); 92} 93 94static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable) 95{ 96 struct drm_i915_private *dev_priv = dev->dev_private; 97 98 I915_READ8(st01); 99 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); 100 return I915_READ8(VGA_AR_DATA_READ); 101} 102 103static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable) 104{ 105 struct drm_i915_private *dev_priv = dev->dev_private; 106 107 I915_READ8(st01); 108 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); 109 I915_WRITE8(VGA_AR_DATA_WRITE, val); 110} 111 112static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val) 113{ 114 struct drm_i915_private *dev_priv = dev->dev_private; 115 116 I915_WRITE8(index_port, reg); 117 I915_WRITE8(data_port, val); 118} 119 120static void i915_save_vga(struct drm_device *dev) 121{ 122 struct drm_i915_private *dev_priv = dev->dev_private; 123 int i; 124 u16 cr_index, cr_data, st01; 125 126 /* VGA color palette registers */ 127 dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK); 128 129 /* MSR bits */ 130 dev_priv->saveMSR = I915_READ8(VGA_MSR_READ); 131 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { 132 cr_index = VGA_CR_INDEX_CGA; 133 cr_data = VGA_CR_DATA_CGA; 134 st01 = VGA_ST01_CGA; 135 } else { 136 cr_index = VGA_CR_INDEX_MDA; 137 cr_data = VGA_CR_DATA_MDA; 138 st01 = VGA_ST01_MDA; 139 } 140 141 /* CRT controller regs */ 142 i915_write_indexed(dev, cr_index, cr_data, 0x11, 143 i915_read_indexed(dev, cr_index, cr_data, 0x11) & 144 (~0x80)); 145 for (i = 0; i <= 0x24; i++) 146 dev_priv->saveCR[i] = 147 i915_read_indexed(dev, cr_index, cr_data, i); 148 /* Make sure we don't turn off CR group 0 writes */ 149 dev_priv->saveCR[0x11] &= ~0x80; 150 151 /* Attribute controller registers */ 152 I915_READ8(st01); 153 dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX); 154 for (i = 0; i <= 0x14; i++) 155 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0); 156 I915_READ8(st01); 157 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX); 158 I915_READ8(st01); 159 160 /* Graphics controller registers */ 161 for (i = 0; i < 9; i++) 162 dev_priv->saveGR[i] = 163 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i); 164 165 dev_priv->saveGR[0x10] = 166 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10); 167 dev_priv->saveGR[0x11] = 168 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11); 169 dev_priv->saveGR[0x18] = 170 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18); 171 172 /* Sequencer registers */ 173 for (i = 0; i < 8; i++) 174 dev_priv->saveSR[i] = 175 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i); 176} 177 178static void i915_restore_vga(struct drm_device *dev) 179{ 180 struct drm_i915_private *dev_priv = dev->dev_private; 181 int i; 182 u16 cr_index, cr_data, st01; 183 184 /* MSR bits */ 185 I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR); 186 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { 187 cr_index = VGA_CR_INDEX_CGA; 188 cr_data = VGA_CR_DATA_CGA; 189 st01 = VGA_ST01_CGA; 190 } else { 191 cr_index = VGA_CR_INDEX_MDA; 192 cr_data = VGA_CR_DATA_MDA; 193 st01 = VGA_ST01_MDA; 194 } 195 196 /* Sequencer registers, don't write SR07 */ 197 for (i = 0; i < 7; i++) 198 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i, 199 dev_priv->saveSR[i]); 200 201 /* CRT controller regs */ 202 /* Enable CR group 0 writes */ 203 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]); 204 for (i = 0; i <= 0x24; i++) 205 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]); 206 207 /* Graphics controller regs */ 208 for (i = 0; i < 9; i++) 209 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i, 210 dev_priv->saveGR[i]); 211 212 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10, 213 dev_priv->saveGR[0x10]); 214 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11, 215 dev_priv->saveGR[0x11]); 216 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18, 217 dev_priv->saveGR[0x18]); 218 219 /* Attribute controller registers */ 220 I915_READ8(st01); /* switch back to index mode */ 221 for (i = 0; i <= 0x14; i++) 222 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0); 223 I915_READ8(st01); /* switch back to index mode */ 224 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20); 225 I915_READ8(st01); 226 227 /* VGA color palette registers */ 228 I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK); 229} 230 231int i915_save_state(struct drm_device *dev) 232{ 233 struct drm_i915_private *dev_priv = dev->dev_private; 234 int i; 235 236#if defined(__FreeBSD__) 237 dev_priv->saveLBB = (u8) pci_read_config(dev->device, LBB, 1); 238#else 239 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); 240#endif 241 242 /* Render Standby */ 243 if (IS_I965G(dev) && IS_MOBILE(dev)) 244 dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY); 245 246 /* Hardware status page */ 247 dev_priv->saveHWS = I915_READ(HWS_PGA); 248 249 /* Display arbitration control */ 250 dev_priv->saveDSPARB = I915_READ(DSPARB); 251 252 /* Pipe & plane A info */ 253 dev_priv->savePIPEACONF = I915_READ(PIPEACONF); 254 dev_priv->savePIPEASRC = I915_READ(PIPEASRC); 255 dev_priv->saveFPA0 = I915_READ(FPA0); 256 dev_priv->saveFPA1 = I915_READ(FPA1); 257 dev_priv->saveDPLL_A = I915_READ(DPLL_A); 258 if (IS_I965G(dev)) 259 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); 260 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); 261 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); 262 dev_priv->saveHSYNC_A = I915_READ(HSYNC_A); 263 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); 264 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); 265 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); 266 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 267 268 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR); 269 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE); 270 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE); 271 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS); 272 dev_priv->saveDSPAADDR = I915_READ(DSPAADDR); 273 if (IS_I965G(dev)) { 274 dev_priv->saveDSPASURF = I915_READ(DSPASURF); 275 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF); 276 } 277 i915_save_palette(dev, PIPE_A); 278 dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT); 279 280 /* Pipe & plane B info */ 281 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); 282 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); 283 dev_priv->saveFPB0 = I915_READ(FPB0); 284 dev_priv->saveFPB1 = I915_READ(FPB1); 285 dev_priv->saveDPLL_B = I915_READ(DPLL_B); 286 if (IS_I965G(dev)) 287 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); 288 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); 289 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); 290 dev_priv->saveHSYNC_B = I915_READ(HSYNC_B); 291 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); 292 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); 293 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); 294 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 295 296 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR); 297 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE); 298 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE); 299 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS); 300 dev_priv->saveDSPBADDR = I915_READ(DSPBADDR); 301 if (IS_I965GM(dev) || IS_GM45(dev)) { 302 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF); 303 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF); 304 } 305 i915_save_palette(dev, PIPE_B); 306 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT); 307 308 /* CRT state */ 309 dev_priv->saveADPA = I915_READ(ADPA); 310 311 /* LVDS state */ 312 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL); 313 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); 314 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); 315 if (IS_I965G(dev)) 316 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); 317 if (IS_MOBILE(dev) && !IS_I830(dev)) 318 dev_priv->saveLVDS = I915_READ(LVDS); 319 if (!IS_I830(dev) && !IS_845G(dev)) 320 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); 321 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); 322 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); 323 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR); 324 325 /* FIXME: save TV & SDVO state */ 326 327 /* FBC state */ 328 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE); 329 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE); 330 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); 331 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); 332 333 /* Interrupt state */ 334 dev_priv->saveIIR = I915_READ(IIR); 335 dev_priv->saveIER = I915_READ(IER); 336 dev_priv->saveIMR = I915_READ(IMR); 337 338 /* VGA state */ 339 dev_priv->saveVGA0 = I915_READ(VGA0); 340 dev_priv->saveVGA1 = I915_READ(VGA1); 341 dev_priv->saveVGA_PD = I915_READ(VGA_PD); 342 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); 343 344 /* Clock gating state */ 345 dev_priv->saveD_STATE = I915_READ(D_STATE); 346 dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS); 347 348 /* Cache mode state */ 349 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); 350 351 /* Memory Arbitration state */ 352 dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); 353 354 /* Scratch space */ 355 for (i = 0; i < 16; i++) { 356 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2)); 357 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2)); 358 } 359 for (i = 0; i < 3; i++) 360 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2)); 361 362 i915_save_vga(dev); 363 364 return 0; 365} 366 367int i915_restore_state(struct drm_device *dev) 368{ 369 struct drm_i915_private *dev_priv = dev->dev_private; 370 int i; 371 372#if defined(__FreeBSD__) 373 pci_write_config(dev->device, LBB, dev_priv->saveLBB, 1); 374#else 375 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 376#endif 377 378 /* Render Standby */ 379 if (IS_I965G(dev) && IS_MOBILE(dev)) 380 I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY); 381 382 /* Hardware status page */ 383 I915_WRITE(HWS_PGA, dev_priv->saveHWS); 384 385 /* Display arbitration */ 386 I915_WRITE(DSPARB, dev_priv->saveDSPARB); 387 388 /* Pipe & plane A info */ 389 /* Prime the clock */ 390 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { 391 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A & 392 ~DPLL_VCO_ENABLE); 393 DRM_UDELAY(150); 394 } 395 I915_WRITE(FPA0, dev_priv->saveFPA0); 396 I915_WRITE(FPA1, dev_priv->saveFPA1); 397 /* Actually enable it */ 398 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A); 399 DRM_UDELAY(150); 400 if (IS_I965G(dev)) 401 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); 402 DRM_UDELAY(150); 403 404 /* Restore mode */ 405 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A); 406 I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A); 407 I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A); 408 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); 409 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); 410 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); 411 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); 412 413 /* Restore plane info */ 414 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE); 415 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS); 416 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC); 417 I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR); 418 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE); 419 if (IS_I965G(dev)) { 420 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF); 421 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF); 422 } 423 424 I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF); 425 426 i915_restore_palette(dev, PIPE_A); 427 /* Enable the plane */ 428 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR); 429 I915_WRITE(DSPAADDR, I915_READ(DSPAADDR)); 430 431 /* Pipe & plane B info */ 432 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { 433 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B & 434 ~DPLL_VCO_ENABLE); 435 DRM_UDELAY(150); 436 } 437 I915_WRITE(FPB0, dev_priv->saveFPB0); 438 I915_WRITE(FPB1, dev_priv->saveFPB1); 439 /* Actually enable it */ 440 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B); 441 DRM_UDELAY(150); 442 if (IS_I965G(dev)) 443 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD); 444 DRM_UDELAY(150); 445 446 /* Restore mode */ 447 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B); 448 I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B); 449 I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B); 450 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); 451 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); 452 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); 453 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); 454 455 /* Restore plane info */ 456 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE); 457 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS); 458 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC); 459 I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR); 460 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE); 461 if (IS_I965G(dev)) { 462 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF); 463 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF); 464 } 465 466 I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF); 467 468 i915_restore_palette(dev, PIPE_B); 469 /* Enable the plane */ 470 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR); 471 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR)); 472 473 /* CRT state */ 474 I915_WRITE(ADPA, dev_priv->saveADPA); 475 476 /* LVDS state */ 477 if (IS_I965G(dev)) 478 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); 479 if (IS_MOBILE(dev) && !IS_I830(dev)) 480 I915_WRITE(LVDS, dev_priv->saveLVDS); 481 if (!IS_I830(dev) && !IS_845G(dev)) 482 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); 483 484 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); 485 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); 486 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); 487 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); 488 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR); 489 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); 490 491 /* FIXME: restore TV & SDVO state */ 492 493 /* FBC info */ 494 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE); 495 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE); 496 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2); 497 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL); 498 499 /* VGA state */ 500 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); 501 I915_WRITE(VGA0, dev_priv->saveVGA0); 502 I915_WRITE(VGA1, dev_priv->saveVGA1); 503 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); 504 DRM_UDELAY(150); 505 506 /* Clock gating state */ 507 I915_WRITE (D_STATE, dev_priv->saveD_STATE); 508 I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS); 509 510 /* Cache mode state */ 511 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); 512 513 /* Memory arbitration state */ 514 I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000); 515 516 for (i = 0; i < 16; i++) { 517 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]); 518 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]); 519 } 520 for (i = 0; i < 3; i++) 521 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]); 522 523 i915_restore_vga(dev); 524 525 return 0; 526} 527 528