i915_suspend.c revision 182080
1/*- 2 * 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/drm/i915_suspend.c 182080 2008-08-23 20:59:12Z rnoland $"); 30 31#include "dev/drm/drmP.h" 32#include "dev/drm/drm.h" 33#include "dev/drm/i915_drm.h" 34#include "dev/drm/i915_drv.h" 35 36static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe) 37{ 38 struct drm_i915_private *dev_priv = dev->dev_private; 39 40 if (pipe == PIPE_A) 41 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE); 42 else 43 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE); 44} 45 46static void i915_save_palette(struct drm_device *dev, enum pipe pipe) 47{ 48 struct drm_i915_private *dev_priv = dev->dev_private; 49 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); 50 u32 *array; 51 int i; 52 53 if (!i915_pipe_enabled(dev, pipe)) 54 return; 55 56 if (pipe == PIPE_A) 57 array = dev_priv->save_palette_a; 58 else 59 array = dev_priv->save_palette_b; 60 61 for(i = 0; i < 256; i++) 62 array[i] = I915_READ(reg + (i << 2)); 63} 64 65static void i915_restore_palette(struct drm_device *dev, enum pipe pipe) 66{ 67 struct drm_i915_private *dev_priv = dev->dev_private; 68 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B); 69 u32 *array; 70 int i; 71 72 if (!i915_pipe_enabled(dev, pipe)) 73 return; 74 75 if (pipe == PIPE_A) 76 array = dev_priv->save_palette_a; 77 else 78 array = dev_priv->save_palette_b; 79 80 for(i = 0; i < 256; i++) 81 I915_WRITE(reg + (i << 2), array[i]); 82} 83 84static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg) 85{ 86 struct drm_i915_private *dev_priv = dev->dev_private; 87 88 I915_WRITE8(index_port, reg); 89 return I915_READ8(data_port); 90} 91 92static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable) 93{ 94 struct drm_i915_private *dev_priv = dev->dev_private; 95 96 I915_READ8(st01); 97 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); 98 return I915_READ8(VGA_AR_DATA_READ); 99} 100 101static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable) 102{ 103 struct drm_i915_private *dev_priv = dev->dev_private; 104 105 I915_READ8(st01); 106 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); 107 I915_WRITE8(VGA_AR_DATA_WRITE, val); 108} 109 110static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val) 111{ 112 struct drm_i915_private *dev_priv = dev->dev_private; 113 114 I915_WRITE8(index_port, reg); 115 I915_WRITE8(data_port, val); 116} 117 118static void i915_save_vga(struct drm_device *dev) 119{ 120 struct drm_i915_private *dev_priv = dev->dev_private; 121 int i; 122 u16 cr_index, cr_data, st01; 123 124 /* VGA color palette registers */ 125 dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK); 126 /* DACCRX automatically increments during read */ 127 I915_WRITE8(VGA_DACRX, 0); 128 /* Read 3 bytes of color data from each index */ 129 for (i = 0; i < 256 * 3; i++) 130 dev_priv->saveDACDATA[i] = I915_READ8(VGA_DACDATA); 131 132 /* MSR bits */ 133 dev_priv->saveMSR = I915_READ8(VGA_MSR_READ); 134 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { 135 cr_index = VGA_CR_INDEX_CGA; 136 cr_data = VGA_CR_DATA_CGA; 137 st01 = VGA_ST01_CGA; 138 } else { 139 cr_index = VGA_CR_INDEX_MDA; 140 cr_data = VGA_CR_DATA_MDA; 141 st01 = VGA_ST01_MDA; 142 } 143 144 /* CRT controller regs */ 145 i915_write_indexed(dev, cr_index, cr_data, 0x11, 146 i915_read_indexed(dev, cr_index, cr_data, 0x11) & 147 (~0x80)); 148 for (i = 0; i <= 0x24; i++) 149 dev_priv->saveCR[i] = 150 i915_read_indexed(dev, cr_index, cr_data, i); 151 /* Make sure we don't turn off CR group 0 writes */ 152 dev_priv->saveCR[0x11] &= ~0x80; 153 154 /* Attribute controller registers */ 155 I915_READ8(st01); 156 dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX); 157 for (i = 0; i <= 0x14; i++) 158 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0); 159 I915_READ8(st01); 160 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX); 161 I915_READ8(st01); 162 163 /* Graphics controller registers */ 164 for (i = 0; i < 9; i++) 165 dev_priv->saveGR[i] = 166 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i); 167 168 dev_priv->saveGR[0x10] = 169 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10); 170 dev_priv->saveGR[0x11] = 171 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11); 172 dev_priv->saveGR[0x18] = 173 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18); 174 175 /* Sequencer registers */ 176 for (i = 0; i < 8; i++) 177 dev_priv->saveSR[i] = 178 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i); 179} 180 181static void i915_restore_vga(struct drm_device *dev) 182{ 183 struct drm_i915_private *dev_priv = dev->dev_private; 184 int i; 185 u16 cr_index, cr_data, st01; 186 187 /* MSR bits */ 188 I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR); 189 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) { 190 cr_index = VGA_CR_INDEX_CGA; 191 cr_data = VGA_CR_DATA_CGA; 192 st01 = VGA_ST01_CGA; 193 } else { 194 cr_index = VGA_CR_INDEX_MDA; 195 cr_data = VGA_CR_DATA_MDA; 196 st01 = VGA_ST01_MDA; 197 } 198 199 /* Sequencer registers, don't write SR07 */ 200 for (i = 0; i < 7; i++) 201 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i, 202 dev_priv->saveSR[i]); 203 204 /* CRT controller regs */ 205 /* Enable CR group 0 writes */ 206 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]); 207 for (i = 0; i <= 0x24; i++) 208 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]); 209 210 /* Graphics controller regs */ 211 for (i = 0; i < 9; i++) 212 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i, 213 dev_priv->saveGR[i]); 214 215 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10, 216 dev_priv->saveGR[0x10]); 217 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11, 218 dev_priv->saveGR[0x11]); 219 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18, 220 dev_priv->saveGR[0x18]); 221 222 /* Attribute controller registers */ 223 I915_READ8(st01); /* switch back to index mode */ 224 for (i = 0; i <= 0x14; i++) 225 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0); 226 I915_READ8(st01); /* switch back to index mode */ 227 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20); 228 I915_READ8(st01); 229 230 /* VGA color palette registers */ 231 I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK); 232 /* DACCRX automatically increments during read */ 233 I915_WRITE8(VGA_DACWX, 0); 234 /* Read 3 bytes of color data from each index */ 235 for (i = 0; i < 256 * 3; i++) 236 I915_WRITE8(VGA_DACDATA, dev_priv->saveDACDATA[i]); 237 238} 239 240int i915_save_state(struct drm_device *dev) 241{ 242 struct drm_i915_private *dev_priv = dev->dev_private; 243 int i; 244 245#if defined(__FreeBSD__) 246 dev_priv->saveLBB = (u8) pci_read_config(dev->device, LBB, 1); 247#else 248 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); 249#endif 250 251 /* Display arbitration control */ 252 dev_priv->saveDSPARB = I915_READ(DSPARB); 253 254 /* Pipe & plane A info */ 255 dev_priv->savePIPEACONF = I915_READ(PIPEACONF); 256 dev_priv->savePIPEASRC = I915_READ(PIPEASRC); 257 dev_priv->saveFPA0 = I915_READ(FPA0); 258 dev_priv->saveFPA1 = I915_READ(FPA1); 259 dev_priv->saveDPLL_A = I915_READ(DPLL_A); 260 if (IS_I965G(dev)) 261 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); 262 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); 263 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); 264 dev_priv->saveHSYNC_A = I915_READ(HSYNC_A); 265 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); 266 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); 267 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); 268 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 269 270 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR); 271 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE); 272 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE); 273 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS); 274 dev_priv->saveDSPAADDR = I915_READ(DSPAADDR); 275 if (IS_I965G(dev)) { 276 dev_priv->saveDSPASURF = I915_READ(DSPASURF); 277 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF); 278 } 279 i915_save_palette(dev, PIPE_A); 280 dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT); 281 282 /* Pipe & plane B info */ 283 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); 284 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); 285 dev_priv->saveFPB0 = I915_READ(FPB0); 286 dev_priv->saveFPB1 = I915_READ(FPB1); 287 dev_priv->saveDPLL_B = I915_READ(DPLL_B); 288 if (IS_I965G(dev)) 289 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); 290 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); 291 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); 292 dev_priv->saveHSYNC_B = I915_READ(HSYNC_B); 293 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); 294 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); 295 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); 296 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 297 298 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR); 299 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE); 300 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE); 301 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS); 302 dev_priv->saveDSPBADDR = I915_READ(DSPBADDR); 303 if (IS_I965GM(dev) || IS_GM45(dev)) { 304 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF); 305 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF); 306 } 307 i915_save_palette(dev, PIPE_B); 308 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT); 309 310 /* CRT state */ 311 dev_priv->saveADPA = I915_READ(ADPA); 312 313 /* LVDS state */ 314 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL); 315 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); 316 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); 317 if (IS_I965G(dev)) 318 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); 319 if (IS_MOBILE(dev) && !IS_I830(dev)) 320 dev_priv->saveLVDS = I915_READ(LVDS); 321 if (!IS_I830(dev) && !IS_845G(dev)) 322 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); 323 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); 324 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); 325 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR); 326 327 /* FIXME: save TV & SDVO state */ 328 329 /* FBC state */ 330 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE); 331 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE); 332 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); 333 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); 334 335 /* Interrupt state */ 336 dev_priv->saveIIR = I915_READ(IIR); 337 dev_priv->saveIER = I915_READ(IER); 338 dev_priv->saveIMR = I915_READ(IMR); 339 340 /* VGA state */ 341 dev_priv->saveVGA0 = I915_READ(VGA0); 342 dev_priv->saveVGA1 = I915_READ(VGA1); 343 dev_priv->saveVGA_PD = I915_READ(VGA_PD); 344 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); 345 346 /* Clock gating state */ 347 dev_priv->saveD_STATE = I915_READ(D_STATE); 348 dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS); 349 350 /* Cache mode state */ 351 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); 352 353 /* Memory Arbitration state */ 354 dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); 355 356 /* Scratch space */ 357 for (i = 0; i < 16; i++) { 358 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2)); 359 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2)); 360 } 361 for (i = 0; i < 3; i++) 362 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2)); 363 364 i915_save_vga(dev); 365 366 return 0; 367} 368 369int i915_restore_state(struct drm_device *dev) 370{ 371 struct drm_i915_private *dev_priv = dev->dev_private; 372 int i; 373 374#if defined(__FreeBSD__) 375 pci_write_config(dev->device, LBB, dev_priv->saveLBB, 1); 376#else 377 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); 378#endif 379 380 I915_WRITE(DSPARB, dev_priv->saveDSPARB); 381 382 /* Pipe & plane A info */ 383 /* Prime the clock */ 384 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { 385 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A & 386 ~DPLL_VCO_ENABLE); 387 DRM_UDELAY(150); 388 } 389 I915_WRITE(FPA0, dev_priv->saveFPA0); 390 I915_WRITE(FPA1, dev_priv->saveFPA1); 391 /* Actually enable it */ 392 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A); 393 DRM_UDELAY(150); 394 if (IS_I965G(dev)) 395 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); 396 DRM_UDELAY(150); 397 398 /* Restore mode */ 399 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A); 400 I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A); 401 I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A); 402 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); 403 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); 404 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); 405 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); 406 407 /* Restore plane info */ 408 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE); 409 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS); 410 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC); 411 I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR); 412 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE); 413 if (IS_I965G(dev)) { 414 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF); 415 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF); 416 } 417 418 I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF); 419 420 i915_restore_palette(dev, PIPE_A); 421 /* Enable the plane */ 422 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR); 423 I915_WRITE(DSPAADDR, I915_READ(DSPAADDR)); 424 425 /* Pipe & plane B info */ 426 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { 427 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B & 428 ~DPLL_VCO_ENABLE); 429 DRM_UDELAY(150); 430 } 431 I915_WRITE(FPB0, dev_priv->saveFPB0); 432 I915_WRITE(FPB1, dev_priv->saveFPB1); 433 /* Actually enable it */ 434 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B); 435 DRM_UDELAY(150); 436 if (IS_I965G(dev)) 437 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD); 438 DRM_UDELAY(150); 439 440 /* Restore mode */ 441 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B); 442 I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B); 443 I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B); 444 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); 445 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); 446 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); 447 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); 448 449 /* Restore plane info */ 450 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE); 451 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS); 452 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC); 453 I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR); 454 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE); 455 if (IS_I965G(dev)) { 456 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF); 457 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF); 458 } 459 460 I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF); 461 462 i915_restore_palette(dev, PIPE_B); 463 /* Enable the plane */ 464 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR); 465 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR)); 466 467 /* CRT state */ 468 I915_WRITE(ADPA, dev_priv->saveADPA); 469 470 /* LVDS state */ 471 if (IS_I965G(dev)) 472 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); 473 if (IS_MOBILE(dev) && !IS_I830(dev)) 474 I915_WRITE(LVDS, dev_priv->saveLVDS); 475 if (!IS_I830(dev) && !IS_845G(dev)) 476 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); 477 478 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); 479 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); 480 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); 481 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); 482 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR); 483 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); 484 485 /* FIXME: restore TV & SDVO state */ 486 487 /* FBC info */ 488 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE); 489 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE); 490 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2); 491 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL); 492 493 /* VGA state */ 494 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); 495 I915_WRITE(VGA0, dev_priv->saveVGA0); 496 I915_WRITE(VGA1, dev_priv->saveVGA1); 497 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); 498 DRM_UDELAY(150); 499 500 /* Clock gating state */ 501 I915_WRITE (D_STATE, dev_priv->saveD_STATE); 502 I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS); 503 504 /* Cache mode state */ 505 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); 506 507 /* Memory arbitration state */ 508 I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000); 509 510 for (i = 0; i < 16; i++) { 511 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]); 512 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]); 513 } 514 for (i = 0; i < 3; i++) 515 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]); 516 517 i915_restore_vga(dev); 518 519 return 0; 520} 521 522