i915_dma.c revision 184373
1/* i915_dma.c -- DMA support for the I915 -*- linux-c -*- 2 */ 3/*- 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/drm/i915_dma.c 184373 2008-10-27 21:16:07Z rnoland $"); 31 32#include "dev/drm/drmP.h" 33#include "dev/drm/drm.h" 34#include "dev/drm/i915_drm.h" 35#include "dev/drm/i915_drv.h" 36 37/* Really want an OS-independent resettable timer. Would like to have 38 * this loop run for (eg) 3 sec, but have the timer reset every time 39 * the head pointer changes, so that EBUSY only happens if the ring 40 * actually stalls for (eg) 3 seconds. 41 */ 42int i915_wait_ring(struct drm_device * dev, int n, const char *caller) 43{ 44 drm_i915_private_t *dev_priv = dev->dev_private; 45 drm_i915_ring_buffer_t *ring = &(dev_priv->ring); 46 u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR; 47 u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD; 48 u32 last_acthd = I915_READ(acthd_reg); 49 u32 acthd; 50 int i; 51 52 for (i = 0; i < 100000; i++) { 53 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; 54 acthd = I915_READ(acthd_reg); 55 ring->space = ring->head - (ring->tail + 8); 56 if (ring->space < 0) 57 ring->space += ring->Size; 58 if (ring->space >= n) 59 return 0; 60 61 if (ring->head != last_head) 62 i = 0; 63 64 if (acthd != last_acthd) 65 i = 0; 66 67 last_head = ring->head; 68 last_acthd = acthd; 69 DRM_UDELAY(10 * 1000); 70 } 71 72 return -EBUSY; 73} 74 75int i915_init_hardware_status(struct drm_device *dev) 76{ 77 drm_i915_private_t *dev_priv = dev->dev_private; 78 drm_dma_handle_t *dmah; 79 80 /* Program Hardware Status Page */ 81#ifdef __FreeBSD__ 82 DRM_UNLOCK(); 83#endif 84 dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); 85#ifdef __FreeBSD__ 86 DRM_LOCK(); 87#endif 88 if (!dmah) { 89 DRM_ERROR("Can not allocate hardware status page\n"); 90 return -ENOMEM; 91 } 92 93 dev_priv->status_page_dmah = dmah; 94 dev_priv->hw_status_page = dmah->vaddr; 95 dev_priv->dma_status_page = dmah->busaddr; 96 97 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 98 99 I915_WRITE(0x02080, dev_priv->dma_status_page); 100 DRM_DEBUG("Enabled hardware status page\n"); 101 return 0; 102} 103 104void i915_free_hardware_status(struct drm_device *dev) 105{ 106 drm_i915_private_t *dev_priv = dev->dev_private; 107 if (dev_priv->status_page_dmah) { 108 drm_pci_free(dev, dev_priv->status_page_dmah); 109 dev_priv->status_page_dmah = NULL; 110 /* Need to rewrite hardware status page */ 111 I915_WRITE(0x02080, 0x1ffff000); 112 } 113 114 if (dev_priv->status_gfx_addr) { 115 dev_priv->status_gfx_addr = 0; 116 drm_core_ioremapfree(&dev_priv->hws_map, dev); 117 I915_WRITE(0x02080, 0x1ffff000); 118 } 119} 120 121#if I915_RING_VALIDATE 122/** 123 * Validate the cached ring tail value 124 * 125 * If the X server writes to the ring and DRM doesn't 126 * reload the head and tail pointers, it will end up writing 127 * data to the wrong place in the ring, causing havoc. 128 */ 129void i915_ring_validate(struct drm_device *dev, const char *func, int line) 130{ 131 drm_i915_private_t *dev_priv = dev->dev_private; 132 drm_i915_ring_buffer_t *ring = &(dev_priv->ring); 133 u32 tail = I915_READ(PRB0_TAIL) & HEAD_ADDR; 134 u32 head = I915_READ(PRB0_HEAD) & HEAD_ADDR; 135 136 if (tail != ring->tail) { 137 DRM_ERROR("%s:%d head sw %x, hw %x. tail sw %x hw %x\n", 138 func, line, 139 ring->head, head, ring->tail, tail); 140#ifdef __linux__ 141 BUG_ON(1); 142#endif 143 } 144} 145#endif 146 147void i915_kernel_lost_context(struct drm_device * dev) 148{ 149 drm_i915_private_t *dev_priv = dev->dev_private; 150 drm_i915_ring_buffer_t *ring = &(dev_priv->ring); 151 152 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; 153 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; 154 ring->space = ring->head - (ring->tail + 8); 155 if (ring->space < 0) 156 ring->space += ring->Size; 157} 158 159static int i915_dma_cleanup(struct drm_device * dev) 160{ 161 drm_i915_private_t *dev_priv = dev->dev_private; 162 /* Make sure interrupts are disabled here because the uninstall ioctl 163 * may not have been called from userspace and after dev_private 164 * is freed, it's too late. 165 */ 166 if (dev->irq_enabled) 167 drm_irq_uninstall(dev); 168 169 if (dev_priv->ring.virtual_start) { 170 drm_core_ioremapfree(&dev_priv->ring.map, dev); 171 dev_priv->ring.virtual_start = 0; 172 dev_priv->ring.map.handle = 0; 173 dev_priv->ring.map.size = 0; 174 } 175 176 if (I915_NEED_GFX_HWS(dev)) 177 i915_free_hardware_status(dev); 178 179 return 0; 180} 181 182#if defined(I915_HAVE_BUFFER) 183#define DRI2_SAREA_BLOCK_TYPE(b) ((b) >> 16) 184#define DRI2_SAREA_BLOCK_SIZE(b) ((b) & 0xffff) 185#define DRI2_SAREA_BLOCK_NEXT(p) \ 186 ((void *) ((unsigned char *) (p) + \ 187 DRI2_SAREA_BLOCK_SIZE(*(unsigned int *) p))) 188 189#define DRI2_SAREA_BLOCK_END 0x0000 190#define DRI2_SAREA_BLOCK_LOCK 0x0001 191#define DRI2_SAREA_BLOCK_EVENT_BUFFER 0x0002 192 193static int 194setup_dri2_sarea(struct drm_device * dev, 195 struct drm_file *file_priv, 196 drm_i915_init_t * init) 197{ 198 drm_i915_private_t *dev_priv = dev->dev_private; 199 int ret; 200 unsigned int *p, *end, *next; 201 202 mutex_lock(&dev->struct_mutex); 203 dev_priv->sarea_bo = 204 drm_lookup_buffer_object(file_priv, 205 init->sarea_handle, 1); 206 mutex_unlock(&dev->struct_mutex); 207 208 if (!dev_priv->sarea_bo) { 209 DRM_ERROR("did not find sarea bo\n"); 210 return -EINVAL; 211 } 212 213 ret = drm_bo_kmap(dev_priv->sarea_bo, 0, 214 dev_priv->sarea_bo->num_pages, 215 &dev_priv->sarea_kmap); 216 if (ret) { 217 DRM_ERROR("could not map sarea bo\n"); 218 return ret; 219 } 220 221 p = dev_priv->sarea_kmap.virtual; 222 end = (void *) p + (dev_priv->sarea_bo->num_pages << PAGE_SHIFT); 223 while (p < end && DRI2_SAREA_BLOCK_TYPE(*p) != DRI2_SAREA_BLOCK_END) { 224 switch (DRI2_SAREA_BLOCK_TYPE(*p)) { 225 case DRI2_SAREA_BLOCK_LOCK: 226 dev->lock.hw_lock = (void *) (p + 1); 227 dev->sigdata.lock = dev->lock.hw_lock; 228 break; 229 } 230 next = DRI2_SAREA_BLOCK_NEXT(p); 231 if (next <= p || end < next) { 232 DRM_ERROR("malformed dri2 sarea: next is %p should be within %p-%p\n", 233 next, p, end); 234 return -EINVAL; 235 } 236 p = next; 237 } 238 239 return 0; 240} 241#endif 242 243static int i915_initialize(struct drm_device * dev, 244 struct drm_file *file_priv, 245 drm_i915_init_t * init) 246{ 247 drm_i915_private_t *dev_priv = dev->dev_private; 248#if defined(I915_HAVE_BUFFER) 249 int ret; 250#endif 251 dev_priv->sarea = drm_getsarea(dev); 252 if (!dev_priv->sarea) { 253 DRM_ERROR("can not find sarea!\n"); 254 i915_dma_cleanup(dev); 255 return -EINVAL; 256 } 257 258#ifdef I915_HAVE_BUFFER 259 dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS; 260#endif 261 262 if (init->sarea_priv_offset) 263 dev_priv->sarea_priv = (drm_i915_sarea_t *) 264 ((u8 *) dev_priv->sarea->handle + 265 init->sarea_priv_offset); 266 else { 267 /* No sarea_priv for you! */ 268 dev_priv->sarea_priv = NULL; 269 } 270 271 if (init->ring_size != 0) { 272 dev_priv->ring.Size = init->ring_size; 273 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; 274 275 dev_priv->ring.map.offset = init->ring_start; 276 dev_priv->ring.map.size = init->ring_size; 277 dev_priv->ring.map.type = 0; 278 dev_priv->ring.map.flags = 0; 279 dev_priv->ring.map.mtrr = 0; 280 281 drm_core_ioremap(&dev_priv->ring.map, dev); 282 283 if (dev_priv->ring.map.handle == NULL) { 284 i915_dma_cleanup(dev); 285 DRM_ERROR("can not ioremap virtual address for" 286 " ring buffer\n"); 287 return -ENOMEM; 288 } 289 290 dev_priv->ring.virtual_start = dev_priv->ring.map.handle; 291 } 292 293 dev_priv->cpp = init->cpp; 294 295 if (dev_priv->sarea_priv) 296 dev_priv->sarea_priv->pf_current_page = 0; 297 298 /* We are using separate values as placeholders for mechanisms for 299 * private backbuffer/depthbuffer usage. 300 */ 301 302 /* Allow hardware batchbuffers unless told otherwise. 303 */ 304 dev_priv->allow_batchbuffer = 1; 305 306 /* Enable vblank on pipe A for older X servers 307 */ 308 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A; 309 310#ifdef I915_HAVE_BUFFER 311 mutex_init(&dev_priv->cmdbuf_mutex); 312#endif 313#if defined(I915_HAVE_BUFFER) 314 if (init->func == I915_INIT_DMA2) { 315 ret = setup_dri2_sarea(dev, file_priv, init); 316 if (ret) { 317 i915_dma_cleanup(dev); 318 DRM_ERROR("could not set up dri2 sarea\n"); 319 return ret; 320 } 321 } 322#endif 323 324 return 0; 325} 326 327static int i915_dma_resume(struct drm_device * dev) 328{ 329 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 330 331 DRM_DEBUG("\n"); 332 333 if (!dev_priv->sarea) { 334 DRM_ERROR("can not find sarea!\n"); 335 return -EINVAL; 336 } 337 338 if (dev_priv->ring.map.handle == NULL) { 339 DRM_ERROR("can not ioremap virtual address for" 340 " ring buffer\n"); 341 return -ENOMEM; 342 } 343 344 /* Program Hardware Status Page */ 345 if (!dev_priv->hw_status_page) { 346 DRM_ERROR("Can not find hardware status page\n"); 347 return -EINVAL; 348 } 349 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); 350 351 if (dev_priv->status_gfx_addr != 0) 352 I915_WRITE(0x02080, dev_priv->status_gfx_addr); 353 else 354 I915_WRITE(0x02080, dev_priv->dma_status_page); 355 DRM_DEBUG("Enabled hardware status page\n"); 356 357 return 0; 358} 359 360static int i915_dma_init(struct drm_device *dev, void *data, 361 struct drm_file *file_priv) 362{ 363 drm_i915_init_t *init = data; 364 int retcode = 0; 365 366 switch (init->func) { 367 case I915_INIT_DMA: 368 case I915_INIT_DMA2: 369 retcode = i915_initialize(dev, file_priv, init); 370 break; 371 case I915_CLEANUP_DMA: 372 retcode = i915_dma_cleanup(dev); 373 break; 374 case I915_RESUME_DMA: 375 retcode = i915_dma_resume(dev); 376 break; 377 default: 378 retcode = -EINVAL; 379 break; 380 } 381 382 return retcode; 383} 384 385/* Implement basically the same security restrictions as hardware does 386 * for MI_BATCH_NON_SECURE. These can be made stricter at any time. 387 * 388 * Most of the calculations below involve calculating the size of a 389 * particular instruction. It's important to get the size right as 390 * that tells us where the next instruction to check is. Any illegal 391 * instruction detected will be given a size of zero, which is a 392 * signal to abort the rest of the buffer. 393 */ 394static int do_validate_cmd(int cmd) 395{ 396 switch (((cmd >> 29) & 0x7)) { 397 case 0x0: 398 switch ((cmd >> 23) & 0x3f) { 399 case 0x0: 400 return 1; /* MI_NOOP */ 401 case 0x4: 402 return 1; /* MI_FLUSH */ 403 default: 404 return 0; /* disallow everything else */ 405 } 406 break; 407 case 0x1: 408 return 0; /* reserved */ 409 case 0x2: 410 return (cmd & 0xff) + 2; /* 2d commands */ 411 case 0x3: 412 if (((cmd >> 24) & 0x1f) <= 0x18) 413 return 1; 414 415 switch ((cmd >> 24) & 0x1f) { 416 case 0x1c: 417 return 1; 418 case 0x1d: 419 switch ((cmd >> 16) & 0xff) { 420 case 0x3: 421 return (cmd & 0x1f) + 2; 422 case 0x4: 423 return (cmd & 0xf) + 2; 424 default: 425 return (cmd & 0xffff) + 2; 426 } 427 case 0x1e: 428 if (cmd & (1 << 23)) 429 return (cmd & 0xffff) + 1; 430 else 431 return 1; 432 case 0x1f: 433 if ((cmd & (1 << 23)) == 0) /* inline vertices */ 434 return (cmd & 0x1ffff) + 2; 435 else if (cmd & (1 << 17)) /* indirect random */ 436 if ((cmd & 0xffff) == 0) 437 return 0; /* unknown length, too hard */ 438 else 439 return (((cmd & 0xffff) + 1) / 2) + 1; 440 else 441 return 2; /* indirect sequential */ 442 default: 443 return 0; 444 } 445 default: 446 return 0; 447 } 448 449 return 0; 450} 451 452static int validate_cmd(int cmd) 453{ 454 int ret = do_validate_cmd(cmd); 455 456/* printk("validate_cmd( %x ): %d\n", cmd, ret); */ 457 458 return ret; 459} 460 461static int i915_emit_cmds(struct drm_device *dev, int __user *buffer, 462 int dwords) 463{ 464 drm_i915_private_t *dev_priv = dev->dev_private; 465 int i; 466 RING_LOCALS; 467 468 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) 469 return -EINVAL; 470 471 BEGIN_LP_RING((dwords+1)&~1); 472 473 for (i = 0; i < dwords;) { 474 int cmd, sz; 475 476 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) 477 return -EINVAL; 478 479 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) 480 return -EINVAL; 481 482 OUT_RING(cmd); 483 484 while (++i, --sz) { 485 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], 486 sizeof(cmd))) { 487 return -EINVAL; 488 } 489 OUT_RING(cmd); 490 } 491 } 492 493 if (dwords & 1) 494 OUT_RING(0); 495 496 ADVANCE_LP_RING(); 497 498 return 0; 499} 500 501int i915_emit_box(struct drm_device * dev, 502 struct drm_clip_rect __user * boxes, 503 int i, int DR1, int DR4) 504{ 505 drm_i915_private_t *dev_priv = dev->dev_private; 506 struct drm_clip_rect box; 507 RING_LOCALS; 508 509 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) { 510 return -EFAULT; 511 } 512 513 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { 514 DRM_ERROR("Bad box %d,%d..%d,%d\n", 515 box.x1, box.y1, box.x2, box.y2); 516 return -EINVAL; 517 } 518 519 if (IS_I965G(dev)) { 520 BEGIN_LP_RING(4); 521 OUT_RING(GFX_OP_DRAWRECT_INFO_I965); 522 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); 523 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); 524 OUT_RING(DR4); 525 ADVANCE_LP_RING(); 526 } else { 527 BEGIN_LP_RING(6); 528 OUT_RING(GFX_OP_DRAWRECT_INFO); 529 OUT_RING(DR1); 530 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); 531 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); 532 OUT_RING(DR4); 533 OUT_RING(0); 534 ADVANCE_LP_RING(); 535 } 536 537 return 0; 538} 539 540/* XXX: Emitting the counter should really be moved to part of the IRQ 541 * emit. For now, do it in both places: 542 */ 543 544void i915_emit_breadcrumb(struct drm_device *dev) 545{ 546 drm_i915_private_t *dev_priv = dev->dev_private; 547 RING_LOCALS; 548 549 if (++dev_priv->counter > BREADCRUMB_MASK) { 550 dev_priv->counter = 1; 551 DRM_DEBUG("Breadcrumb counter wrapped around\n"); 552 } 553 554 if (dev_priv->sarea_priv) 555 dev_priv->sarea_priv->last_enqueue = dev_priv->counter; 556 557 BEGIN_LP_RING(4); 558 OUT_RING(MI_STORE_DWORD_INDEX); 559 OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT); 560 OUT_RING(dev_priv->counter); 561 OUT_RING(0); 562 ADVANCE_LP_RING(); 563} 564 565 566int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush) 567{ 568 drm_i915_private_t *dev_priv = dev->dev_private; 569 uint32_t flush_cmd = MI_FLUSH; 570 RING_LOCALS; 571 572 flush_cmd |= flush; 573 574 i915_kernel_lost_context(dev); 575 576 BEGIN_LP_RING(4); 577 OUT_RING(flush_cmd); 578 OUT_RING(0); 579 OUT_RING(0); 580 OUT_RING(0); 581 ADVANCE_LP_RING(); 582 583 return 0; 584} 585 586 587static int i915_dispatch_cmdbuffer(struct drm_device * dev, 588 drm_i915_cmdbuffer_t * cmd) 589{ 590#ifdef I915_HAVE_FENCE 591 drm_i915_private_t *dev_priv = dev->dev_private; 592#endif 593 int nbox = cmd->num_cliprects; 594 int i = 0, count, ret; 595 596 if (cmd->sz & 0x3) { 597 DRM_ERROR("alignment\n"); 598 return -EINVAL; 599 } 600 601 i915_kernel_lost_context(dev); 602 603 count = nbox ? nbox : 1; 604 605 for (i = 0; i < count; i++) { 606 if (i < nbox) { 607 ret = i915_emit_box(dev, cmd->cliprects, i, 608 cmd->DR1, cmd->DR4); 609 if (ret) 610 return ret; 611 } 612 613 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4); 614 if (ret) 615 return ret; 616 } 617 618 i915_emit_breadcrumb(dev); 619#ifdef I915_HAVE_FENCE 620 if (unlikely((dev_priv->counter & 0xFF) == 0)) 621 drm_fence_flush_old(dev, 0, dev_priv->counter); 622#endif 623 return 0; 624} 625 626int i915_dispatch_batchbuffer(struct drm_device * dev, 627 drm_i915_batchbuffer_t * batch) 628{ 629 drm_i915_private_t *dev_priv = dev->dev_private; 630 struct drm_clip_rect __user *boxes = batch->cliprects; 631 int nbox = batch->num_cliprects; 632 int i = 0, count; 633 RING_LOCALS; 634 635 if ((batch->start | batch->used) & 0x7) { 636 DRM_ERROR("alignment\n"); 637 return -EINVAL; 638 } 639 640 i915_kernel_lost_context(dev); 641 642 count = nbox ? nbox : 1; 643 644 for (i = 0; i < count; i++) { 645 if (i < nbox) { 646 int ret = i915_emit_box(dev, boxes, i, 647 batch->DR1, batch->DR4); 648 if (ret) 649 return ret; 650 } 651 652 if (IS_I830(dev) || IS_845G(dev)) { 653 BEGIN_LP_RING(4); 654 OUT_RING(MI_BATCH_BUFFER); 655 OUT_RING(batch->start | MI_BATCH_NON_SECURE); 656 OUT_RING(batch->start + batch->used - 4); 657 OUT_RING(0); 658 ADVANCE_LP_RING(); 659 } else { 660 BEGIN_LP_RING(2); 661 if (IS_I965G(dev)) { 662 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); 663 OUT_RING(batch->start); 664 } else { 665 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); 666 OUT_RING(batch->start | MI_BATCH_NON_SECURE); 667 } 668 ADVANCE_LP_RING(); 669 } 670 } 671 672 i915_emit_breadcrumb(dev); 673#ifdef I915_HAVE_FENCE 674 if (unlikely((dev_priv->counter & 0xFF) == 0)) 675 drm_fence_flush_old(dev, 0, dev_priv->counter); 676#endif 677 return 0; 678} 679 680static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync) 681{ 682 drm_i915_private_t *dev_priv = dev->dev_private; 683 u32 num_pages, current_page, next_page, dspbase; 684 int shift = 2 * plane, x, y; 685 RING_LOCALS; 686 687 /* Calculate display base offset */ 688 num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2; 689 current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3; 690 next_page = (current_page + 1) % num_pages; 691 692 switch (next_page) { 693 default: 694 case 0: 695 dspbase = dev_priv->sarea_priv->front_offset; 696 break; 697 case 1: 698 dspbase = dev_priv->sarea_priv->back_offset; 699 break; 700 case 2: 701 dspbase = dev_priv->sarea_priv->third_offset; 702 break; 703 } 704 705 if (plane == 0) { 706 x = dev_priv->sarea_priv->planeA_x; 707 y = dev_priv->sarea_priv->planeA_y; 708 } else { 709 x = dev_priv->sarea_priv->planeB_x; 710 y = dev_priv->sarea_priv->planeB_y; 711 } 712 713 dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp; 714 715 DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page, 716 dspbase); 717 718 BEGIN_LP_RING(4); 719 OUT_RING(sync ? 0 : 720 (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP : 721 MI_WAIT_FOR_PLANE_A_FLIP))); 722 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) | 723 (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A)); 724 OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp); 725 OUT_RING(dspbase); 726 ADVANCE_LP_RING(); 727 728 dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift); 729 dev_priv->sarea_priv->pf_current_page |= next_page << shift; 730} 731 732void i915_dispatch_flip(struct drm_device * dev, int planes, int sync) 733{ 734 drm_i915_private_t *dev_priv = dev->dev_private; 735 int i; 736 737 DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n", 738 planes, dev_priv->sarea_priv->pf_current_page); 739 740 i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH); 741 742 for (i = 0; i < 2; i++) 743 if (planes & (1 << i)) 744 i915_do_dispatch_flip(dev, i, sync); 745 746 i915_emit_breadcrumb(dev); 747#ifdef I915_HAVE_FENCE 748 if (unlikely(!sync && ((dev_priv->counter & 0xFF) == 0))) 749 drm_fence_flush_old(dev, 0, dev_priv->counter); 750#endif 751} 752 753int i915_quiescent(struct drm_device *dev) 754{ 755 drm_i915_private_t *dev_priv = dev->dev_private; 756 int ret; 757 758 i915_kernel_lost_context(dev); 759 ret = i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__); 760 if (ret) 761 { 762 i915_kernel_lost_context (dev); 763 DRM_ERROR ("not quiescent head %08x tail %08x space %08x\n", 764 dev_priv->ring.head, 765 dev_priv->ring.tail, 766 dev_priv->ring.space); 767 } 768 return ret; 769} 770 771static int i915_flush_ioctl(struct drm_device *dev, void *data, 772 struct drm_file *file_priv) 773{ 774 775 LOCK_TEST_WITH_RETURN(dev, file_priv); 776 777 return i915_quiescent(dev); 778} 779 780static int i915_batchbuffer(struct drm_device *dev, void *data, 781 struct drm_file *file_priv) 782{ 783 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 784 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 785 dev_priv->sarea_priv; 786 drm_i915_batchbuffer_t *batch = data; 787 int ret; 788 789 if (!dev_priv->allow_batchbuffer) { 790 DRM_ERROR("Batchbuffer ioctl disabled\n"); 791 return -EINVAL; 792 } 793 794 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n", 795 batch->start, batch->used, batch->num_cliprects); 796 797 LOCK_TEST_WITH_RETURN(dev, file_priv); 798 799 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects, 800 batch->num_cliprects * 801 sizeof(struct drm_clip_rect))) 802 return -EFAULT; 803 804 ret = i915_dispatch_batchbuffer(dev, batch); 805 806 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 807 return ret; 808} 809 810static int i915_cmdbuffer(struct drm_device *dev, void *data, 811 struct drm_file *file_priv) 812{ 813 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 814 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 815 dev_priv->sarea_priv; 816 drm_i915_cmdbuffer_t *cmdbuf = data; 817 int ret; 818 819 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n", 820 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); 821 822 LOCK_TEST_WITH_RETURN(dev, file_priv); 823 824 if (cmdbuf->num_cliprects && 825 DRM_VERIFYAREA_READ(cmdbuf->cliprects, 826 cmdbuf->num_cliprects * 827 sizeof(struct drm_clip_rect))) { 828 DRM_ERROR("Fault accessing cliprects\n"); 829 return -EFAULT; 830 } 831 832 ret = i915_dispatch_cmdbuffer(dev, cmdbuf); 833 if (ret) { 834 DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); 835 return ret; 836 } 837 838 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 839 return 0; 840} 841 842#if defined(DRM_DEBUG_CODE) 843#define DRM_DEBUG_RELOCATION (drm_debug != 0) 844#else 845#define DRM_DEBUG_RELOCATION 0 846#endif 847 848static int i915_do_cleanup_pageflip(struct drm_device * dev) 849{ 850 drm_i915_private_t *dev_priv = dev->dev_private; 851 int i, planes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2; 852 853 DRM_DEBUG("\n"); 854 855 for (i = 0, planes = 0; i < 2; i++) 856 if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) { 857 dev_priv->sarea_priv->pf_current_page = 858 (dev_priv->sarea_priv->pf_current_page & 859 ~(0x3 << (2 * i))) | ((num_pages - 1) << (2 * i)); 860 861 planes |= 1 << i; 862 } 863 864 if (planes) 865 i915_dispatch_flip(dev, planes, 0); 866 867 return 0; 868} 869 870static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv) 871{ 872 drm_i915_flip_t *param = data; 873 874 DRM_DEBUG("\n"); 875 876 LOCK_TEST_WITH_RETURN(dev, file_priv); 877 878 /* This is really planes */ 879 if (param->pipes & ~0x3) { 880 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n", 881 param->pipes); 882 return -EINVAL; 883 } 884 885 i915_dispatch_flip(dev, param->pipes, 0); 886 887 return 0; 888} 889 890 891static int i915_getparam(struct drm_device *dev, void *data, 892 struct drm_file *file_priv) 893{ 894 drm_i915_private_t *dev_priv = dev->dev_private; 895 drm_i915_getparam_t *param = data; 896 int value; 897 898 if (!dev_priv) { 899 DRM_ERROR("called with no initialization\n"); 900 return -EINVAL; 901 } 902 903 switch (param->param) { 904 case I915_PARAM_IRQ_ACTIVE: 905 value = dev->irq_enabled ? 1 : 0; 906 break; 907 case I915_PARAM_ALLOW_BATCHBUFFER: 908 value = dev_priv->allow_batchbuffer ? 1 : 0; 909 break; 910 case I915_PARAM_LAST_DISPATCH: 911 value = READ_BREADCRUMB(dev_priv); 912 break; 913 case I915_PARAM_CHIPSET_ID: 914 value = dev->pci_device; 915 break; 916 case I915_PARAM_HAS_GEM: 917 /* We need to reset this to 1 once we have GEM */ 918 value = 0; 919 break; 920 default: 921 DRM_ERROR("Unknown parameter %d\n", param->param); 922 return -EINVAL; 923 } 924 925 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { 926 DRM_ERROR("DRM_COPY_TO_USER failed\n"); 927 return -EFAULT; 928 } 929 930 return 0; 931} 932 933static int i915_setparam(struct drm_device *dev, void *data, 934 struct drm_file *file_priv) 935{ 936 drm_i915_private_t *dev_priv = dev->dev_private; 937 drm_i915_setparam_t *param = data; 938 939 if (!dev_priv) { 940 DRM_ERROR("called with no initialization\n"); 941 return -EINVAL; 942 } 943 944 switch (param->param) { 945 case I915_SETPARAM_USE_MI_BATCHBUFFER_START: 946 break; 947 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: 948 dev_priv->tex_lru_log_granularity = param->value; 949 break; 950 case I915_SETPARAM_ALLOW_BATCHBUFFER: 951 dev_priv->allow_batchbuffer = param->value; 952 break; 953 default: 954 DRM_ERROR("unknown parameter %d\n", param->param); 955 return -EINVAL; 956 } 957 958 return 0; 959} 960 961drm_i915_mmio_entry_t mmio_table[] = { 962 [MMIO_REGS_PS_DEPTH_COUNT] = { 963 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE, 964 0x2350, 965 8 966 } 967}; 968 969static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t); 970 971static int i915_mmio(struct drm_device *dev, void *data, 972 struct drm_file *file_priv) 973{ 974 uint32_t buf[8]; 975 drm_i915_private_t *dev_priv = dev->dev_private; 976 drm_i915_mmio_entry_t *e; 977 drm_i915_mmio_t *mmio = data; 978 void __iomem *base; 979 int i; 980 981 if (!dev_priv) { 982 DRM_ERROR("called with no initialization\n"); 983 return -EINVAL; 984 } 985 986 if (mmio->reg >= mmio_table_size) 987 return -EINVAL; 988 989 e = &mmio_table[mmio->reg]; 990 base = (u8 *) dev_priv->mmio_map->handle + e->offset; 991 992 switch (mmio->read_write) { 993 case I915_MMIO_READ: 994 if (!(e->flag & I915_MMIO_MAY_READ)) 995 return -EINVAL; 996 for (i = 0; i < e->size / 4; i++) 997 buf[i] = I915_READ(e->offset + i * 4); 998 if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) { 999 DRM_ERROR("DRM_COPY_TO_USER failed\n"); 1000 return -EFAULT; 1001 } 1002 break; 1003 1004 case I915_MMIO_WRITE: 1005 if (!(e->flag & I915_MMIO_MAY_WRITE)) 1006 return -EINVAL; 1007 if (DRM_COPY_FROM_USER(buf, mmio->data, e->size)) { 1008 DRM_ERROR("DRM_COPY_TO_USER failed\n"); 1009 return -EFAULT; 1010 } 1011 for (i = 0; i < e->size / 4; i++) 1012 I915_WRITE(e->offset + i * 4, buf[i]); 1013 break; 1014 } 1015 return 0; 1016} 1017 1018static int i915_set_status_page(struct drm_device *dev, void *data, 1019 struct drm_file *file_priv) 1020{ 1021 drm_i915_private_t *dev_priv = dev->dev_private; 1022 drm_i915_hws_addr_t *hws = data; 1023 1024 if (!I915_NEED_GFX_HWS(dev)) 1025 return -EINVAL; 1026 1027 if (!dev_priv) { 1028 DRM_ERROR("called with no initialization\n"); 1029 return -EINVAL; 1030 } 1031 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr); 1032 1033 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); 1034 1035 dev_priv->hws_map.offset = dev->agp->base + hws->addr; 1036 dev_priv->hws_map.size = 4*1024; 1037 dev_priv->hws_map.type = 0; 1038 dev_priv->hws_map.flags = 0; 1039 dev_priv->hws_map.mtrr = 0; 1040 1041 drm_core_ioremap(&dev_priv->hws_map, dev); 1042 if (dev_priv->hws_map.handle == NULL) { 1043 i915_dma_cleanup(dev); 1044 dev_priv->status_gfx_addr = 0; 1045 DRM_ERROR("can not ioremap virtual address for" 1046 " G33 hw status page\n"); 1047 return -ENOMEM; 1048 } 1049 dev_priv->hw_status_page = dev_priv->hws_map.handle; 1050 1051 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 1052 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); 1053 DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n", 1054 dev_priv->status_gfx_addr); 1055 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page); 1056 return 0; 1057} 1058 1059int i915_driver_load(struct drm_device *dev, unsigned long flags) 1060{ 1061 struct drm_i915_private *dev_priv; 1062 unsigned long base, size; 1063 int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1; 1064 1065 /* i915 has 4 more counters */ 1066 dev->counters += 4; 1067 dev->types[6] = _DRM_STAT_IRQ; 1068 dev->types[7] = _DRM_STAT_PRIMARY; 1069 dev->types[8] = _DRM_STAT_SECONDARY; 1070 dev->types[9] = _DRM_STAT_DMA; 1071 1072 dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER); 1073 if (dev_priv == NULL) 1074 return -ENOMEM; 1075 1076 memset(dev_priv, 0, sizeof(drm_i915_private_t)); 1077 1078 dev->dev_private = (void *)dev_priv; 1079 dev_priv->dev = dev; 1080 1081 /* Add register map (needed for suspend/resume) */ 1082 base = drm_get_resource_start(dev, mmio_bar); 1083 size = drm_get_resource_len(dev, mmio_bar); 1084 1085 ret = drm_addmap(dev, base, size, _DRM_REGISTERS, 1086 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map); 1087#ifdef I915_HAVE_GEM 1088 i915_gem_load(dev); 1089#endif 1090 DRM_SPININIT(&dev_priv->swaps_lock, "swap"); 1091 DRM_SPININIT(&dev_priv->user_irq_lock, "userirq"); 1092 1093#ifdef __linux__ 1094#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) 1095 intel_init_chipset_flush_compat(dev); 1096#endif 1097#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25) 1098 intel_opregion_init(dev); 1099#endif 1100#endif 1101 1102 /* Init HWS */ 1103 if (!I915_NEED_GFX_HWS(dev)) { 1104 ret = i915_init_hardware_status(dev); 1105 if(ret) 1106 return ret; 1107 } 1108 1109 return ret; 1110} 1111 1112int i915_driver_unload(struct drm_device *dev) 1113{ 1114 struct drm_i915_private *dev_priv = dev->dev_private; 1115 1116 i915_free_hardware_status(dev); 1117 1118 drm_rmmap(dev, dev_priv->mmio_map); 1119 1120 DRM_SPINUNINIT(&dev_priv->swaps_lock); 1121 DRM_SPINUNINIT(&dev_priv->user_irq_lock); 1122 1123#ifdef __linux__ 1124#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,25) 1125 intel_opregion_free(dev); 1126#endif 1127#endif 1128 1129 drm_free(dev->dev_private, sizeof(drm_i915_private_t), 1130 DRM_MEM_DRIVER); 1131 dev->dev_private = NULL; 1132 1133#ifdef __linux__ 1134#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) 1135 intel_fini_chipset_flush_compat(dev); 1136#endif 1137#endif 1138 return 0; 1139} 1140 1141void i915_driver_lastclose(struct drm_device * dev) 1142{ 1143 drm_i915_private_t *dev_priv = dev->dev_private; 1144 1145 /* agp off can use this to get called before dev_priv */ 1146 if (!dev_priv) 1147 return; 1148 1149#ifdef I915_HAVE_BUFFER 1150 if (dev_priv->val_bufs) { 1151 vfree(dev_priv->val_bufs); 1152 dev_priv->val_bufs = NULL; 1153 } 1154#endif 1155#ifdef I915_HAVE_GEM 1156 i915_gem_lastclose(dev); 1157#endif 1158 if (drm_getsarea(dev) && dev_priv->sarea_priv) 1159 i915_do_cleanup_pageflip(dev); 1160 if (dev_priv->sarea_priv) 1161 dev_priv->sarea_priv = NULL; 1162 if (dev_priv->agp_heap) 1163 i915_mem_takedown(&(dev_priv->agp_heap)); 1164#if defined(I915_HAVE_BUFFER) 1165 if (dev_priv->sarea_kmap.virtual) { 1166 drm_bo_kunmap(&dev_priv->sarea_kmap); 1167 dev_priv->sarea_kmap.virtual = NULL; 1168 dev->lock.hw_lock = NULL; 1169 dev->sigdata.lock = NULL; 1170 } 1171 1172 if (dev_priv->sarea_bo) { 1173 mutex_lock(&dev->struct_mutex); 1174 drm_bo_usage_deref_locked(&dev_priv->sarea_bo); 1175 mutex_unlock(&dev->struct_mutex); 1176 dev_priv->sarea_bo = NULL; 1177 } 1178#endif 1179 i915_dma_cleanup(dev); 1180} 1181 1182int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1183{ 1184 struct drm_i915_file_private *i915_file_priv; 1185 1186 DRM_DEBUG("\n"); 1187 i915_file_priv = (struct drm_i915_file_private *) 1188 drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES); 1189 1190 if (!i915_file_priv) 1191 return -ENOMEM; 1192 1193 file_priv->driver_priv = i915_file_priv; 1194 1195 i915_file_priv->mm.last_gem_seqno = 0; 1196 i915_file_priv->mm.last_gem_throttle_seqno = 0; 1197 1198 return 0; 1199} 1200 1201void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) 1202{ 1203 drm_i915_private_t *dev_priv = dev->dev_private; 1204 i915_mem_release(dev, file_priv, dev_priv->agp_heap); 1205} 1206 1207void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) 1208{ 1209 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; 1210 1211 drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES); 1212} 1213 1214struct drm_ioctl_desc i915_ioctls[] = { 1215 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1216 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), 1217 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), 1218 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), 1219 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), 1220 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), 1221 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), 1222 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1223 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), 1224 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), 1225 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1226 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), 1227 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), 1228 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), 1229 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), 1230 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), 1231 DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH), 1232 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1233#ifdef I915_HAVE_BUFFER 1234 DRM_IOCTL_DEF(DRM_I915_EXECBUFFER, i915_execbuffer, DRM_AUTH), 1235#endif 1236#ifdef I915_HAVE_GEM 1237 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH), 1238 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), 1239 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1240 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1241 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH), 1242 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH), 1243 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH), 1244 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH), 1245 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0), 1246 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0), 1247 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0), 1248 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0), 1249 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0), 1250 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0), 1251 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0), 1252 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0), 1253#endif 1254}; 1255 1256int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); 1257 1258/** 1259 * Determine if the device really is AGP or not. 1260 * 1261 * All Intel graphics chipsets are treated as AGP, even if they are really 1262 * PCI-e. 1263 * 1264 * \param dev The device to be tested. 1265 * 1266 * \returns 1267 * A value of 1 is always retured to indictate every i9x5 is AGP. 1268 */ 1269int i915_driver_device_is_agp(struct drm_device * dev) 1270{ 1271 return 1; 1272} 1273 1274int i915_driver_firstopen(struct drm_device *dev) 1275{ 1276#ifdef I915_HAVE_BUFFER 1277 drm_bo_driver_init(dev); 1278#endif 1279 return 0; 1280} 1281