i915_dma.c revision 189130
1/* i915_dma.c -- DMA support for the I915 -*- linux-c -*- 2 */ 3/*- 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: head/sys/dev/drm/i915_dma.c 189130 2009-02-28 02:37:55Z rnoland $"); 31 32#include "dev/drm/drmP.h" 33#include "dev/drm/drm.h" 34#include "dev/drm/i915_drm.h" 35#include "dev/drm/i915_drv.h" 36 37/* Really want an OS-independent resettable timer. Would like to have 38 * this loop run for (eg) 3 sec, but have the timer reset every time 39 * the head pointer changes, so that EBUSY only happens if the ring 40 * actually stalls for (eg) 3 seconds. 41 */ 42int i915_wait_ring(struct drm_device * dev, int n, const char *caller) 43{ 44 drm_i915_private_t *dev_priv = dev->dev_private; 45 drm_i915_ring_buffer_t *ring = &(dev_priv->ring); 46 u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR; 47 u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD; 48 u32 last_acthd = I915_READ(acthd_reg); 49 u32 acthd; 50 int i; 51 52 for (i = 0; i < 100000; i++) { 53 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; 54 acthd = I915_READ(acthd_reg); 55 ring->space = ring->head - (ring->tail + 8); 56 if (ring->space < 0) 57 ring->space += ring->Size; 58 if (ring->space >= n) 59 return 0; 60 61 if (dev_priv->sarea_priv) 62 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; 63 64 if (ring->head != last_head) 65 i = 0; 66 67 if (acthd != last_acthd) 68 i = 0; 69 70 last_head = ring->head; 71 last_acthd = acthd; 72 DRM_UDELAY(10 * 1000); 73 } 74 75 return -EBUSY; 76} 77 78/** 79 * Sets up the hardware status page for devices that need a physical address 80 * in the register. 81 */ 82static int i915_init_phys_hws(struct drm_device *dev) 83{ 84 drm_i915_private_t *dev_priv = dev->dev_private; 85 86 /* Program Hardware Status Page */ 87 DRM_UNLOCK(); 88 dev_priv->status_page_dmah = 89 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff); 90 DRM_LOCK(); 91 if (!dev_priv->status_page_dmah) { 92 DRM_ERROR("Can not allocate hardware status page\n"); 93 return -ENOMEM; 94 } 95 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; 96 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; 97 98 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 99 100 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); 101 DRM_DEBUG("Enabled hardware status page\n"); 102 return 0; 103} 104 105/** 106 * Frees the hardware status page, whether it's a physical address or a virtual 107 * address set up by the X Server. 108 */ 109static void i915_free_hws(struct drm_device *dev) 110{ 111 drm_i915_private_t *dev_priv = dev->dev_private; 112 if (dev_priv->status_page_dmah) { 113 drm_pci_free(dev, dev_priv->status_page_dmah); 114 dev_priv->status_page_dmah = NULL; 115 } 116 117 if (dev_priv->status_gfx_addr) { 118 dev_priv->status_gfx_addr = 0; 119 drm_core_ioremapfree(&dev_priv->hws_map, dev); 120 } 121 122 /* Need to rewrite hardware status page */ 123 I915_WRITE(HWS_PGA, 0x1ffff000); 124} 125 126void i915_kernel_lost_context(struct drm_device * dev) 127{ 128 drm_i915_private_t *dev_priv = dev->dev_private; 129 drm_i915_ring_buffer_t *ring = &(dev_priv->ring); 130 131 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; 132 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; 133 ring->space = ring->head - (ring->tail + 8); 134 if (ring->space < 0) 135 ring->space += ring->Size; 136 137 if (ring->head == ring->tail && dev_priv->sarea_priv) 138 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; 139} 140 141static int i915_dma_cleanup(struct drm_device * dev) 142{ 143 drm_i915_private_t *dev_priv = dev->dev_private; 144 /* Make sure interrupts are disabled here because the uninstall ioctl 145 * may not have been called from userspace and after dev_private 146 * is freed, it's too late. 147 */ 148 if (dev->irq_enabled) 149 drm_irq_uninstall(dev); 150 151 if (dev_priv->ring.virtual_start) { 152 drm_core_ioremapfree(&dev_priv->ring.map, dev); 153 dev_priv->ring.virtual_start = NULL; 154 dev_priv->ring.map.handle = NULL; 155 dev_priv->ring.map.size = 0; 156 } 157 158 /* Clear the HWS virtual address at teardown */ 159 if (I915_NEED_GFX_HWS(dev)) 160 i915_free_hws(dev); 161 162 return 0; 163} 164 165static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init) 166{ 167 drm_i915_private_t *dev_priv = dev->dev_private; 168 169 dev_priv->sarea = drm_getsarea(dev); 170 if (!dev_priv->sarea) { 171 DRM_ERROR("can not find sarea!\n"); 172 i915_dma_cleanup(dev); 173 return -EINVAL; 174 } 175 176 dev_priv->sarea_priv = (drm_i915_sarea_t *) 177 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); 178 179 if (init->ring_size != 0) { 180 if (dev_priv->ring.ring_obj != NULL) { 181 i915_dma_cleanup(dev); 182 DRM_ERROR("Client tried to initialize ringbuffer in " 183 "GEM mode\n"); 184 return -EINVAL; 185 } 186 187 dev_priv->ring.Size = init->ring_size; 188 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; 189 190 dev_priv->ring.map.offset = init->ring_start; 191 dev_priv->ring.map.size = init->ring_size; 192 dev_priv->ring.map.type = 0; 193 dev_priv->ring.map.flags = 0; 194 dev_priv->ring.map.mtrr = 0; 195 196 drm_core_ioremap(&dev_priv->ring.map, dev); 197 198 if (dev_priv->ring.map.handle == NULL) { 199 i915_dma_cleanup(dev); 200 DRM_ERROR("can not ioremap virtual address for" 201 " ring buffer\n"); 202 return -ENOMEM; 203 } 204 } 205 206 dev_priv->ring.virtual_start = dev_priv->ring.map.handle; 207 208 dev_priv->cpp = init->cpp; 209 dev_priv->back_offset = init->back_offset; 210 dev_priv->front_offset = init->front_offset; 211 dev_priv->current_page = 0; 212 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; 213 214 /* Allow hardware batchbuffers unless told otherwise. 215 */ 216 dev_priv->allow_batchbuffer = 1; 217 218 return 0; 219} 220 221static int i915_dma_resume(struct drm_device * dev) 222{ 223 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 224 225 DRM_DEBUG("\n"); 226 227 if (!dev_priv->sarea) { 228 DRM_ERROR("can not find sarea!\n"); 229 return -EINVAL; 230 } 231 232 if (dev_priv->ring.map.handle == NULL) { 233 DRM_ERROR("can not ioremap virtual address for" 234 " ring buffer\n"); 235 return -ENOMEM; 236 } 237 238 /* Program Hardware Status Page */ 239 if (!dev_priv->hw_status_page) { 240 DRM_ERROR("Can not find hardware status page\n"); 241 return -EINVAL; 242 } 243 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); 244 245 if (dev_priv->status_gfx_addr != 0) 246 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); 247 else 248 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); 249 DRM_DEBUG("Enabled hardware status page\n"); 250 251 return 0; 252} 253 254static int i915_dma_init(struct drm_device *dev, void *data, 255 struct drm_file *file_priv) 256{ 257 drm_i915_init_t *init = data; 258 int retcode = 0; 259 260 switch (init->func) { 261 case I915_INIT_DMA: 262 retcode = i915_initialize(dev, init); 263 break; 264 case I915_CLEANUP_DMA: 265 retcode = i915_dma_cleanup(dev); 266 break; 267 case I915_RESUME_DMA: 268 retcode = i915_dma_resume(dev); 269 break; 270 default: 271 retcode = -EINVAL; 272 break; 273 } 274 275 return retcode; 276} 277 278/* Implement basically the same security restrictions as hardware does 279 * for MI_BATCH_NON_SECURE. These can be made stricter at any time. 280 * 281 * Most of the calculations below involve calculating the size of a 282 * particular instruction. It's important to get the size right as 283 * that tells us where the next instruction to check is. Any illegal 284 * instruction detected will be given a size of zero, which is a 285 * signal to abort the rest of the buffer. 286 */ 287static int do_validate_cmd(int cmd) 288{ 289 switch (((cmd >> 29) & 0x7)) { 290 case 0x0: 291 switch ((cmd >> 23) & 0x3f) { 292 case 0x0: 293 return 1; /* MI_NOOP */ 294 case 0x4: 295 return 1; /* MI_FLUSH */ 296 default: 297 return 0; /* disallow everything else */ 298 } 299 break; 300 case 0x1: 301 return 0; /* reserved */ 302 case 0x2: 303 return (cmd & 0xff) + 2; /* 2d commands */ 304 case 0x3: 305 if (((cmd >> 24) & 0x1f) <= 0x18) 306 return 1; 307 308 switch ((cmd >> 24) & 0x1f) { 309 case 0x1c: 310 return 1; 311 case 0x1d: 312 switch ((cmd >> 16) & 0xff) { 313 case 0x3: 314 return (cmd & 0x1f) + 2; 315 case 0x4: 316 return (cmd & 0xf) + 2; 317 default: 318 return (cmd & 0xffff) + 2; 319 } 320 case 0x1e: 321 if (cmd & (1 << 23)) 322 return (cmd & 0xffff) + 1; 323 else 324 return 1; 325 case 0x1f: 326 if ((cmd & (1 << 23)) == 0) /* inline vertices */ 327 return (cmd & 0x1ffff) + 2; 328 else if (cmd & (1 << 17)) /* indirect random */ 329 if ((cmd & 0xffff) == 0) 330 return 0; /* unknown length, too hard */ 331 else 332 return (((cmd & 0xffff) + 1) / 2) + 1; 333 else 334 return 2; /* indirect sequential */ 335 default: 336 return 0; 337 } 338 default: 339 return 0; 340 } 341 342 return 0; 343} 344 345static int validate_cmd(int cmd) 346{ 347 int ret = do_validate_cmd(cmd); 348 349/* printk("validate_cmd( %x ): %d\n", cmd, ret); */ 350 351 return ret; 352} 353 354static int i915_emit_cmds(struct drm_device *dev, int __user *buffer, 355 int dwords) 356{ 357 drm_i915_private_t *dev_priv = dev->dev_private; 358 int i; 359 RING_LOCALS; 360 361 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) 362 return -EINVAL; 363 364 BEGIN_LP_RING((dwords+1)&~1); 365 366 for (i = 0; i < dwords;) { 367 int cmd, sz; 368 369 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) 370 return -EINVAL; 371 372 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) 373 return -EINVAL; 374 375 OUT_RING(cmd); 376 377 while (++i, --sz) { 378 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], 379 sizeof(cmd))) { 380 return -EINVAL; 381 } 382 OUT_RING(cmd); 383 } 384 } 385 386 if (dwords & 1) 387 OUT_RING(0); 388 389 ADVANCE_LP_RING(); 390 391 return 0; 392} 393 394int i915_emit_box(struct drm_device * dev, 395 struct drm_clip_rect __user * boxes, 396 int i, int DR1, int DR4) 397{ 398 drm_i915_private_t *dev_priv = dev->dev_private; 399 struct drm_clip_rect box; 400 RING_LOCALS; 401 402 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) { 403 return -EFAULT; 404 } 405 406 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) { 407 DRM_ERROR("Bad box %d,%d..%d,%d\n", 408 box.x1, box.y1, box.x2, box.y2); 409 return -EINVAL; 410 } 411 412 if (IS_I965G(dev)) { 413 BEGIN_LP_RING(4); 414 OUT_RING(GFX_OP_DRAWRECT_INFO_I965); 415 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); 416 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); 417 OUT_RING(DR4); 418 ADVANCE_LP_RING(); 419 } else { 420 BEGIN_LP_RING(6); 421 OUT_RING(GFX_OP_DRAWRECT_INFO); 422 OUT_RING(DR1); 423 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); 424 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16)); 425 OUT_RING(DR4); 426 OUT_RING(0); 427 ADVANCE_LP_RING(); 428 } 429 430 return 0; 431} 432 433/* XXX: Emitting the counter should really be moved to part of the IRQ 434 * emit. For now, do it in both places: 435 */ 436 437static void i915_emit_breadcrumb(struct drm_device *dev) 438{ 439 drm_i915_private_t *dev_priv = dev->dev_private; 440 RING_LOCALS; 441 442 dev_priv->counter++; 443 if (dev_priv->counter > 0x7FFFFFFFUL) 444 dev_priv->counter = 0; 445 if (dev_priv->sarea_priv) 446 dev_priv->sarea_priv->last_enqueue = dev_priv->counter; 447 448 BEGIN_LP_RING(4); 449 OUT_RING(MI_STORE_DWORD_INDEX); 450 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 451 OUT_RING(dev_priv->counter); 452 OUT_RING(0); 453 ADVANCE_LP_RING(); 454} 455 456static int i915_dispatch_cmdbuffer(struct drm_device * dev, 457 drm_i915_cmdbuffer_t * cmd) 458{ 459 int nbox = cmd->num_cliprects; 460 int i = 0, count, ret; 461 462 if (cmd->sz & 0x3) { 463 DRM_ERROR("alignment\n"); 464 return -EINVAL; 465 } 466 467 i915_kernel_lost_context(dev); 468 469 count = nbox ? nbox : 1; 470 471 for (i = 0; i < count; i++) { 472 if (i < nbox) { 473 ret = i915_emit_box(dev, cmd->cliprects, i, 474 cmd->DR1, cmd->DR4); 475 if (ret) 476 return ret; 477 } 478 479 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4); 480 if (ret) 481 return ret; 482 } 483 484 i915_emit_breadcrumb(dev); 485 return 0; 486} 487 488static int i915_dispatch_batchbuffer(struct drm_device * dev, 489 drm_i915_batchbuffer_t * batch) 490{ 491 drm_i915_private_t *dev_priv = dev->dev_private; 492 struct drm_clip_rect __user *boxes = batch->cliprects; 493 int nbox = batch->num_cliprects; 494 int i = 0, count; 495 RING_LOCALS; 496 497 if ((batch->start | batch->used) & 0x7) { 498 DRM_ERROR("alignment\n"); 499 return -EINVAL; 500 } 501 502 i915_kernel_lost_context(dev); 503 504 count = nbox ? nbox : 1; 505 506 for (i = 0; i < count; i++) { 507 if (i < nbox) { 508 int ret = i915_emit_box(dev, boxes, i, 509 batch->DR1, batch->DR4); 510 if (ret) 511 return ret; 512 } 513 514 if (!IS_I830(dev) && !IS_845G(dev)) { 515 BEGIN_LP_RING(2); 516 if (IS_I965G(dev)) { 517 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); 518 OUT_RING(batch->start); 519 } else { 520 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); 521 OUT_RING(batch->start | MI_BATCH_NON_SECURE); 522 } 523 ADVANCE_LP_RING(); 524 } else { 525 BEGIN_LP_RING(4); 526 OUT_RING(MI_BATCH_BUFFER); 527 OUT_RING(batch->start | MI_BATCH_NON_SECURE); 528 OUT_RING(batch->start + batch->used - 4); 529 OUT_RING(0); 530 ADVANCE_LP_RING(); 531 } 532 } 533 534 i915_emit_breadcrumb(dev); 535 536 return 0; 537} 538 539static int i915_dispatch_flip(struct drm_device * dev) 540{ 541 drm_i915_private_t *dev_priv = dev->dev_private; 542 RING_LOCALS; 543 544 if (!dev_priv->sarea_priv) 545 return -EINVAL; 546 547 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", 548 __func__, 549 dev_priv->current_page, 550 dev_priv->sarea_priv->pf_current_page); 551 552 i915_kernel_lost_context(dev); 553 554 BEGIN_LP_RING(2); 555 OUT_RING(MI_FLUSH | MI_READ_FLUSH); 556 OUT_RING(0); 557 ADVANCE_LP_RING(); 558 559 BEGIN_LP_RING(6); 560 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); 561 OUT_RING(0); 562 if (dev_priv->current_page == 0) { 563 OUT_RING(dev_priv->back_offset); 564 dev_priv->current_page = 1; 565 } else { 566 OUT_RING(dev_priv->front_offset); 567 dev_priv->current_page = 0; 568 } 569 OUT_RING(0); 570 ADVANCE_LP_RING(); 571 572 BEGIN_LP_RING(2); 573 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); 574 OUT_RING(0); 575 ADVANCE_LP_RING(); 576 577 dev_priv->sarea_priv->last_enqueue = dev_priv->counter++; 578 579 BEGIN_LP_RING(4); 580 OUT_RING(MI_STORE_DWORD_INDEX); 581 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 582 OUT_RING(dev_priv->counter); 583 OUT_RING(0); 584 ADVANCE_LP_RING(); 585 586 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; 587 return 0; 588} 589 590static int i915_quiescent(struct drm_device * dev) 591{ 592 drm_i915_private_t *dev_priv = dev->dev_private; 593 594 i915_kernel_lost_context(dev); 595 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__); 596} 597 598static int i915_flush_ioctl(struct drm_device *dev, void *data, 599 struct drm_file *file_priv) 600{ 601 int ret; 602 603 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 604 605 ret = i915_quiescent(dev); 606 607 return ret; 608} 609 610static int i915_batchbuffer(struct drm_device *dev, void *data, 611 struct drm_file *file_priv) 612{ 613 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 614 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 615 dev_priv->sarea_priv; 616 drm_i915_batchbuffer_t *batch = data; 617 size_t cliplen; 618 int ret; 619 620 if (!dev_priv->allow_batchbuffer) { 621 DRM_ERROR("Batchbuffer ioctl disabled\n"); 622 return -EINVAL; 623 } 624 625 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n", 626 batch->start, batch->used, batch->num_cliprects); 627 628 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 629 630 DRM_UNLOCK(); 631 cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect); 632 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects, 633 cliplen)) { 634 DRM_LOCK(); 635 return -EFAULT; 636 } 637 if (batch->num_cliprects) { 638 ret = vslock(batch->cliprects, cliplen); 639 if (ret) { 640 DRM_ERROR("Fault wiring cliprects\n"); 641 DRM_LOCK(); 642 return -EFAULT; 643 } 644 } 645 DRM_LOCK(); 646 647 ret = i915_dispatch_batchbuffer(dev, batch); 648 649 if (sarea_priv) 650 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 651 652 DRM_UNLOCK(); 653 if (batch->num_cliprects) 654 vsunlock(batch->cliprects, cliplen); 655 DRM_LOCK(); 656 657 return ret; 658} 659 660static int i915_cmdbuffer(struct drm_device *dev, void *data, 661 struct drm_file *file_priv) 662{ 663 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 664 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 665 dev_priv->sarea_priv; 666 drm_i915_cmdbuffer_t *cmdbuf = data; 667 size_t cliplen; 668 int ret; 669 670 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n", 671 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); 672 673 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 674 675 DRM_UNLOCK(); 676 cliplen = cmdbuf->num_cliprects * sizeof(struct drm_clip_rect); 677 if (cmdbuf->num_cliprects && DRM_VERIFYAREA_READ(cmdbuf->cliprects, 678 cliplen)) { 679 DRM_ERROR("Fault accessing cliprects\n"); 680 DRM_LOCK(); 681 return -EFAULT; 682 } 683 if (cmdbuf->num_cliprects) { 684 ret = vslock(cmdbuf->cliprects, cliplen); 685 if (ret) { 686 DRM_ERROR("Fault wiring cliprects\n"); 687 DRM_LOCK(); 688 return -EFAULT; 689 } 690 ret = vslock(cmdbuf->buf, cmdbuf->sz); 691 if (ret) { 692 vsunlock(cmdbuf->cliprects, cliplen); 693 DRM_ERROR("Fault wiring cmds\n"); 694 DRM_LOCK(); 695 return -EFAULT; 696 } 697 } 698 DRM_LOCK(); 699 700 ret = i915_dispatch_cmdbuffer(dev, cmdbuf); 701 DRM_UNLOCK(); 702 if (cmdbuf->num_cliprects) { 703 vsunlock(cmdbuf->buf, cmdbuf->sz); 704 vsunlock(cmdbuf->cliprects, cliplen); 705 } 706 DRM_LOCK(); 707 if (ret) { 708 DRM_ERROR("i915_dispatch_cmdbuffer failed\n"); 709 return ret; 710 } 711 712 if (sarea_priv) 713 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 714 return 0; 715} 716 717static int i915_flip_bufs(struct drm_device *dev, void *data, 718 struct drm_file *file_priv) 719{ 720 int ret; 721 722 DRM_DEBUG("%s\n", __func__); 723 724 LOCK_TEST_WITH_RETURN(dev, file_priv); 725 726 ret = i915_dispatch_flip(dev); 727 728 return ret; 729} 730 731static int i915_getparam(struct drm_device *dev, void *data, 732 struct drm_file *file_priv) 733{ 734 drm_i915_private_t *dev_priv = dev->dev_private; 735 drm_i915_getparam_t *param = data; 736 int value; 737 738 if (!dev_priv) { 739 DRM_ERROR("called with no initialization\n"); 740 return -EINVAL; 741 } 742 743 switch (param->param) { 744 case I915_PARAM_IRQ_ACTIVE: 745 value = dev->irq_enabled ? 1 : 0; 746 break; 747 case I915_PARAM_ALLOW_BATCHBUFFER: 748 value = dev_priv->allow_batchbuffer ? 1 : 0; 749 break; 750 case I915_PARAM_LAST_DISPATCH: 751 value = READ_BREADCRUMB(dev_priv); 752 break; 753 case I915_PARAM_CHIPSET_ID: 754 value = dev->pci_device; 755 break; 756 case I915_PARAM_HAS_GEM: 757 /* We need to reset this to 1 once we have GEM */ 758 value = 0; 759 break; 760 default: 761 DRM_ERROR("Unknown parameter %d\n", param->param); 762 return -EINVAL; 763 } 764 765 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { 766 DRM_ERROR("DRM_COPY_TO_USER failed\n"); 767 return -EFAULT; 768 } 769 770 return 0; 771} 772 773static int i915_setparam(struct drm_device *dev, void *data, 774 struct drm_file *file_priv) 775{ 776 drm_i915_private_t *dev_priv = dev->dev_private; 777 drm_i915_setparam_t *param = data; 778 779 if (!dev_priv) { 780 DRM_ERROR("called with no initialization\n"); 781 return -EINVAL; 782 } 783 784 switch (param->param) { 785 case I915_SETPARAM_USE_MI_BATCHBUFFER_START: 786 break; 787 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: 788 dev_priv->tex_lru_log_granularity = param->value; 789 break; 790 case I915_SETPARAM_ALLOW_BATCHBUFFER: 791 dev_priv->allow_batchbuffer = param->value; 792 break; 793 default: 794 DRM_ERROR("unknown parameter %d\n", param->param); 795 return -EINVAL; 796 } 797 798 return 0; 799} 800 801static int i915_set_status_page(struct drm_device *dev, void *data, 802 struct drm_file *file_priv) 803{ 804 drm_i915_private_t *dev_priv = dev->dev_private; 805 drm_i915_hws_addr_t *hws = data; 806 807 if (!I915_NEED_GFX_HWS(dev)) 808 return -EINVAL; 809 810 if (!dev_priv) { 811 DRM_ERROR("called with no initialization\n"); 812 return -EINVAL; 813 } 814 815 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr); 816 817 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); 818 819 dev_priv->hws_map.offset = dev->agp->base + hws->addr; 820 dev_priv->hws_map.size = 4*1024; 821 dev_priv->hws_map.type = 0; 822 dev_priv->hws_map.flags = 0; 823 dev_priv->hws_map.mtrr = 0; 824 825 drm_core_ioremap(&dev_priv->hws_map, dev); 826 if (dev_priv->hws_map.handle == NULL) { 827 i915_dma_cleanup(dev); 828 dev_priv->status_gfx_addr = 0; 829 DRM_ERROR("can not ioremap virtual address for" 830 " G33 hw status page\n"); 831 return -ENOMEM; 832 } 833 dev_priv->hw_status_page = dev_priv->hws_map.handle; 834 835 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 836 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); 837 DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n", 838 dev_priv->status_gfx_addr); 839 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page); 840 return 0; 841} 842 843int i915_driver_load(struct drm_device *dev, unsigned long flags) 844{ 845 struct drm_i915_private *dev_priv = dev->dev_private; 846 unsigned long base, size; 847 int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1; 848 849 /* i915 has 4 more counters */ 850 dev->counters += 4; 851 dev->types[6] = _DRM_STAT_IRQ; 852 dev->types[7] = _DRM_STAT_PRIMARY; 853 dev->types[8] = _DRM_STAT_SECONDARY; 854 dev->types[9] = _DRM_STAT_DMA; 855 856 dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER); 857 if (dev_priv == NULL) 858 return -ENOMEM; 859 860 memset(dev_priv, 0, sizeof(drm_i915_private_t)); 861 862 dev->dev_private = (void *)dev_priv; 863 dev_priv->dev = dev; 864 865 /* Add register map (needed for suspend/resume) */ 866 base = drm_get_resource_start(dev, mmio_bar); 867 size = drm_get_resource_len(dev, mmio_bar); 868 869 ret = drm_addmap(dev, base, size, _DRM_REGISTERS, 870 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map); 871 872 if (IS_GM45(dev)) 873 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 874 else 875 dev->driver->get_vblank_counter = i915_get_vblank_counter; 876 877#ifdef I915_HAVE_GEM 878 i915_gem_load(dev); 879#endif 880 /* Init HWS */ 881 if (!I915_NEED_GFX_HWS(dev)) { 882 ret = i915_init_phys_hws(dev); 883 if (ret != 0) 884 return ret; 885 } 886#ifdef __linux__ 887 /* On the 945G/GM, the chipset reports the MSI capability on the 888 * integrated graphics even though the support isn't actually there 889 * according to the published specs. It doesn't appear to function 890 * correctly in testing on 945G. 891 * This may be a side effect of MSI having been made available for PEG 892 * and the registers being closely associated. 893 * 894 * According to chipset errata, on the 965GM, MSI interrupts may 895 * be lost or delayed 896 */ 897 if (!IS_I945G(dev) && !IS_I945GM(dev) && !IS_I965GM(dev)) 898 if (pci_enable_msi(dev->pdev)) 899 DRM_ERROR("failed to enable MSI\n"); 900 901 intel_opregion_init(dev); 902#endif 903 DRM_SPININIT(&dev_priv->user_irq_lock, "userirq"); 904 905 ret = drm_vblank_init(dev, I915_NUM_PIPE); 906 907 if (ret) { 908 (void) i915_driver_unload(dev); 909 return ret; 910 } 911 912 return ret; 913} 914 915int i915_driver_unload(struct drm_device *dev) 916{ 917 struct drm_i915_private *dev_priv = dev->dev_private; 918 919 i915_free_hws(dev); 920 921 drm_rmmap(dev, dev_priv->mmio_map); 922#ifdef __linux__ 923 intel_opregion_free(dev); 924#endif 925 DRM_SPINUNINIT(&dev_priv->user_irq_lock); 926 927 drm_free(dev->dev_private, sizeof(drm_i915_private_t), 928 DRM_MEM_DRIVER); 929 930 return 0; 931} 932 933int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) 934{ 935 struct drm_i915_file_private *i915_file_priv; 936 937 DRM_DEBUG("\n"); 938 i915_file_priv = (struct drm_i915_file_private *) 939 drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES); 940 941 if (!i915_file_priv) 942 return -ENOMEM; 943 944 file_priv->driver_priv = i915_file_priv; 945 946 i915_file_priv->mm.last_gem_seqno = 0; 947 i915_file_priv->mm.last_gem_throttle_seqno = 0; 948 949 return 0; 950} 951 952void i915_driver_lastclose(struct drm_device * dev) 953{ 954 drm_i915_private_t *dev_priv = dev->dev_private; 955 956 if (!dev_priv) 957 return; 958#ifdef I915_HAVE_GEM 959 i915_gem_lastclose(dev); 960#endif 961 if (dev_priv->agp_heap) 962 i915_mem_takedown(&(dev_priv->agp_heap)); 963 964 i915_dma_cleanup(dev); 965} 966 967void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) 968{ 969 drm_i915_private_t *dev_priv = dev->dev_private; 970 i915_mem_release(dev, file_priv, dev_priv->agp_heap); 971} 972 973void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) 974{ 975 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; 976 977 drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES); 978} 979 980struct drm_ioctl_desc i915_ioctls[] = { 981 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 982 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), 983 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), 984 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), 985 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), 986 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), 987 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), 988 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 989 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), 990 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), 991 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 992 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), 993 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), 994 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), 995 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), 996 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), 997 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 998#ifdef I915_HAVE_GEM 999 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1000 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), 1001 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1002 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1003 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH), 1004 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH), 1005 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1006 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1007 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0), 1008 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0), 1009 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0), 1010 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0), 1011 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0), 1012 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0), 1013 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0), 1014 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0), 1015#endif 1016}; 1017 1018int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); 1019 1020/** 1021 * Determine if the device really is AGP or not. 1022 * 1023 * All Intel graphics chipsets are treated as AGP, even if they are really 1024 * PCI-e. 1025 * 1026 * \param dev The device to be tested. 1027 * 1028 * \returns 1029 * A value of 1 is always retured to indictate every i9x5 is AGP. 1030 */ 1031int i915_driver_device_is_agp(struct drm_device * dev) 1032{ 1033 return 1; 1034} 1035