1296177Sjhibbits/*-
2296177Sjhibbits * Copyright (c) 2011-2012 Semihalf.
3296177Sjhibbits * All rights reserved.
4296177Sjhibbits *
5296177Sjhibbits * Redistribution and use in source and binary forms, with or without
6296177Sjhibbits * modification, are permitted provided that the following conditions
7296177Sjhibbits * are met:
8296177Sjhibbits * 1. Redistributions of source code must retain the above copyright
9296177Sjhibbits *    notice, this list of conditions and the following disclaimer.
10296177Sjhibbits * 2. Redistributions in binary form must reproduce the above copyright
11296177Sjhibbits *    notice, this list of conditions and the following disclaimer in the
12296177Sjhibbits *    documentation and/or other materials provided with the distribution.
13296177Sjhibbits *
14296177Sjhibbits * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15296177Sjhibbits * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16296177Sjhibbits * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17296177Sjhibbits * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18296177Sjhibbits * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19296177Sjhibbits * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20296177Sjhibbits * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21296177Sjhibbits * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22296177Sjhibbits * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23296177Sjhibbits * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24296177Sjhibbits * SUCH DAMAGE.
25296177Sjhibbits *
26296177Sjhibbits * $FreeBSD$
27296177Sjhibbits */
28296177Sjhibbits
29296177Sjhibbits#ifndef IF_DTSEC_H_
30296177Sjhibbits#define IF_DTSEC_H_
31296177Sjhibbits
32296177Sjhibbits/**
33296177Sjhibbits * @group dTSEC common API.
34296177Sjhibbits * @{
35296177Sjhibbits */
36296177Sjhibbits#define DTSEC_MODE_REGULAR		0
37296177Sjhibbits#define DTSEC_MODE_INDEPENDENT		1
38296177Sjhibbits
39296177Sjhibbits#define DTSEC_LOCK(sc)			mtx_lock(&(sc)->sc_lock)
40296177Sjhibbits#define DTSEC_UNLOCK(sc)		mtx_unlock(&(sc)->sc_lock)
41296177Sjhibbits#define DTSEC_LOCK_ASSERT(sc)		mtx_assert(&(sc)->sc_lock, MA_OWNED)
42296177Sjhibbits#define DTSEC_MII_LOCK(sc)		mtx_lock(&(sc)->sc_mii_lock)
43296177Sjhibbits#define DTSEC_MII_UNLOCK(sc)		mtx_unlock(&(sc)->sc_mii_lock)
44296177Sjhibbits
45296177Sjhibbitsenum eth_dev_type {
46296177Sjhibbits	ETH_DTSEC = 0x1,
47296177Sjhibbits	ETH_10GSEC = 0x2
48296177Sjhibbits};
49296177Sjhibbits
50296177Sjhibbitsstruct dtsec_softc {
51296177Sjhibbits	/* XXX MII bus requires that struct ifnet is first!!! */
52296177Sjhibbits	struct ifnet			*sc_ifnet;
53296177Sjhibbits
54296177Sjhibbits	device_t			sc_dev;
55296177Sjhibbits	struct mtx			sc_lock;
56296177Sjhibbits	int				sc_mode;
57296177Sjhibbits
58296177Sjhibbits	/* Methods */
59296177Sjhibbits	int				(*sc_port_rx_init)
60296177Sjhibbits	    (struct dtsec_softc *sc, int unit);
61296177Sjhibbits	int				(*sc_port_tx_init)
62296177Sjhibbits	    (struct dtsec_softc *sc, int unit);
63296177Sjhibbits	void				(*sc_start_locked)
64296177Sjhibbits	    (struct dtsec_softc *sc);
65296177Sjhibbits
66296177Sjhibbits	/* dTSEC data */
67296177Sjhibbits	enum eth_dev_type		sc_eth_dev_type;
68296177Sjhibbits	uint8_t				sc_eth_id;
69296177Sjhibbits	uintptr_t			sc_mac_mem_offset;
70296177Sjhibbits	e_EnetMode			sc_mac_enet_mode;
71296177Sjhibbits	int				sc_mac_mdio_irq;
72296177Sjhibbits	uint8_t				sc_mac_addr[6];
73296177Sjhibbits	int				sc_port_rx_hw_id;
74296177Sjhibbits	int				sc_port_tx_hw_id;
75296177Sjhibbits	uint32_t			sc_port_tx_qman_chan;
76296177Sjhibbits	int				sc_phy_addr;
77296177Sjhibbits	bool				sc_hidden;
78296177Sjhibbits
79296177Sjhibbits	/* Params from fman_bus driver */
80296177Sjhibbits	vm_offset_t			sc_fm_base;
81296177Sjhibbits	t_Handle			sc_fmh;
82296177Sjhibbits	t_Handle			sc_muramh;
83296177Sjhibbits
84296177Sjhibbits	t_Handle			sc_mach;
85296177Sjhibbits	t_Handle			sc_rxph;
86296177Sjhibbits	t_Handle			sc_txph;
87296177Sjhibbits
88296177Sjhibbits	/* MII data */
89296177Sjhibbits	struct mii_data			*sc_mii;
90296177Sjhibbits	device_t			sc_mii_dev;
91296177Sjhibbits	struct mtx			sc_mii_lock;
92296177Sjhibbits
93296177Sjhibbits	struct callout			sc_tick_callout;
94296177Sjhibbits
95296177Sjhibbits	/* RX Pool */
96296177Sjhibbits	t_Handle			sc_rx_pool;
97296177Sjhibbits	uint8_t				sc_rx_bpid;
98296177Sjhibbits	uma_zone_t			sc_rx_zone;
99296177Sjhibbits	char				sc_rx_zname[64];
100296177Sjhibbits
101296177Sjhibbits	/* RX Frame Queue */
102296177Sjhibbits	t_Handle			sc_rx_fqr;
103296177Sjhibbits	uint32_t			sc_rx_fqid;
104296177Sjhibbits
105296177Sjhibbits	/* TX Frame Queue */
106296177Sjhibbits	t_Handle			sc_tx_fqr;
107296177Sjhibbits	bool				sc_tx_fqr_full;
108296177Sjhibbits	t_Handle			sc_tx_conf_fqr;
109296177Sjhibbits	uint32_t			sc_tx_conf_fqid;
110296177Sjhibbits
111296177Sjhibbits	/* Frame Info Zone */
112296177Sjhibbits	uma_zone_t			sc_fi_zone;
113296177Sjhibbits	char				sc_fi_zname[64];
114296177Sjhibbits};
115296177Sjhibbits/** @} */
116296177Sjhibbits
117296177Sjhibbits
118296177Sjhibbits/**
119296177Sjhibbits * @group dTSEC FMan PORT API.
120296177Sjhibbits * @{
121296177Sjhibbits */
122296177Sjhibbitsenum dtsec_fm_port_params {
123296177Sjhibbits	FM_PORT_LIODN_BASE	= 0,
124296177Sjhibbits	FM_PORT_LIODN_OFFSET 	= 0,
125296177Sjhibbits	FM_PORT_MEM_ID		= 0,
126296177Sjhibbits	FM_PORT_MEM_ATTR	= MEMORY_ATTR_CACHEABLE,
127296177Sjhibbits	FM_PORT_BUFFER_SIZE	= MCLBYTES,
128296177Sjhibbits};
129296177Sjhibbits
130296177Sjhibbitse_FmPortType	dtsec_fm_port_rx_type(enum eth_dev_type type);
131296177Sjhibbitsvoid		dtsec_fm_port_rx_exception_callback(t_Handle app,
132296177Sjhibbits		    e_FmPortExceptions exception);
133296177Sjhibbitsvoid		dtsec_fm_port_tx_exception_callback(t_Handle app,
134296177Sjhibbits		    e_FmPortExceptions exception);
135296177Sjhibbitse_FmPortType	dtsec_fm_port_tx_type(enum eth_dev_type type);
136296177Sjhibbits/** @} */
137296177Sjhibbits
138296177Sjhibbits
139296177Sjhibbits/**
140296177Sjhibbits * @group dTSEC bus interface.
141296177Sjhibbits * @{
142296177Sjhibbits */
143296177Sjhibbitsint		dtsec_attach(device_t dev);
144296177Sjhibbitsint		dtsec_detach(device_t dev);
145296177Sjhibbitsint		dtsec_suspend(device_t dev);
146296177Sjhibbitsint		dtsec_resume(device_t dev);
147296177Sjhibbitsint		dtsec_shutdown(device_t dev);
148296177Sjhibbitsint		dtsec_miibus_readreg(device_t dev, int phy, int reg);
149296177Sjhibbitsint		dtsec_miibus_writereg(device_t dev, int phy, int reg,
150296177Sjhibbits		    int value);
151296177Sjhibbitsvoid		dtsec_miibus_statchg(device_t dev);
152296177Sjhibbits/** @} */
153296177Sjhibbits
154296177Sjhibbits#endif /* IF_DTSEC_H_ */
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