t4_main.c revision 346878
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/11/sys/dev/cxgbe/t4_main.c 346878 2019-04-29 05:01:34Z np $"); 30 31#include "opt_ddb.h" 32#include "opt_inet.h" 33#include "opt_inet6.h" 34#include "opt_rss.h" 35 36#include <sys/param.h> 37#include <sys/conf.h> 38#include <sys/priv.h> 39#include <sys/kernel.h> 40#include <sys/bus.h> 41#include <sys/module.h> 42#include <sys/malloc.h> 43#include <sys/queue.h> 44#include <sys/taskqueue.h> 45#include <sys/pciio.h> 46#include <dev/pci/pcireg.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pci_private.h> 49#include <sys/firmware.h> 50#include <sys/sbuf.h> 51#include <sys/smp.h> 52#include <sys/socket.h> 53#include <sys/sockio.h> 54#include <sys/sysctl.h> 55#include <net/ethernet.h> 56#include <net/if.h> 57#include <net/if_types.h> 58#include <net/if_dl.h> 59#include <net/if_vlan_var.h> 60#ifdef RSS 61#include <net/rss_config.h> 62#endif 63#if defined(__i386__) || defined(__amd64__) 64#include <machine/md_var.h> 65#include <machine/cputypes.h> 66#include <vm/vm.h> 67#include <vm/pmap.h> 68#endif 69#include <crypto/rijndael/rijndael.h> 70#ifdef DDB 71#include <ddb/ddb.h> 72#include <ddb/db_lex.h> 73#endif 74 75#include "common/common.h" 76#include "common/t4_msg.h" 77#include "common/t4_regs.h" 78#include "common/t4_regs_values.h" 79#include "cudbg/cudbg.h" 80#include "t4_ioctl.h" 81#include "t4_l2t.h" 82#include "t4_mp_ring.h" 83#include "t4_if.h" 84#include "t4_smt.h" 85 86/* T4 bus driver interface */ 87static int t4_probe(device_t); 88static int t4_attach(device_t); 89static int t4_detach(device_t); 90static int t4_child_location_str(device_t, device_t, char *, size_t); 91static int t4_ready(device_t); 92static int t4_read_port_device(device_t, int, device_t *); 93static device_method_t t4_methods[] = { 94 DEVMETHOD(device_probe, t4_probe), 95 DEVMETHOD(device_attach, t4_attach), 96 DEVMETHOD(device_detach, t4_detach), 97 98 DEVMETHOD(bus_child_location_str, t4_child_location_str), 99 100 DEVMETHOD(t4_is_main_ready, t4_ready), 101 DEVMETHOD(t4_read_port_device, t4_read_port_device), 102 103 DEVMETHOD_END 104}; 105static driver_t t4_driver = { 106 "t4nex", 107 t4_methods, 108 sizeof(struct adapter) 109}; 110 111 112/* T4 port (cxgbe) interface */ 113static int cxgbe_probe(device_t); 114static int cxgbe_attach(device_t); 115static int cxgbe_detach(device_t); 116device_method_t cxgbe_methods[] = { 117 DEVMETHOD(device_probe, cxgbe_probe), 118 DEVMETHOD(device_attach, cxgbe_attach), 119 DEVMETHOD(device_detach, cxgbe_detach), 120 { 0, 0 } 121}; 122static driver_t cxgbe_driver = { 123 "cxgbe", 124 cxgbe_methods, 125 sizeof(struct port_info) 126}; 127 128/* T4 VI (vcxgbe) interface */ 129static int vcxgbe_probe(device_t); 130static int vcxgbe_attach(device_t); 131static int vcxgbe_detach(device_t); 132static device_method_t vcxgbe_methods[] = { 133 DEVMETHOD(device_probe, vcxgbe_probe), 134 DEVMETHOD(device_attach, vcxgbe_attach), 135 DEVMETHOD(device_detach, vcxgbe_detach), 136 { 0, 0 } 137}; 138static driver_t vcxgbe_driver = { 139 "vcxgbe", 140 vcxgbe_methods, 141 sizeof(struct vi_info) 142}; 143 144static d_ioctl_t t4_ioctl; 145 146static struct cdevsw t4_cdevsw = { 147 .d_version = D_VERSION, 148 .d_ioctl = t4_ioctl, 149 .d_name = "t4nex", 150}; 151 152/* T5 bus driver interface */ 153static int t5_probe(device_t); 154static device_method_t t5_methods[] = { 155 DEVMETHOD(device_probe, t5_probe), 156 DEVMETHOD(device_attach, t4_attach), 157 DEVMETHOD(device_detach, t4_detach), 158 159 DEVMETHOD(bus_child_location_str, t4_child_location_str), 160 161 DEVMETHOD(t4_is_main_ready, t4_ready), 162 DEVMETHOD(t4_read_port_device, t4_read_port_device), 163 164 DEVMETHOD_END 165}; 166static driver_t t5_driver = { 167 "t5nex", 168 t5_methods, 169 sizeof(struct adapter) 170}; 171 172 173/* T5 port (cxl) interface */ 174static driver_t cxl_driver = { 175 "cxl", 176 cxgbe_methods, 177 sizeof(struct port_info) 178}; 179 180/* T5 VI (vcxl) interface */ 181static driver_t vcxl_driver = { 182 "vcxl", 183 vcxgbe_methods, 184 sizeof(struct vi_info) 185}; 186 187/* T6 bus driver interface */ 188static int t6_probe(device_t); 189static device_method_t t6_methods[] = { 190 DEVMETHOD(device_probe, t6_probe), 191 DEVMETHOD(device_attach, t4_attach), 192 DEVMETHOD(device_detach, t4_detach), 193 194 DEVMETHOD(bus_child_location_str, t4_child_location_str), 195 196 DEVMETHOD(t4_is_main_ready, t4_ready), 197 DEVMETHOD(t4_read_port_device, t4_read_port_device), 198 199 DEVMETHOD_END 200}; 201static driver_t t6_driver = { 202 "t6nex", 203 t6_methods, 204 sizeof(struct adapter) 205}; 206 207 208/* T6 port (cc) interface */ 209static driver_t cc_driver = { 210 "cc", 211 cxgbe_methods, 212 sizeof(struct port_info) 213}; 214 215/* T6 VI (vcc) interface */ 216static driver_t vcc_driver = { 217 "vcc", 218 vcxgbe_methods, 219 sizeof(struct vi_info) 220}; 221 222/* ifnet + media interface */ 223static void cxgbe_init(void *); 224static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 225static int cxgbe_transmit(struct ifnet *, struct mbuf *); 226static void cxgbe_qflush(struct ifnet *); 227static int cxgbe_media_change(struct ifnet *); 228static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 229 230MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 231 232/* 233 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 234 * then ADAPTER_LOCK, then t4_uld_list_lock. 235 */ 236static struct sx t4_list_lock; 237SLIST_HEAD(, adapter) t4_list; 238#ifdef TCP_OFFLOAD 239static struct sx t4_uld_list_lock; 240SLIST_HEAD(, uld_info) t4_uld_list; 241#endif 242 243/* 244 * Tunables. See tweak_tunables() too. 245 * 246 * Each tunable is set to a default value here if it's known at compile-time. 247 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 248 * provide a reasonable default (upto n) when the driver is loaded. 249 * 250 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 251 * T5 are under hw.cxl. 252 */ 253SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe(4) parameters"); 254SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD, 0, "cxgbe(4) T5+ parameters"); 255SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD, 0, "cxgbe(4) TOE parameters"); 256 257/* 258 * Number of queues for tx and rx, NIC and offload. 259 */ 260#define NTXQ 16 261int t4_ntxq = -NTXQ; 262SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 263 "Number of TX queues per port"); 264TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 265 266#define NRXQ 8 267int t4_nrxq = -NRXQ; 268SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 269 "Number of RX queues per port"); 270TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 271 272#define NTXQ_VI 1 273static int t4_ntxq_vi = -NTXQ_VI; 274SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 275 "Number of TX queues per VI"); 276 277#define NRXQ_VI 1 278static int t4_nrxq_vi = -NRXQ_VI; 279SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 280 "Number of RX queues per VI"); 281 282static int t4_rsrv_noflowq = 0; 283SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 284 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 285 286#ifdef TCP_OFFLOAD 287#define NOFLDTXQ 8 288static int t4_nofldtxq = -NOFLDTXQ; 289SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 290 "Number of offload TX queues per port"); 291 292#define NOFLDRXQ 2 293static int t4_nofldrxq = -NOFLDRXQ; 294SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 295 "Number of offload RX queues per port"); 296 297#define NOFLDTXQ_VI 1 298static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 299SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 300 "Number of offload TX queues per VI"); 301 302#define NOFLDRXQ_VI 1 303static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 304SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 305 "Number of offload RX queues per VI"); 306 307#define TMR_IDX_OFLD 1 308int t4_tmr_idx_ofld = TMR_IDX_OFLD; 309SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 310 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 311 312#define PKTC_IDX_OFLD (-1) 313int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 314SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 315 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 316 317/* 0 means chip/fw default, non-zero number is value in microseconds */ 318static u_long t4_toe_keepalive_idle = 0; 319SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 320 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 321 322/* 0 means chip/fw default, non-zero number is value in microseconds */ 323static u_long t4_toe_keepalive_interval = 0; 324SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 325 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 326 327/* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 328static int t4_toe_keepalive_count = 0; 329SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 330 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 331 332/* 0 means chip/fw default, non-zero number is value in microseconds */ 333static u_long t4_toe_rexmt_min = 0; 334SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 335 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 336 337/* 0 means chip/fw default, non-zero number is value in microseconds */ 338static u_long t4_toe_rexmt_max = 0; 339SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 340 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 341 342/* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 343static int t4_toe_rexmt_count = 0; 344SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 345 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 346 347/* -1 means chip/fw default, other values are raw backoff values to use */ 348static int t4_toe_rexmt_backoff[16] = { 349 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 350}; 351SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, CTLFLAG_RD, 0, 352 "cxgbe(4) TOE retransmit backoff values"); 353SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 354 &t4_toe_rexmt_backoff[0], 0, ""); 355SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 356 &t4_toe_rexmt_backoff[1], 0, ""); 357SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 358 &t4_toe_rexmt_backoff[2], 0, ""); 359SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 360 &t4_toe_rexmt_backoff[3], 0, ""); 361SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 362 &t4_toe_rexmt_backoff[4], 0, ""); 363SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 364 &t4_toe_rexmt_backoff[5], 0, ""); 365SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 366 &t4_toe_rexmt_backoff[6], 0, ""); 367SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 368 &t4_toe_rexmt_backoff[7], 0, ""); 369SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 370 &t4_toe_rexmt_backoff[8], 0, ""); 371SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 372 &t4_toe_rexmt_backoff[9], 0, ""); 373SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 374 &t4_toe_rexmt_backoff[10], 0, ""); 375SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 376 &t4_toe_rexmt_backoff[11], 0, ""); 377SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 378 &t4_toe_rexmt_backoff[12], 0, ""); 379SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 380 &t4_toe_rexmt_backoff[13], 0, ""); 381SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 382 &t4_toe_rexmt_backoff[14], 0, ""); 383SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 384 &t4_toe_rexmt_backoff[15], 0, ""); 385#endif 386 387#ifdef DEV_NETMAP 388#define NNMTXQ_VI 2 389static int t4_nnmtxq_vi = -NNMTXQ_VI; 390SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 391 "Number of netmap TX queues per VI"); 392 393#define NNMRXQ_VI 2 394static int t4_nnmrxq_vi = -NNMRXQ_VI; 395SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 396 "Number of netmap RX queues per VI"); 397#endif 398 399/* 400 * Holdoff parameters for ports. 401 */ 402#define TMR_IDX 1 403int t4_tmr_idx = TMR_IDX; 404SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 405 0, "Holdoff timer index"); 406TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 407 408#define PKTC_IDX (-1) 409int t4_pktc_idx = PKTC_IDX; 410SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 411 0, "Holdoff packet counter index"); 412TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 413 414/* 415 * Size (# of entries) of each tx and rx queue. 416 */ 417unsigned int t4_qsize_txq = TX_EQ_QSIZE; 418SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 419 "Number of descriptors in each TX queue"); 420 421unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 422SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 423 "Number of descriptors in each RX queue"); 424 425/* 426 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 427 */ 428int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 429SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 430 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 431 432/* 433 * Configuration file. All the _CF names here are special. 434 */ 435#define DEFAULT_CF "default" 436#define BUILTIN_CF "built-in" 437#define FLASH_CF "flash" 438#define UWIRE_CF "uwire" 439#define FPGA_CF "fpga" 440static char t4_cfg_file[32] = DEFAULT_CF; 441SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 442 sizeof(t4_cfg_file), "Firmware configuration file"); 443 444/* 445 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 446 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 447 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 448 * mark or when signalled to do so, 0 to never emit PAUSE. 449 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 450 * negotiated settings will override rx_pause/tx_pause. 451 * Otherwise rx_pause/tx_pause are applied forcibly. 452 */ 453static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 454SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 455 &t4_pause_settings, 0, 456 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 457 458/* 459 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 460 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 461 * 0 to disable FEC. 462 */ 463static int t4_fec = -1; 464SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 465 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 466 467/* 468 * Link autonegotiation. 469 * -1 to run with the firmware default. 470 * 0 to disable. 471 * 1 to enable. 472 */ 473static int t4_autoneg = -1; 474SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 475 "Link autonegotiation"); 476 477/* 478 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 479 * encouraged respectively). 480 */ 481static unsigned int t4_fw_install = 1; 482SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 483 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 484 485/* 486 * ASIC features that will be used. Disable the ones you don't want so that the 487 * chip resources aren't wasted on features that will not be used. 488 */ 489static int t4_nbmcaps_allowed = 0; 490SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 491 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 492 493static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 494SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 495 &t4_linkcaps_allowed, 0, "Default link capabilities"); 496 497static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 498 FW_CAPS_CONFIG_SWITCH_EGRESS; 499SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 500 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 501 502static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 503 FW_CAPS_CONFIG_NIC_HASHFILTER; 504SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 505 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 506 507static int t4_toecaps_allowed = -1; 508SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 509 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 510 511static int t4_rdmacaps_allowed = -1; 512SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 513 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 514 515static int t4_cryptocaps_allowed = -1; 516SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 517 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 518 519static int t4_iscsicaps_allowed = -1; 520SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 521 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 522 523static int t4_fcoecaps_allowed = 0; 524SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 525 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 526 527static int t5_write_combine = 0; 528SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 529 0, "Use WC instead of UC for BAR2"); 530 531static int t4_num_vis = 1; 532SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 533 "Number of VIs per port"); 534 535/* 536 * PCIe Relaxed Ordering. 537 * -1: driver should figure out a good value. 538 * 0: disable RO. 539 * 1: enable RO. 540 * 2: leave RO alone. 541 */ 542static int pcie_relaxed_ordering = -1; 543SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 544 &pcie_relaxed_ordering, 0, 545 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 546 547static int t4_panic_on_fatal_err = 0; 548TUNABLE_INT("hw.cxgbe.panic_on_fatal_err", &t4_panic_on_fatal_err); 549 550#ifdef TCP_OFFLOAD 551/* 552 * TOE tunables. 553 */ 554static int t4_cop_managed_offloading = 0; 555TUNABLE_INT("hw.cxgbe.cop_managed_offloading", &t4_cop_managed_offloading); 556#endif 557 558/* Functions used by VIs to obtain unique MAC addresses for each VI. */ 559static int vi_mac_funcs[] = { 560 FW_VI_FUNC_ETH, 561 FW_VI_FUNC_OFLD, 562 FW_VI_FUNC_IWARP, 563 FW_VI_FUNC_OPENISCSI, 564 FW_VI_FUNC_OPENFCOE, 565 FW_VI_FUNC_FOISCSI, 566 FW_VI_FUNC_FOFCOE, 567}; 568 569struct intrs_and_queues { 570 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 571 uint16_t num_vis; /* number of VIs for each port */ 572 uint16_t nirq; /* Total # of vectors */ 573 uint16_t ntxq; /* # of NIC txq's for each port */ 574 uint16_t nrxq; /* # of NIC rxq's for each port */ 575 uint16_t nofldtxq; /* # of TOE txq's for each port */ 576 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 577 578 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 579 uint16_t ntxq_vi; /* # of NIC txq's */ 580 uint16_t nrxq_vi; /* # of NIC rxq's */ 581 uint16_t nofldtxq_vi; /* # of TOE txq's */ 582 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 583 uint16_t nnmtxq_vi; /* # of netmap txq's */ 584 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 585}; 586 587static void setup_memwin(struct adapter *); 588static void position_memwin(struct adapter *, int, uint32_t); 589static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 590static int fwmtype_to_hwmtype(int); 591static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 592 uint32_t *); 593static int fixup_devlog_params(struct adapter *); 594static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 595static int prep_firmware(struct adapter *); 596static int partition_resources(struct adapter *, const struct firmware *, 597 const char *); 598static int get_params__pre_init(struct adapter *); 599static int get_params__post_init(struct adapter *); 600static int set_params__post_init(struct adapter *); 601static void t4_set_desc(struct adapter *); 602static bool fixed_ifmedia(struct port_info *); 603static void build_medialist(struct port_info *); 604static void init_link_config(struct port_info *); 605static int fixup_link_config(struct port_info *); 606static int apply_link_config(struct port_info *); 607static int cxgbe_init_synchronized(struct vi_info *); 608static int cxgbe_uninit_synchronized(struct vi_info *); 609static void quiesce_txq(struct adapter *, struct sge_txq *); 610static void quiesce_wrq(struct adapter *, struct sge_wrq *); 611static void quiesce_iq(struct adapter *, struct sge_iq *); 612static void quiesce_fl(struct adapter *, struct sge_fl *); 613static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 614 driver_intr_t *, void *, char *); 615static int t4_free_irq(struct adapter *, struct irq *); 616static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 617static void vi_refresh_stats(struct adapter *, struct vi_info *); 618static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 619static void cxgbe_tick(void *); 620static void cxgbe_sysctls(struct port_info *); 621static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 622static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 623static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 624static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 625static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 626static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 627static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 628static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 629static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 630static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 631static int sysctl_fec(SYSCTL_HANDLER_ARGS); 632static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 633static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 634static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 635static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 636static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 637static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 638static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 639static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS); 640static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 641static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 642static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 643static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 644static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 645static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 646static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 647static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 648static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 649static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 650static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 651static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 652static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 653static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 654static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 655static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 656static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 657static int sysctl_tids(SYSCTL_HANDLER_ARGS); 658static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 659static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 660static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 661static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 662static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 663static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 664static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 665#ifdef TCP_OFFLOAD 666static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS); 667static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 668static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 669static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 670static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 671static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 672static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 673static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 674#endif 675static int get_sge_context(struct adapter *, struct t4_sge_context *); 676static int load_fw(struct adapter *, struct t4_data *); 677static int load_cfg(struct adapter *, struct t4_data *); 678static int load_boot(struct adapter *, struct t4_bootrom *); 679static int load_bootcfg(struct adapter *, struct t4_data *); 680static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 681static void free_offload_policy(struct t4_offload_policy *); 682static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 683static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 684static int read_i2c(struct adapter *, struct t4_i2c_data *); 685#ifdef TCP_OFFLOAD 686static int toe_capability(struct vi_info *, int); 687#endif 688static int mod_event(module_t, int, void *); 689static int notify_siblings(device_t, int); 690 691struct { 692 uint16_t device; 693 char *desc; 694} t4_pciids[] = { 695 {0xa000, "Chelsio Terminator 4 FPGA"}, 696 {0x4400, "Chelsio T440-dbg"}, 697 {0x4401, "Chelsio T420-CR"}, 698 {0x4402, "Chelsio T422-CR"}, 699 {0x4403, "Chelsio T440-CR"}, 700 {0x4404, "Chelsio T420-BCH"}, 701 {0x4405, "Chelsio T440-BCH"}, 702 {0x4406, "Chelsio T440-CH"}, 703 {0x4407, "Chelsio T420-SO"}, 704 {0x4408, "Chelsio T420-CX"}, 705 {0x4409, "Chelsio T420-BT"}, 706 {0x440a, "Chelsio T404-BT"}, 707 {0x440e, "Chelsio T440-LP-CR"}, 708}, t5_pciids[] = { 709 {0xb000, "Chelsio Terminator 5 FPGA"}, 710 {0x5400, "Chelsio T580-dbg"}, 711 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 712 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 713 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 714 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 715 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 716 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 717 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 718 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 719 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 720 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 721 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 722 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 723 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 724 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 725 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 726 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 727 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 728 729 /* Custom */ 730 {0x5483, "Custom T540-CR"}, 731 {0x5484, "Custom T540-BT"}, 732}, t6_pciids[] = { 733 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 734 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 735 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 736 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 737 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 738 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 739 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 740 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 741 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 742 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 743 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 744 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 745 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 746 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 747 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 748 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 749 750 /* Custom */ 751 {0x6480, "Custom T6225-CR"}, 752 {0x6481, "Custom T62100-CR"}, 753 {0x6482, "Custom T6225-CR"}, 754 {0x6483, "Custom T62100-CR"}, 755 {0x6484, "Custom T64100-CR"}, 756 {0x6485, "Custom T6240-SO"}, 757 {0x6486, "Custom T6225-SO-CR"}, 758 {0x6487, "Custom T6225-CR"}, 759}; 760 761#ifdef TCP_OFFLOAD 762/* 763 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 764 * be exactly the same for both rxq and ofld_rxq. 765 */ 766CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 767CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 768#endif 769CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 770 771static int 772t4_probe(device_t dev) 773{ 774 int i; 775 uint16_t v = pci_get_vendor(dev); 776 uint16_t d = pci_get_device(dev); 777 uint8_t f = pci_get_function(dev); 778 779 if (v != PCI_VENDOR_ID_CHELSIO) 780 return (ENXIO); 781 782 /* Attach only to PF0 of the FPGA */ 783 if (d == 0xa000 && f != 0) 784 return (ENXIO); 785 786 for (i = 0; i < nitems(t4_pciids); i++) { 787 if (d == t4_pciids[i].device) { 788 device_set_desc(dev, t4_pciids[i].desc); 789 return (BUS_PROBE_DEFAULT); 790 } 791 } 792 793 return (ENXIO); 794} 795 796static int 797t5_probe(device_t dev) 798{ 799 int i; 800 uint16_t v = pci_get_vendor(dev); 801 uint16_t d = pci_get_device(dev); 802 uint8_t f = pci_get_function(dev); 803 804 if (v != PCI_VENDOR_ID_CHELSIO) 805 return (ENXIO); 806 807 /* Attach only to PF0 of the FPGA */ 808 if (d == 0xb000 && f != 0) 809 return (ENXIO); 810 811 for (i = 0; i < nitems(t5_pciids); i++) { 812 if (d == t5_pciids[i].device) { 813 device_set_desc(dev, t5_pciids[i].desc); 814 return (BUS_PROBE_DEFAULT); 815 } 816 } 817 818 return (ENXIO); 819} 820 821static int 822t6_probe(device_t dev) 823{ 824 int i; 825 uint16_t v = pci_get_vendor(dev); 826 uint16_t d = pci_get_device(dev); 827 828 if (v != PCI_VENDOR_ID_CHELSIO) 829 return (ENXIO); 830 831 for (i = 0; i < nitems(t6_pciids); i++) { 832 if (d == t6_pciids[i].device) { 833 device_set_desc(dev, t6_pciids[i].desc); 834 return (BUS_PROBE_DEFAULT); 835 } 836 } 837 838 return (ENXIO); 839} 840 841static void 842t5_attribute_workaround(device_t dev) 843{ 844 device_t root_port; 845 uint32_t v; 846 847 /* 848 * The T5 chips do not properly echo the No Snoop and Relaxed 849 * Ordering attributes when replying to a TLP from a Root 850 * Port. As a workaround, find the parent Root Port and 851 * disable No Snoop and Relaxed Ordering. Note that this 852 * affects all devices under this root port. 853 */ 854 root_port = pci_find_pcie_root_port(dev); 855 if (root_port == NULL) { 856 device_printf(dev, "Unable to find parent root port\n"); 857 return; 858 } 859 860 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 861 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 862 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 863 0) 864 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 865 device_get_nameunit(root_port)); 866} 867 868static const struct devnames devnames[] = { 869 { 870 .nexus_name = "t4nex", 871 .ifnet_name = "cxgbe", 872 .vi_ifnet_name = "vcxgbe", 873 .pf03_drv_name = "t4iov", 874 .vf_nexus_name = "t4vf", 875 .vf_ifnet_name = "cxgbev" 876 }, { 877 .nexus_name = "t5nex", 878 .ifnet_name = "cxl", 879 .vi_ifnet_name = "vcxl", 880 .pf03_drv_name = "t5iov", 881 .vf_nexus_name = "t5vf", 882 .vf_ifnet_name = "cxlv" 883 }, { 884 .nexus_name = "t6nex", 885 .ifnet_name = "cc", 886 .vi_ifnet_name = "vcc", 887 .pf03_drv_name = "t6iov", 888 .vf_nexus_name = "t6vf", 889 .vf_ifnet_name = "ccv" 890 } 891}; 892 893void 894t4_init_devnames(struct adapter *sc) 895{ 896 int id; 897 898 id = chip_id(sc); 899 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 900 sc->names = &devnames[id - CHELSIO_T4]; 901 else { 902 device_printf(sc->dev, "chip id %d is not supported.\n", id); 903 sc->names = NULL; 904 } 905} 906 907static int 908t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 909{ 910 const char *parent, *name; 911 long value; 912 int line, unit; 913 914 line = 0; 915 parent = device_get_nameunit(sc->dev); 916 name = sc->names->ifnet_name; 917 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 918 if (resource_long_value(name, unit, "port", &value) == 0 && 919 value == pi->port_id) 920 return (unit); 921 } 922 return (-1); 923} 924 925static int 926t4_attach(device_t dev) 927{ 928 struct adapter *sc; 929 int rc = 0, i, j, rqidx, tqidx, nports; 930 struct make_dev_args mda; 931 struct intrs_and_queues iaq; 932 struct sge *s; 933 uint32_t *buf; 934#ifdef TCP_OFFLOAD 935 int ofld_rqidx, ofld_tqidx; 936#endif 937#ifdef DEV_NETMAP 938 int nm_rqidx, nm_tqidx; 939#endif 940 int num_vis; 941 942 sc = device_get_softc(dev); 943 sc->dev = dev; 944 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 945 946 if ((pci_get_device(dev) & 0xff00) == 0x5400) 947 t5_attribute_workaround(dev); 948 pci_enable_busmaster(dev); 949 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 950 uint32_t v; 951 952 pci_set_max_read_req(dev, 4096); 953 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 954 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 955 if (pcie_relaxed_ordering == 0 && 956 (v | PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 957 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 958 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 959 } else if (pcie_relaxed_ordering == 1 && 960 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 961 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 962 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 963 } 964 } 965 966 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 967 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 968 sc->traceq = -1; 969 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 970 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 971 device_get_nameunit(dev)); 972 973 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 974 device_get_nameunit(dev)); 975 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 976 t4_add_adapter(sc); 977 978 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 979 TAILQ_INIT(&sc->sfl); 980 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 981 982 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 983 984 sc->policy = NULL; 985 rw_init(&sc->policy_lock, "connection offload policy"); 986 987 rc = t4_map_bars_0_and_4(sc); 988 if (rc != 0) 989 goto done; /* error message displayed already */ 990 991 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 992 993 /* Prepare the adapter for operation. */ 994 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 995 rc = -t4_prep_adapter(sc, buf); 996 free(buf, M_CXGBE); 997 if (rc != 0) { 998 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 999 goto done; 1000 } 1001 1002 /* 1003 * This is the real PF# to which we're attaching. Works from within PCI 1004 * passthrough environments too, where pci_get_function() could return a 1005 * different PF# depending on the passthrough configuration. We need to 1006 * use the real PF# in all our communication with the firmware. 1007 */ 1008 j = t4_read_reg(sc, A_PL_WHOAMI); 1009 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1010 sc->mbox = sc->pf; 1011 1012 t4_init_devnames(sc); 1013 if (sc->names == NULL) { 1014 rc = ENOTSUP; 1015 goto done; /* error message displayed already */ 1016 } 1017 1018 /* 1019 * Do this really early, with the memory windows set up even before the 1020 * character device. The userland tool's register i/o and mem read 1021 * will work even in "recovery mode". 1022 */ 1023 setup_memwin(sc); 1024 if (t4_init_devlog_params(sc, 0) == 0) 1025 fixup_devlog_params(sc); 1026 make_dev_args_init(&mda); 1027 mda.mda_devsw = &t4_cdevsw; 1028 mda.mda_uid = UID_ROOT; 1029 mda.mda_gid = GID_WHEEL; 1030 mda.mda_mode = 0600; 1031 mda.mda_si_drv1 = sc; 1032 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1033 if (rc != 0) 1034 device_printf(dev, "failed to create nexus char device: %d.\n", 1035 rc); 1036 1037 /* Go no further if recovery mode has been requested. */ 1038 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1039 device_printf(dev, "recovery mode.\n"); 1040 goto done; 1041 } 1042 1043#if defined(__i386__) 1044 if ((cpu_feature & CPUID_CX8) == 0) { 1045 device_printf(dev, "64 bit atomics not available.\n"); 1046 rc = ENOTSUP; 1047 goto done; 1048 } 1049#endif 1050 1051 /* Prepare the firmware for operation */ 1052 rc = prep_firmware(sc); 1053 if (rc != 0) 1054 goto done; /* error message displayed already */ 1055 1056 rc = get_params__post_init(sc); 1057 if (rc != 0) 1058 goto done; /* error message displayed already */ 1059 1060 rc = set_params__post_init(sc); 1061 if (rc != 0) 1062 goto done; /* error message displayed already */ 1063 1064 rc = t4_map_bar_2(sc); 1065 if (rc != 0) 1066 goto done; /* error message displayed already */ 1067 1068 rc = t4_create_dma_tag(sc); 1069 if (rc != 0) 1070 goto done; /* error message displayed already */ 1071 1072 /* 1073 * First pass over all the ports - allocate VIs and initialize some 1074 * basic parameters like mac address, port type, etc. 1075 */ 1076 for_each_port(sc, i) { 1077 struct port_info *pi; 1078 1079 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1080 sc->port[i] = pi; 1081 1082 /* These must be set before t4_port_init */ 1083 pi->adapter = sc; 1084 pi->port_id = i; 1085 /* 1086 * XXX: vi[0] is special so we can't delay this allocation until 1087 * pi->nvi's final value is known. 1088 */ 1089 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1090 M_ZERO | M_WAITOK); 1091 1092 /* 1093 * Allocate the "main" VI and initialize parameters 1094 * like mac addr. 1095 */ 1096 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1097 if (rc != 0) { 1098 device_printf(dev, "unable to initialize port %d: %d\n", 1099 i, rc); 1100 free(pi->vi, M_CXGBE); 1101 free(pi, M_CXGBE); 1102 sc->port[i] = NULL; 1103 goto done; 1104 } 1105 1106 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1107 device_get_nameunit(dev), i); 1108 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1109 sc->chan_map[pi->tx_chan] = i; 1110 1111 /* All VIs on this port share this media. */ 1112 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1113 cxgbe_media_status); 1114 1115 PORT_LOCK(pi); 1116 init_link_config(pi); 1117 fixup_link_config(pi); 1118 build_medialist(pi); 1119 if (fixed_ifmedia(pi)) 1120 pi->flags |= FIXED_IFMEDIA; 1121 PORT_UNLOCK(pi); 1122 1123 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1124 t4_ifnet_unit(sc, pi)); 1125 if (pi->dev == NULL) { 1126 device_printf(dev, 1127 "failed to add device for port %d.\n", i); 1128 rc = ENXIO; 1129 goto done; 1130 } 1131 pi->vi[0].dev = pi->dev; 1132 device_set_softc(pi->dev, pi); 1133 } 1134 1135 /* 1136 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1137 */ 1138 nports = sc->params.nports; 1139 rc = cfg_itype_and_nqueues(sc, &iaq); 1140 if (rc != 0) 1141 goto done; /* error message displayed already */ 1142 1143 num_vis = iaq.num_vis; 1144 sc->intr_type = iaq.intr_type; 1145 sc->intr_count = iaq.nirq; 1146 1147 s = &sc->sge; 1148 s->nrxq = nports * iaq.nrxq; 1149 s->ntxq = nports * iaq.ntxq; 1150 if (num_vis > 1) { 1151 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1152 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1153 } 1154 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1155 s->neq += nports; /* ctrl queues: 1 per port */ 1156 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1157#ifdef TCP_OFFLOAD 1158 if (is_offload(sc)) { 1159 s->nofldrxq = nports * iaq.nofldrxq; 1160 s->nofldtxq = nports * iaq.nofldtxq; 1161 if (num_vis > 1) { 1162 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1163 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1164 } 1165 s->neq += s->nofldtxq + s->nofldrxq; 1166 s->niq += s->nofldrxq; 1167 1168 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1169 M_CXGBE, M_ZERO | M_WAITOK); 1170 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1171 M_CXGBE, M_ZERO | M_WAITOK); 1172 } 1173#endif 1174#ifdef DEV_NETMAP 1175 if (num_vis > 1) { 1176 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi; 1177 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi; 1178 } 1179 s->neq += s->nnmtxq + s->nnmrxq; 1180 s->niq += s->nnmrxq; 1181 1182 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1183 M_CXGBE, M_ZERO | M_WAITOK); 1184 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1185 M_CXGBE, M_ZERO | M_WAITOK); 1186#endif 1187 1188 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1189 M_ZERO | M_WAITOK); 1190 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1191 M_ZERO | M_WAITOK); 1192 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1193 M_ZERO | M_WAITOK); 1194 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1195 M_ZERO | M_WAITOK); 1196 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1197 M_ZERO | M_WAITOK); 1198 1199 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1200 M_ZERO | M_WAITOK); 1201 1202 t4_init_l2t(sc, M_WAITOK); 1203 t4_init_smt(sc, M_WAITOK); 1204 t4_init_tx_sched(sc); 1205 if (sc->vres.key.size != 0) 1206 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1207 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1208 1209 /* 1210 * Second pass over the ports. This time we know the number of rx and 1211 * tx queues that each port should get. 1212 */ 1213 rqidx = tqidx = 0; 1214#ifdef TCP_OFFLOAD 1215 ofld_rqidx = ofld_tqidx = 0; 1216#endif 1217#ifdef DEV_NETMAP 1218 nm_rqidx = nm_tqidx = 0; 1219#endif 1220 for_each_port(sc, i) { 1221 struct port_info *pi = sc->port[i]; 1222 struct vi_info *vi; 1223 1224 if (pi == NULL) 1225 continue; 1226 1227 pi->nvi = num_vis; 1228 for_each_vi(pi, j, vi) { 1229 vi->pi = pi; 1230 vi->qsize_rxq = t4_qsize_rxq; 1231 vi->qsize_txq = t4_qsize_txq; 1232 1233 vi->first_rxq = rqidx; 1234 vi->first_txq = tqidx; 1235 vi->tmr_idx = t4_tmr_idx; 1236 vi->pktc_idx = t4_pktc_idx; 1237 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1238 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1239 1240 rqidx += vi->nrxq; 1241 tqidx += vi->ntxq; 1242 1243 if (j == 0 && vi->ntxq > 1) 1244 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1245 else 1246 vi->rsrv_noflowq = 0; 1247 1248#ifdef TCP_OFFLOAD 1249 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1250 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1251 vi->first_ofld_rxq = ofld_rqidx; 1252 vi->first_ofld_txq = ofld_tqidx; 1253 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1254 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1255 1256 ofld_rqidx += vi->nofldrxq; 1257 ofld_tqidx += vi->nofldtxq; 1258#endif 1259#ifdef DEV_NETMAP 1260 if (j > 0) { 1261 vi->first_nm_rxq = nm_rqidx; 1262 vi->first_nm_txq = nm_tqidx; 1263 vi->nnmrxq = iaq.nnmrxq_vi; 1264 vi->nnmtxq = iaq.nnmtxq_vi; 1265 nm_rqidx += vi->nnmrxq; 1266 nm_tqidx += vi->nnmtxq; 1267 } 1268#endif 1269 } 1270 } 1271 1272 rc = t4_setup_intr_handlers(sc); 1273 if (rc != 0) { 1274 device_printf(dev, 1275 "failed to setup interrupt handlers: %d\n", rc); 1276 goto done; 1277 } 1278 1279 rc = bus_generic_probe(dev); 1280 if (rc != 0) { 1281 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1282 goto done; 1283 } 1284 1285 /* 1286 * Ensure thread-safe mailbox access (in debug builds). 1287 * 1288 * So far this was the only thread accessing the mailbox but various 1289 * ifnets and sysctls are about to be created and their handlers/ioctls 1290 * will access the mailbox from different threads. 1291 */ 1292 sc->flags |= CHK_MBOX_ACCESS; 1293 1294 rc = bus_generic_attach(dev); 1295 if (rc != 0) { 1296 device_printf(dev, 1297 "failed to attach all child ports: %d\n", rc); 1298 goto done; 1299 } 1300 1301 device_printf(dev, 1302 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1303 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1304 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1305 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1306 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1307 1308 t4_set_desc(sc); 1309 1310 notify_siblings(dev, 0); 1311 1312done: 1313 if (rc != 0 && sc->cdev) { 1314 /* cdev was created and so cxgbetool works; recover that way. */ 1315 device_printf(dev, 1316 "error during attach, adapter is now in recovery mode.\n"); 1317 rc = 0; 1318 } 1319 1320 if (rc != 0) 1321 t4_detach_common(dev); 1322 else 1323 t4_sysctls(sc); 1324 1325 return (rc); 1326} 1327 1328static int 1329t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen) 1330{ 1331 struct adapter *sc; 1332 struct port_info *pi; 1333 int i; 1334 1335 sc = device_get_softc(bus); 1336 buf[0] = '\0'; 1337 for_each_port(sc, i) { 1338 pi = sc->port[i]; 1339 if (pi != NULL && pi->dev == dev) { 1340 snprintf(buf, buflen, "port=%d", pi->port_id); 1341 break; 1342 } 1343 } 1344 return (0); 1345} 1346 1347static int 1348t4_ready(device_t dev) 1349{ 1350 struct adapter *sc; 1351 1352 sc = device_get_softc(dev); 1353 if (sc->flags & FW_OK) 1354 return (0); 1355 return (ENXIO); 1356} 1357 1358static int 1359t4_read_port_device(device_t dev, int port, device_t *child) 1360{ 1361 struct adapter *sc; 1362 struct port_info *pi; 1363 1364 sc = device_get_softc(dev); 1365 if (port < 0 || port >= MAX_NPORTS) 1366 return (EINVAL); 1367 pi = sc->port[port]; 1368 if (pi == NULL || pi->dev == NULL) 1369 return (ENXIO); 1370 *child = pi->dev; 1371 return (0); 1372} 1373 1374static int 1375notify_siblings(device_t dev, int detaching) 1376{ 1377 device_t sibling; 1378 int error, i; 1379 1380 error = 0; 1381 for (i = 0; i < PCI_FUNCMAX; i++) { 1382 if (i == pci_get_function(dev)) 1383 continue; 1384 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1385 pci_get_slot(dev), i); 1386 if (sibling == NULL || !device_is_attached(sibling)) 1387 continue; 1388 if (detaching) 1389 error = T4_DETACH_CHILD(sibling); 1390 else 1391 (void)T4_ATTACH_CHILD(sibling); 1392 if (error) 1393 break; 1394 } 1395 return (error); 1396} 1397 1398/* 1399 * Idempotent 1400 */ 1401static int 1402t4_detach(device_t dev) 1403{ 1404 struct adapter *sc; 1405 int rc; 1406 1407 sc = device_get_softc(dev); 1408 1409 rc = notify_siblings(dev, 1); 1410 if (rc) { 1411 device_printf(dev, 1412 "failed to detach sibling devices: %d\n", rc); 1413 return (rc); 1414 } 1415 1416 return (t4_detach_common(dev)); 1417} 1418 1419int 1420t4_detach_common(device_t dev) 1421{ 1422 struct adapter *sc; 1423 struct port_info *pi; 1424 int i, rc; 1425 1426 sc = device_get_softc(dev); 1427 1428 if (sc->cdev) { 1429 destroy_dev(sc->cdev); 1430 sc->cdev = NULL; 1431 } 1432 1433 sc->flags &= ~CHK_MBOX_ACCESS; 1434 if (sc->flags & FULL_INIT_DONE) { 1435 if (!(sc->flags & IS_VF)) 1436 t4_intr_disable(sc); 1437 } 1438 1439 if (device_is_attached(dev)) { 1440 rc = bus_generic_detach(dev); 1441 if (rc) { 1442 device_printf(dev, 1443 "failed to detach child devices: %d\n", rc); 1444 return (rc); 1445 } 1446 } 1447 1448 for (i = 0; i < sc->intr_count; i++) 1449 t4_free_irq(sc, &sc->irq[i]); 1450 1451 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1452 t4_free_tx_sched(sc); 1453 1454 for (i = 0; i < MAX_NPORTS; i++) { 1455 pi = sc->port[i]; 1456 if (pi) { 1457 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1458 if (pi->dev) 1459 device_delete_child(dev, pi->dev); 1460 1461 mtx_destroy(&pi->pi_lock); 1462 free(pi->vi, M_CXGBE); 1463 free(pi, M_CXGBE); 1464 } 1465 } 1466 1467 device_delete_children(dev); 1468 1469 if (sc->flags & FULL_INIT_DONE) 1470 adapter_full_uninit(sc); 1471 1472 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1473 t4_fw_bye(sc, sc->mbox); 1474 1475 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1476 pci_release_msi(dev); 1477 1478 if (sc->regs_res) 1479 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1480 sc->regs_res); 1481 1482 if (sc->udbs_res) 1483 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1484 sc->udbs_res); 1485 1486 if (sc->msix_res) 1487 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1488 sc->msix_res); 1489 1490 if (sc->l2t) 1491 t4_free_l2t(sc->l2t); 1492 if (sc->key_map) 1493 vmem_destroy(sc->key_map); 1494 if (sc->smt) 1495 t4_free_smt(sc->smt); 1496 1497#ifdef TCP_OFFLOAD 1498 free(sc->sge.ofld_rxq, M_CXGBE); 1499 free(sc->sge.ofld_txq, M_CXGBE); 1500#endif 1501#ifdef DEV_NETMAP 1502 free(sc->sge.nm_rxq, M_CXGBE); 1503 free(sc->sge.nm_txq, M_CXGBE); 1504#endif 1505 free(sc->irq, M_CXGBE); 1506 free(sc->sge.rxq, M_CXGBE); 1507 free(sc->sge.txq, M_CXGBE); 1508 free(sc->sge.ctrlq, M_CXGBE); 1509 free(sc->sge.iqmap, M_CXGBE); 1510 free(sc->sge.eqmap, M_CXGBE); 1511 free(sc->tids.ftid_tab, M_CXGBE); 1512 free(sc->tids.hpftid_tab, M_CXGBE); 1513 free_hftid_hash(&sc->tids); 1514 free(sc->tids.atid_tab, M_CXGBE); 1515 free(sc->tids.tid_tab, M_CXGBE); 1516 free(sc->tt.tls_rx_ports, M_CXGBE); 1517 t4_destroy_dma_tag(sc); 1518 if (mtx_initialized(&sc->sc_lock)) { 1519 sx_xlock(&t4_list_lock); 1520 SLIST_REMOVE(&t4_list, sc, adapter, link); 1521 sx_xunlock(&t4_list_lock); 1522 mtx_destroy(&sc->sc_lock); 1523 } 1524 1525 callout_drain(&sc->sfl_callout); 1526 if (mtx_initialized(&sc->tids.ftid_lock)) { 1527 mtx_destroy(&sc->tids.ftid_lock); 1528 cv_destroy(&sc->tids.ftid_cv); 1529 } 1530 if (mtx_initialized(&sc->tids.atid_lock)) 1531 mtx_destroy(&sc->tids.atid_lock); 1532 if (mtx_initialized(&sc->sfl_lock)) 1533 mtx_destroy(&sc->sfl_lock); 1534 if (mtx_initialized(&sc->ifp_lock)) 1535 mtx_destroy(&sc->ifp_lock); 1536 if (mtx_initialized(&sc->reg_lock)) 1537 mtx_destroy(&sc->reg_lock); 1538 1539 if (rw_initialized(&sc->policy_lock)) { 1540 rw_destroy(&sc->policy_lock); 1541#ifdef TCP_OFFLOAD 1542 if (sc->policy != NULL) 1543 free_offload_policy(sc->policy); 1544#endif 1545 } 1546 1547 for (i = 0; i < NUM_MEMWIN; i++) { 1548 struct memwin *mw = &sc->memwin[i]; 1549 1550 if (rw_initialized(&mw->mw_lock)) 1551 rw_destroy(&mw->mw_lock); 1552 } 1553 1554 bzero(sc, sizeof(*sc)); 1555 1556 return (0); 1557} 1558 1559static int 1560cxgbe_probe(device_t dev) 1561{ 1562 char buf[128]; 1563 struct port_info *pi = device_get_softc(dev); 1564 1565 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1566 device_set_desc_copy(dev, buf); 1567 1568 return (BUS_PROBE_DEFAULT); 1569} 1570 1571#define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1572 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1573 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS) 1574#define T4_CAP_ENABLE (T4_CAP) 1575 1576static int 1577cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1578{ 1579 struct ifnet *ifp; 1580 struct sbuf *sb; 1581 1582 vi->xact_addr_filt = -1; 1583 callout_init(&vi->tick, 1); 1584 1585 /* Allocate an ifnet and set it up */ 1586 ifp = if_alloc(IFT_ETHER); 1587 if (ifp == NULL) { 1588 device_printf(dev, "Cannot allocate ifnet\n"); 1589 return (ENOMEM); 1590 } 1591 vi->ifp = ifp; 1592 ifp->if_softc = vi; 1593 1594 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1595 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1596 1597 ifp->if_init = cxgbe_init; 1598 ifp->if_ioctl = cxgbe_ioctl; 1599 ifp->if_transmit = cxgbe_transmit; 1600 ifp->if_qflush = cxgbe_qflush; 1601 ifp->if_get_counter = cxgbe_get_counter; 1602 1603 ifp->if_capabilities = T4_CAP; 1604#ifdef TCP_OFFLOAD 1605 if (vi->nofldrxq != 0) 1606 ifp->if_capabilities |= IFCAP_TOE; 1607#endif 1608 ifp->if_capenable = T4_CAP_ENABLE; 1609 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1610 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1611 1612 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 1613 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS; 1614 ifp->if_hw_tsomaxsegsize = 65536; 1615 1616 ether_ifattach(ifp, vi->hw_addr); 1617#ifdef DEV_NETMAP 1618 if (vi->nnmrxq != 0) 1619 cxgbe_nm_attach(vi); 1620#endif 1621 sb = sbuf_new_auto(); 1622 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1623#ifdef TCP_OFFLOAD 1624 if (ifp->if_capabilities & IFCAP_TOE) 1625 sbuf_printf(sb, "; %d txq, %d rxq (TOE)", 1626 vi->nofldtxq, vi->nofldrxq); 1627#endif 1628#ifdef DEV_NETMAP 1629 if (ifp->if_capabilities & IFCAP_NETMAP) 1630 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1631 vi->nnmtxq, vi->nnmrxq); 1632#endif 1633 sbuf_finish(sb); 1634 device_printf(dev, "%s\n", sbuf_data(sb)); 1635 sbuf_delete(sb); 1636 1637 vi_sysctls(vi); 1638 1639 return (0); 1640} 1641 1642static int 1643cxgbe_attach(device_t dev) 1644{ 1645 struct port_info *pi = device_get_softc(dev); 1646 struct adapter *sc = pi->adapter; 1647 struct vi_info *vi; 1648 int i, rc; 1649 1650 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1651 1652 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1653 if (rc) 1654 return (rc); 1655 1656 for_each_vi(pi, i, vi) { 1657 if (i == 0) 1658 continue; 1659 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1660 if (vi->dev == NULL) { 1661 device_printf(dev, "failed to add VI %d\n", i); 1662 continue; 1663 } 1664 device_set_softc(vi->dev, vi); 1665 } 1666 1667 cxgbe_sysctls(pi); 1668 1669 bus_generic_attach(dev); 1670 1671 return (0); 1672} 1673 1674static void 1675cxgbe_vi_detach(struct vi_info *vi) 1676{ 1677 struct ifnet *ifp = vi->ifp; 1678 1679 ether_ifdetach(ifp); 1680 1681 /* Let detach proceed even if these fail. */ 1682#ifdef DEV_NETMAP 1683 if (ifp->if_capabilities & IFCAP_NETMAP) 1684 cxgbe_nm_detach(vi); 1685#endif 1686 cxgbe_uninit_synchronized(vi); 1687 callout_drain(&vi->tick); 1688 vi_full_uninit(vi); 1689 1690 if_free(vi->ifp); 1691 vi->ifp = NULL; 1692} 1693 1694static int 1695cxgbe_detach(device_t dev) 1696{ 1697 struct port_info *pi = device_get_softc(dev); 1698 struct adapter *sc = pi->adapter; 1699 int rc; 1700 1701 /* Detach the extra VIs first. */ 1702 rc = bus_generic_detach(dev); 1703 if (rc) 1704 return (rc); 1705 device_delete_children(dev); 1706 1707 doom_vi(sc, &pi->vi[0]); 1708 1709 if (pi->flags & HAS_TRACEQ) { 1710 sc->traceq = -1; /* cloner should not create ifnet */ 1711 t4_tracer_port_detach(sc); 1712 } 1713 1714 cxgbe_vi_detach(&pi->vi[0]); 1715 callout_drain(&pi->tick); 1716 ifmedia_removeall(&pi->media); 1717 1718 end_synchronized_op(sc, 0); 1719 1720 return (0); 1721} 1722 1723static void 1724cxgbe_init(void *arg) 1725{ 1726 struct vi_info *vi = arg; 1727 struct adapter *sc = vi->pi->adapter; 1728 1729 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1730 return; 1731 cxgbe_init_synchronized(vi); 1732 end_synchronized_op(sc, 0); 1733} 1734 1735static int 1736cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1737{ 1738 int rc = 0, mtu, can_sleep, if_flags, if_drv_flags, vi_if_flags; 1739 struct vi_info *vi = ifp->if_softc; 1740 struct port_info *pi = vi->pi; 1741 struct adapter *sc = pi->adapter; 1742 struct ifreq *ifr = (struct ifreq *)data; 1743 uint32_t mask; 1744 1745 switch (cmd) { 1746 case SIOCSIFMTU: 1747 mtu = ifr->ifr_mtu; 1748 if (mtu < ETHERMIN || mtu > MAX_MTU) 1749 return (EINVAL); 1750 1751 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1752 if (rc) 1753 return (rc); 1754 ifp->if_mtu = mtu; 1755 if (vi->flags & VI_INIT_DONE) { 1756 t4_update_fl_bufsize(ifp); 1757 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1758 rc = update_mac_settings(ifp, XGMAC_MTU); 1759 } 1760 end_synchronized_op(sc, 0); 1761 break; 1762 1763 case SIOCSIFFLAGS: 1764 /* 1765 * Decide what to do, with the port lock held. 1766 */ 1767 PORT_LOCK(pi); 1768 if_flags = ifp->if_flags; 1769 if_drv_flags = ifp->if_drv_flags; 1770 vi_if_flags = vi->if_flags; 1771 if (if_flags & IFF_UP && if_drv_flags & IFF_DRV_RUNNING && 1772 (vi_if_flags ^ if_flags) & (IFF_PROMISC | IFF_ALLMULTI)) { 1773 can_sleep = 0; 1774 } else { 1775 can_sleep = 1; 1776 } 1777 PORT_UNLOCK(pi); 1778 1779 /* 1780 * ifp/vi flags may change here but we'll just do what our local 1781 * copy of the flags indicates and then update the driver owned 1782 * ifp/vi flags (in a synch-op and with the port lock held) to 1783 * reflect what we did. 1784 */ 1785 1786 rc = begin_synchronized_op(sc, vi, 1787 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg"); 1788 if (rc) { 1789 if_printf(ifp, "%ssleepable synch operation failed: %d." 1790 " if_flags 0x%08x, if_drv_flags 0x%08x\n", 1791 can_sleep ? "" : "non-", rc, if_flags, 1792 if_drv_flags); 1793 return (rc); 1794 } 1795 1796 if (if_flags & IFF_UP) { 1797 if (if_drv_flags & IFF_DRV_RUNNING) { 1798 if ((if_flags ^ vi_if_flags) & 1799 (IFF_PROMISC | IFF_ALLMULTI)) { 1800 MPASS(can_sleep == 0); 1801 rc = update_mac_settings(ifp, 1802 XGMAC_PROMISC | XGMAC_ALLMULTI); 1803 } 1804 } else { 1805 MPASS(can_sleep == 1); 1806 rc = cxgbe_init_synchronized(vi); 1807 } 1808 } else if (if_drv_flags & IFF_DRV_RUNNING) { 1809 MPASS(can_sleep == 1); 1810 rc = cxgbe_uninit_synchronized(vi); 1811 } 1812 PORT_LOCK(pi); 1813 vi->if_flags = if_flags; 1814 PORT_UNLOCK(pi); 1815 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD); 1816 break; 1817 1818 case SIOCADDMULTI: 1819 case SIOCDELMULTI: /* these two are called with a mutex held :-( */ 1820 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi"); 1821 if (rc) 1822 return (rc); 1823 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1824 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1825 end_synchronized_op(sc, LOCK_HELD); 1826 break; 1827 1828 case SIOCSIFCAP: 1829 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1830 if (rc) 1831 return (rc); 1832 1833 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1834 if (mask & IFCAP_TXCSUM) { 1835 ifp->if_capenable ^= IFCAP_TXCSUM; 1836 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1837 1838 if (IFCAP_TSO4 & ifp->if_capenable && 1839 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1840 ifp->if_capenable &= ~IFCAP_TSO4; 1841 if_printf(ifp, 1842 "tso4 disabled due to -txcsum.\n"); 1843 } 1844 } 1845 if (mask & IFCAP_TXCSUM_IPV6) { 1846 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1847 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1848 1849 if (IFCAP_TSO6 & ifp->if_capenable && 1850 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1851 ifp->if_capenable &= ~IFCAP_TSO6; 1852 if_printf(ifp, 1853 "tso6 disabled due to -txcsum6.\n"); 1854 } 1855 } 1856 if (mask & IFCAP_RXCSUM) 1857 ifp->if_capenable ^= IFCAP_RXCSUM; 1858 if (mask & IFCAP_RXCSUM_IPV6) 1859 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1860 1861 /* 1862 * Note that we leave CSUM_TSO alone (it is always set). The 1863 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1864 * sending a TSO request our way, so it's sufficient to toggle 1865 * IFCAP_TSOx only. 1866 */ 1867 if (mask & IFCAP_TSO4) { 1868 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1869 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1870 if_printf(ifp, "enable txcsum first.\n"); 1871 rc = EAGAIN; 1872 goto fail; 1873 } 1874 ifp->if_capenable ^= IFCAP_TSO4; 1875 } 1876 if (mask & IFCAP_TSO6) { 1877 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1878 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1879 if_printf(ifp, "enable txcsum6 first.\n"); 1880 rc = EAGAIN; 1881 goto fail; 1882 } 1883 ifp->if_capenable ^= IFCAP_TSO6; 1884 } 1885 if (mask & IFCAP_LRO) { 1886#if defined(INET) || defined(INET6) 1887 int i; 1888 struct sge_rxq *rxq; 1889 1890 ifp->if_capenable ^= IFCAP_LRO; 1891 for_each_rxq(vi, i, rxq) { 1892 if (ifp->if_capenable & IFCAP_LRO) 1893 rxq->iq.flags |= IQ_LRO_ENABLED; 1894 else 1895 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1896 } 1897#endif 1898 } 1899#ifdef TCP_OFFLOAD 1900 if (mask & IFCAP_TOE) { 1901 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1902 1903 rc = toe_capability(vi, enable); 1904 if (rc != 0) 1905 goto fail; 1906 1907 ifp->if_capenable ^= mask; 1908 } 1909#endif 1910 if (mask & IFCAP_VLAN_HWTAGGING) { 1911 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1912 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1913 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1914 } 1915 if (mask & IFCAP_VLAN_MTU) { 1916 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1917 1918 /* Need to find out how to disable auto-mtu-inflation */ 1919 } 1920 if (mask & IFCAP_VLAN_HWTSO) 1921 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1922 if (mask & IFCAP_VLAN_HWCSUM) 1923 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1924 1925#ifdef VLAN_CAPABILITIES 1926 VLAN_CAPABILITIES(ifp); 1927#endif 1928fail: 1929 end_synchronized_op(sc, 0); 1930 break; 1931 1932 case SIOCSIFMEDIA: 1933 case SIOCGIFMEDIA: 1934 case SIOCGIFXMEDIA: 1935 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 1936 break; 1937 1938 case SIOCGI2C: { 1939 struct ifi2creq i2c; 1940 1941 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 1942 if (rc != 0) 1943 break; 1944 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 1945 rc = EPERM; 1946 break; 1947 } 1948 if (i2c.len > sizeof(i2c.data)) { 1949 rc = EINVAL; 1950 break; 1951 } 1952 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 1953 if (rc) 1954 return (rc); 1955 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 1956 i2c.offset, i2c.len, &i2c.data[0]); 1957 end_synchronized_op(sc, 0); 1958 if (rc == 0) 1959 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 1960 break; 1961 } 1962 1963 default: 1964 rc = ether_ioctl(ifp, cmd, data); 1965 } 1966 1967 return (rc); 1968} 1969 1970static int 1971cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 1972{ 1973 struct vi_info *vi = ifp->if_softc; 1974 struct port_info *pi = vi->pi; 1975 struct adapter *sc = pi->adapter; 1976 struct sge_txq *txq; 1977 void *items[1]; 1978 int rc; 1979 1980 M_ASSERTPKTHDR(m); 1981 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 1982 1983 if (__predict_false(pi->link_cfg.link_ok == false)) { 1984 m_freem(m); 1985 return (ENETDOWN); 1986 } 1987 1988 rc = parse_pkt(sc, &m); 1989 if (__predict_false(rc != 0)) { 1990 MPASS(m == NULL); /* was freed already */ 1991 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 1992 return (rc); 1993 } 1994 1995 /* Select a txq. */ 1996 txq = &sc->sge.txq[vi->first_txq]; 1997 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 1998 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 1999 vi->rsrv_noflowq); 2000 2001 items[0] = m; 2002 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 2003 if (__predict_false(rc != 0)) 2004 m_freem(m); 2005 2006 return (rc); 2007} 2008 2009static void 2010cxgbe_qflush(struct ifnet *ifp) 2011{ 2012 struct vi_info *vi = ifp->if_softc; 2013 struct sge_txq *txq; 2014 int i; 2015 2016 /* queues do not exist if !VI_INIT_DONE. */ 2017 if (vi->flags & VI_INIT_DONE) { 2018 for_each_txq(vi, i, txq) { 2019 TXQ_LOCK(txq); 2020 txq->eq.flags |= EQ_QFLUSH; 2021 TXQ_UNLOCK(txq); 2022 while (!mp_ring_is_idle(txq->r)) { 2023 mp_ring_check_drainage(txq->r, 0); 2024 pause("qflush", 1); 2025 } 2026 TXQ_LOCK(txq); 2027 txq->eq.flags &= ~EQ_QFLUSH; 2028 TXQ_UNLOCK(txq); 2029 } 2030 } 2031 if_qflush(ifp); 2032} 2033 2034static uint64_t 2035vi_get_counter(struct ifnet *ifp, ift_counter c) 2036{ 2037 struct vi_info *vi = ifp->if_softc; 2038 struct fw_vi_stats_vf *s = &vi->stats; 2039 2040 vi_refresh_stats(vi->pi->adapter, vi); 2041 2042 switch (c) { 2043 case IFCOUNTER_IPACKETS: 2044 return (s->rx_bcast_frames + s->rx_mcast_frames + 2045 s->rx_ucast_frames); 2046 case IFCOUNTER_IERRORS: 2047 return (s->rx_err_frames); 2048 case IFCOUNTER_OPACKETS: 2049 return (s->tx_bcast_frames + s->tx_mcast_frames + 2050 s->tx_ucast_frames + s->tx_offload_frames); 2051 case IFCOUNTER_OERRORS: 2052 return (s->tx_drop_frames); 2053 case IFCOUNTER_IBYTES: 2054 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 2055 s->rx_ucast_bytes); 2056 case IFCOUNTER_OBYTES: 2057 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 2058 s->tx_ucast_bytes + s->tx_offload_bytes); 2059 case IFCOUNTER_IMCASTS: 2060 return (s->rx_mcast_frames); 2061 case IFCOUNTER_OMCASTS: 2062 return (s->tx_mcast_frames); 2063 case IFCOUNTER_OQDROPS: { 2064 uint64_t drops; 2065 2066 drops = 0; 2067 if (vi->flags & VI_INIT_DONE) { 2068 int i; 2069 struct sge_txq *txq; 2070 2071 for_each_txq(vi, i, txq) 2072 drops += counter_u64_fetch(txq->r->drops); 2073 } 2074 2075 return (drops); 2076 2077 } 2078 2079 default: 2080 return (if_get_counter_default(ifp, c)); 2081 } 2082} 2083 2084uint64_t 2085cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 2086{ 2087 struct vi_info *vi = ifp->if_softc; 2088 struct port_info *pi = vi->pi; 2089 struct adapter *sc = pi->adapter; 2090 struct port_stats *s = &pi->stats; 2091 2092 if (pi->nvi > 1 || sc->flags & IS_VF) 2093 return (vi_get_counter(ifp, c)); 2094 2095 cxgbe_refresh_stats(sc, pi); 2096 2097 switch (c) { 2098 case IFCOUNTER_IPACKETS: 2099 return (s->rx_frames); 2100 2101 case IFCOUNTER_IERRORS: 2102 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 2103 s->rx_fcs_err + s->rx_len_err); 2104 2105 case IFCOUNTER_OPACKETS: 2106 return (s->tx_frames); 2107 2108 case IFCOUNTER_OERRORS: 2109 return (s->tx_error_frames); 2110 2111 case IFCOUNTER_IBYTES: 2112 return (s->rx_octets); 2113 2114 case IFCOUNTER_OBYTES: 2115 return (s->tx_octets); 2116 2117 case IFCOUNTER_IMCASTS: 2118 return (s->rx_mcast_frames); 2119 2120 case IFCOUNTER_OMCASTS: 2121 return (s->tx_mcast_frames); 2122 2123 case IFCOUNTER_IQDROPS: 2124 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 2125 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 2126 s->rx_trunc3 + pi->tnl_cong_drops); 2127 2128 case IFCOUNTER_OQDROPS: { 2129 uint64_t drops; 2130 2131 drops = s->tx_drop; 2132 if (vi->flags & VI_INIT_DONE) { 2133 int i; 2134 struct sge_txq *txq; 2135 2136 for_each_txq(vi, i, txq) 2137 drops += counter_u64_fetch(txq->r->drops); 2138 } 2139 2140 return (drops); 2141 2142 } 2143 2144 default: 2145 return (if_get_counter_default(ifp, c)); 2146 } 2147} 2148 2149/* 2150 * The kernel picks a media from the list we had provided but we still validate 2151 * the requeste. 2152 */ 2153static int 2154cxgbe_media_change(struct ifnet *ifp) 2155{ 2156 struct vi_info *vi = ifp->if_softc; 2157 struct port_info *pi = vi->pi; 2158 struct ifmedia *ifm = &pi->media; 2159 struct link_config *lc = &pi->link_cfg; 2160 struct adapter *sc = pi->adapter; 2161 int rc; 2162 2163 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 2164 if (rc != 0) 2165 return (rc); 2166 PORT_LOCK(pi); 2167 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 2168 /* ifconfig .. media autoselect */ 2169 if (!(lc->supported & FW_PORT_CAP32_ANEG)) { 2170 rc = ENOTSUP; /* AN not supported by transceiver */ 2171 goto done; 2172 } 2173 lc->requested_aneg = AUTONEG_ENABLE; 2174 lc->requested_speed = 0; 2175 lc->requested_fc |= PAUSE_AUTONEG; 2176 } else { 2177 lc->requested_aneg = AUTONEG_DISABLE; 2178 lc->requested_speed = 2179 ifmedia_baudrate(ifm->ifm_media) / 1000000; 2180 lc->requested_fc = 0; 2181 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 2182 lc->requested_fc |= PAUSE_RX; 2183 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 2184 lc->requested_fc |= PAUSE_TX; 2185 } 2186 if (pi->up_vis > 0) { 2187 fixup_link_config(pi); 2188 rc = apply_link_config(pi); 2189 } 2190done: 2191 PORT_UNLOCK(pi); 2192 end_synchronized_op(sc, 0); 2193 return (rc); 2194} 2195 2196/* 2197 * Base media word (without ETHER, pause, link active, etc.) for the port at the 2198 * given speed. 2199 */ 2200static int 2201port_mword(struct port_info *pi, uint32_t speed) 2202{ 2203 2204 MPASS(speed & M_FW_PORT_CAP32_SPEED); 2205 MPASS(powerof2(speed)); 2206 2207 switch(pi->port_type) { 2208 case FW_PORT_TYPE_BT_SGMII: 2209 case FW_PORT_TYPE_BT_XFI: 2210 case FW_PORT_TYPE_BT_XAUI: 2211 /* BaseT */ 2212 switch (speed) { 2213 case FW_PORT_CAP32_SPEED_100M: 2214 return (IFM_100_T); 2215 case FW_PORT_CAP32_SPEED_1G: 2216 return (IFM_1000_T); 2217 case FW_PORT_CAP32_SPEED_10G: 2218 return (IFM_10G_T); 2219 } 2220 break; 2221 case FW_PORT_TYPE_KX4: 2222 if (speed == FW_PORT_CAP32_SPEED_10G) 2223 return (IFM_10G_KX4); 2224 break; 2225 case FW_PORT_TYPE_CX4: 2226 if (speed == FW_PORT_CAP32_SPEED_10G) 2227 return (IFM_10G_CX4); 2228 break; 2229 case FW_PORT_TYPE_KX: 2230 if (speed == FW_PORT_CAP32_SPEED_1G) 2231 return (IFM_1000_KX); 2232 break; 2233 case FW_PORT_TYPE_KR: 2234 case FW_PORT_TYPE_BP_AP: 2235 case FW_PORT_TYPE_BP4_AP: 2236 case FW_PORT_TYPE_BP40_BA: 2237 case FW_PORT_TYPE_KR4_100G: 2238 case FW_PORT_TYPE_KR_SFP28: 2239 case FW_PORT_TYPE_KR_XLAUI: 2240 switch (speed) { 2241 case FW_PORT_CAP32_SPEED_1G: 2242 return (IFM_1000_KX); 2243 case FW_PORT_CAP32_SPEED_10G: 2244 return (IFM_10G_KR); 2245 case FW_PORT_CAP32_SPEED_25G: 2246 return (IFM_25G_KR); 2247 case FW_PORT_CAP32_SPEED_40G: 2248 return (IFM_40G_KR4); 2249 case FW_PORT_CAP32_SPEED_50G: 2250 return (IFM_50G_KR2); 2251 case FW_PORT_CAP32_SPEED_100G: 2252 return (IFM_100G_KR4); 2253 } 2254 break; 2255 case FW_PORT_TYPE_FIBER_XFI: 2256 case FW_PORT_TYPE_FIBER_XAUI: 2257 case FW_PORT_TYPE_SFP: 2258 case FW_PORT_TYPE_QSFP_10G: 2259 case FW_PORT_TYPE_QSA: 2260 case FW_PORT_TYPE_QSFP: 2261 case FW_PORT_TYPE_CR4_QSFP: 2262 case FW_PORT_TYPE_CR_QSFP: 2263 case FW_PORT_TYPE_CR2_QSFP: 2264 case FW_PORT_TYPE_SFP28: 2265 /* Pluggable transceiver */ 2266 switch (pi->mod_type) { 2267 case FW_PORT_MOD_TYPE_LR: 2268 switch (speed) { 2269 case FW_PORT_CAP32_SPEED_1G: 2270 return (IFM_1000_LX); 2271 case FW_PORT_CAP32_SPEED_10G: 2272 return (IFM_10G_LR); 2273 case FW_PORT_CAP32_SPEED_25G: 2274 return (IFM_25G_LR); 2275 case FW_PORT_CAP32_SPEED_40G: 2276 return (IFM_40G_LR4); 2277 case FW_PORT_CAP32_SPEED_50G: 2278 return (IFM_50G_LR2); 2279 case FW_PORT_CAP32_SPEED_100G: 2280 return (IFM_100G_LR4); 2281 } 2282 break; 2283 case FW_PORT_MOD_TYPE_SR: 2284 switch (speed) { 2285 case FW_PORT_CAP32_SPEED_1G: 2286 return (IFM_1000_SX); 2287 case FW_PORT_CAP32_SPEED_10G: 2288 return (IFM_10G_SR); 2289 case FW_PORT_CAP32_SPEED_25G: 2290 return (IFM_25G_SR); 2291 case FW_PORT_CAP32_SPEED_40G: 2292 return (IFM_40G_SR4); 2293 case FW_PORT_CAP32_SPEED_50G: 2294 return (IFM_50G_SR2); 2295 case FW_PORT_CAP32_SPEED_100G: 2296 return (IFM_100G_SR4); 2297 } 2298 break; 2299 case FW_PORT_MOD_TYPE_ER: 2300 if (speed == FW_PORT_CAP32_SPEED_10G) 2301 return (IFM_10G_ER); 2302 break; 2303 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 2304 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 2305 switch (speed) { 2306 case FW_PORT_CAP32_SPEED_1G: 2307 return (IFM_1000_CX); 2308 case FW_PORT_CAP32_SPEED_10G: 2309 return (IFM_10G_TWINAX); 2310 case FW_PORT_CAP32_SPEED_25G: 2311 return (IFM_25G_CR); 2312 case FW_PORT_CAP32_SPEED_40G: 2313 return (IFM_40G_CR4); 2314 case FW_PORT_CAP32_SPEED_50G: 2315 return (IFM_50G_CR2); 2316 case FW_PORT_CAP32_SPEED_100G: 2317 return (IFM_100G_CR4); 2318 } 2319 break; 2320 case FW_PORT_MOD_TYPE_LRM: 2321 if (speed == FW_PORT_CAP32_SPEED_10G) 2322 return (IFM_10G_LRM); 2323 break; 2324 case FW_PORT_MOD_TYPE_NA: 2325 MPASS(0); /* Not pluggable? */ 2326 /* fall throough */ 2327 case FW_PORT_MOD_TYPE_ERROR: 2328 case FW_PORT_MOD_TYPE_UNKNOWN: 2329 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 2330 break; 2331 case FW_PORT_MOD_TYPE_NONE: 2332 return (IFM_NONE); 2333 } 2334 break; 2335 case FW_PORT_TYPE_NONE: 2336 return (IFM_NONE); 2337 } 2338 2339 return (IFM_UNKNOWN); 2340} 2341 2342static void 2343cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2344{ 2345 struct vi_info *vi = ifp->if_softc; 2346 struct port_info *pi = vi->pi; 2347 struct adapter *sc = pi->adapter; 2348 struct link_config *lc = &pi->link_cfg; 2349 2350 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0) 2351 return; 2352 PORT_LOCK(pi); 2353 2354 if (pi->up_vis == 0) { 2355 /* 2356 * If all the interfaces are administratively down the firmware 2357 * does not report transceiver changes. Refresh port info here 2358 * so that ifconfig displays accurate ifmedia at all times. 2359 * This is the only reason we have a synchronized op in this 2360 * function. Just PORT_LOCK would have been enough otherwise. 2361 */ 2362 t4_update_port_info(pi); 2363 build_medialist(pi); 2364 } 2365 2366 /* ifm_status */ 2367 ifmr->ifm_status = IFM_AVALID; 2368 if (lc->link_ok == false) 2369 goto done; 2370 ifmr->ifm_status |= IFM_ACTIVE; 2371 2372 /* ifm_active */ 2373 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2374 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 2375 if (lc->fc & PAUSE_RX) 2376 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2377 if (lc->fc & PAUSE_TX) 2378 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2379 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 2380done: 2381 PORT_UNLOCK(pi); 2382 end_synchronized_op(sc, 0); 2383} 2384 2385static int 2386vcxgbe_probe(device_t dev) 2387{ 2388 char buf[128]; 2389 struct vi_info *vi = device_get_softc(dev); 2390 2391 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2392 vi - vi->pi->vi); 2393 device_set_desc_copy(dev, buf); 2394 2395 return (BUS_PROBE_DEFAULT); 2396} 2397 2398static int 2399alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 2400{ 2401 int func, index, rc; 2402 uint32_t param, val; 2403 2404 ASSERT_SYNCHRONIZED_OP(sc); 2405 2406 index = vi - pi->vi; 2407 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 2408 KASSERT(index < nitems(vi_mac_funcs), 2409 ("%s: VI %s doesn't have a MAC func", __func__, 2410 device_get_nameunit(vi->dev))); 2411 func = vi_mac_funcs[index]; 2412 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2413 vi->hw_addr, &vi->rss_size, func, 0); 2414 if (rc < 0) { 2415 device_printf(vi->dev, "failed to allocate virtual interface %d" 2416 "for port %d: %d\n", index, pi->port_id, -rc); 2417 return (-rc); 2418 } 2419 vi->viid = rc; 2420 if (chip_id(sc) <= CHELSIO_T5) 2421 vi->smt_idx = (rc & 0x7f) << 1; 2422 else 2423 vi->smt_idx = (rc & 0x7f); 2424 2425 if (vi->rss_size == 1) { 2426 /* 2427 * This VI didn't get a slice of the RSS table. Reduce the 2428 * number of VIs being created (hw.cxgbe.num_vis) or modify the 2429 * configuration file (nvi, rssnvi for this PF) if this is a 2430 * problem. 2431 */ 2432 device_printf(vi->dev, "RSS table not available.\n"); 2433 vi->rss_base = 0xffff; 2434 2435 return (0); 2436 } 2437 2438 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2439 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2440 V_FW_PARAMS_PARAM_YZ(vi->viid); 2441 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2442 if (rc) 2443 vi->rss_base = 0xffff; 2444 else { 2445 MPASS((val >> 16) == vi->rss_size); 2446 vi->rss_base = val & 0xffff; 2447 } 2448 2449 return (0); 2450} 2451 2452static int 2453vcxgbe_attach(device_t dev) 2454{ 2455 struct vi_info *vi; 2456 struct port_info *pi; 2457 struct adapter *sc; 2458 int rc; 2459 2460 vi = device_get_softc(dev); 2461 pi = vi->pi; 2462 sc = pi->adapter; 2463 2464 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 2465 if (rc) 2466 return (rc); 2467 rc = alloc_extra_vi(sc, pi, vi); 2468 end_synchronized_op(sc, 0); 2469 if (rc) 2470 return (rc); 2471 2472 rc = cxgbe_vi_attach(dev, vi); 2473 if (rc) { 2474 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2475 return (rc); 2476 } 2477 return (0); 2478} 2479 2480static int 2481vcxgbe_detach(device_t dev) 2482{ 2483 struct vi_info *vi; 2484 struct adapter *sc; 2485 2486 vi = device_get_softc(dev); 2487 sc = vi->pi->adapter; 2488 2489 doom_vi(sc, vi); 2490 2491 cxgbe_vi_detach(vi); 2492 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2493 2494 end_synchronized_op(sc, 0); 2495 2496 return (0); 2497} 2498 2499void 2500t4_fatal_err(struct adapter *sc) 2501{ 2502 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 2503 t4_intr_disable(sc); 2504 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n", 2505 device_get_nameunit(sc->dev)); 2506 if (t4_panic_on_fatal_err) 2507 panic("panic requested on fatal error"); 2508} 2509 2510void 2511t4_add_adapter(struct adapter *sc) 2512{ 2513 sx_xlock(&t4_list_lock); 2514 SLIST_INSERT_HEAD(&t4_list, sc, link); 2515 sx_xunlock(&t4_list_lock); 2516} 2517 2518int 2519t4_map_bars_0_and_4(struct adapter *sc) 2520{ 2521 sc->regs_rid = PCIR_BAR(0); 2522 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2523 &sc->regs_rid, RF_ACTIVE); 2524 if (sc->regs_res == NULL) { 2525 device_printf(sc->dev, "cannot map registers.\n"); 2526 return (ENXIO); 2527 } 2528 sc->bt = rman_get_bustag(sc->regs_res); 2529 sc->bh = rman_get_bushandle(sc->regs_res); 2530 sc->mmio_len = rman_get_size(sc->regs_res); 2531 setbit(&sc->doorbells, DOORBELL_KDB); 2532 2533 sc->msix_rid = PCIR_BAR(4); 2534 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2535 &sc->msix_rid, RF_ACTIVE); 2536 if (sc->msix_res == NULL) { 2537 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2538 return (ENXIO); 2539 } 2540 2541 return (0); 2542} 2543 2544int 2545t4_map_bar_2(struct adapter *sc) 2546{ 2547 2548 /* 2549 * T4: only iWARP driver uses the userspace doorbells. There is no need 2550 * to map it if RDMA is disabled. 2551 */ 2552 if (is_t4(sc) && sc->rdmacaps == 0) 2553 return (0); 2554 2555 sc->udbs_rid = PCIR_BAR(2); 2556 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2557 &sc->udbs_rid, RF_ACTIVE); 2558 if (sc->udbs_res == NULL) { 2559 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2560 return (ENXIO); 2561 } 2562 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2563 2564 if (chip_id(sc) >= CHELSIO_T5) { 2565 setbit(&sc->doorbells, DOORBELL_UDB); 2566#if defined(__i386__) || defined(__amd64__) 2567 if (t5_write_combine) { 2568 int rc, mode; 2569 2570 /* 2571 * Enable write combining on BAR2. This is the 2572 * userspace doorbell BAR and is split into 128B 2573 * (UDBS_SEG_SIZE) doorbell regions, each associated 2574 * with an egress queue. The first 64B has the doorbell 2575 * and the second 64B can be used to submit a tx work 2576 * request with an implicit doorbell. 2577 */ 2578 2579 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2580 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2581 if (rc == 0) { 2582 clrbit(&sc->doorbells, DOORBELL_UDB); 2583 setbit(&sc->doorbells, DOORBELL_WCWR); 2584 setbit(&sc->doorbells, DOORBELL_UDBWC); 2585 } else { 2586 device_printf(sc->dev, 2587 "couldn't enable write combining: %d\n", 2588 rc); 2589 } 2590 2591 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2592 t4_write_reg(sc, A_SGE_STAT_CFG, 2593 V_STATSOURCE_T5(7) | mode); 2594 } 2595#endif 2596 } 2597 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 2598 2599 return (0); 2600} 2601 2602struct memwin_init { 2603 uint32_t base; 2604 uint32_t aperture; 2605}; 2606 2607static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2608 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2609 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2610 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2611}; 2612 2613static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2614 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2615 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2616 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2617}; 2618 2619static void 2620setup_memwin(struct adapter *sc) 2621{ 2622 const struct memwin_init *mw_init; 2623 struct memwin *mw; 2624 int i; 2625 uint32_t bar0; 2626 2627 if (is_t4(sc)) { 2628 /* 2629 * Read low 32b of bar0 indirectly via the hardware backdoor 2630 * mechanism. Works from within PCI passthrough environments 2631 * too, where rman_get_start() can return a different value. We 2632 * need to program the T4 memory window decoders with the actual 2633 * addresses that will be coming across the PCIe link. 2634 */ 2635 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2636 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2637 2638 mw_init = &t4_memwin[0]; 2639 } else { 2640 /* T5+ use the relative offset inside the PCIe BAR */ 2641 bar0 = 0; 2642 2643 mw_init = &t5_memwin[0]; 2644 } 2645 2646 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2647 rw_init(&mw->mw_lock, "memory window access"); 2648 mw->mw_base = mw_init->base; 2649 mw->mw_aperture = mw_init->aperture; 2650 mw->mw_curpos = 0; 2651 t4_write_reg(sc, 2652 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2653 (mw->mw_base + bar0) | V_BIR(0) | 2654 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2655 rw_wlock(&mw->mw_lock); 2656 position_memwin(sc, i, 0); 2657 rw_wunlock(&mw->mw_lock); 2658 } 2659 2660 /* flush */ 2661 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2662} 2663 2664/* 2665 * Positions the memory window at the given address in the card's address space. 2666 * There are some alignment requirements and the actual position may be at an 2667 * address prior to the requested address. mw->mw_curpos always has the actual 2668 * position of the window. 2669 */ 2670static void 2671position_memwin(struct adapter *sc, int idx, uint32_t addr) 2672{ 2673 struct memwin *mw; 2674 uint32_t pf; 2675 uint32_t reg; 2676 2677 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2678 mw = &sc->memwin[idx]; 2679 rw_assert(&mw->mw_lock, RA_WLOCKED); 2680 2681 if (is_t4(sc)) { 2682 pf = 0; 2683 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2684 } else { 2685 pf = V_PFNUM(sc->pf); 2686 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2687 } 2688 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2689 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2690 t4_read_reg(sc, reg); /* flush */ 2691} 2692 2693int 2694rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2695 int len, int rw) 2696{ 2697 struct memwin *mw; 2698 uint32_t mw_end, v; 2699 2700 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2701 2702 /* Memory can only be accessed in naturally aligned 4 byte units */ 2703 if (addr & 3 || len & 3 || len <= 0) 2704 return (EINVAL); 2705 2706 mw = &sc->memwin[idx]; 2707 while (len > 0) { 2708 rw_rlock(&mw->mw_lock); 2709 mw_end = mw->mw_curpos + mw->mw_aperture; 2710 if (addr >= mw_end || addr < mw->mw_curpos) { 2711 /* Will need to reposition the window */ 2712 if (!rw_try_upgrade(&mw->mw_lock)) { 2713 rw_runlock(&mw->mw_lock); 2714 rw_wlock(&mw->mw_lock); 2715 } 2716 rw_assert(&mw->mw_lock, RA_WLOCKED); 2717 position_memwin(sc, idx, addr); 2718 rw_downgrade(&mw->mw_lock); 2719 mw_end = mw->mw_curpos + mw->mw_aperture; 2720 } 2721 rw_assert(&mw->mw_lock, RA_RLOCKED); 2722 while (addr < mw_end && len > 0) { 2723 if (rw == 0) { 2724 v = t4_read_reg(sc, mw->mw_base + addr - 2725 mw->mw_curpos); 2726 *val++ = le32toh(v); 2727 } else { 2728 v = *val++; 2729 t4_write_reg(sc, mw->mw_base + addr - 2730 mw->mw_curpos, htole32(v)); 2731 } 2732 addr += 4; 2733 len -= 4; 2734 } 2735 rw_runlock(&mw->mw_lock); 2736 } 2737 2738 return (0); 2739} 2740 2741int 2742alloc_atid_tab(struct tid_info *t, int flags) 2743{ 2744 int i; 2745 2746 MPASS(t->natids > 0); 2747 MPASS(t->atid_tab == NULL); 2748 2749 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 2750 M_ZERO | flags); 2751 if (t->atid_tab == NULL) 2752 return (ENOMEM); 2753 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 2754 t->afree = t->atid_tab; 2755 t->atids_in_use = 0; 2756 for (i = 1; i < t->natids; i++) 2757 t->atid_tab[i - 1].next = &t->atid_tab[i]; 2758 t->atid_tab[t->natids - 1].next = NULL; 2759 2760 return (0); 2761} 2762 2763void 2764free_atid_tab(struct tid_info *t) 2765{ 2766 2767 KASSERT(t->atids_in_use == 0, 2768 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 2769 2770 if (mtx_initialized(&t->atid_lock)) 2771 mtx_destroy(&t->atid_lock); 2772 free(t->atid_tab, M_CXGBE); 2773 t->atid_tab = NULL; 2774} 2775 2776int 2777alloc_atid(struct adapter *sc, void *ctx) 2778{ 2779 struct tid_info *t = &sc->tids; 2780 int atid = -1; 2781 2782 mtx_lock(&t->atid_lock); 2783 if (t->afree) { 2784 union aopen_entry *p = t->afree; 2785 2786 atid = p - t->atid_tab; 2787 MPASS(atid <= M_TID_TID); 2788 t->afree = p->next; 2789 p->data = ctx; 2790 t->atids_in_use++; 2791 } 2792 mtx_unlock(&t->atid_lock); 2793 return (atid); 2794} 2795 2796void * 2797lookup_atid(struct adapter *sc, int atid) 2798{ 2799 struct tid_info *t = &sc->tids; 2800 2801 return (t->atid_tab[atid].data); 2802} 2803 2804void 2805free_atid(struct adapter *sc, int atid) 2806{ 2807 struct tid_info *t = &sc->tids; 2808 union aopen_entry *p = &t->atid_tab[atid]; 2809 2810 mtx_lock(&t->atid_lock); 2811 p->next = t->afree; 2812 t->afree = p; 2813 t->atids_in_use--; 2814 mtx_unlock(&t->atid_lock); 2815} 2816 2817static void 2818queue_tid_release(struct adapter *sc, int tid) 2819{ 2820 2821 CXGBE_UNIMPLEMENTED("deferred tid release"); 2822} 2823 2824void 2825release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 2826{ 2827 struct wrqe *wr; 2828 struct cpl_tid_release *req; 2829 2830 wr = alloc_wrqe(sizeof(*req), ctrlq); 2831 if (wr == NULL) { 2832 queue_tid_release(sc, tid); /* defer */ 2833 return; 2834 } 2835 req = wrtod(wr); 2836 2837 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 2838 2839 t4_wrq_tx(sc, wr); 2840} 2841 2842static int 2843t4_range_cmp(const void *a, const void *b) 2844{ 2845 return ((const struct t4_range *)a)->start - 2846 ((const struct t4_range *)b)->start; 2847} 2848 2849/* 2850 * Verify that the memory range specified by the addr/len pair is valid within 2851 * the card's address space. 2852 */ 2853static int 2854validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 2855{ 2856 struct t4_range mem_ranges[4], *r, *next; 2857 uint32_t em, addr_len; 2858 int i, n, remaining; 2859 2860 /* Memory can only be accessed in naturally aligned 4 byte units */ 2861 if (addr & 3 || len & 3 || len == 0) 2862 return (EINVAL); 2863 2864 /* Enabled memories */ 2865 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2866 2867 r = &mem_ranges[0]; 2868 n = 0; 2869 bzero(r, sizeof(mem_ranges)); 2870 if (em & F_EDRAM0_ENABLE) { 2871 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2872 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2873 if (r->size > 0) { 2874 r->start = G_EDRAM0_BASE(addr_len) << 20; 2875 if (addr >= r->start && 2876 addr + len <= r->start + r->size) 2877 return (0); 2878 r++; 2879 n++; 2880 } 2881 } 2882 if (em & F_EDRAM1_ENABLE) { 2883 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2884 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2885 if (r->size > 0) { 2886 r->start = G_EDRAM1_BASE(addr_len) << 20; 2887 if (addr >= r->start && 2888 addr + len <= r->start + r->size) 2889 return (0); 2890 r++; 2891 n++; 2892 } 2893 } 2894 if (em & F_EXT_MEM_ENABLE) { 2895 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2896 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2897 if (r->size > 0) { 2898 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2899 if (addr >= r->start && 2900 addr + len <= r->start + r->size) 2901 return (0); 2902 r++; 2903 n++; 2904 } 2905 } 2906 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 2907 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2908 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 2909 if (r->size > 0) { 2910 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 2911 if (addr >= r->start && 2912 addr + len <= r->start + r->size) 2913 return (0); 2914 r++; 2915 n++; 2916 } 2917 } 2918 MPASS(n <= nitems(mem_ranges)); 2919 2920 if (n > 1) { 2921 /* Sort and merge the ranges. */ 2922 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 2923 2924 /* Start from index 0 and examine the next n - 1 entries. */ 2925 r = &mem_ranges[0]; 2926 for (remaining = n - 1; remaining > 0; remaining--, r++) { 2927 2928 MPASS(r->size > 0); /* r is a valid entry. */ 2929 next = r + 1; 2930 MPASS(next->size > 0); /* and so is the next one. */ 2931 2932 while (r->start + r->size >= next->start) { 2933 /* Merge the next one into the current entry. */ 2934 r->size = max(r->start + r->size, 2935 next->start + next->size) - r->start; 2936 n--; /* One fewer entry in total. */ 2937 if (--remaining == 0) 2938 goto done; /* short circuit */ 2939 next++; 2940 } 2941 if (next != r + 1) { 2942 /* 2943 * Some entries were merged into r and next 2944 * points to the first valid entry that couldn't 2945 * be merged. 2946 */ 2947 MPASS(next->size > 0); /* must be valid */ 2948 memcpy(r + 1, next, remaining * sizeof(*r)); 2949#ifdef INVARIANTS 2950 /* 2951 * This so that the foo->size assertion in the 2952 * next iteration of the loop do the right 2953 * thing for entries that were pulled up and are 2954 * no longer valid. 2955 */ 2956 MPASS(n < nitems(mem_ranges)); 2957 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 2958 sizeof(struct t4_range)); 2959#endif 2960 } 2961 } 2962done: 2963 /* Done merging the ranges. */ 2964 MPASS(n > 0); 2965 r = &mem_ranges[0]; 2966 for (i = 0; i < n; i++, r++) { 2967 if (addr >= r->start && 2968 addr + len <= r->start + r->size) 2969 return (0); 2970 } 2971 } 2972 2973 return (EFAULT); 2974} 2975 2976static int 2977fwmtype_to_hwmtype(int mtype) 2978{ 2979 2980 switch (mtype) { 2981 case FW_MEMTYPE_EDC0: 2982 return (MEM_EDC0); 2983 case FW_MEMTYPE_EDC1: 2984 return (MEM_EDC1); 2985 case FW_MEMTYPE_EXTMEM: 2986 return (MEM_MC0); 2987 case FW_MEMTYPE_EXTMEM1: 2988 return (MEM_MC1); 2989 default: 2990 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 2991 } 2992} 2993 2994/* 2995 * Verify that the memory range specified by the memtype/offset/len pair is 2996 * valid and lies entirely within the memtype specified. The global address of 2997 * the start of the range is returned in addr. 2998 */ 2999static int 3000validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 3001 uint32_t *addr) 3002{ 3003 uint32_t em, addr_len, maddr; 3004 3005 /* Memory can only be accessed in naturally aligned 4 byte units */ 3006 if (off & 3 || len & 3 || len == 0) 3007 return (EINVAL); 3008 3009 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 3010 switch (fwmtype_to_hwmtype(mtype)) { 3011 case MEM_EDC0: 3012 if (!(em & F_EDRAM0_ENABLE)) 3013 return (EINVAL); 3014 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 3015 maddr = G_EDRAM0_BASE(addr_len) << 20; 3016 break; 3017 case MEM_EDC1: 3018 if (!(em & F_EDRAM1_ENABLE)) 3019 return (EINVAL); 3020 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 3021 maddr = G_EDRAM1_BASE(addr_len) << 20; 3022 break; 3023 case MEM_MC: 3024 if (!(em & F_EXT_MEM_ENABLE)) 3025 return (EINVAL); 3026 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 3027 maddr = G_EXT_MEM_BASE(addr_len) << 20; 3028 break; 3029 case MEM_MC1: 3030 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 3031 return (EINVAL); 3032 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 3033 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 3034 break; 3035 default: 3036 return (EINVAL); 3037 } 3038 3039 *addr = maddr + off; /* global address */ 3040 return (validate_mem_range(sc, *addr, len)); 3041} 3042 3043static int 3044fixup_devlog_params(struct adapter *sc) 3045{ 3046 struct devlog_params *dparams = &sc->params.devlog; 3047 int rc; 3048 3049 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 3050 dparams->size, &dparams->addr); 3051 3052 return (rc); 3053} 3054 3055static void 3056update_nirq(struct intrs_and_queues *iaq, int nports) 3057{ 3058 int extra = T4_EXTRA_INTR; 3059 3060 iaq->nirq = extra; 3061 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq); 3062 iaq->nirq += nports * (iaq->num_vis - 1) * 3063 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 3064 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 3065} 3066 3067/* 3068 * Adjust requirements to fit the number of interrupts available. 3069 */ 3070static void 3071calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 3072 int navail) 3073{ 3074 int old_nirq; 3075 const int nports = sc->params.nports; 3076 3077 MPASS(nports > 0); 3078 MPASS(navail > 0); 3079 3080 bzero(iaq, sizeof(*iaq)); 3081 iaq->intr_type = itype; 3082 iaq->num_vis = t4_num_vis; 3083 iaq->ntxq = t4_ntxq; 3084 iaq->ntxq_vi = t4_ntxq_vi; 3085 iaq->nrxq = t4_nrxq; 3086 iaq->nrxq_vi = t4_nrxq_vi; 3087#ifdef TCP_OFFLOAD 3088 if (is_offload(sc)) { 3089 iaq->nofldtxq = t4_nofldtxq; 3090 iaq->nofldtxq_vi = t4_nofldtxq_vi; 3091 iaq->nofldrxq = t4_nofldrxq; 3092 iaq->nofldrxq_vi = t4_nofldrxq_vi; 3093 } 3094#endif 3095#ifdef DEV_NETMAP 3096 iaq->nnmtxq_vi = t4_nnmtxq_vi; 3097 iaq->nnmrxq_vi = t4_nnmrxq_vi; 3098#endif 3099 3100 update_nirq(iaq, nports); 3101 if (iaq->nirq <= navail && 3102 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3103 /* 3104 * This is the normal case -- there are enough interrupts for 3105 * everything. 3106 */ 3107 goto done; 3108 } 3109 3110 /* 3111 * If extra VIs have been configured try reducing their count and see if 3112 * that works. 3113 */ 3114 while (iaq->num_vis > 1) { 3115 iaq->num_vis--; 3116 update_nirq(iaq, nports); 3117 if (iaq->nirq <= navail && 3118 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3119 device_printf(sc->dev, "virtual interfaces per port " 3120 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 3121 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 3122 "itype %d, navail %u, nirq %d.\n", 3123 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 3124 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 3125 itype, navail, iaq->nirq); 3126 goto done; 3127 } 3128 } 3129 3130 /* 3131 * Extra VIs will not be created. Log a message if they were requested. 3132 */ 3133 MPASS(iaq->num_vis == 1); 3134 iaq->ntxq_vi = iaq->nrxq_vi = 0; 3135 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 3136 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 3137 if (iaq->num_vis != t4_num_vis) { 3138 device_printf(sc->dev, "extra virtual interfaces disabled. " 3139 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 3140 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 3141 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 3142 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 3143 } 3144 3145 /* 3146 * Keep reducing the number of NIC rx queues to the next lower power of 3147 * 2 (for even RSS distribution) and halving the TOE rx queues and see 3148 * if that works. 3149 */ 3150 do { 3151 if (iaq->nrxq > 1) { 3152 do { 3153 iaq->nrxq--; 3154 } while (!powerof2(iaq->nrxq)); 3155 } 3156 if (iaq->nofldrxq > 1) 3157 iaq->nofldrxq >>= 1; 3158 3159 old_nirq = iaq->nirq; 3160 update_nirq(iaq, nports); 3161 if (iaq->nirq <= navail && 3162 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3163 device_printf(sc->dev, "running with reduced number of " 3164 "rx queues because of shortage of interrupts. " 3165 "nrxq=%u, nofldrxq=%u. " 3166 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 3167 iaq->nofldrxq, itype, navail, iaq->nirq); 3168 goto done; 3169 } 3170 } while (old_nirq != iaq->nirq); 3171 3172 /* One interrupt for everything. Ugh. */ 3173 device_printf(sc->dev, "running with minimal number of queues. " 3174 "itype %d, navail %u.\n", itype, navail); 3175 iaq->nirq = 1; 3176 MPASS(iaq->nrxq == 1); 3177 iaq->ntxq = 1; 3178 if (iaq->nofldrxq > 1) 3179 iaq->nofldtxq = 1; 3180done: 3181 MPASS(iaq->num_vis > 0); 3182 if (iaq->num_vis > 1) { 3183 MPASS(iaq->nrxq_vi > 0); 3184 MPASS(iaq->ntxq_vi > 0); 3185 } 3186 MPASS(iaq->nirq > 0); 3187 MPASS(iaq->nrxq > 0); 3188 MPASS(iaq->ntxq > 0); 3189 if (itype == INTR_MSI) { 3190 MPASS(powerof2(iaq->nirq)); 3191 } 3192} 3193 3194static int 3195cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 3196{ 3197 int rc, itype, navail, nalloc; 3198 3199 for (itype = INTR_MSIX; itype; itype >>= 1) { 3200 3201 if ((itype & t4_intr_types) == 0) 3202 continue; /* not allowed */ 3203 3204 if (itype == INTR_MSIX) 3205 navail = pci_msix_count(sc->dev); 3206 else if (itype == INTR_MSI) 3207 navail = pci_msi_count(sc->dev); 3208 else 3209 navail = 1; 3210restart: 3211 if (navail == 0) 3212 continue; 3213 3214 calculate_iaq(sc, iaq, itype, navail); 3215 nalloc = iaq->nirq; 3216 rc = 0; 3217 if (itype == INTR_MSIX) 3218 rc = pci_alloc_msix(sc->dev, &nalloc); 3219 else if (itype == INTR_MSI) 3220 rc = pci_alloc_msi(sc->dev, &nalloc); 3221 3222 if (rc == 0 && nalloc > 0) { 3223 if (nalloc == iaq->nirq) 3224 return (0); 3225 3226 /* 3227 * Didn't get the number requested. Use whatever number 3228 * the kernel is willing to allocate. 3229 */ 3230 device_printf(sc->dev, "fewer vectors than requested, " 3231 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 3232 itype, iaq->nirq, nalloc); 3233 pci_release_msi(sc->dev); 3234 navail = nalloc; 3235 goto restart; 3236 } 3237 3238 device_printf(sc->dev, 3239 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 3240 itype, rc, iaq->nirq, nalloc); 3241 } 3242 3243 device_printf(sc->dev, 3244 "failed to find a usable interrupt type. " 3245 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 3246 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 3247 3248 return (ENXIO); 3249} 3250 3251#define FW_VERSION(chip) ( \ 3252 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 3253 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 3254 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 3255 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 3256#define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 3257 3258struct fw_info { 3259 uint8_t chip; 3260 char *kld_name; 3261 char *fw_mod_name; 3262 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ 3263} fw_info[] = { 3264 { 3265 .chip = CHELSIO_T4, 3266 .kld_name = "t4fw_cfg", 3267 .fw_mod_name = "t4fw", 3268 .fw_hdr = { 3269 .chip = FW_HDR_CHIP_T4, 3270 .fw_ver = htobe32(FW_VERSION(T4)), 3271 .intfver_nic = FW_INTFVER(T4, NIC), 3272 .intfver_vnic = FW_INTFVER(T4, VNIC), 3273 .intfver_ofld = FW_INTFVER(T4, OFLD), 3274 .intfver_ri = FW_INTFVER(T4, RI), 3275 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 3276 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3277 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 3278 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3279 }, 3280 }, { 3281 .chip = CHELSIO_T5, 3282 .kld_name = "t5fw_cfg", 3283 .fw_mod_name = "t5fw", 3284 .fw_hdr = { 3285 .chip = FW_HDR_CHIP_T5, 3286 .fw_ver = htobe32(FW_VERSION(T5)), 3287 .intfver_nic = FW_INTFVER(T5, NIC), 3288 .intfver_vnic = FW_INTFVER(T5, VNIC), 3289 .intfver_ofld = FW_INTFVER(T5, OFLD), 3290 .intfver_ri = FW_INTFVER(T5, RI), 3291 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 3292 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3293 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 3294 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3295 }, 3296 }, { 3297 .chip = CHELSIO_T6, 3298 .kld_name = "t6fw_cfg", 3299 .fw_mod_name = "t6fw", 3300 .fw_hdr = { 3301 .chip = FW_HDR_CHIP_T6, 3302 .fw_ver = htobe32(FW_VERSION(T6)), 3303 .intfver_nic = FW_INTFVER(T6, NIC), 3304 .intfver_vnic = FW_INTFVER(T6, VNIC), 3305 .intfver_ofld = FW_INTFVER(T6, OFLD), 3306 .intfver_ri = FW_INTFVER(T6, RI), 3307 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3308 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3309 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3310 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3311 }, 3312 } 3313}; 3314 3315static struct fw_info * 3316find_fw_info(int chip) 3317{ 3318 int i; 3319 3320 for (i = 0; i < nitems(fw_info); i++) { 3321 if (fw_info[i].chip == chip) 3322 return (&fw_info[i]); 3323 } 3324 return (NULL); 3325} 3326 3327/* 3328 * Is the given firmware API compatible with the one the driver was compiled 3329 * with? 3330 */ 3331static int 3332fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) 3333{ 3334 3335 /* short circuit if it's the exact same firmware version */ 3336 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 3337 return (1); 3338 3339 /* 3340 * XXX: Is this too conservative? Perhaps I should limit this to the 3341 * features that are supported in the driver. 3342 */ 3343#define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 3344 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 3345 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 3346 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 3347 return (1); 3348#undef SAME_INTF 3349 3350 return (0); 3351} 3352 3353/* 3354 * The firmware in the KLD is usable, but should it be installed? This routine 3355 * explains itself in detail if it indicates the KLD firmware should be 3356 * installed. 3357 */ 3358static int 3359should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c) 3360{ 3361 const char *reason; 3362 3363 if (!card_fw_usable) { 3364 reason = "incompatible or unusable"; 3365 goto install; 3366 } 3367 3368 if (k > c) { 3369 reason = "older than the version bundled with this driver"; 3370 goto install; 3371 } 3372 3373 if (t4_fw_install == 2 && k != c) { 3374 reason = "different than the version bundled with this driver"; 3375 goto install; 3376 } 3377 3378 return (0); 3379 3380install: 3381 if (t4_fw_install == 0) { 3382 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3383 "but the driver is prohibited from installing a different " 3384 "firmware on the card.\n", 3385 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3386 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3387 3388 return (0); 3389 } 3390 3391 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3392 "installing firmware %u.%u.%u.%u on card.\n", 3393 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3394 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 3395 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3396 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3397 3398 return (1); 3399} 3400 3401/* 3402 * Establish contact with the firmware and determine if we are the master driver 3403 * or not, and whether we are responsible for chip initialization. 3404 */ 3405static int 3406prep_firmware(struct adapter *sc) 3407{ 3408 const struct firmware *fw = NULL, *default_cfg; 3409 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1; 3410 enum dev_state state; 3411 struct fw_info *fw_info; 3412 struct fw_hdr *card_fw; /* fw on the card */ 3413 const struct fw_hdr *kld_fw; /* fw in the KLD */ 3414 const struct fw_hdr *drv_fw; /* fw header the driver was compiled 3415 against */ 3416 3417 /* This is the firmware whose headers the driver was compiled against */ 3418 fw_info = find_fw_info(chip_id(sc)); 3419 if (fw_info == NULL) { 3420 device_printf(sc->dev, 3421 "unable to look up firmware information for chip %d.\n", 3422 chip_id(sc)); 3423 return (EINVAL); 3424 } 3425 drv_fw = &fw_info->fw_hdr; 3426 3427 /* 3428 * The firmware KLD contains many modules. The KLD name is also the 3429 * name of the module that contains the default config file. 3430 */ 3431 default_cfg = firmware_get(fw_info->kld_name); 3432 3433 /* This is the firmware in the KLD */ 3434 fw = firmware_get(fw_info->fw_mod_name); 3435 if (fw != NULL) { 3436 kld_fw = (const void *)fw->data; 3437 kld_fw_usable = fw_compatible(drv_fw, kld_fw); 3438 } else { 3439 kld_fw = NULL; 3440 kld_fw_usable = 0; 3441 } 3442 3443 /* Read the header of the firmware on the card */ 3444 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 3445 rc = -t4_read_flash(sc, FLASH_FW_START, 3446 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1); 3447 if (rc == 0) { 3448 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw); 3449 if (card_fw->fw_ver == be32toh(0xffffffff)) { 3450 uint32_t d = be32toh(kld_fw->fw_ver); 3451 3452 if (!kld_fw_usable) { 3453 device_printf(sc->dev, 3454 "no firmware on the card and no usable " 3455 "firmware bundled with the driver.\n"); 3456 rc = EIO; 3457 goto done; 3458 } else if (t4_fw_install == 0) { 3459 device_printf(sc->dev, 3460 "no firmware on the card and the driver " 3461 "is prohibited from installing new " 3462 "firmware.\n"); 3463 rc = EIO; 3464 goto done; 3465 } 3466 3467 device_printf(sc->dev, "no firmware on the card, " 3468 "installing firmware %d.%d.%d.%d\n", 3469 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3470 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3471 rc = t4_fw_forceinstall(sc, fw->data, fw->datasize); 3472 if (rc < 0) { 3473 rc = -rc; 3474 device_printf(sc->dev, 3475 "firmware install failed: %d.\n", rc); 3476 goto done; 3477 } 3478 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3479 card_fw_usable = 1; 3480 need_fw_reset = 0; 3481 } 3482 } else { 3483 device_printf(sc->dev, 3484 "Unable to read card's firmware header: %d\n", rc); 3485 card_fw_usable = 0; 3486 } 3487 3488 /* Contact firmware. */ 3489 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 3490 if (rc < 0 || state == DEV_STATE_ERR) { 3491 rc = -rc; 3492 device_printf(sc->dev, 3493 "failed to connect to the firmware: %d, %d.\n", rc, state); 3494 goto done; 3495 } 3496 pf = rc; 3497 if (pf == sc->mbox) 3498 sc->flags |= MASTER_PF; 3499 else if (state == DEV_STATE_UNINIT) { 3500 /* 3501 * We didn't get to be the master so we definitely won't be 3502 * configuring the chip. It's a bug if someone else hasn't 3503 * configured it already. 3504 */ 3505 device_printf(sc->dev, "couldn't be master(%d), " 3506 "device not already initialized either(%d).\n", rc, state); 3507 rc = EPROTO; 3508 goto done; 3509 } 3510 3511 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && 3512 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) { 3513 /* 3514 * Common case: the firmware on the card is an exact match and 3515 * the KLD is an exact match too, or the KLD is 3516 * absent/incompatible. Note that t4_fw_install = 2 is ignored 3517 * here -- use cxgbetool loadfw if you want to reinstall the 3518 * same firmware as the one on the card. 3519 */ 3520 } else if (kld_fw_usable && state == DEV_STATE_UNINIT && 3521 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver), 3522 be32toh(card_fw->fw_ver))) { 3523 3524 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3525 if (rc != 0) { 3526 device_printf(sc->dev, 3527 "failed to install firmware: %d\n", rc); 3528 goto done; 3529 } 3530 3531 /* Installed successfully, update the cached header too. */ 3532 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3533 card_fw_usable = 1; 3534 need_fw_reset = 0; /* already reset as part of load_fw */ 3535 } 3536 3537 if (!card_fw_usable) { 3538 uint32_t d, c, k; 3539 3540 d = ntohl(drv_fw->fw_ver); 3541 c = ntohl(card_fw->fw_ver); 3542 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0; 3543 3544 device_printf(sc->dev, "Cannot find a usable firmware: " 3545 "fw_install %d, chip state %d, " 3546 "driver compiled with %d.%d.%d.%d, " 3547 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n", 3548 t4_fw_install, state, 3549 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3550 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d), 3551 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3552 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), 3553 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3554 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3555 rc = EINVAL; 3556 goto done; 3557 } 3558 3559 /* Reset device */ 3560 if (need_fw_reset && 3561 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) { 3562 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 3563 if (rc != ETIMEDOUT && rc != EIO) 3564 t4_fw_bye(sc, sc->mbox); 3565 goto done; 3566 } 3567 sc->flags |= FW_OK; 3568 3569 rc = get_params__pre_init(sc); 3570 if (rc != 0) 3571 goto done; /* error message displayed already */ 3572 3573 /* Partition adapter resources as specified in the config file. */ 3574 if (state == DEV_STATE_UNINIT) { 3575 3576 KASSERT(sc->flags & MASTER_PF, 3577 ("%s: trying to change chip settings when not master.", 3578 __func__)); 3579 3580 rc = partition_resources(sc, default_cfg, fw_info->kld_name); 3581 if (rc != 0) 3582 goto done; /* error message displayed already */ 3583 3584 t4_tweak_chip_settings(sc); 3585 3586 /* get basic stuff going */ 3587 rc = -t4_fw_initialize(sc, sc->mbox); 3588 if (rc != 0) { 3589 device_printf(sc->dev, "fw init failed: %d.\n", rc); 3590 goto done; 3591 } 3592 } else { 3593 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf); 3594 sc->cfcsum = 0; 3595 } 3596 3597done: 3598 free(card_fw, M_CXGBE); 3599 if (fw != NULL) 3600 firmware_put(fw, FIRMWARE_UNLOAD); 3601 if (default_cfg != NULL) 3602 firmware_put(default_cfg, FIRMWARE_UNLOAD); 3603 3604 return (rc); 3605} 3606 3607#define FW_PARAM_DEV(param) \ 3608 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 3609 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 3610#define FW_PARAM_PFVF(param) \ 3611 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 3612 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 3613 3614/* 3615 * Partition chip resources for use between various PFs, VFs, etc. 3616 */ 3617static int 3618partition_resources(struct adapter *sc, const struct firmware *default_cfg, 3619 const char *name_prefix) 3620{ 3621 const struct firmware *cfg = NULL; 3622 int rc = 0; 3623 struct fw_caps_config_cmd caps; 3624 uint32_t mtype, moff, finicsum, cfcsum; 3625 3626 /* 3627 * Figure out what configuration file to use. Pick the default config 3628 * file for the card if the user hasn't specified one explicitly. 3629 */ 3630 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file); 3631 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3632 /* Card specific overrides go here. */ 3633 if (pci_get_device(sc->dev) == 0x440a) 3634 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF); 3635 if (is_fpga(sc)) 3636 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF); 3637 } else if (strncmp(t4_cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) 3638 goto use_built_in_config; /* go straight to config. */ 3639 3640 /* 3641 * We need to load another module if the profile is anything except 3642 * "default" or "flash". 3643 */ 3644 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 && 3645 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3646 char s[32]; 3647 3648 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file); 3649 cfg = firmware_get(s); 3650 if (cfg == NULL) { 3651 if (default_cfg != NULL) { 3652 device_printf(sc->dev, 3653 "unable to load module \"%s\" for " 3654 "configuration profile \"%s\", will use " 3655 "the default config file instead.\n", 3656 s, sc->cfg_file); 3657 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3658 "%s", DEFAULT_CF); 3659 } else { 3660 device_printf(sc->dev, 3661 "unable to load module \"%s\" for " 3662 "configuration profile \"%s\", will use " 3663 "the config file on the card's flash " 3664 "instead.\n", s, sc->cfg_file); 3665 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3666 "%s", FLASH_CF); 3667 } 3668 } 3669 } 3670 3671 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 && 3672 default_cfg == NULL) { 3673 device_printf(sc->dev, 3674 "default config file not available, will use the config " 3675 "file on the card's flash instead.\n"); 3676 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF); 3677 } 3678 3679 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3680 u_int cflen; 3681 const uint32_t *cfdata; 3682 uint32_t param, val, addr; 3683 3684 KASSERT(cfg != NULL || default_cfg != NULL, 3685 ("%s: no config to upload", __func__)); 3686 3687 /* 3688 * Ask the firmware where it wants us to upload the config file. 3689 */ 3690 param = FW_PARAM_DEV(CF); 3691 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3692 if (rc != 0) { 3693 /* No support for config file? Shouldn't happen. */ 3694 device_printf(sc->dev, 3695 "failed to query config file location: %d.\n", rc); 3696 goto done; 3697 } 3698 mtype = G_FW_PARAMS_PARAM_Y(val); 3699 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3700 3701 /* 3702 * XXX: sheer laziness. We deliberately added 4 bytes of 3703 * useless stuffing/comments at the end of the config file so 3704 * it's ok to simply throw away the last remaining bytes when 3705 * the config file is not an exact multiple of 4. This also 3706 * helps with the validate_mt_off_len check. 3707 */ 3708 if (cfg != NULL) { 3709 cflen = cfg->datasize & ~3; 3710 cfdata = cfg->data; 3711 } else { 3712 cflen = default_cfg->datasize & ~3; 3713 cfdata = default_cfg->data; 3714 } 3715 3716 if (cflen > FLASH_CFG_MAX_SIZE) { 3717 device_printf(sc->dev, 3718 "config file too long (%d, max allowed is %d). " 3719 "Will try to use the config on the card, if any.\n", 3720 cflen, FLASH_CFG_MAX_SIZE); 3721 goto use_config_on_flash; 3722 } 3723 3724 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3725 if (rc != 0) { 3726 device_printf(sc->dev, 3727 "%s: addr (%d/0x%x) or len %d is not valid: %d. " 3728 "Will try to use the config on the card, if any.\n", 3729 __func__, mtype, moff, cflen, rc); 3730 goto use_config_on_flash; 3731 } 3732 write_via_memwin(sc, 2, addr, cfdata, cflen); 3733 } else { 3734use_config_on_flash: 3735 mtype = FW_MEMTYPE_FLASH; 3736 moff = t4_flash_cfg_addr(sc); 3737 } 3738 3739 bzero(&caps, sizeof(caps)); 3740 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3741 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3742 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3743 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3744 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps)); 3745 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3746 if (rc != 0) { 3747 device_printf(sc->dev, 3748 "failed to pre-process config file: %d " 3749 "(mtype %d, moff 0x%x). Will reset the firmware and retry " 3750 "with the built-in configuration.\n", rc, mtype, moff); 3751 3752 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 3753 if (rc != 0) { 3754 device_printf(sc->dev, 3755 "firmware reset failed: %d.\n", rc); 3756 if (rc != ETIMEDOUT && rc != EIO) { 3757 t4_fw_bye(sc, sc->mbox); 3758 sc->flags &= ~FW_OK; 3759 } 3760 goto done; 3761 } 3762 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", "built-in"); 3763use_built_in_config: 3764 bzero(&caps, sizeof(caps)); 3765 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3766 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3767 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3768 rc = t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3769 if (rc != 0) { 3770 device_printf(sc->dev, 3771 "built-in configuration failed: %d.\n", rc); 3772 goto done; 3773 } 3774 } 3775 3776 finicsum = be32toh(caps.finicsum); 3777 cfcsum = be32toh(caps.cfcsum); 3778 if (finicsum != cfcsum) { 3779 device_printf(sc->dev, 3780 "WARNING: config file checksum mismatch: %08x %08x\n", 3781 finicsum, cfcsum); 3782 } 3783 sc->cfcsum = cfcsum; 3784 3785#define LIMIT_CAPS(x) do { \ 3786 caps.x &= htobe16(t4_##x##_allowed); \ 3787} while (0) 3788 3789 /* 3790 * Let the firmware know what features will (not) be used so it can tune 3791 * things accordingly. 3792 */ 3793 LIMIT_CAPS(nbmcaps); 3794 LIMIT_CAPS(linkcaps); 3795 LIMIT_CAPS(switchcaps); 3796 LIMIT_CAPS(niccaps); 3797 LIMIT_CAPS(toecaps); 3798 LIMIT_CAPS(rdmacaps); 3799 LIMIT_CAPS(cryptocaps); 3800 LIMIT_CAPS(iscsicaps); 3801 LIMIT_CAPS(fcoecaps); 3802#undef LIMIT_CAPS 3803 3804 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 3805 /* 3806 * TOE and hashfilters are mutually exclusive. It is a config 3807 * file or firmware bug if both are reported as available. Try 3808 * to cope with the situation in non-debug builds by disabling 3809 * TOE. 3810 */ 3811 MPASS(caps.toecaps == 0); 3812 3813 caps.toecaps = 0; 3814 caps.rdmacaps = 0; 3815 caps.iscsicaps = 0; 3816 } 3817 3818 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3819 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3820 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3821 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3822 if (rc != 0) { 3823 device_printf(sc->dev, 3824 "failed to process config file: %d.\n", rc); 3825 } 3826done: 3827 if (cfg != NULL) 3828 firmware_put(cfg, FIRMWARE_UNLOAD); 3829 return (rc); 3830} 3831 3832/* 3833 * Retrieve parameters that are needed (or nice to have) very early. 3834 */ 3835static int 3836get_params__pre_init(struct adapter *sc) 3837{ 3838 int rc; 3839 uint32_t param[2], val[2]; 3840 3841 t4_get_version_info(sc); 3842 3843 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 3844 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 3845 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 3846 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 3847 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 3848 3849 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 3850 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 3851 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 3852 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 3853 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 3854 3855 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 3856 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 3857 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 3858 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 3859 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 3860 3861 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 3862 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 3863 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 3864 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 3865 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 3866 3867 param[0] = FW_PARAM_DEV(PORTVEC); 3868 param[1] = FW_PARAM_DEV(CCLK); 3869 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3870 if (rc != 0) { 3871 device_printf(sc->dev, 3872 "failed to query parameters (pre_init): %d.\n", rc); 3873 return (rc); 3874 } 3875 3876 sc->params.portvec = val[0]; 3877 sc->params.nports = bitcount32(val[0]); 3878 sc->params.vpd.cclk = val[1]; 3879 3880 /* Read device log parameters. */ 3881 rc = -t4_init_devlog_params(sc, 1); 3882 if (rc == 0) 3883 fixup_devlog_params(sc); 3884 else { 3885 device_printf(sc->dev, 3886 "failed to get devlog parameters: %d.\n", rc); 3887 rc = 0; /* devlog isn't critical for device operation */ 3888 } 3889 3890 return (rc); 3891} 3892 3893/* 3894 * Retrieve various parameters that are of interest to the driver. The device 3895 * has been initialized by the firmware at this point. 3896 */ 3897static int 3898get_params__post_init(struct adapter *sc) 3899{ 3900 int rc; 3901 uint32_t param[7], val[7]; 3902 struct fw_caps_config_cmd caps; 3903 3904 param[0] = FW_PARAM_PFVF(IQFLINT_START); 3905 param[1] = FW_PARAM_PFVF(EQ_START); 3906 param[2] = FW_PARAM_PFVF(FILTER_START); 3907 param[3] = FW_PARAM_PFVF(FILTER_END); 3908 param[4] = FW_PARAM_PFVF(L2T_START); 3909 param[5] = FW_PARAM_PFVF(L2T_END); 3910 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3911 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 3912 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 3913 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 3914 if (rc != 0) { 3915 device_printf(sc->dev, 3916 "failed to query parameters (post_init): %d.\n", rc); 3917 return (rc); 3918 } 3919 3920 sc->sge.iq_start = val[0]; 3921 sc->sge.eq_start = val[1]; 3922 if (val[3] > val[2]) { 3923 sc->tids.ftid_base = val[2]; 3924 sc->tids.ftid_end = val[3]; 3925 sc->tids.nftids = val[3] - val[2] + 1; 3926 } 3927 sc->vres.l2t.start = val[4]; 3928 sc->vres.l2t.size = val[5] - val[4] + 1; 3929 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 3930 ("%s: L2 table size (%u) larger than expected (%u)", 3931 __func__, sc->vres.l2t.size, L2T_SIZE)); 3932 sc->params.core_vdd = val[6]; 3933 3934 if (chip_id(sc) >= CHELSIO_T6) { 3935 3936#ifdef INVARIANTS 3937 if (sc->params.fw_vers >= 3938 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 3939 V_FW_HDR_FW_VER_MICRO(1) | V_FW_HDR_FW_VER_BUILD(0))) { 3940 /* 3941 * Note that the code to enable the region should run 3942 * before t4_fw_initialize and not here. This is just a 3943 * reminder to add said code. 3944 */ 3945 device_printf(sc->dev, 3946 "hpfilter region not enabled.\n"); 3947 } 3948#endif 3949 3950 sc->tids.tid_base = t4_read_reg(sc, 3951 A_LE_DB_ACTIVE_TABLE_START_INDEX); 3952 3953 param[0] = FW_PARAM_PFVF(HPFILTER_START); 3954 param[1] = FW_PARAM_PFVF(HPFILTER_END); 3955 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3956 if (rc != 0) { 3957 device_printf(sc->dev, 3958 "failed to query hpfilter parameters: %d.\n", rc); 3959 return (rc); 3960 } 3961 if ((int)val[1] > (int)val[0]) { 3962 sc->tids.hpftid_base = val[0]; 3963 sc->tids.hpftid_end = val[1]; 3964 sc->tids.nhpftids = val[1] - val[0] + 1; 3965 3966 /* 3967 * These should go off if the layout changes and the 3968 * driver needs to catch up. 3969 */ 3970 MPASS(sc->tids.hpftid_base == 0); 3971 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 3972 } 3973 } 3974 3975 /* 3976 * MPSBGMAP is queried separately because only recent firmwares support 3977 * it as a parameter and we don't want the compound query above to fail 3978 * on older firmwares. 3979 */ 3980 param[0] = FW_PARAM_DEV(MPSBGMAP); 3981 val[0] = 0; 3982 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 3983 if (rc == 0) 3984 sc->params.mps_bg_map = val[0]; 3985 else 3986 sc->params.mps_bg_map = 0; 3987 3988 /* 3989 * Determine whether the firmware supports the filter2 work request. 3990 * This is queried separately for the same reason as MPSBGMAP above. 3991 */ 3992 param[0] = FW_PARAM_DEV(FILTER2_WR); 3993 val[0] = 0; 3994 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 3995 if (rc == 0) 3996 sc->params.filter2_wr_support = val[0] != 0; 3997 else 3998 sc->params.filter2_wr_support = 0; 3999 4000 /* get capabilites */ 4001 bzero(&caps, sizeof(caps)); 4002 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4003 F_FW_CMD_REQUEST | F_FW_CMD_READ); 4004 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4005 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 4006 if (rc != 0) { 4007 device_printf(sc->dev, 4008 "failed to get card capabilities: %d.\n", rc); 4009 return (rc); 4010 } 4011 4012#define READ_CAPS(x) do { \ 4013 sc->x = htobe16(caps.x); \ 4014} while (0) 4015 READ_CAPS(nbmcaps); 4016 READ_CAPS(linkcaps); 4017 READ_CAPS(switchcaps); 4018 READ_CAPS(niccaps); 4019 READ_CAPS(toecaps); 4020 READ_CAPS(rdmacaps); 4021 READ_CAPS(cryptocaps); 4022 READ_CAPS(iscsicaps); 4023 READ_CAPS(fcoecaps); 4024 4025 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 4026 MPASS(chip_id(sc) > CHELSIO_T4); 4027 MPASS(sc->toecaps == 0); 4028 sc->toecaps = 0; 4029 4030 param[0] = FW_PARAM_DEV(NTID); 4031 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4032 if (rc != 0) { 4033 device_printf(sc->dev, 4034 "failed to query HASHFILTER parameters: %d.\n", rc); 4035 return (rc); 4036 } 4037 sc->tids.ntids = val[0]; 4038 if (sc->params.fw_vers < 4039 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4040 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) { 4041 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4042 sc->tids.ntids -= sc->tids.nhpftids; 4043 } 4044 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4045 sc->params.hash_filter = 1; 4046 } 4047 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 4048 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 4049 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 4050 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4051 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 4052 if (rc != 0) { 4053 device_printf(sc->dev, 4054 "failed to query NIC parameters: %d.\n", rc); 4055 return (rc); 4056 } 4057 if (val[1] > val[0]) { 4058 sc->tids.etid_base = val[0]; 4059 sc->tids.etid_end = val[1]; 4060 sc->tids.netids = val[1] - val[0] + 1; 4061 sc->params.eo_wr_cred = val[2]; 4062 sc->params.ethoffload = 1; 4063 } 4064 } 4065 if (sc->toecaps) { 4066 /* query offload-related parameters */ 4067 param[0] = FW_PARAM_DEV(NTID); 4068 param[1] = FW_PARAM_PFVF(SERVER_START); 4069 param[2] = FW_PARAM_PFVF(SERVER_END); 4070 param[3] = FW_PARAM_PFVF(TDDP_START); 4071 param[4] = FW_PARAM_PFVF(TDDP_END); 4072 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4073 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4074 if (rc != 0) { 4075 device_printf(sc->dev, 4076 "failed to query TOE parameters: %d.\n", rc); 4077 return (rc); 4078 } 4079 sc->tids.ntids = val[0]; 4080 if (sc->params.fw_vers < 4081 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4082 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) { 4083 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4084 sc->tids.ntids -= sc->tids.nhpftids; 4085 } 4086 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4087 if (val[2] > val[1]) { 4088 sc->tids.stid_base = val[1]; 4089 sc->tids.nstids = val[2] - val[1] + 1; 4090 } 4091 sc->vres.ddp.start = val[3]; 4092 sc->vres.ddp.size = val[4] - val[3] + 1; 4093 sc->params.ofldq_wr_cred = val[5]; 4094 sc->params.offload = 1; 4095 } else { 4096 /* 4097 * The firmware attempts memfree TOE configuration for -SO cards 4098 * and will report toecaps=0 if it runs out of resources (this 4099 * depends on the config file). It may not report 0 for other 4100 * capabilities dependent on the TOE in this case. Set them to 4101 * 0 here so that the driver doesn't bother tracking resources 4102 * that will never be used. 4103 */ 4104 sc->iscsicaps = 0; 4105 sc->rdmacaps = 0; 4106 } 4107 if (sc->rdmacaps) { 4108 param[0] = FW_PARAM_PFVF(STAG_START); 4109 param[1] = FW_PARAM_PFVF(STAG_END); 4110 param[2] = FW_PARAM_PFVF(RQ_START); 4111 param[3] = FW_PARAM_PFVF(RQ_END); 4112 param[4] = FW_PARAM_PFVF(PBL_START); 4113 param[5] = FW_PARAM_PFVF(PBL_END); 4114 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4115 if (rc != 0) { 4116 device_printf(sc->dev, 4117 "failed to query RDMA parameters(1): %d.\n", rc); 4118 return (rc); 4119 } 4120 sc->vres.stag.start = val[0]; 4121 sc->vres.stag.size = val[1] - val[0] + 1; 4122 sc->vres.rq.start = val[2]; 4123 sc->vres.rq.size = val[3] - val[2] + 1; 4124 sc->vres.pbl.start = val[4]; 4125 sc->vres.pbl.size = val[5] - val[4] + 1; 4126 4127 param[0] = FW_PARAM_PFVF(SQRQ_START); 4128 param[1] = FW_PARAM_PFVF(SQRQ_END); 4129 param[2] = FW_PARAM_PFVF(CQ_START); 4130 param[3] = FW_PARAM_PFVF(CQ_END); 4131 param[4] = FW_PARAM_PFVF(OCQ_START); 4132 param[5] = FW_PARAM_PFVF(OCQ_END); 4133 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4134 if (rc != 0) { 4135 device_printf(sc->dev, 4136 "failed to query RDMA parameters(2): %d.\n", rc); 4137 return (rc); 4138 } 4139 sc->vres.qp.start = val[0]; 4140 sc->vres.qp.size = val[1] - val[0] + 1; 4141 sc->vres.cq.start = val[2]; 4142 sc->vres.cq.size = val[3] - val[2] + 1; 4143 sc->vres.ocq.start = val[4]; 4144 sc->vres.ocq.size = val[5] - val[4] + 1; 4145 4146 param[0] = FW_PARAM_PFVF(SRQ_START); 4147 param[1] = FW_PARAM_PFVF(SRQ_END); 4148 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 4149 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4150 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 4151 if (rc != 0) { 4152 device_printf(sc->dev, 4153 "failed to query RDMA parameters(3): %d.\n", rc); 4154 return (rc); 4155 } 4156 sc->vres.srq.start = val[0]; 4157 sc->vres.srq.size = val[1] - val[0] + 1; 4158 sc->params.max_ordird_qp = val[2]; 4159 sc->params.max_ird_adapter = val[3]; 4160 } 4161 if (sc->iscsicaps) { 4162 param[0] = FW_PARAM_PFVF(ISCSI_START); 4163 param[1] = FW_PARAM_PFVF(ISCSI_END); 4164 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4165 if (rc != 0) { 4166 device_printf(sc->dev, 4167 "failed to query iSCSI parameters: %d.\n", rc); 4168 return (rc); 4169 } 4170 sc->vres.iscsi.start = val[0]; 4171 sc->vres.iscsi.size = val[1] - val[0] + 1; 4172 } 4173 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 4174 param[0] = FW_PARAM_PFVF(TLS_START); 4175 param[1] = FW_PARAM_PFVF(TLS_END); 4176 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4177 if (rc != 0) { 4178 device_printf(sc->dev, 4179 "failed to query TLS parameters: %d.\n", rc); 4180 return (rc); 4181 } 4182 sc->vres.key.start = val[0]; 4183 sc->vres.key.size = val[1] - val[0] + 1; 4184 } 4185 4186 t4_init_sge_params(sc); 4187 4188 /* 4189 * We've got the params we wanted to query via the firmware. Now grab 4190 * some others directly from the chip. 4191 */ 4192 rc = t4_read_chip_settings(sc); 4193 4194 return (rc); 4195} 4196 4197static int 4198set_params__post_init(struct adapter *sc) 4199{ 4200 uint32_t param, val; 4201#ifdef TCP_OFFLOAD 4202 int i, v, shift; 4203#endif 4204 4205 /* ask for encapsulated CPLs */ 4206 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 4207 val = 1; 4208 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4209 4210 /* Enable 32b port caps if the firmware supports it. */ 4211 param = FW_PARAM_PFVF(PORT_CAPS32); 4212 val = 1; 4213 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 4214 sc->params.port_caps32 = 1; 4215 4216#ifdef TCP_OFFLOAD 4217 /* 4218 * Override the TOE timers with user provided tunables. This is not the 4219 * recommended way to change the timers (the firmware config file is) so 4220 * these tunables are not documented. 4221 * 4222 * All the timer tunables are in microseconds. 4223 */ 4224 if (t4_toe_keepalive_idle != 0) { 4225 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 4226 v &= M_KEEPALIVEIDLE; 4227 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 4228 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 4229 } 4230 if (t4_toe_keepalive_interval != 0) { 4231 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 4232 v &= M_KEEPALIVEINTVL; 4233 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 4234 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 4235 } 4236 if (t4_toe_keepalive_count != 0) { 4237 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 4238 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4239 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 4240 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 4241 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 4242 } 4243 if (t4_toe_rexmt_min != 0) { 4244 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 4245 v &= M_RXTMIN; 4246 t4_set_reg_field(sc, A_TP_RXT_MIN, 4247 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 4248 } 4249 if (t4_toe_rexmt_max != 0) { 4250 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 4251 v &= M_RXTMAX; 4252 t4_set_reg_field(sc, A_TP_RXT_MAX, 4253 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 4254 } 4255 if (t4_toe_rexmt_count != 0) { 4256 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 4257 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4258 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 4259 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 4260 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 4261 } 4262 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 4263 if (t4_toe_rexmt_backoff[i] != -1) { 4264 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 4265 shift = (i & 3) << 3; 4266 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 4267 M_TIMERBACKOFFINDEX0 << shift, v << shift); 4268 } 4269 } 4270#endif 4271 return (0); 4272} 4273 4274#undef FW_PARAM_PFVF 4275#undef FW_PARAM_DEV 4276 4277static void 4278t4_set_desc(struct adapter *sc) 4279{ 4280 char buf[128]; 4281 struct adapter_params *p = &sc->params; 4282 4283 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 4284 4285 device_set_desc_copy(sc->dev, buf); 4286} 4287 4288static inline void 4289ifmedia_add4(struct ifmedia *ifm, int m) 4290{ 4291 4292 ifmedia_add(ifm, m, 0, NULL); 4293 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 4294 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 4295 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 4296} 4297 4298/* 4299 * This is the selected media, which is not quite the same as the active media. 4300 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 4301 * and active are not the same, and "media: Ethernet selected" otherwise. 4302 */ 4303static void 4304set_current_media(struct port_info *pi) 4305{ 4306 struct link_config *lc; 4307 struct ifmedia *ifm; 4308 int mword; 4309 u_int speed; 4310 4311 PORT_LOCK_ASSERT_OWNED(pi); 4312 4313 /* Leave current media alone if it's already set to IFM_NONE. */ 4314 ifm = &pi->media; 4315 if (ifm->ifm_cur != NULL && 4316 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 4317 return; 4318 4319 lc = &pi->link_cfg; 4320 if (lc->requested_aneg != AUTONEG_DISABLE && 4321 lc->supported & FW_PORT_CAP32_ANEG) { 4322 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 4323 return; 4324 } 4325 mword = IFM_ETHER | IFM_FDX; 4326 if (lc->requested_fc & PAUSE_TX) 4327 mword |= IFM_ETH_TXPAUSE; 4328 if (lc->requested_fc & PAUSE_RX) 4329 mword |= IFM_ETH_RXPAUSE; 4330 if (lc->requested_speed == 0) 4331 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 4332 else 4333 speed = lc->requested_speed; 4334 mword |= port_mword(pi, speed_to_fwcap(speed)); 4335 ifmedia_set(ifm, mword); 4336} 4337 4338/* 4339 * Returns true if the ifmedia list for the port cannot change. 4340 */ 4341static bool 4342fixed_ifmedia(struct port_info *pi) 4343{ 4344 4345 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 4346 pi->port_type == FW_PORT_TYPE_BT_XFI || 4347 pi->port_type == FW_PORT_TYPE_BT_XAUI || 4348 pi->port_type == FW_PORT_TYPE_KX4 || 4349 pi->port_type == FW_PORT_TYPE_KX || 4350 pi->port_type == FW_PORT_TYPE_KR || 4351 pi->port_type == FW_PORT_TYPE_BP_AP || 4352 pi->port_type == FW_PORT_TYPE_BP4_AP || 4353 pi->port_type == FW_PORT_TYPE_BP40_BA || 4354 pi->port_type == FW_PORT_TYPE_KR4_100G || 4355 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 4356 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 4357} 4358 4359static void 4360build_medialist(struct port_info *pi) 4361{ 4362 uint32_t ss, speed; 4363 int unknown, mword, bit; 4364 struct link_config *lc; 4365 struct ifmedia *ifm; 4366 4367 PORT_LOCK_ASSERT_OWNED(pi); 4368 4369 if (pi->flags & FIXED_IFMEDIA) 4370 return; 4371 4372 /* 4373 * Rebuild the ifmedia list. 4374 */ 4375 ifm = &pi->media; 4376 ifmedia_removeall(ifm); 4377 lc = &pi->link_cfg; 4378 ss = G_FW_PORT_CAP32_SPEED(lc->supported); /* Supported Speeds */ 4379 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 4380 MPASS(ss != 0); 4381no_media: 4382 MPASS(LIST_EMPTY(&ifm->ifm_list)); 4383 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 4384 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 4385 return; 4386 } 4387 4388 unknown = 0; 4389 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 4390 speed = 1 << bit; 4391 MPASS(speed & M_FW_PORT_CAP32_SPEED); 4392 if (ss & speed) { 4393 mword = port_mword(pi, speed); 4394 if (mword == IFM_NONE) { 4395 goto no_media; 4396 } else if (mword == IFM_UNKNOWN) 4397 unknown++; 4398 else 4399 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 4400 } 4401 } 4402 if (unknown > 0) /* Add one unknown for all unknown media types. */ 4403 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 4404 if (lc->supported & FW_PORT_CAP32_ANEG) 4405 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 4406 4407 set_current_media(pi); 4408} 4409 4410/* 4411 * Initialize the requested fields in the link config based on driver tunables. 4412 */ 4413static void 4414init_link_config(struct port_info *pi) 4415{ 4416 struct link_config *lc = &pi->link_cfg; 4417 4418 PORT_LOCK_ASSERT_OWNED(pi); 4419 4420 lc->requested_speed = 0; 4421 4422 if (t4_autoneg == 0) 4423 lc->requested_aneg = AUTONEG_DISABLE; 4424 else if (t4_autoneg == 1) 4425 lc->requested_aneg = AUTONEG_ENABLE; 4426 else 4427 lc->requested_aneg = AUTONEG_AUTO; 4428 4429 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 4430 PAUSE_AUTONEG); 4431 4432 if (t4_fec == -1 || t4_fec & FEC_AUTO) 4433 lc->requested_fec = FEC_AUTO; 4434 else { 4435 lc->requested_fec = FEC_NONE; 4436 if (t4_fec & FEC_RS) 4437 lc->requested_fec |= FEC_RS; 4438 if (t4_fec & FEC_BASER_RS) 4439 lc->requested_fec |= FEC_BASER_RS; 4440 } 4441} 4442 4443/* 4444 * Makes sure that all requested settings comply with what's supported by the 4445 * port. Returns the number of settings that were invalid and had to be fixed. 4446 */ 4447static int 4448fixup_link_config(struct port_info *pi) 4449{ 4450 int n = 0; 4451 struct link_config *lc = &pi->link_cfg; 4452 uint32_t fwspeed; 4453 4454 PORT_LOCK_ASSERT_OWNED(pi); 4455 4456 /* Speed (when not autonegotiating) */ 4457 if (lc->requested_speed != 0) { 4458 fwspeed = speed_to_fwcap(lc->requested_speed); 4459 if ((fwspeed & lc->supported) == 0) { 4460 n++; 4461 lc->requested_speed = 0; 4462 } 4463 } 4464 4465 /* Link autonegotiation */ 4466 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 4467 lc->requested_aneg == AUTONEG_DISABLE || 4468 lc->requested_aneg == AUTONEG_AUTO); 4469 if (lc->requested_aneg == AUTONEG_ENABLE && 4470 !(lc->supported & FW_PORT_CAP32_ANEG)) { 4471 n++; 4472 lc->requested_aneg = AUTONEG_AUTO; 4473 } 4474 4475 /* Flow control */ 4476 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 4477 if (lc->requested_fc & PAUSE_TX && 4478 !(lc->supported & FW_PORT_CAP32_FC_TX)) { 4479 n++; 4480 lc->requested_fc &= ~PAUSE_TX; 4481 } 4482 if (lc->requested_fc & PAUSE_RX && 4483 !(lc->supported & FW_PORT_CAP32_FC_RX)) { 4484 n++; 4485 lc->requested_fc &= ~PAUSE_RX; 4486 } 4487 if (!(lc->requested_fc & PAUSE_AUTONEG) && 4488 !(lc->supported & FW_PORT_CAP32_FORCE_PAUSE)) { 4489 n++; 4490 lc->requested_fc |= PAUSE_AUTONEG; 4491 } 4492 4493 /* FEC */ 4494 if ((lc->requested_fec & FEC_RS && 4495 !(lc->supported & FW_PORT_CAP32_FEC_RS)) || 4496 (lc->requested_fec & FEC_BASER_RS && 4497 !(lc->supported & FW_PORT_CAP32_FEC_BASER_RS))) { 4498 n++; 4499 lc->requested_fec = FEC_AUTO; 4500 } 4501 4502 return (n); 4503} 4504 4505/* 4506 * Apply the requested L1 settings, which are expected to be valid, to the 4507 * hardware. 4508 */ 4509static int 4510apply_link_config(struct port_info *pi) 4511{ 4512 struct adapter *sc = pi->adapter; 4513 struct link_config *lc = &pi->link_cfg; 4514 int rc; 4515 4516#ifdef INVARIANTS 4517 ASSERT_SYNCHRONIZED_OP(sc); 4518 PORT_LOCK_ASSERT_OWNED(pi); 4519 4520 if (lc->requested_aneg == AUTONEG_ENABLE) 4521 MPASS(lc->supported & FW_PORT_CAP32_ANEG); 4522 if (!(lc->requested_fc & PAUSE_AUTONEG)) 4523 MPASS(lc->supported & FW_PORT_CAP32_FORCE_PAUSE); 4524 if (lc->requested_fc & PAUSE_TX) 4525 MPASS(lc->supported & FW_PORT_CAP32_FC_TX); 4526 if (lc->requested_fc & PAUSE_RX) 4527 MPASS(lc->supported & FW_PORT_CAP32_FC_RX); 4528 if (lc->requested_fec & FEC_RS) 4529 MPASS(lc->supported & FW_PORT_CAP32_FEC_RS); 4530 if (lc->requested_fec & FEC_BASER_RS) 4531 MPASS(lc->supported & FW_PORT_CAP32_FEC_BASER_RS); 4532#endif 4533 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 4534 if (rc != 0) { 4535 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 4536 } else { 4537 /* 4538 * An L1_CFG will almost always result in a link-change event if 4539 * the link is up, and the driver will refresh the actual 4540 * fec/fc/etc. when the notification is processed. If the link 4541 * is down then the actual settings are meaningless. 4542 * 4543 * This takes care of the case where a change in the L1 settings 4544 * may not result in a notification. 4545 */ 4546 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 4547 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 4548 } 4549 return (rc); 4550} 4551 4552#define FW_MAC_EXACT_CHUNK 7 4553 4554/* 4555 * Program the port's XGMAC based on parameters in ifnet. The caller also 4556 * indicates which parameters should be programmed (the rest are left alone). 4557 */ 4558int 4559update_mac_settings(struct ifnet *ifp, int flags) 4560{ 4561 int rc = 0; 4562 struct vi_info *vi = ifp->if_softc; 4563 struct port_info *pi = vi->pi; 4564 struct adapter *sc = pi->adapter; 4565 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 4566 4567 ASSERT_SYNCHRONIZED_OP(sc); 4568 KASSERT(flags, ("%s: not told what to update.", __func__)); 4569 4570 if (flags & XGMAC_MTU) 4571 mtu = ifp->if_mtu; 4572 4573 if (flags & XGMAC_PROMISC) 4574 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 4575 4576 if (flags & XGMAC_ALLMULTI) 4577 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 4578 4579 if (flags & XGMAC_VLANEX) 4580 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 4581 4582 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 4583 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 4584 allmulti, 1, vlanex, false); 4585 if (rc) { 4586 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 4587 rc); 4588 return (rc); 4589 } 4590 } 4591 4592 if (flags & XGMAC_UCADDR) { 4593 uint8_t ucaddr[ETHER_ADDR_LEN]; 4594 4595 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 4596 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 4597 ucaddr, true, true); 4598 if (rc < 0) { 4599 rc = -rc; 4600 if_printf(ifp, "change_mac failed: %d\n", rc); 4601 return (rc); 4602 } else { 4603 vi->xact_addr_filt = rc; 4604 rc = 0; 4605 } 4606 } 4607 4608 if (flags & XGMAC_MCADDRS) { 4609 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 4610 int del = 1; 4611 uint64_t hash = 0; 4612 struct ifmultiaddr *ifma; 4613 int i = 0, j; 4614 4615 if_maddr_rlock(ifp); 4616 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4617 if (ifma->ifma_addr->sa_family != AF_LINK) 4618 continue; 4619 mcaddr[i] = 4620 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 4621 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 4622 i++; 4623 4624 if (i == FW_MAC_EXACT_CHUNK) { 4625 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 4626 del, i, mcaddr, NULL, &hash, 0); 4627 if (rc < 0) { 4628 rc = -rc; 4629 for (j = 0; j < i; j++) { 4630 if_printf(ifp, 4631 "failed to add mc address" 4632 " %02x:%02x:%02x:" 4633 "%02x:%02x:%02x rc=%d\n", 4634 mcaddr[j][0], mcaddr[j][1], 4635 mcaddr[j][2], mcaddr[j][3], 4636 mcaddr[j][4], mcaddr[j][5], 4637 rc); 4638 } 4639 goto mcfail; 4640 } 4641 del = 0; 4642 i = 0; 4643 } 4644 } 4645 if (i > 0) { 4646 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 4647 mcaddr, NULL, &hash, 0); 4648 if (rc < 0) { 4649 rc = -rc; 4650 for (j = 0; j < i; j++) { 4651 if_printf(ifp, 4652 "failed to add mc address" 4653 " %02x:%02x:%02x:" 4654 "%02x:%02x:%02x rc=%d\n", 4655 mcaddr[j][0], mcaddr[j][1], 4656 mcaddr[j][2], mcaddr[j][3], 4657 mcaddr[j][4], mcaddr[j][5], 4658 rc); 4659 } 4660 goto mcfail; 4661 } 4662 } 4663 4664 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 4665 if (rc != 0) 4666 if_printf(ifp, "failed to set mc address hash: %d", rc); 4667mcfail: 4668 if_maddr_runlock(ifp); 4669 } 4670 4671 return (rc); 4672} 4673 4674/* 4675 * {begin|end}_synchronized_op must be called from the same thread. 4676 */ 4677int 4678begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 4679 char *wmesg) 4680{ 4681 int rc, pri; 4682 4683#ifdef WITNESS 4684 /* the caller thinks it's ok to sleep, but is it really? */ 4685 if (flags & SLEEP_OK) 4686 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 4687 "begin_synchronized_op"); 4688#endif 4689 4690 if (INTR_OK) 4691 pri = PCATCH; 4692 else 4693 pri = 0; 4694 4695 ADAPTER_LOCK(sc); 4696 for (;;) { 4697 4698 if (vi && IS_DOOMED(vi)) { 4699 rc = ENXIO; 4700 goto done; 4701 } 4702 4703 if (!IS_BUSY(sc)) { 4704 rc = 0; 4705 break; 4706 } 4707 4708 if (!(flags & SLEEP_OK)) { 4709 rc = EBUSY; 4710 goto done; 4711 } 4712 4713 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 4714 rc = EINTR; 4715 goto done; 4716 } 4717 } 4718 4719 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 4720 SET_BUSY(sc); 4721#ifdef INVARIANTS 4722 sc->last_op = wmesg; 4723 sc->last_op_thr = curthread; 4724 sc->last_op_flags = flags; 4725#endif 4726 4727done: 4728 if (!(flags & HOLD_LOCK) || rc) 4729 ADAPTER_UNLOCK(sc); 4730 4731 return (rc); 4732} 4733 4734/* 4735 * Tell if_ioctl and if_init that the VI is going away. This is 4736 * special variant of begin_synchronized_op and must be paired with a 4737 * call to end_synchronized_op. 4738 */ 4739void 4740doom_vi(struct adapter *sc, struct vi_info *vi) 4741{ 4742 4743 ADAPTER_LOCK(sc); 4744 SET_DOOMED(vi); 4745 wakeup(&sc->flags); 4746 while (IS_BUSY(sc)) 4747 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 4748 SET_BUSY(sc); 4749#ifdef INVARIANTS 4750 sc->last_op = "t4detach"; 4751 sc->last_op_thr = curthread; 4752 sc->last_op_flags = 0; 4753#endif 4754 ADAPTER_UNLOCK(sc); 4755} 4756 4757/* 4758 * {begin|end}_synchronized_op must be called from the same thread. 4759 */ 4760void 4761end_synchronized_op(struct adapter *sc, int flags) 4762{ 4763 4764 if (flags & LOCK_HELD) 4765 ADAPTER_LOCK_ASSERT_OWNED(sc); 4766 else 4767 ADAPTER_LOCK(sc); 4768 4769 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 4770 CLR_BUSY(sc); 4771 wakeup(&sc->flags); 4772 ADAPTER_UNLOCK(sc); 4773} 4774 4775static int 4776cxgbe_init_synchronized(struct vi_info *vi) 4777{ 4778 struct port_info *pi = vi->pi; 4779 struct adapter *sc = pi->adapter; 4780 struct ifnet *ifp = vi->ifp; 4781 int rc = 0, i; 4782 struct sge_txq *txq; 4783 4784 ASSERT_SYNCHRONIZED_OP(sc); 4785 4786 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4787 return (0); /* already running */ 4788 4789 if (!(sc->flags & FULL_INIT_DONE) && 4790 ((rc = adapter_full_init(sc)) != 0)) 4791 return (rc); /* error message displayed already */ 4792 4793 if (!(vi->flags & VI_INIT_DONE) && 4794 ((rc = vi_full_init(vi)) != 0)) 4795 return (rc); /* error message displayed already */ 4796 4797 rc = update_mac_settings(ifp, XGMAC_ALL); 4798 if (rc) 4799 goto done; /* error message displayed already */ 4800 4801 PORT_LOCK(pi); 4802 if (pi->up_vis == 0) { 4803 t4_update_port_info(pi); 4804 fixup_link_config(pi); 4805 build_medialist(pi); 4806 apply_link_config(pi); 4807 } 4808 4809 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 4810 if (rc != 0) { 4811 if_printf(ifp, "enable_vi failed: %d\n", rc); 4812 PORT_UNLOCK(pi); 4813 goto done; 4814 } 4815 4816 /* 4817 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 4818 * if this changes. 4819 */ 4820 4821 for_each_txq(vi, i, txq) { 4822 TXQ_LOCK(txq); 4823 txq->eq.flags |= EQ_ENABLED; 4824 TXQ_UNLOCK(txq); 4825 } 4826 4827 /* 4828 * The first iq of the first port to come up is used for tracing. 4829 */ 4830 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 4831 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 4832 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 4833 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 4834 V_QUEUENUMBER(sc->traceq)); 4835 pi->flags |= HAS_TRACEQ; 4836 } 4837 4838 /* all ok */ 4839 pi->up_vis++; 4840 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4841 4842 if (pi->nvi > 1 || sc->flags & IS_VF) 4843 callout_reset(&vi->tick, hz, vi_tick, vi); 4844 else 4845 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 4846 PORT_UNLOCK(pi); 4847done: 4848 if (rc != 0) 4849 cxgbe_uninit_synchronized(vi); 4850 4851 return (rc); 4852} 4853 4854/* 4855 * Idempotent. 4856 */ 4857static int 4858cxgbe_uninit_synchronized(struct vi_info *vi) 4859{ 4860 struct port_info *pi = vi->pi; 4861 struct adapter *sc = pi->adapter; 4862 struct ifnet *ifp = vi->ifp; 4863 int rc, i; 4864 struct sge_txq *txq; 4865 4866 ASSERT_SYNCHRONIZED_OP(sc); 4867 4868 if (!(vi->flags & VI_INIT_DONE)) { 4869 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4870 KASSERT(0, ("uninited VI is running")); 4871 if_printf(ifp, "uninited VI with running ifnet. " 4872 "vi->flags 0x%016lx, if_flags 0x%08x, " 4873 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags, 4874 ifp->if_drv_flags); 4875 } 4876 return (0); 4877 } 4878 4879 /* 4880 * Disable the VI so that all its data in either direction is discarded 4881 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 4882 * tick) intact as the TP can deliver negative advice or data that it's 4883 * holding in its RAM (for an offloaded connection) even after the VI is 4884 * disabled. 4885 */ 4886 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 4887 if (rc) { 4888 if_printf(ifp, "disable_vi failed: %d\n", rc); 4889 return (rc); 4890 } 4891 4892 for_each_txq(vi, i, txq) { 4893 TXQ_LOCK(txq); 4894 txq->eq.flags &= ~EQ_ENABLED; 4895 TXQ_UNLOCK(txq); 4896 } 4897 4898 PORT_LOCK(pi); 4899 if (pi->nvi > 1 || sc->flags & IS_VF) 4900 callout_stop(&vi->tick); 4901 else 4902 callout_stop(&pi->tick); 4903 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4904 PORT_UNLOCK(pi); 4905 return (0); 4906 } 4907 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4908 pi->up_vis--; 4909 if (pi->up_vis > 0) { 4910 PORT_UNLOCK(pi); 4911 return (0); 4912 } 4913 4914 pi->link_cfg.link_ok = false; 4915 pi->link_cfg.speed = 0; 4916 pi->link_cfg.link_down_rc = 255; 4917 t4_os_link_changed(pi); 4918 PORT_UNLOCK(pi); 4919 4920 return (0); 4921} 4922 4923/* 4924 * It is ok for this function to fail midway and return right away. t4_detach 4925 * will walk the entire sc->irq list and clean up whatever is valid. 4926 */ 4927int 4928t4_setup_intr_handlers(struct adapter *sc) 4929{ 4930 int rc, rid, p, q, v; 4931 char s[8]; 4932 struct irq *irq; 4933 struct port_info *pi; 4934 struct vi_info *vi; 4935 struct sge *sge = &sc->sge; 4936 struct sge_rxq *rxq; 4937#ifdef TCP_OFFLOAD 4938 struct sge_ofld_rxq *ofld_rxq; 4939#endif 4940#ifdef DEV_NETMAP 4941 struct sge_nm_rxq *nm_rxq; 4942#endif 4943#ifdef RSS 4944 int nbuckets = rss_getnumbuckets(); 4945#endif 4946 4947 /* 4948 * Setup interrupts. 4949 */ 4950 irq = &sc->irq[0]; 4951 rid = sc->intr_type == INTR_INTX ? 0 : 1; 4952 if (forwarding_intr_to_fwq(sc)) 4953 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 4954 4955 /* Multiple interrupts. */ 4956 if (sc->flags & IS_VF) 4957 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 4958 ("%s: too few intr.", __func__)); 4959 else 4960 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 4961 ("%s: too few intr.", __func__)); 4962 4963 /* The first one is always error intr on PFs */ 4964 if (!(sc->flags & IS_VF)) { 4965 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 4966 if (rc != 0) 4967 return (rc); 4968 irq++; 4969 rid++; 4970 } 4971 4972 /* The second one is always the firmware event queue (first on VFs) */ 4973 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 4974 if (rc != 0) 4975 return (rc); 4976 irq++; 4977 rid++; 4978 4979 for_each_port(sc, p) { 4980 pi = sc->port[p]; 4981 for_each_vi(pi, v, vi) { 4982 vi->first_intr = rid - 1; 4983 4984 if (vi->nnmrxq > 0) { 4985 int n = max(vi->nrxq, vi->nnmrxq); 4986 4987 rxq = &sge->rxq[vi->first_rxq]; 4988#ifdef DEV_NETMAP 4989 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 4990#endif 4991 for (q = 0; q < n; q++) { 4992 snprintf(s, sizeof(s), "%x%c%x", p, 4993 'a' + v, q); 4994 if (q < vi->nrxq) 4995 irq->rxq = rxq++; 4996#ifdef DEV_NETMAP 4997 if (q < vi->nnmrxq) 4998 irq->nm_rxq = nm_rxq++; 4999 5000 if (irq->nm_rxq != NULL && 5001 irq->rxq == NULL) { 5002 /* Netmap rx only */ 5003 rc = t4_alloc_irq(sc, irq, rid, 5004 t4_nm_intr, irq->nm_rxq, s); 5005 } 5006 if (irq->nm_rxq != NULL && 5007 irq->rxq != NULL) { 5008 /* NIC and Netmap rx */ 5009 rc = t4_alloc_irq(sc, irq, rid, 5010 t4_vi_intr, irq, s); 5011 } 5012#endif 5013 if (irq->rxq != NULL && 5014 irq->nm_rxq == NULL) { 5015 /* NIC rx only */ 5016 rc = t4_alloc_irq(sc, irq, rid, 5017 t4_intr, irq->rxq, s); 5018 } 5019 if (rc != 0) 5020 return (rc); 5021#ifdef RSS 5022 if (q < vi->nrxq) { 5023 bus_bind_intr(sc->dev, irq->res, 5024 rss_getcpu(q % nbuckets)); 5025 } 5026#endif 5027 irq++; 5028 rid++; 5029 vi->nintr++; 5030 } 5031 } else { 5032 for_each_rxq(vi, q, rxq) { 5033 snprintf(s, sizeof(s), "%x%c%x", p, 5034 'a' + v, q); 5035 rc = t4_alloc_irq(sc, irq, rid, 5036 t4_intr, rxq, s); 5037 if (rc != 0) 5038 return (rc); 5039#ifdef RSS 5040 bus_bind_intr(sc->dev, irq->res, 5041 rss_getcpu(q % nbuckets)); 5042#endif 5043 irq++; 5044 rid++; 5045 vi->nintr++; 5046 } 5047 } 5048#ifdef TCP_OFFLOAD 5049 for_each_ofld_rxq(vi, q, ofld_rxq) { 5050 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 5051 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 5052 ofld_rxq, s); 5053 if (rc != 0) 5054 return (rc); 5055 irq++; 5056 rid++; 5057 vi->nintr++; 5058 } 5059#endif 5060 } 5061 } 5062 MPASS(irq == &sc->irq[sc->intr_count]); 5063 5064 return (0); 5065} 5066 5067int 5068adapter_full_init(struct adapter *sc) 5069{ 5070 int rc, i; 5071#ifdef RSS 5072 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5073 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5074#endif 5075 5076 ASSERT_SYNCHRONIZED_OP(sc); 5077 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5078 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 5079 ("%s: FULL_INIT_DONE already", __func__)); 5080 5081 /* 5082 * queues that belong to the adapter (not any particular port). 5083 */ 5084 rc = t4_setup_adapter_queues(sc); 5085 if (rc != 0) 5086 goto done; 5087 5088 for (i = 0; i < nitems(sc->tq); i++) { 5089 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 5090 taskqueue_thread_enqueue, &sc->tq[i]); 5091 if (sc->tq[i] == NULL) { 5092 device_printf(sc->dev, 5093 "failed to allocate task queue %d\n", i); 5094 rc = ENOMEM; 5095 goto done; 5096 } 5097 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 5098 device_get_nameunit(sc->dev), i); 5099 } 5100#ifdef RSS 5101 MPASS(RSS_KEYSIZE == 40); 5102 rss_getkey((void *)&raw_rss_key[0]); 5103 for (i = 0; i < nitems(rss_key); i++) { 5104 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 5105 } 5106 t4_write_rss_key(sc, &rss_key[0], -1, 1); 5107#endif 5108 5109 if (!(sc->flags & IS_VF)) 5110 t4_intr_enable(sc); 5111 sc->flags |= FULL_INIT_DONE; 5112done: 5113 if (rc != 0) 5114 adapter_full_uninit(sc); 5115 5116 return (rc); 5117} 5118 5119int 5120adapter_full_uninit(struct adapter *sc) 5121{ 5122 int i; 5123 5124 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5125 5126 t4_teardown_adapter_queues(sc); 5127 5128 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 5129 taskqueue_free(sc->tq[i]); 5130 sc->tq[i] = NULL; 5131 } 5132 5133 sc->flags &= ~FULL_INIT_DONE; 5134 5135 return (0); 5136} 5137 5138#ifdef RSS 5139#define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 5140 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 5141 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 5142 RSS_HASHTYPE_RSS_UDP_IPV6) 5143 5144/* Translates kernel hash types to hardware. */ 5145static int 5146hashconfig_to_hashen(int hashconfig) 5147{ 5148 int hashen = 0; 5149 5150 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 5151 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 5152 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 5153 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 5154 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 5155 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5156 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5157 } 5158 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 5159 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5160 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5161 } 5162 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 5163 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5164 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 5165 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5166 5167 return (hashen); 5168} 5169 5170/* Translates hardware hash types to kernel. */ 5171static int 5172hashen_to_hashconfig(int hashen) 5173{ 5174 int hashconfig = 0; 5175 5176 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 5177 /* 5178 * If UDP hashing was enabled it must have been enabled for 5179 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 5180 * enabling any 4-tuple hash is nonsense configuration. 5181 */ 5182 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5183 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 5184 5185 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5186 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 5187 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5188 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 5189 } 5190 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5191 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 5192 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5193 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 5194 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 5195 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 5196 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 5197 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 5198 5199 return (hashconfig); 5200} 5201#endif 5202 5203int 5204vi_full_init(struct vi_info *vi) 5205{ 5206 struct adapter *sc = vi->pi->adapter; 5207 struct ifnet *ifp = vi->ifp; 5208 uint16_t *rss; 5209 struct sge_rxq *rxq; 5210 int rc, i, j, hashen; 5211#ifdef RSS 5212 int nbuckets = rss_getnumbuckets(); 5213 int hashconfig = rss_gethashconfig(); 5214 int extra; 5215#endif 5216 5217 ASSERT_SYNCHRONIZED_OP(sc); 5218 KASSERT((vi->flags & VI_INIT_DONE) == 0, 5219 ("%s: VI_INIT_DONE already", __func__)); 5220 5221 sysctl_ctx_init(&vi->ctx); 5222 vi->flags |= VI_SYSCTL_CTX; 5223 5224 /* 5225 * Allocate tx/rx/fl queues for this VI. 5226 */ 5227 rc = t4_setup_vi_queues(vi); 5228 if (rc != 0) 5229 goto done; /* error message displayed already */ 5230 5231 /* 5232 * Setup RSS for this VI. Save a copy of the RSS table for later use. 5233 */ 5234 if (vi->nrxq > vi->rss_size) { 5235 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 5236 "some queues will never receive traffic.\n", vi->nrxq, 5237 vi->rss_size); 5238 } else if (vi->rss_size % vi->nrxq) { 5239 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 5240 "expect uneven traffic distribution.\n", vi->nrxq, 5241 vi->rss_size); 5242 } 5243#ifdef RSS 5244 if (vi->nrxq != nbuckets) { 5245 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 5246 "performance will be impacted.\n", vi->nrxq, nbuckets); 5247 } 5248#endif 5249 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 5250 for (i = 0; i < vi->rss_size;) { 5251#ifdef RSS 5252 j = rss_get_indirection_to_bucket(i); 5253 j %= vi->nrxq; 5254 rxq = &sc->sge.rxq[vi->first_rxq + j]; 5255 rss[i++] = rxq->iq.abs_id; 5256#else 5257 for_each_rxq(vi, j, rxq) { 5258 rss[i++] = rxq->iq.abs_id; 5259 if (i == vi->rss_size) 5260 break; 5261 } 5262#endif 5263 } 5264 5265 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 5266 vi->rss_size); 5267 if (rc != 0) { 5268 if_printf(ifp, "rss_config failed: %d\n", rc); 5269 goto done; 5270 } 5271 5272#ifdef RSS 5273 hashen = hashconfig_to_hashen(hashconfig); 5274 5275 /* 5276 * We may have had to enable some hashes even though the global config 5277 * wants them disabled. This is a potential problem that must be 5278 * reported to the user. 5279 */ 5280 extra = hashen_to_hashconfig(hashen) ^ hashconfig; 5281 5282 /* 5283 * If we consider only the supported hash types, then the enabled hashes 5284 * are a superset of the requested hashes. In other words, there cannot 5285 * be any supported hash that was requested but not enabled, but there 5286 * can be hashes that were not requested but had to be enabled. 5287 */ 5288 extra &= SUPPORTED_RSS_HASHTYPES; 5289 MPASS((extra & hashconfig) == 0); 5290 5291 if (extra) { 5292 if_printf(ifp, 5293 "global RSS config (0x%x) cannot be accommodated.\n", 5294 hashconfig); 5295 } 5296 if (extra & RSS_HASHTYPE_RSS_IPV4) 5297 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 5298 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 5299 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 5300 if (extra & RSS_HASHTYPE_RSS_IPV6) 5301 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 5302 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 5303 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 5304 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 5305 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 5306 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 5307 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 5308#else 5309 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 5310 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 5311 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5312 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 5313#endif 5314 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0); 5315 if (rc != 0) { 5316 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 5317 goto done; 5318 } 5319 5320 vi->rss = rss; 5321 vi->flags |= VI_INIT_DONE; 5322done: 5323 if (rc != 0) 5324 vi_full_uninit(vi); 5325 5326 return (rc); 5327} 5328 5329/* 5330 * Idempotent. 5331 */ 5332int 5333vi_full_uninit(struct vi_info *vi) 5334{ 5335 struct port_info *pi = vi->pi; 5336 struct adapter *sc = pi->adapter; 5337 int i; 5338 struct sge_rxq *rxq; 5339 struct sge_txq *txq; 5340#ifdef TCP_OFFLOAD 5341 struct sge_ofld_rxq *ofld_rxq; 5342 struct sge_wrq *ofld_txq; 5343#endif 5344 5345 if (vi->flags & VI_INIT_DONE) { 5346 5347 /* Need to quiesce queues. */ 5348 5349 /* XXX: Only for the first VI? */ 5350 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 5351 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 5352 5353 for_each_txq(vi, i, txq) { 5354 quiesce_txq(sc, txq); 5355 } 5356 5357#ifdef TCP_OFFLOAD 5358 for_each_ofld_txq(vi, i, ofld_txq) { 5359 quiesce_wrq(sc, ofld_txq); 5360 } 5361#endif 5362 5363 for_each_rxq(vi, i, rxq) { 5364 quiesce_iq(sc, &rxq->iq); 5365 quiesce_fl(sc, &rxq->fl); 5366 } 5367 5368#ifdef TCP_OFFLOAD 5369 for_each_ofld_rxq(vi, i, ofld_rxq) { 5370 quiesce_iq(sc, &ofld_rxq->iq); 5371 quiesce_fl(sc, &ofld_rxq->fl); 5372 } 5373#endif 5374 free(vi->rss, M_CXGBE); 5375 free(vi->nm_rss, M_CXGBE); 5376 } 5377 5378 t4_teardown_vi_queues(vi); 5379 vi->flags &= ~VI_INIT_DONE; 5380 5381 return (0); 5382} 5383 5384static void 5385quiesce_txq(struct adapter *sc, struct sge_txq *txq) 5386{ 5387 struct sge_eq *eq = &txq->eq; 5388 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5389 5390 (void) sc; /* unused */ 5391 5392#ifdef INVARIANTS 5393 TXQ_LOCK(txq); 5394 MPASS((eq->flags & EQ_ENABLED) == 0); 5395 TXQ_UNLOCK(txq); 5396#endif 5397 5398 /* Wait for the mp_ring to empty. */ 5399 while (!mp_ring_is_idle(txq->r)) { 5400 mp_ring_check_drainage(txq->r, 0); 5401 pause("rquiesce", 1); 5402 } 5403 5404 /* Then wait for the hardware to finish. */ 5405 while (spg->cidx != htobe16(eq->pidx)) 5406 pause("equiesce", 1); 5407 5408 /* Finally, wait for the driver to reclaim all descriptors. */ 5409 while (eq->cidx != eq->pidx) 5410 pause("dquiesce", 1); 5411} 5412 5413static void 5414quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 5415{ 5416 5417 /* XXXTX */ 5418} 5419 5420static void 5421quiesce_iq(struct adapter *sc, struct sge_iq *iq) 5422{ 5423 (void) sc; /* unused */ 5424 5425 /* Synchronize with the interrupt handler */ 5426 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 5427 pause("iqfree", 1); 5428} 5429 5430static void 5431quiesce_fl(struct adapter *sc, struct sge_fl *fl) 5432{ 5433 mtx_lock(&sc->sfl_lock); 5434 FL_LOCK(fl); 5435 fl->flags |= FL_DOOMED; 5436 FL_UNLOCK(fl); 5437 callout_stop(&sc->sfl_callout); 5438 mtx_unlock(&sc->sfl_lock); 5439 5440 KASSERT((fl->flags & FL_STARVING) == 0, 5441 ("%s: still starving", __func__)); 5442} 5443 5444static int 5445t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 5446 driver_intr_t *handler, void *arg, char *name) 5447{ 5448 int rc; 5449 5450 irq->rid = rid; 5451 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 5452 RF_SHAREABLE | RF_ACTIVE); 5453 if (irq->res == NULL) { 5454 device_printf(sc->dev, 5455 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 5456 return (ENOMEM); 5457 } 5458 5459 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 5460 NULL, handler, arg, &irq->tag); 5461 if (rc != 0) { 5462 device_printf(sc->dev, 5463 "failed to setup interrupt for rid %d, name %s: %d\n", 5464 rid, name, rc); 5465 } else if (name) 5466 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 5467 5468 return (rc); 5469} 5470 5471static int 5472t4_free_irq(struct adapter *sc, struct irq *irq) 5473{ 5474 if (irq->tag) 5475 bus_teardown_intr(sc->dev, irq->res, irq->tag); 5476 if (irq->res) 5477 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 5478 5479 bzero(irq, sizeof(*irq)); 5480 5481 return (0); 5482} 5483 5484static void 5485get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 5486{ 5487 5488 regs->version = chip_id(sc) | chip_rev(sc) << 10; 5489 t4_get_regs(sc, buf, regs->len); 5490} 5491 5492#define A_PL_INDIR_CMD 0x1f8 5493 5494#define S_PL_AUTOINC 31 5495#define M_PL_AUTOINC 0x1U 5496#define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 5497#define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 5498 5499#define S_PL_VFID 20 5500#define M_PL_VFID 0xffU 5501#define V_PL_VFID(x) ((x) << S_PL_VFID) 5502#define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 5503 5504#define S_PL_ADDR 0 5505#define M_PL_ADDR 0xfffffU 5506#define V_PL_ADDR(x) ((x) << S_PL_ADDR) 5507#define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 5508 5509#define A_PL_INDIR_DATA 0x1fc 5510 5511static uint64_t 5512read_vf_stat(struct adapter *sc, unsigned int viid, int reg) 5513{ 5514 u32 stats[2]; 5515 5516 mtx_assert(&sc->reg_lock, MA_OWNED); 5517 if (sc->flags & IS_VF) { 5518 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 5519 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 5520 } else { 5521 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5522 V_PL_VFID(G_FW_VIID_VIN(viid)) | 5523 V_PL_ADDR(VF_MPS_REG(reg))); 5524 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 5525 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 5526 } 5527 return (((uint64_t)stats[1]) << 32 | stats[0]); 5528} 5529 5530static void 5531t4_get_vi_stats(struct adapter *sc, unsigned int viid, 5532 struct fw_vi_stats_vf *stats) 5533{ 5534 5535#define GET_STAT(name) \ 5536 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L) 5537 5538 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 5539 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 5540 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 5541 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 5542 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 5543 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 5544 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 5545 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 5546 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 5547 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 5548 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 5549 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 5550 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 5551 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 5552 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 5553 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 5554 5555#undef GET_STAT 5556} 5557 5558static void 5559t4_clr_vi_stats(struct adapter *sc, unsigned int viid) 5560{ 5561 int reg; 5562 5563 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5564 V_PL_VFID(G_FW_VIID_VIN(viid)) | 5565 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 5566 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 5567 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 5568 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 5569} 5570 5571static void 5572vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 5573{ 5574 struct timeval tv; 5575 const struct timeval interval = {0, 250000}; /* 250ms */ 5576 5577 if (!(vi->flags & VI_INIT_DONE)) 5578 return; 5579 5580 getmicrotime(&tv); 5581 timevalsub(&tv, &interval); 5582 if (timevalcmp(&tv, &vi->last_refreshed, <)) 5583 return; 5584 5585 mtx_lock(&sc->reg_lock); 5586 t4_get_vi_stats(sc, vi->viid, &vi->stats); 5587 getmicrotime(&vi->last_refreshed); 5588 mtx_unlock(&sc->reg_lock); 5589} 5590 5591static void 5592cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 5593{ 5594 u_int i, v, tnl_cong_drops, bg_map; 5595 struct timeval tv; 5596 const struct timeval interval = {0, 250000}; /* 250ms */ 5597 5598 getmicrotime(&tv); 5599 timevalsub(&tv, &interval); 5600 if (timevalcmp(&tv, &pi->last_refreshed, <)) 5601 return; 5602 5603 tnl_cong_drops = 0; 5604 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 5605 bg_map = pi->mps_bg_map; 5606 while (bg_map) { 5607 i = ffs(bg_map) - 1; 5608 mtx_lock(&sc->reg_lock); 5609 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 5610 A_TP_MIB_TNL_CNG_DROP_0 + i); 5611 mtx_unlock(&sc->reg_lock); 5612 tnl_cong_drops += v; 5613 bg_map &= ~(1 << i); 5614 } 5615 pi->tnl_cong_drops = tnl_cong_drops; 5616 getmicrotime(&pi->last_refreshed); 5617} 5618 5619static void 5620cxgbe_tick(void *arg) 5621{ 5622 struct port_info *pi = arg; 5623 struct adapter *sc = pi->adapter; 5624 5625 PORT_LOCK_ASSERT_OWNED(pi); 5626 cxgbe_refresh_stats(sc, pi); 5627 5628 callout_schedule(&pi->tick, hz); 5629} 5630 5631void 5632vi_tick(void *arg) 5633{ 5634 struct vi_info *vi = arg; 5635 struct adapter *sc = vi->pi->adapter; 5636 5637 vi_refresh_stats(sc, vi); 5638 5639 callout_schedule(&vi->tick, hz); 5640} 5641 5642/* 5643 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 5644 */ 5645static char *caps_decoder[] = { 5646 "\20\001IPMI\002NCSI", /* 0: NBM */ 5647 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 5648 "\20\001INGRESS\002EGRESS", /* 2: switch */ 5649 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 5650 "\006HASHFILTER\007ETHOFLD", 5651 "\20\001TOE", /* 4: TOE */ 5652 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 5653 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 5654 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 5655 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 5656 "\007T10DIF" 5657 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 5658 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 5659 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 5660 "\004PO_INITIATOR\005PO_TARGET", 5661}; 5662 5663void 5664t4_sysctls(struct adapter *sc) 5665{ 5666 struct sysctl_ctx_list *ctx; 5667 struct sysctl_oid *oid; 5668 struct sysctl_oid_list *children, *c0; 5669 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 5670 5671 ctx = device_get_sysctl_ctx(sc->dev); 5672 5673 /* 5674 * dev.t4nex.X. 5675 */ 5676 oid = device_get_sysctl_tree(sc->dev); 5677 c0 = children = SYSCTL_CHILDREN(oid); 5678 5679 sc->sc_do_rxcopy = 1; 5680 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 5681 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 5682 5683 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 5684 sc->params.nports, "# of ports"); 5685 5686 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 5687 CTLTYPE_STRING | CTLFLAG_RD, doorbells, (uintptr_t)&sc->doorbells, 5688 sysctl_bitfield_8b, "A", "available doorbells"); 5689 5690 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 5691 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 5692 5693 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 5694 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 5695 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 5696 "interrupt holdoff timer values (us)"); 5697 5698 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 5699 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 5700 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 5701 "interrupt holdoff packet counter values"); 5702 5703 t4_sge_sysctls(sc, ctx, children); 5704 5705 sc->lro_timeout = 100; 5706 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 5707 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 5708 5709 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 5710 &sc->debug_flags, 0, "flags to enable runtime debugging"); 5711 5712 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 5713 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 5714 5715 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 5716 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 5717 5718 if (sc->flags & IS_VF) 5719 return; 5720 5721 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 5722 NULL, chip_rev(sc), "chip hardware revision"); 5723 5724 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 5725 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 5726 5727 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 5728 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 5729 5730 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 5731 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 5732 5733 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 5734 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 5735 5736 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 5737 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 5738 5739 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 5740 sc->er_version, 0, "expansion ROM version"); 5741 5742 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 5743 sc->bs_version, 0, "bootstrap firmware version"); 5744 5745 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 5746 NULL, sc->params.scfg_vers, "serial config version"); 5747 5748 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 5749 NULL, sc->params.vpd_vers, "VPD version"); 5750 5751 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 5752 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 5753 5754 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 5755 sc->cfcsum, "config file checksum"); 5756 5757#define SYSCTL_CAP(name, n, text) \ 5758 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 5759 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], (uintptr_t)&sc->name, \ 5760 sysctl_bitfield_16b, "A", "available " text " capabilities") 5761 5762 SYSCTL_CAP(nbmcaps, 0, "NBM"); 5763 SYSCTL_CAP(linkcaps, 1, "link"); 5764 SYSCTL_CAP(switchcaps, 2, "switch"); 5765 SYSCTL_CAP(niccaps, 3, "NIC"); 5766 SYSCTL_CAP(toecaps, 4, "TCP offload"); 5767 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 5768 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 5769 SYSCTL_CAP(cryptocaps, 7, "crypto"); 5770 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 5771#undef SYSCTL_CAP 5772 5773 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 5774 NULL, sc->tids.nftids, "number of filters"); 5775 5776 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 5777 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 5778 "chip temperature (in Celsius)"); 5779 5780 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING | 5781 CTLFLAG_RD, sc, 0, sysctl_loadavg, "A", 5782 "microprocessor load averages (debug firmwares only)"); 5783 5784 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD, 5785 &sc->params.core_vdd, 0, "core Vdd (in mV)"); 5786 5787 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 5788 CTLTYPE_STRING | CTLFLAG_RD, sc, LOCAL_CPUS, 5789 sysctl_cpus, "A", "local CPUs"); 5790 5791 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 5792 CTLTYPE_STRING | CTLFLAG_RD, sc, INTR_CPUS, 5793 sysctl_cpus, "A", "preferred CPUs for interrupts"); 5794 5795 /* 5796 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 5797 */ 5798 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 5799 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 5800 "logs and miscellaneous information"); 5801 children = SYSCTL_CHILDREN(oid); 5802 5803 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 5804 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5805 sysctl_cctrl, "A", "congestion control"); 5806 5807 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 5808 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5809 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 5810 5811 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 5812 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 5813 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 5814 5815 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 5816 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 5817 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 5818 5819 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 5820 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 5821 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 5822 5823 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 5824 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 5825 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 5826 5827 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 5828 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 5829 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 5830 5831 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 5832 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5833 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6, 5834 "A", "CIM logic analyzer"); 5835 5836 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 5837 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5838 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 5839 5840 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 5841 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 5842 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 5843 5844 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 5845 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 5846 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 5847 5848 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 5849 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 5850 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 5851 5852 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 5853 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 5854 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 5855 5856 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 5857 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 5858 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 5859 5860 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 5861 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 5862 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 5863 5864 if (chip_id(sc) > CHELSIO_T4) { 5865 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 5866 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 5867 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 5868 5869 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 5870 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 5871 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 5872 } 5873 5874 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 5875 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5876 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 5877 5878 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 5879 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5880 sysctl_cim_qcfg, "A", "CIM queue configuration"); 5881 5882 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 5883 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5884 sysctl_cpl_stats, "A", "CPL statistics"); 5885 5886 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 5887 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5888 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 5889 5890 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 5891 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5892 sysctl_devlog, "A", "firmware's device log"); 5893 5894 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 5895 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5896 sysctl_fcoe_stats, "A", "FCoE statistics"); 5897 5898 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 5899 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5900 sysctl_hw_sched, "A", "hardware scheduler "); 5901 5902 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 5903 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5904 sysctl_l2t, "A", "hardware L2 table"); 5905 5906 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 5907 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5908 sysctl_smt, "A", "hardware source MAC table"); 5909 5910 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 5911 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5912 sysctl_lb_stats, "A", "loopback statistics"); 5913 5914 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 5915 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5916 sysctl_meminfo, "A", "memory regions"); 5917 5918 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 5919 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5920 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 5921 "A", "MPS TCAM entries"); 5922 5923 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 5924 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5925 sysctl_path_mtus, "A", "path MTUs"); 5926 5927 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 5928 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5929 sysctl_pm_stats, "A", "PM statistics"); 5930 5931 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 5932 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5933 sysctl_rdma_stats, "A", "RDMA statistics"); 5934 5935 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 5936 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5937 sysctl_tcp_stats, "A", "TCP statistics"); 5938 5939 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 5940 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5941 sysctl_tids, "A", "TID information"); 5942 5943 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 5944 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5945 sysctl_tp_err_stats, "A", "TP error statistics"); 5946 5947 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 5948 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 5949 "TP logic analyzer event capture mask"); 5950 5951 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 5952 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5953 sysctl_tp_la, "A", "TP logic analyzer"); 5954 5955 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 5956 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5957 sysctl_tx_rate, "A", "Tx rate"); 5958 5959 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 5960 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5961 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 5962 5963 if (chip_id(sc) >= CHELSIO_T5) { 5964 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 5965 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5966 sysctl_wcwr_stats, "A", "write combined work requests"); 5967 } 5968 5969#ifdef TCP_OFFLOAD 5970 if (is_offload(sc)) { 5971 int i; 5972 char s[4]; 5973 5974 /* 5975 * dev.t4nex.X.toe. 5976 */ 5977 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 5978 NULL, "TOE parameters"); 5979 children = SYSCTL_CHILDREN(oid); 5980 5981 sc->tt.cong_algorithm = -1; 5982 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 5983 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 5984 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 5985 "3 = highspeed)"); 5986 5987 sc->tt.sndbuf = 256 * 1024; 5988 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 5989 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 5990 5991 sc->tt.ddp = 0; 5992 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 5993 &sc->tt.ddp, 0, "DDP allowed"); 5994 5995 sc->tt.rx_coalesce = 1; 5996 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 5997 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 5998 5999 sc->tt.tls = 0; 6000 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW, 6001 &sc->tt.tls, 0, "Inline TLS allowed"); 6002 6003 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports", 6004 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports, 6005 "I", "TCP ports that use inline TLS+TOE RX"); 6006 6007 sc->tt.tx_align = 1; 6008 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 6009 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 6010 6011 sc->tt.tx_zcopy = 0; 6012 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 6013 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 6014 "Enable zero-copy aio_write(2)"); 6015 6016 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 6017 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6018 "cop_managed_offloading", CTLFLAG_RW, 6019 &sc->tt.cop_managed_offloading, 0, 6020 "COP (Connection Offload Policy) controls all TOE offload"); 6021 6022 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 6023 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 6024 "TP timer tick (us)"); 6025 6026 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 6027 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 6028 "TCP timestamp tick (us)"); 6029 6030 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 6031 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 6032 "DACK tick (us)"); 6033 6034 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 6035 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 6036 "IU", "DACK timer (us)"); 6037 6038 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 6039 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 6040 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)"); 6041 6042 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 6043 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 6044 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)"); 6045 6046 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 6047 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 6048 sysctl_tp_timer, "LU", "Persist timer min (us)"); 6049 6050 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 6051 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 6052 sysctl_tp_timer, "LU", "Persist timer max (us)"); 6053 6054 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 6055 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 6056 sysctl_tp_timer, "LU", "Keepalive idle timer (us)"); 6057 6058 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 6059 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 6060 sysctl_tp_timer, "LU", "Keepalive interval timer (us)"); 6061 6062 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 6063 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 6064 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 6065 6066 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 6067 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 6068 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 6069 6070 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 6071 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX, 6072 sysctl_tp_shift_cnt, "IU", 6073 "Number of SYN retransmissions before abort"); 6074 6075 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 6076 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2, 6077 sysctl_tp_shift_cnt, "IU", 6078 "Number of retransmissions before abort"); 6079 6080 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 6081 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2, 6082 sysctl_tp_shift_cnt, "IU", 6083 "Number of keepalive probes before abort"); 6084 6085 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 6086 CTLFLAG_RD, NULL, "TOE retransmit backoffs"); 6087 children = SYSCTL_CHILDREN(oid); 6088 for (i = 0; i < 16; i++) { 6089 snprintf(s, sizeof(s), "%u", i); 6090 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 6091 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff, 6092 "IU", "TOE retransmit backoff"); 6093 } 6094 } 6095#endif 6096} 6097 6098void 6099vi_sysctls(struct vi_info *vi) 6100{ 6101 struct sysctl_ctx_list *ctx; 6102 struct sysctl_oid *oid; 6103 struct sysctl_oid_list *children; 6104 6105 ctx = device_get_sysctl_ctx(vi->dev); 6106 6107 /* 6108 * dev.v?(cxgbe|cxl).X. 6109 */ 6110 oid = device_get_sysctl_tree(vi->dev); 6111 children = SYSCTL_CHILDREN(oid); 6112 6113 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 6114 vi->viid, "VI identifer"); 6115 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 6116 &vi->nrxq, 0, "# of rx queues"); 6117 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 6118 &vi->ntxq, 0, "# of tx queues"); 6119 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 6120 &vi->first_rxq, 0, "index of first rx queue"); 6121 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 6122 &vi->first_txq, 0, "index of first tx queue"); 6123 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 6124 vi->rss_size, "size of RSS indirection table"); 6125 6126 if (IS_MAIN_VI(vi)) { 6127 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 6128 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 6129 "Reserve queue 0 for non-flowid packets"); 6130 } 6131 6132#ifdef TCP_OFFLOAD 6133 if (vi->nofldrxq != 0) { 6134 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 6135 &vi->nofldrxq, 0, 6136 "# of rx queues for offloaded TCP connections"); 6137 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 6138 &vi->nofldtxq, 0, 6139 "# of tx queues for offloaded TCP connections"); 6140 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 6141 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 6142 "index of first TOE rx queue"); 6143 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 6144 CTLFLAG_RD, &vi->first_ofld_txq, 0, 6145 "index of first TOE tx queue"); 6146 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 6147 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 6148 sysctl_holdoff_tmr_idx_ofld, "I", 6149 "holdoff timer index for TOE queues"); 6150 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 6151 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 6152 sysctl_holdoff_pktc_idx_ofld, "I", 6153 "holdoff packet counter index for TOE queues"); 6154 } 6155#endif 6156#ifdef DEV_NETMAP 6157 if (vi->nnmrxq != 0) { 6158 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 6159 &vi->nnmrxq, 0, "# of netmap rx queues"); 6160 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 6161 &vi->nnmtxq, 0, "# of netmap tx queues"); 6162 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 6163 CTLFLAG_RD, &vi->first_nm_rxq, 0, 6164 "index of first netmap rx queue"); 6165 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 6166 CTLFLAG_RD, &vi->first_nm_txq, 0, 6167 "index of first netmap tx queue"); 6168 } 6169#endif 6170 6171 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 6172 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 6173 "holdoff timer index"); 6174 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 6175 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 6176 "holdoff packet counter index"); 6177 6178 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 6179 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 6180 "rx queue size"); 6181 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 6182 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 6183 "tx queue size"); 6184} 6185 6186static void 6187cxgbe_sysctls(struct port_info *pi) 6188{ 6189 struct sysctl_ctx_list *ctx; 6190 struct sysctl_oid *oid; 6191 struct sysctl_oid_list *children, *children2; 6192 struct adapter *sc = pi->adapter; 6193 int i; 6194 char name[16]; 6195 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"}; 6196 6197 ctx = device_get_sysctl_ctx(pi->dev); 6198 6199 /* 6200 * dev.cxgbe.X. 6201 */ 6202 oid = device_get_sysctl_tree(pi->dev); 6203 children = SYSCTL_CHILDREN(oid); 6204 6205 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 6206 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 6207 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 6208 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 6209 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 6210 "PHY temperature (in Celsius)"); 6211 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 6212 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 6213 "PHY firmware version"); 6214 } 6215 6216 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 6217 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A", 6218 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 6219 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 6220 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A", 6221 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 6222 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 6223 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I", 6224 "autonegotiation (-1 = not supported)"); 6225 6226 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 6227 port_top_speed(pi), "max speed (in Gbps)"); 6228 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 6229 pi->mps_bg_map, "MPS buffer group map"); 6230 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 6231 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 6232 6233 if (sc->flags & IS_VF) 6234 return; 6235 6236 /* 6237 * dev.(cxgbe|cxl).X.tc. 6238 */ 6239 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 6240 "Tx scheduler traffic classes (cl_rl)"); 6241 children2 = SYSCTL_CHILDREN(oid); 6242 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 6243 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 6244 "pktsize for per-flow cl-rl (0 means up to the driver )"); 6245 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 6246 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 6247 "burstsize for per-flow cl-rl (0 means up to the driver)"); 6248 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 6249 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 6250 6251 snprintf(name, sizeof(name), "%d", i); 6252 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 6253 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 6254 "traffic class")); 6255 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 6256 CTLTYPE_STRING | CTLFLAG_RD, tc_flags, (uintptr_t)&tc->flags, 6257 sysctl_bitfield_8b, "A", "flags"); 6258 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 6259 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 6260 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 6261 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 6262 sysctl_tc_params, "A", "traffic class parameters"); 6263 } 6264 6265 /* 6266 * dev.cxgbe.X.stats. 6267 */ 6268 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 6269 NULL, "port statistics"); 6270 children = SYSCTL_CHILDREN(oid); 6271 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 6272 &pi->tx_parse_error, 0, 6273 "# of tx packets with invalid length or # of segments"); 6274 6275#define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 6276 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 6277 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 6278 sysctl_handle_t4_reg64, "QU", desc) 6279 6280 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 6281 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 6282 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 6283 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 6284 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 6285 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 6286 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 6287 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 6288 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 6289 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 6290 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 6291 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 6292 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 6293 "# of tx frames in this range", 6294 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 6295 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 6296 "# of tx frames in this range", 6297 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 6298 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 6299 "# of tx frames in this range", 6300 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 6301 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 6302 "# of tx frames in this range", 6303 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 6304 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 6305 "# of tx frames in this range", 6306 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 6307 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 6308 "# of tx frames in this range", 6309 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 6310 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 6311 "# of tx frames in this range", 6312 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 6313 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 6314 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 6315 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 6316 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 6317 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 6318 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 6319 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 6320 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 6321 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 6322 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 6323 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 6324 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 6325 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 6326 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 6327 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 6328 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 6329 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 6330 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 6331 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 6332 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 6333 6334 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 6335 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 6336 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 6337 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 6338 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 6339 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 6340 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 6341 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 6342 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 6343 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 6344 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 6345 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 6346 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 6347 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 6348 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 6349 "# of frames received with bad FCS", 6350 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 6351 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 6352 "# of frames received with length error", 6353 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 6354 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 6355 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 6356 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 6357 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 6358 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 6359 "# of rx frames in this range", 6360 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 6361 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 6362 "# of rx frames in this range", 6363 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 6364 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 6365 "# of rx frames in this range", 6366 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 6367 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 6368 "# of rx frames in this range", 6369 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 6370 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 6371 "# of rx frames in this range", 6372 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 6373 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 6374 "# of rx frames in this range", 6375 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 6376 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 6377 "# of rx frames in this range", 6378 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 6379 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 6380 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 6381 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 6382 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 6383 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 6384 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 6385 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 6386 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 6387 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 6388 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 6389 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 6390 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 6391 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 6392 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 6393 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 6394 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 6395 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 6396 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 6397 6398#undef SYSCTL_ADD_T4_REG64 6399 6400#define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 6401 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 6402 &pi->stats.name, desc) 6403 6404 /* We get these from port_stats and they may be stale by up to 1s */ 6405 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 6406 "# drops due to buffer-group 0 overflows"); 6407 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 6408 "# drops due to buffer-group 1 overflows"); 6409 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 6410 "# drops due to buffer-group 2 overflows"); 6411 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 6412 "# drops due to buffer-group 3 overflows"); 6413 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 6414 "# of buffer-group 0 truncated packets"); 6415 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 6416 "# of buffer-group 1 truncated packets"); 6417 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 6418 "# of buffer-group 2 truncated packets"); 6419 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 6420 "# of buffer-group 3 truncated packets"); 6421 6422#undef SYSCTL_ADD_T4_PORTSTAT 6423 6424 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records", 6425 CTLFLAG_RD, &pi->tx_tls_records, 6426 "# of TLS records transmitted"); 6427 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets", 6428 CTLFLAG_RD, &pi->tx_tls_octets, 6429 "# of payload octets in transmitted TLS records"); 6430 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records", 6431 CTLFLAG_RD, &pi->rx_tls_records, 6432 "# of TLS records received"); 6433 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets", 6434 CTLFLAG_RD, &pi->rx_tls_octets, 6435 "# of payload octets in received TLS records"); 6436} 6437 6438static int 6439sysctl_int_array(SYSCTL_HANDLER_ARGS) 6440{ 6441 int rc, *i, space = 0; 6442 struct sbuf sb; 6443 6444 sbuf_new_for_sysctl(&sb, NULL, 64, req); 6445 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 6446 if (space) 6447 sbuf_printf(&sb, " "); 6448 sbuf_printf(&sb, "%d", *i); 6449 space = 1; 6450 } 6451 rc = sbuf_finish(&sb); 6452 sbuf_delete(&sb); 6453 return (rc); 6454} 6455 6456static int 6457sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 6458{ 6459 int rc; 6460 struct sbuf *sb; 6461 6462 rc = sysctl_wire_old_buffer(req, 0); 6463 if (rc != 0) 6464 return(rc); 6465 6466 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6467 if (sb == NULL) 6468 return (ENOMEM); 6469 6470 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 6471 rc = sbuf_finish(sb); 6472 sbuf_delete(sb); 6473 6474 return (rc); 6475} 6476 6477static int 6478sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 6479{ 6480 int rc; 6481 struct sbuf *sb; 6482 6483 rc = sysctl_wire_old_buffer(req, 0); 6484 if (rc != 0) 6485 return(rc); 6486 6487 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6488 if (sb == NULL) 6489 return (ENOMEM); 6490 6491 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 6492 rc = sbuf_finish(sb); 6493 sbuf_delete(sb); 6494 6495 return (rc); 6496} 6497 6498static int 6499sysctl_btphy(SYSCTL_HANDLER_ARGS) 6500{ 6501 struct port_info *pi = arg1; 6502 int op = arg2; 6503 struct adapter *sc = pi->adapter; 6504 u_int v; 6505 int rc; 6506 6507 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 6508 if (rc) 6509 return (rc); 6510 /* XXX: magic numbers */ 6511 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 6512 &v); 6513 end_synchronized_op(sc, 0); 6514 if (rc) 6515 return (rc); 6516 if (op == 0) 6517 v /= 256; 6518 6519 rc = sysctl_handle_int(oidp, &v, 0, req); 6520 return (rc); 6521} 6522 6523static int 6524sysctl_noflowq(SYSCTL_HANDLER_ARGS) 6525{ 6526 struct vi_info *vi = arg1; 6527 int rc, val; 6528 6529 val = vi->rsrv_noflowq; 6530 rc = sysctl_handle_int(oidp, &val, 0, req); 6531 if (rc != 0 || req->newptr == NULL) 6532 return (rc); 6533 6534 if ((val >= 1) && (vi->ntxq > 1)) 6535 vi->rsrv_noflowq = 1; 6536 else 6537 vi->rsrv_noflowq = 0; 6538 6539 return (rc); 6540} 6541 6542static int 6543sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 6544{ 6545 struct vi_info *vi = arg1; 6546 struct adapter *sc = vi->pi->adapter; 6547 int idx, rc, i; 6548 struct sge_rxq *rxq; 6549 uint8_t v; 6550 6551 idx = vi->tmr_idx; 6552 6553 rc = sysctl_handle_int(oidp, &idx, 0, req); 6554 if (rc != 0 || req->newptr == NULL) 6555 return (rc); 6556 6557 if (idx < 0 || idx >= SGE_NTIMERS) 6558 return (EINVAL); 6559 6560 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6561 "t4tmr"); 6562 if (rc) 6563 return (rc); 6564 6565 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 6566 for_each_rxq(vi, i, rxq) { 6567#ifdef atomic_store_rel_8 6568 atomic_store_rel_8(&rxq->iq.intr_params, v); 6569#else 6570 rxq->iq.intr_params = v; 6571#endif 6572 } 6573 vi->tmr_idx = idx; 6574 6575 end_synchronized_op(sc, LOCK_HELD); 6576 return (0); 6577} 6578 6579static int 6580sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 6581{ 6582 struct vi_info *vi = arg1; 6583 struct adapter *sc = vi->pi->adapter; 6584 int idx, rc; 6585 6586 idx = vi->pktc_idx; 6587 6588 rc = sysctl_handle_int(oidp, &idx, 0, req); 6589 if (rc != 0 || req->newptr == NULL) 6590 return (rc); 6591 6592 if (idx < -1 || idx >= SGE_NCOUNTERS) 6593 return (EINVAL); 6594 6595 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6596 "t4pktc"); 6597 if (rc) 6598 return (rc); 6599 6600 if (vi->flags & VI_INIT_DONE) 6601 rc = EBUSY; /* cannot be changed once the queues are created */ 6602 else 6603 vi->pktc_idx = idx; 6604 6605 end_synchronized_op(sc, LOCK_HELD); 6606 return (rc); 6607} 6608 6609static int 6610sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 6611{ 6612 struct vi_info *vi = arg1; 6613 struct adapter *sc = vi->pi->adapter; 6614 int qsize, rc; 6615 6616 qsize = vi->qsize_rxq; 6617 6618 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6619 if (rc != 0 || req->newptr == NULL) 6620 return (rc); 6621 6622 if (qsize < 128 || (qsize & 7)) 6623 return (EINVAL); 6624 6625 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6626 "t4rxqs"); 6627 if (rc) 6628 return (rc); 6629 6630 if (vi->flags & VI_INIT_DONE) 6631 rc = EBUSY; /* cannot be changed once the queues are created */ 6632 else 6633 vi->qsize_rxq = qsize; 6634 6635 end_synchronized_op(sc, LOCK_HELD); 6636 return (rc); 6637} 6638 6639static int 6640sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 6641{ 6642 struct vi_info *vi = arg1; 6643 struct adapter *sc = vi->pi->adapter; 6644 int qsize, rc; 6645 6646 qsize = vi->qsize_txq; 6647 6648 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6649 if (rc != 0 || req->newptr == NULL) 6650 return (rc); 6651 6652 if (qsize < 128 || qsize > 65536) 6653 return (EINVAL); 6654 6655 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6656 "t4txqs"); 6657 if (rc) 6658 return (rc); 6659 6660 if (vi->flags & VI_INIT_DONE) 6661 rc = EBUSY; /* cannot be changed once the queues are created */ 6662 else 6663 vi->qsize_txq = qsize; 6664 6665 end_synchronized_op(sc, LOCK_HELD); 6666 return (rc); 6667} 6668 6669static int 6670sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 6671{ 6672 struct port_info *pi = arg1; 6673 struct adapter *sc = pi->adapter; 6674 struct link_config *lc = &pi->link_cfg; 6675 int rc; 6676 6677 if (req->newptr == NULL) { 6678 struct sbuf *sb; 6679 static char *bits = "\20\1RX\2TX\3AUTO"; 6680 6681 rc = sysctl_wire_old_buffer(req, 0); 6682 if (rc != 0) 6683 return(rc); 6684 6685 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6686 if (sb == NULL) 6687 return (ENOMEM); 6688 6689 if (lc->link_ok) { 6690 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 6691 (lc->requested_fc & PAUSE_AUTONEG), bits); 6692 } else { 6693 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 6694 PAUSE_RX | PAUSE_AUTONEG), bits); 6695 } 6696 rc = sbuf_finish(sb); 6697 sbuf_delete(sb); 6698 } else { 6699 char s[2]; 6700 int n; 6701 6702 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 6703 PAUSE_AUTONEG)); 6704 s[1] = 0; 6705 6706 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6707 if (rc != 0) 6708 return(rc); 6709 6710 if (s[1] != 0) 6711 return (EINVAL); 6712 if (s[0] < '0' || s[0] > '9') 6713 return (EINVAL); /* not a number */ 6714 n = s[0] - '0'; 6715 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 6716 return (EINVAL); /* some other bit is set too */ 6717 6718 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6719 "t4PAUSE"); 6720 if (rc) 6721 return (rc); 6722 PORT_LOCK(pi); 6723 lc->requested_fc = n; 6724 fixup_link_config(pi); 6725 if (pi->up_vis > 0) 6726 rc = apply_link_config(pi); 6727 set_current_media(pi); 6728 PORT_UNLOCK(pi); 6729 end_synchronized_op(sc, 0); 6730 } 6731 6732 return (rc); 6733} 6734 6735static int 6736sysctl_fec(SYSCTL_HANDLER_ARGS) 6737{ 6738 struct port_info *pi = arg1; 6739 struct adapter *sc = pi->adapter; 6740 struct link_config *lc = &pi->link_cfg; 6741 int rc; 6742 int8_t old; 6743 6744 if (req->newptr == NULL) { 6745 struct sbuf *sb; 6746 static char *bits = "\20\1RS\2BASE-R\3RSVD1\4RSVD2\5RSVD3\6AUTO"; 6747 6748 rc = sysctl_wire_old_buffer(req, 0); 6749 if (rc != 0) 6750 return(rc); 6751 6752 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6753 if (sb == NULL) 6754 return (ENOMEM); 6755 6756 /* 6757 * Display the requested_fec when the link is down -- the actual 6758 * FEC makes sense only when the link is up. 6759 */ 6760 if (lc->link_ok) { 6761 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) | 6762 (lc->requested_fec & FEC_AUTO), bits); 6763 } else { 6764 sbuf_printf(sb, "%b", lc->requested_fec, bits); 6765 } 6766 rc = sbuf_finish(sb); 6767 sbuf_delete(sb); 6768 } else { 6769 char s[3]; 6770 int n; 6771 6772 snprintf(s, sizeof(s), "%d", 6773 lc->requested_fec == FEC_AUTO ? -1 : 6774 lc->requested_fec & M_FW_PORT_CAP32_FEC); 6775 6776 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6777 if (rc != 0) 6778 return(rc); 6779 6780 n = strtol(&s[0], NULL, 0); 6781 if (n < 0 || n & FEC_AUTO) 6782 n = FEC_AUTO; 6783 else { 6784 if (n & ~M_FW_PORT_CAP32_FEC) 6785 return (EINVAL);/* some other bit is set too */ 6786 if (!powerof2(n)) 6787 return (EINVAL);/* one bit can be set at most */ 6788 } 6789 6790 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6791 "t4fec"); 6792 if (rc) 6793 return (rc); 6794 PORT_LOCK(pi); 6795 old = lc->requested_fec; 6796 if (n == FEC_AUTO) 6797 lc->requested_fec = FEC_AUTO; 6798 else if (n == 0) 6799 lc->requested_fec = FEC_NONE; 6800 else { 6801 if ((lc->supported | V_FW_PORT_CAP32_FEC(n)) != 6802 lc->supported) { 6803 rc = ENOTSUP; 6804 goto done; 6805 } 6806 lc->requested_fec = n; 6807 } 6808 fixup_link_config(pi); 6809 if (pi->up_vis > 0) { 6810 rc = apply_link_config(pi); 6811 if (rc != 0) { 6812 lc->requested_fec = old; 6813 if (rc == FW_EPROTO) 6814 rc = ENOTSUP; 6815 } 6816 } 6817done: 6818 PORT_UNLOCK(pi); 6819 end_synchronized_op(sc, 0); 6820 } 6821 6822 return (rc); 6823} 6824 6825static int 6826sysctl_autoneg(SYSCTL_HANDLER_ARGS) 6827{ 6828 struct port_info *pi = arg1; 6829 struct adapter *sc = pi->adapter; 6830 struct link_config *lc = &pi->link_cfg; 6831 int rc, val; 6832 6833 if (lc->supported & FW_PORT_CAP32_ANEG) 6834 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 6835 else 6836 val = -1; 6837 rc = sysctl_handle_int(oidp, &val, 0, req); 6838 if (rc != 0 || req->newptr == NULL) 6839 return (rc); 6840 if (val == 0) 6841 val = AUTONEG_DISABLE; 6842 else if (val == 1) 6843 val = AUTONEG_ENABLE; 6844 else 6845 val = AUTONEG_AUTO; 6846 6847 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6848 "t4aneg"); 6849 if (rc) 6850 return (rc); 6851 PORT_LOCK(pi); 6852 if (val == AUTONEG_ENABLE && !(lc->supported & FW_PORT_CAP32_ANEG)) { 6853 rc = ENOTSUP; 6854 goto done; 6855 } 6856 lc->requested_aneg = val; 6857 fixup_link_config(pi); 6858 if (pi->up_vis > 0) 6859 rc = apply_link_config(pi); 6860 set_current_media(pi); 6861done: 6862 PORT_UNLOCK(pi); 6863 end_synchronized_op(sc, 0); 6864 return (rc); 6865} 6866 6867static int 6868sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 6869{ 6870 struct adapter *sc = arg1; 6871 int reg = arg2; 6872 uint64_t val; 6873 6874 val = t4_read_reg64(sc, reg); 6875 6876 return (sysctl_handle_64(oidp, &val, 0, req)); 6877} 6878 6879static int 6880sysctl_temperature(SYSCTL_HANDLER_ARGS) 6881{ 6882 struct adapter *sc = arg1; 6883 int rc, t; 6884 uint32_t param, val; 6885 6886 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 6887 if (rc) 6888 return (rc); 6889 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6890 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 6891 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 6892 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 6893 end_synchronized_op(sc, 0); 6894 if (rc) 6895 return (rc); 6896 6897 /* unknown is returned as 0 but we display -1 in that case */ 6898 t = val == 0 ? -1 : val; 6899 6900 rc = sysctl_handle_int(oidp, &t, 0, req); 6901 return (rc); 6902} 6903 6904static int 6905sysctl_loadavg(SYSCTL_HANDLER_ARGS) 6906{ 6907 struct adapter *sc = arg1; 6908 struct sbuf *sb; 6909 int rc; 6910 uint32_t param, val; 6911 6912 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 6913 if (rc) 6914 return (rc); 6915 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6916 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 6917 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 6918 end_synchronized_op(sc, 0); 6919 if (rc) 6920 return (rc); 6921 6922 rc = sysctl_wire_old_buffer(req, 0); 6923 if (rc != 0) 6924 return (rc); 6925 6926 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6927 if (sb == NULL) 6928 return (ENOMEM); 6929 6930 if (val == 0xffffffff) { 6931 /* Only debug and custom firmwares report load averages. */ 6932 sbuf_printf(sb, "not available"); 6933 } else { 6934 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 6935 (val >> 16) & 0xff); 6936 } 6937 rc = sbuf_finish(sb); 6938 sbuf_delete(sb); 6939 6940 return (rc); 6941} 6942 6943static int 6944sysctl_cctrl(SYSCTL_HANDLER_ARGS) 6945{ 6946 struct adapter *sc = arg1; 6947 struct sbuf *sb; 6948 int rc, i; 6949 uint16_t incr[NMTUS][NCCTRL_WIN]; 6950 static const char *dec_fac[] = { 6951 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 6952 "0.9375" 6953 }; 6954 6955 rc = sysctl_wire_old_buffer(req, 0); 6956 if (rc != 0) 6957 return (rc); 6958 6959 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6960 if (sb == NULL) 6961 return (ENOMEM); 6962 6963 t4_read_cong_tbl(sc, incr); 6964 6965 for (i = 0; i < NCCTRL_WIN; ++i) { 6966 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 6967 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 6968 incr[5][i], incr[6][i], incr[7][i]); 6969 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 6970 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 6971 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 6972 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 6973 } 6974 6975 rc = sbuf_finish(sb); 6976 sbuf_delete(sb); 6977 6978 return (rc); 6979} 6980 6981static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 6982 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 6983 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 6984 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 6985}; 6986 6987static int 6988sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 6989{ 6990 struct adapter *sc = arg1; 6991 struct sbuf *sb; 6992 int rc, i, n, qid = arg2; 6993 uint32_t *buf, *p; 6994 char *qtype; 6995 u_int cim_num_obq = sc->chip_params->cim_num_obq; 6996 6997 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 6998 ("%s: bad qid %d\n", __func__, qid)); 6999 7000 if (qid < CIM_NUM_IBQ) { 7001 /* inbound queue */ 7002 qtype = "IBQ"; 7003 n = 4 * CIM_IBQ_SIZE; 7004 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7005 rc = t4_read_cim_ibq(sc, qid, buf, n); 7006 } else { 7007 /* outbound queue */ 7008 qtype = "OBQ"; 7009 qid -= CIM_NUM_IBQ; 7010 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 7011 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7012 rc = t4_read_cim_obq(sc, qid, buf, n); 7013 } 7014 7015 if (rc < 0) { 7016 rc = -rc; 7017 goto done; 7018 } 7019 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 7020 7021 rc = sysctl_wire_old_buffer(req, 0); 7022 if (rc != 0) 7023 goto done; 7024 7025 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7026 if (sb == NULL) { 7027 rc = ENOMEM; 7028 goto done; 7029 } 7030 7031 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 7032 for (i = 0, p = buf; i < n; i += 16, p += 4) 7033 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 7034 p[2], p[3]); 7035 7036 rc = sbuf_finish(sb); 7037 sbuf_delete(sb); 7038done: 7039 free(buf, M_CXGBE); 7040 return (rc); 7041} 7042 7043static int 7044sysctl_cim_la(SYSCTL_HANDLER_ARGS) 7045{ 7046 struct adapter *sc = arg1; 7047 u_int cfg; 7048 struct sbuf *sb; 7049 uint32_t *buf, *p; 7050 int rc; 7051 7052 MPASS(chip_id(sc) <= CHELSIO_T5); 7053 7054 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 7055 if (rc != 0) 7056 return (rc); 7057 7058 rc = sysctl_wire_old_buffer(req, 0); 7059 if (rc != 0) 7060 return (rc); 7061 7062 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7063 if (sb == NULL) 7064 return (ENOMEM); 7065 7066 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 7067 M_ZERO | M_WAITOK); 7068 7069 rc = -t4_cim_read_la(sc, buf, NULL); 7070 if (rc != 0) 7071 goto done; 7072 7073 sbuf_printf(sb, "Status Data PC%s", 7074 cfg & F_UPDBGLACAPTPCONLY ? "" : 7075 " LS0Stat LS0Addr LS0Data"); 7076 7077 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 7078 if (cfg & F_UPDBGLACAPTPCONLY) { 7079 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 7080 p[6], p[7]); 7081 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 7082 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 7083 p[4] & 0xff, p[5] >> 8); 7084 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 7085 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7086 p[1] & 0xf, p[2] >> 4); 7087 } else { 7088 sbuf_printf(sb, 7089 "\n %02x %x%07x %x%07x %08x %08x " 7090 "%08x%08x%08x%08x", 7091 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7092 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 7093 p[6], p[7]); 7094 } 7095 } 7096 7097 rc = sbuf_finish(sb); 7098 sbuf_delete(sb); 7099done: 7100 free(buf, M_CXGBE); 7101 return (rc); 7102} 7103 7104static int 7105sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS) 7106{ 7107 struct adapter *sc = arg1; 7108 u_int cfg; 7109 struct sbuf *sb; 7110 uint32_t *buf, *p; 7111 int rc; 7112 7113 MPASS(chip_id(sc) > CHELSIO_T5); 7114 7115 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 7116 if (rc != 0) 7117 return (rc); 7118 7119 rc = sysctl_wire_old_buffer(req, 0); 7120 if (rc != 0) 7121 return (rc); 7122 7123 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7124 if (sb == NULL) 7125 return (ENOMEM); 7126 7127 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 7128 M_ZERO | M_WAITOK); 7129 7130 rc = -t4_cim_read_la(sc, buf, NULL); 7131 if (rc != 0) 7132 goto done; 7133 7134 sbuf_printf(sb, "Status Inst Data PC%s", 7135 cfg & F_UPDBGLACAPTPCONLY ? "" : 7136 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 7137 7138 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 7139 if (cfg & F_UPDBGLACAPTPCONLY) { 7140 sbuf_printf(sb, "\n %02x %08x %08x %08x", 7141 p[3] & 0xff, p[2], p[1], p[0]); 7142 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 7143 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 7144 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 7145 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 7146 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 7147 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 7148 p[6] >> 16); 7149 } else { 7150 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 7151 "%08x %08x %08x %08x %08x %08x", 7152 (p[9] >> 16) & 0xff, 7153 p[9] & 0xffff, p[8] >> 16, 7154 p[8] & 0xffff, p[7] >> 16, 7155 p[7] & 0xffff, p[6] >> 16, 7156 p[2], p[1], p[0], p[5], p[4], p[3]); 7157 } 7158 } 7159 7160 rc = sbuf_finish(sb); 7161 sbuf_delete(sb); 7162done: 7163 free(buf, M_CXGBE); 7164 return (rc); 7165} 7166 7167static int 7168sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 7169{ 7170 struct adapter *sc = arg1; 7171 u_int i; 7172 struct sbuf *sb; 7173 uint32_t *buf, *p; 7174 int rc; 7175 7176 rc = sysctl_wire_old_buffer(req, 0); 7177 if (rc != 0) 7178 return (rc); 7179 7180 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7181 if (sb == NULL) 7182 return (ENOMEM); 7183 7184 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 7185 M_ZERO | M_WAITOK); 7186 7187 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 7188 p = buf; 7189 7190 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 7191 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 7192 p[1], p[0]); 7193 } 7194 7195 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 7196 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 7197 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 7198 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 7199 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 7200 (p[1] >> 2) | ((p[2] & 3) << 30), 7201 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 7202 p[0] & 1); 7203 } 7204 7205 rc = sbuf_finish(sb); 7206 sbuf_delete(sb); 7207 free(buf, M_CXGBE); 7208 return (rc); 7209} 7210 7211static int 7212sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 7213{ 7214 struct adapter *sc = arg1; 7215 u_int i; 7216 struct sbuf *sb; 7217 uint32_t *buf, *p; 7218 int rc; 7219 7220 rc = sysctl_wire_old_buffer(req, 0); 7221 if (rc != 0) 7222 return (rc); 7223 7224 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7225 if (sb == NULL) 7226 return (ENOMEM); 7227 7228 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 7229 M_ZERO | M_WAITOK); 7230 7231 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 7232 p = buf; 7233 7234 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 7235 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 7236 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 7237 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 7238 p[4], p[3], p[2], p[1], p[0]); 7239 } 7240 7241 sbuf_printf(sb, "\n\nCntl ID Data"); 7242 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 7243 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 7244 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 7245 } 7246 7247 rc = sbuf_finish(sb); 7248 sbuf_delete(sb); 7249 free(buf, M_CXGBE); 7250 return (rc); 7251} 7252 7253static int 7254sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 7255{ 7256 struct adapter *sc = arg1; 7257 struct sbuf *sb; 7258 int rc, i; 7259 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 7260 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 7261 uint16_t thres[CIM_NUM_IBQ]; 7262 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 7263 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 7264 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 7265 7266 cim_num_obq = sc->chip_params->cim_num_obq; 7267 if (is_t4(sc)) { 7268 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 7269 obq_rdaddr = A_UP_OBQ_0_REALADDR; 7270 } else { 7271 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 7272 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 7273 } 7274 nq = CIM_NUM_IBQ + cim_num_obq; 7275 7276 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 7277 if (rc == 0) 7278 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 7279 if (rc != 0) 7280 return (rc); 7281 7282 t4_read_cimq_cfg(sc, base, size, thres); 7283 7284 rc = sysctl_wire_old_buffer(req, 0); 7285 if (rc != 0) 7286 return (rc); 7287 7288 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7289 if (sb == NULL) 7290 return (ENOMEM); 7291 7292 sbuf_printf(sb, 7293 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 7294 7295 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 7296 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 7297 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 7298 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7299 G_QUEREMFLITS(p[2]) * 16); 7300 for ( ; i < nq; i++, p += 4, wr += 2) 7301 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 7302 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 7303 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7304 G_QUEREMFLITS(p[2]) * 16); 7305 7306 rc = sbuf_finish(sb); 7307 sbuf_delete(sb); 7308 7309 return (rc); 7310} 7311 7312static int 7313sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 7314{ 7315 struct adapter *sc = arg1; 7316 struct sbuf *sb; 7317 int rc; 7318 struct tp_cpl_stats stats; 7319 7320 rc = sysctl_wire_old_buffer(req, 0); 7321 if (rc != 0) 7322 return (rc); 7323 7324 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7325 if (sb == NULL) 7326 return (ENOMEM); 7327 7328 mtx_lock(&sc->reg_lock); 7329 t4_tp_get_cpl_stats(sc, &stats, 0); 7330 mtx_unlock(&sc->reg_lock); 7331 7332 if (sc->chip_params->nchan > 2) { 7333 sbuf_printf(sb, " channel 0 channel 1" 7334 " channel 2 channel 3"); 7335 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 7336 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 7337 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 7338 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 7339 } else { 7340 sbuf_printf(sb, " channel 0 channel 1"); 7341 sbuf_printf(sb, "\nCPL requests: %10u %10u", 7342 stats.req[0], stats.req[1]); 7343 sbuf_printf(sb, "\nCPL responses: %10u %10u", 7344 stats.rsp[0], stats.rsp[1]); 7345 } 7346 7347 rc = sbuf_finish(sb); 7348 sbuf_delete(sb); 7349 7350 return (rc); 7351} 7352 7353static int 7354sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 7355{ 7356 struct adapter *sc = arg1; 7357 struct sbuf *sb; 7358 int rc; 7359 struct tp_usm_stats stats; 7360 7361 rc = sysctl_wire_old_buffer(req, 0); 7362 if (rc != 0) 7363 return(rc); 7364 7365 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7366 if (sb == NULL) 7367 return (ENOMEM); 7368 7369 t4_get_usm_stats(sc, &stats, 1); 7370 7371 sbuf_printf(sb, "Frames: %u\n", stats.frames); 7372 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 7373 sbuf_printf(sb, "Drops: %u", stats.drops); 7374 7375 rc = sbuf_finish(sb); 7376 sbuf_delete(sb); 7377 7378 return (rc); 7379} 7380 7381static const char * const devlog_level_strings[] = { 7382 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 7383 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 7384 [FW_DEVLOG_LEVEL_ERR] = "ERR", 7385 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 7386 [FW_DEVLOG_LEVEL_INFO] = "INFO", 7387 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 7388}; 7389 7390static const char * const devlog_facility_strings[] = { 7391 [FW_DEVLOG_FACILITY_CORE] = "CORE", 7392 [FW_DEVLOG_FACILITY_CF] = "CF", 7393 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 7394 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 7395 [FW_DEVLOG_FACILITY_RES] = "RES", 7396 [FW_DEVLOG_FACILITY_HW] = "HW", 7397 [FW_DEVLOG_FACILITY_FLR] = "FLR", 7398 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 7399 [FW_DEVLOG_FACILITY_PHY] = "PHY", 7400 [FW_DEVLOG_FACILITY_MAC] = "MAC", 7401 [FW_DEVLOG_FACILITY_PORT] = "PORT", 7402 [FW_DEVLOG_FACILITY_VI] = "VI", 7403 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 7404 [FW_DEVLOG_FACILITY_ACL] = "ACL", 7405 [FW_DEVLOG_FACILITY_TM] = "TM", 7406 [FW_DEVLOG_FACILITY_QFC] = "QFC", 7407 [FW_DEVLOG_FACILITY_DCB] = "DCB", 7408 [FW_DEVLOG_FACILITY_ETH] = "ETH", 7409 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 7410 [FW_DEVLOG_FACILITY_RI] = "RI", 7411 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 7412 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 7413 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 7414 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 7415 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 7416}; 7417 7418static int 7419sysctl_devlog(SYSCTL_HANDLER_ARGS) 7420{ 7421 struct adapter *sc = arg1; 7422 struct devlog_params *dparams = &sc->params.devlog; 7423 struct fw_devlog_e *buf, *e; 7424 int i, j, rc, nentries, first = 0; 7425 struct sbuf *sb; 7426 uint64_t ftstamp = UINT64_MAX; 7427 7428 if (dparams->addr == 0) 7429 return (ENXIO); 7430 7431 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT); 7432 if (buf == NULL) 7433 return (ENOMEM); 7434 7435 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 7436 if (rc != 0) 7437 goto done; 7438 7439 nentries = dparams->size / sizeof(struct fw_devlog_e); 7440 for (i = 0; i < nentries; i++) { 7441 e = &buf[i]; 7442 7443 if (e->timestamp == 0) 7444 break; /* end */ 7445 7446 e->timestamp = be64toh(e->timestamp); 7447 e->seqno = be32toh(e->seqno); 7448 for (j = 0; j < 8; j++) 7449 e->params[j] = be32toh(e->params[j]); 7450 7451 if (e->timestamp < ftstamp) { 7452 ftstamp = e->timestamp; 7453 first = i; 7454 } 7455 } 7456 7457 if (buf[first].timestamp == 0) 7458 goto done; /* nothing in the log */ 7459 7460 rc = sysctl_wire_old_buffer(req, 0); 7461 if (rc != 0) 7462 goto done; 7463 7464 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7465 if (sb == NULL) { 7466 rc = ENOMEM; 7467 goto done; 7468 } 7469 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 7470 "Seq#", "Tstamp", "Level", "Facility", "Message"); 7471 7472 i = first; 7473 do { 7474 e = &buf[i]; 7475 if (e->timestamp == 0) 7476 break; /* end */ 7477 7478 sbuf_printf(sb, "%10d %15ju %8s %8s ", 7479 e->seqno, e->timestamp, 7480 (e->level < nitems(devlog_level_strings) ? 7481 devlog_level_strings[e->level] : "UNKNOWN"), 7482 (e->facility < nitems(devlog_facility_strings) ? 7483 devlog_facility_strings[e->facility] : "UNKNOWN")); 7484 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 7485 e->params[2], e->params[3], e->params[4], 7486 e->params[5], e->params[6], e->params[7]); 7487 7488 if (++i == nentries) 7489 i = 0; 7490 } while (i != first); 7491 7492 rc = sbuf_finish(sb); 7493 sbuf_delete(sb); 7494done: 7495 free(buf, M_CXGBE); 7496 return (rc); 7497} 7498 7499static int 7500sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 7501{ 7502 struct adapter *sc = arg1; 7503 struct sbuf *sb; 7504 int rc; 7505 struct tp_fcoe_stats stats[MAX_NCHAN]; 7506 int i, nchan = sc->chip_params->nchan; 7507 7508 rc = sysctl_wire_old_buffer(req, 0); 7509 if (rc != 0) 7510 return (rc); 7511 7512 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7513 if (sb == NULL) 7514 return (ENOMEM); 7515 7516 for (i = 0; i < nchan; i++) 7517 t4_get_fcoe_stats(sc, i, &stats[i], 1); 7518 7519 if (nchan > 2) { 7520 sbuf_printf(sb, " channel 0 channel 1" 7521 " channel 2 channel 3"); 7522 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 7523 stats[0].octets_ddp, stats[1].octets_ddp, 7524 stats[2].octets_ddp, stats[3].octets_ddp); 7525 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 7526 stats[0].frames_ddp, stats[1].frames_ddp, 7527 stats[2].frames_ddp, stats[3].frames_ddp); 7528 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 7529 stats[0].frames_drop, stats[1].frames_drop, 7530 stats[2].frames_drop, stats[3].frames_drop); 7531 } else { 7532 sbuf_printf(sb, " channel 0 channel 1"); 7533 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 7534 stats[0].octets_ddp, stats[1].octets_ddp); 7535 sbuf_printf(sb, "\nframesDDP: %16u %16u", 7536 stats[0].frames_ddp, stats[1].frames_ddp); 7537 sbuf_printf(sb, "\nframesDrop: %16u %16u", 7538 stats[0].frames_drop, stats[1].frames_drop); 7539 } 7540 7541 rc = sbuf_finish(sb); 7542 sbuf_delete(sb); 7543 7544 return (rc); 7545} 7546 7547static int 7548sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 7549{ 7550 struct adapter *sc = arg1; 7551 struct sbuf *sb; 7552 int rc, i; 7553 unsigned int map, kbps, ipg, mode; 7554 unsigned int pace_tab[NTX_SCHED]; 7555 7556 rc = sysctl_wire_old_buffer(req, 0); 7557 if (rc != 0) 7558 return (rc); 7559 7560 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7561 if (sb == NULL) 7562 return (ENOMEM); 7563 7564 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 7565 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 7566 t4_read_pace_tbl(sc, pace_tab); 7567 7568 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 7569 "Class IPG (0.1 ns) Flow IPG (us)"); 7570 7571 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 7572 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 7573 sbuf_printf(sb, "\n %u %-5s %u ", i, 7574 (mode & (1 << i)) ? "flow" : "class", map & 3); 7575 if (kbps) 7576 sbuf_printf(sb, "%9u ", kbps); 7577 else 7578 sbuf_printf(sb, " disabled "); 7579 7580 if (ipg) 7581 sbuf_printf(sb, "%13u ", ipg); 7582 else 7583 sbuf_printf(sb, " disabled "); 7584 7585 if (pace_tab[i]) 7586 sbuf_printf(sb, "%10u", pace_tab[i]); 7587 else 7588 sbuf_printf(sb, " disabled"); 7589 } 7590 7591 rc = sbuf_finish(sb); 7592 sbuf_delete(sb); 7593 7594 return (rc); 7595} 7596 7597static int 7598sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 7599{ 7600 struct adapter *sc = arg1; 7601 struct sbuf *sb; 7602 int rc, i, j; 7603 uint64_t *p0, *p1; 7604 struct lb_port_stats s[2]; 7605 static const char *stat_name[] = { 7606 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 7607 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 7608 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 7609 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 7610 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 7611 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 7612 "BG2FramesTrunc:", "BG3FramesTrunc:" 7613 }; 7614 7615 rc = sysctl_wire_old_buffer(req, 0); 7616 if (rc != 0) 7617 return (rc); 7618 7619 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7620 if (sb == NULL) 7621 return (ENOMEM); 7622 7623 memset(s, 0, sizeof(s)); 7624 7625 for (i = 0; i < sc->chip_params->nchan; i += 2) { 7626 t4_get_lb_stats(sc, i, &s[0]); 7627 t4_get_lb_stats(sc, i + 1, &s[1]); 7628 7629 p0 = &s[0].octets; 7630 p1 = &s[1].octets; 7631 sbuf_printf(sb, "%s Loopback %u" 7632 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 7633 7634 for (j = 0; j < nitems(stat_name); j++) 7635 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 7636 *p0++, *p1++); 7637 } 7638 7639 rc = sbuf_finish(sb); 7640 sbuf_delete(sb); 7641 7642 return (rc); 7643} 7644 7645static int 7646sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 7647{ 7648 int rc = 0; 7649 struct port_info *pi = arg1; 7650 struct link_config *lc = &pi->link_cfg; 7651 struct sbuf *sb; 7652 7653 rc = sysctl_wire_old_buffer(req, 0); 7654 if (rc != 0) 7655 return(rc); 7656 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 7657 if (sb == NULL) 7658 return (ENOMEM); 7659 7660 if (lc->link_ok || lc->link_down_rc == 255) 7661 sbuf_printf(sb, "n/a"); 7662 else 7663 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 7664 7665 rc = sbuf_finish(sb); 7666 sbuf_delete(sb); 7667 7668 return (rc); 7669} 7670 7671struct mem_desc { 7672 unsigned int base; 7673 unsigned int limit; 7674 unsigned int idx; 7675}; 7676 7677static int 7678mem_desc_cmp(const void *a, const void *b) 7679{ 7680 return ((const struct mem_desc *)a)->base - 7681 ((const struct mem_desc *)b)->base; 7682} 7683 7684static void 7685mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 7686 unsigned int to) 7687{ 7688 unsigned int size; 7689 7690 if (from == to) 7691 return; 7692 7693 size = to - from + 1; 7694 if (size == 0) 7695 return; 7696 7697 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 7698 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 7699} 7700 7701static int 7702sysctl_meminfo(SYSCTL_HANDLER_ARGS) 7703{ 7704 struct adapter *sc = arg1; 7705 struct sbuf *sb; 7706 int rc, i, n; 7707 uint32_t lo, hi, used, alloc; 7708 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 7709 static const char *region[] = { 7710 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 7711 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 7712 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 7713 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 7714 "RQUDP region:", "PBL region:", "TXPBL region:", 7715 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 7716 "On-chip queues:", "TLS keys:", 7717 }; 7718 struct mem_desc avail[4]; 7719 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 7720 struct mem_desc *md = mem; 7721 7722 rc = sysctl_wire_old_buffer(req, 0); 7723 if (rc != 0) 7724 return (rc); 7725 7726 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7727 if (sb == NULL) 7728 return (ENOMEM); 7729 7730 for (i = 0; i < nitems(mem); i++) { 7731 mem[i].limit = 0; 7732 mem[i].idx = i; 7733 } 7734 7735 /* Find and sort the populated memory ranges */ 7736 i = 0; 7737 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 7738 if (lo & F_EDRAM0_ENABLE) { 7739 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 7740 avail[i].base = G_EDRAM0_BASE(hi) << 20; 7741 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 7742 avail[i].idx = 0; 7743 i++; 7744 } 7745 if (lo & F_EDRAM1_ENABLE) { 7746 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 7747 avail[i].base = G_EDRAM1_BASE(hi) << 20; 7748 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 7749 avail[i].idx = 1; 7750 i++; 7751 } 7752 if (lo & F_EXT_MEM_ENABLE) { 7753 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 7754 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 7755 avail[i].limit = avail[i].base + 7756 (G_EXT_MEM_SIZE(hi) << 20); 7757 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 7758 i++; 7759 } 7760 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 7761 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 7762 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 7763 avail[i].limit = avail[i].base + 7764 (G_EXT_MEM1_SIZE(hi) << 20); 7765 avail[i].idx = 4; 7766 i++; 7767 } 7768 if (!i) /* no memory available */ 7769 return 0; 7770 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 7771 7772 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 7773 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 7774 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 7775 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 7776 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 7777 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 7778 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 7779 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 7780 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 7781 7782 /* the next few have explicit upper bounds */ 7783 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 7784 md->limit = md->base - 1 + 7785 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 7786 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 7787 md++; 7788 7789 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 7790 md->limit = md->base - 1 + 7791 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 7792 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 7793 md++; 7794 7795 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 7796 if (chip_id(sc) <= CHELSIO_T5) 7797 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 7798 else 7799 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 7800 md->limit = 0; 7801 } else { 7802 md->base = 0; 7803 md->idx = nitems(region); /* hide it */ 7804 } 7805 md++; 7806 7807#define ulp_region(reg) \ 7808 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 7809 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 7810 7811 ulp_region(RX_ISCSI); 7812 ulp_region(RX_TDDP); 7813 ulp_region(TX_TPT); 7814 ulp_region(RX_STAG); 7815 ulp_region(RX_RQ); 7816 ulp_region(RX_RQUDP); 7817 ulp_region(RX_PBL); 7818 ulp_region(TX_PBL); 7819#undef ulp_region 7820 7821 md->base = 0; 7822 md->idx = nitems(region); 7823 if (!is_t4(sc)) { 7824 uint32_t size = 0; 7825 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 7826 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 7827 7828 if (is_t5(sc)) { 7829 if (sge_ctrl & F_VFIFO_ENABLE) 7830 size = G_DBVFIFO_SIZE(fifo_size); 7831 } else 7832 size = G_T6_DBVFIFO_SIZE(fifo_size); 7833 7834 if (size) { 7835 md->base = G_BASEADDR(t4_read_reg(sc, 7836 A_SGE_DBVFIFO_BADDR)); 7837 md->limit = md->base + (size << 2) - 1; 7838 } 7839 } 7840 md++; 7841 7842 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 7843 md->limit = 0; 7844 md++; 7845 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 7846 md->limit = 0; 7847 md++; 7848 7849 md->base = sc->vres.ocq.start; 7850 if (sc->vres.ocq.size) 7851 md->limit = md->base + sc->vres.ocq.size - 1; 7852 else 7853 md->idx = nitems(region); /* hide it */ 7854 md++; 7855 7856 md->base = sc->vres.key.start; 7857 if (sc->vres.key.size) 7858 md->limit = md->base + sc->vres.key.size - 1; 7859 else 7860 md->idx = nitems(region); /* hide it */ 7861 md++; 7862 7863 /* add any address-space holes, there can be up to 3 */ 7864 for (n = 0; n < i - 1; n++) 7865 if (avail[n].limit < avail[n + 1].base) 7866 (md++)->base = avail[n].limit; 7867 if (avail[n].limit) 7868 (md++)->base = avail[n].limit; 7869 7870 n = md - mem; 7871 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 7872 7873 for (lo = 0; lo < i; lo++) 7874 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 7875 avail[lo].limit - 1); 7876 7877 sbuf_printf(sb, "\n"); 7878 for (i = 0; i < n; i++) { 7879 if (mem[i].idx >= nitems(region)) 7880 continue; /* skip holes */ 7881 if (!mem[i].limit) 7882 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 7883 mem_region_show(sb, region[mem[i].idx], mem[i].base, 7884 mem[i].limit); 7885 } 7886 7887 sbuf_printf(sb, "\n"); 7888 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 7889 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 7890 mem_region_show(sb, "uP RAM:", lo, hi); 7891 7892 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 7893 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 7894 mem_region_show(sb, "uP Extmem2:", lo, hi); 7895 7896 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 7897 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 7898 G_PMRXMAXPAGE(lo), 7899 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 7900 (lo & F_PMRXNUMCHN) ? 2 : 1); 7901 7902 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 7903 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 7904 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 7905 G_PMTXMAXPAGE(lo), 7906 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 7907 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 7908 sbuf_printf(sb, "%u p-structs\n", 7909 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 7910 7911 for (i = 0; i < 4; i++) { 7912 if (chip_id(sc) > CHELSIO_T5) 7913 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 7914 else 7915 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 7916 if (is_t5(sc)) { 7917 used = G_T5_USED(lo); 7918 alloc = G_T5_ALLOC(lo); 7919 } else { 7920 used = G_USED(lo); 7921 alloc = G_ALLOC(lo); 7922 } 7923 /* For T6 these are MAC buffer groups */ 7924 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 7925 i, used, alloc); 7926 } 7927 for (i = 0; i < sc->chip_params->nchan; i++) { 7928 if (chip_id(sc) > CHELSIO_T5) 7929 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 7930 else 7931 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 7932 if (is_t5(sc)) { 7933 used = G_T5_USED(lo); 7934 alloc = G_T5_ALLOC(lo); 7935 } else { 7936 used = G_USED(lo); 7937 alloc = G_ALLOC(lo); 7938 } 7939 /* For T6 these are MAC buffer groups */ 7940 sbuf_printf(sb, 7941 "\nLoopback %d using %u pages out of %u allocated", 7942 i, used, alloc); 7943 } 7944 7945 rc = sbuf_finish(sb); 7946 sbuf_delete(sb); 7947 7948 return (rc); 7949} 7950 7951static inline void 7952tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 7953{ 7954 *mask = x | y; 7955 y = htobe64(y); 7956 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 7957} 7958 7959static int 7960sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 7961{ 7962 struct adapter *sc = arg1; 7963 struct sbuf *sb; 7964 int rc, i; 7965 7966 MPASS(chip_id(sc) <= CHELSIO_T5); 7967 7968 rc = sysctl_wire_old_buffer(req, 0); 7969 if (rc != 0) 7970 return (rc); 7971 7972 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7973 if (sb == NULL) 7974 return (ENOMEM); 7975 7976 sbuf_printf(sb, 7977 "Idx Ethernet address Mask Vld Ports PF" 7978 " VF Replication P0 P1 P2 P3 ML"); 7979 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 7980 uint64_t tcamx, tcamy, mask; 7981 uint32_t cls_lo, cls_hi; 7982 uint8_t addr[ETHER_ADDR_LEN]; 7983 7984 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 7985 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 7986 if (tcamx & tcamy) 7987 continue; 7988 tcamxy2valmask(tcamx, tcamy, addr, &mask); 7989 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 7990 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 7991 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 7992 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 7993 addr[3], addr[4], addr[5], (uintmax_t)mask, 7994 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 7995 G_PORTMAP(cls_hi), G_PF(cls_lo), 7996 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 7997 7998 if (cls_lo & F_REPLICATE) { 7999 struct fw_ldst_cmd ldst_cmd; 8000 8001 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8002 ldst_cmd.op_to_addrspace = 8003 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8004 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8005 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8006 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8007 ldst_cmd.u.mps.rplc.fid_idx = 8008 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8009 V_FW_LDST_CMD_IDX(i)); 8010 8011 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8012 "t4mps"); 8013 if (rc) 8014 break; 8015 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8016 sizeof(ldst_cmd), &ldst_cmd); 8017 end_synchronized_op(sc, 0); 8018 8019 if (rc != 0) { 8020 sbuf_printf(sb, "%36d", rc); 8021 rc = 0; 8022 } else { 8023 sbuf_printf(sb, " %08x %08x %08x %08x", 8024 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8025 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8026 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8027 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8028 } 8029 } else 8030 sbuf_printf(sb, "%36s", ""); 8031 8032 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 8033 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 8034 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 8035 } 8036 8037 if (rc) 8038 (void) sbuf_finish(sb); 8039 else 8040 rc = sbuf_finish(sb); 8041 sbuf_delete(sb); 8042 8043 return (rc); 8044} 8045 8046static int 8047sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 8048{ 8049 struct adapter *sc = arg1; 8050 struct sbuf *sb; 8051 int rc, i; 8052 8053 MPASS(chip_id(sc) > CHELSIO_T5); 8054 8055 rc = sysctl_wire_old_buffer(req, 0); 8056 if (rc != 0) 8057 return (rc); 8058 8059 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8060 if (sb == NULL) 8061 return (ENOMEM); 8062 8063 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 8064 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 8065 " Replication" 8066 " P0 P1 P2 P3 ML\n"); 8067 8068 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8069 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 8070 uint16_t ivlan; 8071 uint64_t tcamx, tcamy, val, mask; 8072 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 8073 uint8_t addr[ETHER_ADDR_LEN]; 8074 8075 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 8076 if (i < 256) 8077 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 8078 else 8079 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 8080 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8081 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8082 tcamy = G_DMACH(val) << 32; 8083 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8084 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8085 lookup_type = G_DATALKPTYPE(data2); 8086 port_num = G_DATAPORTNUM(data2); 8087 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8088 /* Inner header VNI */ 8089 vniy = ((data2 & F_DATAVIDH2) << 23) | 8090 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8091 dip_hit = data2 & F_DATADIPHIT; 8092 vlan_vld = 0; 8093 } else { 8094 vniy = 0; 8095 dip_hit = 0; 8096 vlan_vld = data2 & F_DATAVIDH2; 8097 ivlan = G_VIDL(val); 8098 } 8099 8100 ctl |= V_CTLXYBITSEL(1); 8101 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8102 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8103 tcamx = G_DMACH(val) << 32; 8104 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8105 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8106 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8107 /* Inner header VNI mask */ 8108 vnix = ((data2 & F_DATAVIDH2) << 23) | 8109 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8110 } else 8111 vnix = 0; 8112 8113 if (tcamx & tcamy) 8114 continue; 8115 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8116 8117 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8118 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8119 8120 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8121 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8122 "%012jx %06x %06x - - %3c" 8123 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 8124 addr[1], addr[2], addr[3], addr[4], addr[5], 8125 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 8126 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8127 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8128 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8129 } else { 8130 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8131 "%012jx - - ", i, addr[0], addr[1], 8132 addr[2], addr[3], addr[4], addr[5], 8133 (uintmax_t)mask); 8134 8135 if (vlan_vld) 8136 sbuf_printf(sb, "%4u Y ", ivlan); 8137 else 8138 sbuf_printf(sb, " - N "); 8139 8140 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 8141 lookup_type ? 'I' : 'O', port_num, 8142 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8143 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8144 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8145 } 8146 8147 8148 if (cls_lo & F_T6_REPLICATE) { 8149 struct fw_ldst_cmd ldst_cmd; 8150 8151 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8152 ldst_cmd.op_to_addrspace = 8153 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8154 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8155 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8156 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8157 ldst_cmd.u.mps.rplc.fid_idx = 8158 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8159 V_FW_LDST_CMD_IDX(i)); 8160 8161 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8162 "t6mps"); 8163 if (rc) 8164 break; 8165 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8166 sizeof(ldst_cmd), &ldst_cmd); 8167 end_synchronized_op(sc, 0); 8168 8169 if (rc != 0) { 8170 sbuf_printf(sb, "%72d", rc); 8171 rc = 0; 8172 } else { 8173 sbuf_printf(sb, " %08x %08x %08x %08x" 8174 " %08x %08x %08x %08x", 8175 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 8176 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 8177 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 8178 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 8179 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8180 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8181 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8182 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8183 } 8184 } else 8185 sbuf_printf(sb, "%72s", ""); 8186 8187 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 8188 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 8189 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 8190 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 8191 } 8192 8193 if (rc) 8194 (void) sbuf_finish(sb); 8195 else 8196 rc = sbuf_finish(sb); 8197 sbuf_delete(sb); 8198 8199 return (rc); 8200} 8201 8202static int 8203sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 8204{ 8205 struct adapter *sc = arg1; 8206 struct sbuf *sb; 8207 int rc; 8208 uint16_t mtus[NMTUS]; 8209 8210 rc = sysctl_wire_old_buffer(req, 0); 8211 if (rc != 0) 8212 return (rc); 8213 8214 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8215 if (sb == NULL) 8216 return (ENOMEM); 8217 8218 t4_read_mtu_tbl(sc, mtus, NULL); 8219 8220 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 8221 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 8222 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 8223 mtus[14], mtus[15]); 8224 8225 rc = sbuf_finish(sb); 8226 sbuf_delete(sb); 8227 8228 return (rc); 8229} 8230 8231static int 8232sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 8233{ 8234 struct adapter *sc = arg1; 8235 struct sbuf *sb; 8236 int rc, i; 8237 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 8238 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 8239 static const char *tx_stats[MAX_PM_NSTATS] = { 8240 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 8241 "Tx FIFO wait", NULL, "Tx latency" 8242 }; 8243 static const char *rx_stats[MAX_PM_NSTATS] = { 8244 "Read:", "Write bypass:", "Write mem:", "Flush:", 8245 "Rx FIFO wait", NULL, "Rx latency" 8246 }; 8247 8248 rc = sysctl_wire_old_buffer(req, 0); 8249 if (rc != 0) 8250 return (rc); 8251 8252 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8253 if (sb == NULL) 8254 return (ENOMEM); 8255 8256 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 8257 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 8258 8259 sbuf_printf(sb, " Tx pcmds Tx bytes"); 8260 for (i = 0; i < 4; i++) { 8261 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8262 tx_cyc[i]); 8263 } 8264 8265 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 8266 for (i = 0; i < 4; i++) { 8267 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8268 rx_cyc[i]); 8269 } 8270 8271 if (chip_id(sc) > CHELSIO_T5) { 8272 sbuf_printf(sb, 8273 "\n Total wait Total occupancy"); 8274 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8275 tx_cyc[i]); 8276 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8277 rx_cyc[i]); 8278 8279 i += 2; 8280 MPASS(i < nitems(tx_stats)); 8281 8282 sbuf_printf(sb, 8283 "\n Reads Total wait"); 8284 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8285 tx_cyc[i]); 8286 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8287 rx_cyc[i]); 8288 } 8289 8290 rc = sbuf_finish(sb); 8291 sbuf_delete(sb); 8292 8293 return (rc); 8294} 8295 8296static int 8297sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 8298{ 8299 struct adapter *sc = arg1; 8300 struct sbuf *sb; 8301 int rc; 8302 struct tp_rdma_stats stats; 8303 8304 rc = sysctl_wire_old_buffer(req, 0); 8305 if (rc != 0) 8306 return (rc); 8307 8308 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8309 if (sb == NULL) 8310 return (ENOMEM); 8311 8312 mtx_lock(&sc->reg_lock); 8313 t4_tp_get_rdma_stats(sc, &stats, 0); 8314 mtx_unlock(&sc->reg_lock); 8315 8316 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 8317 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 8318 8319 rc = sbuf_finish(sb); 8320 sbuf_delete(sb); 8321 8322 return (rc); 8323} 8324 8325static int 8326sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 8327{ 8328 struct adapter *sc = arg1; 8329 struct sbuf *sb; 8330 int rc; 8331 struct tp_tcp_stats v4, v6; 8332 8333 rc = sysctl_wire_old_buffer(req, 0); 8334 if (rc != 0) 8335 return (rc); 8336 8337 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8338 if (sb == NULL) 8339 return (ENOMEM); 8340 8341 mtx_lock(&sc->reg_lock); 8342 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 8343 mtx_unlock(&sc->reg_lock); 8344 8345 sbuf_printf(sb, 8346 " IP IPv6\n"); 8347 sbuf_printf(sb, "OutRsts: %20u %20u\n", 8348 v4.tcp_out_rsts, v6.tcp_out_rsts); 8349 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 8350 v4.tcp_in_segs, v6.tcp_in_segs); 8351 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 8352 v4.tcp_out_segs, v6.tcp_out_segs); 8353 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 8354 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 8355 8356 rc = sbuf_finish(sb); 8357 sbuf_delete(sb); 8358 8359 return (rc); 8360} 8361 8362static int 8363sysctl_tids(SYSCTL_HANDLER_ARGS) 8364{ 8365 struct adapter *sc = arg1; 8366 struct sbuf *sb; 8367 int rc; 8368 struct tid_info *t = &sc->tids; 8369 8370 rc = sysctl_wire_old_buffer(req, 0); 8371 if (rc != 0) 8372 return (rc); 8373 8374 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8375 if (sb == NULL) 8376 return (ENOMEM); 8377 8378 if (t->natids) { 8379 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 8380 t->atids_in_use); 8381 } 8382 8383 if (t->nhpftids) { 8384 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 8385 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 8386 } 8387 8388 if (t->ntids) { 8389 sbuf_printf(sb, "TID range: "); 8390 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 8391 uint32_t b, hb; 8392 8393 if (chip_id(sc) <= CHELSIO_T5) { 8394 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 8395 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 8396 } else { 8397 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 8398 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 8399 } 8400 8401 if (b) 8402 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1); 8403 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 8404 } else 8405 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1); 8406 sbuf_printf(sb, ", in use: %u\n", 8407 atomic_load_acq_int(&t->tids_in_use)); 8408 } 8409 8410 if (t->nstids) { 8411 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 8412 t->stid_base + t->nstids - 1, t->stids_in_use); 8413 } 8414 8415 if (t->nftids) { 8416 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 8417 t->ftid_end, t->ftids_in_use); 8418 } 8419 8420 if (t->netids) { 8421 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base, 8422 t->etid_base + t->netids - 1); 8423 } 8424 8425 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 8426 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 8427 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 8428 8429 rc = sbuf_finish(sb); 8430 sbuf_delete(sb); 8431 8432 return (rc); 8433} 8434 8435static int 8436sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 8437{ 8438 struct adapter *sc = arg1; 8439 struct sbuf *sb; 8440 int rc; 8441 struct tp_err_stats stats; 8442 8443 rc = sysctl_wire_old_buffer(req, 0); 8444 if (rc != 0) 8445 return (rc); 8446 8447 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8448 if (sb == NULL) 8449 return (ENOMEM); 8450 8451 mtx_lock(&sc->reg_lock); 8452 t4_tp_get_err_stats(sc, &stats, 0); 8453 mtx_unlock(&sc->reg_lock); 8454 8455 if (sc->chip_params->nchan > 2) { 8456 sbuf_printf(sb, " channel 0 channel 1" 8457 " channel 2 channel 3\n"); 8458 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 8459 stats.mac_in_errs[0], stats.mac_in_errs[1], 8460 stats.mac_in_errs[2], stats.mac_in_errs[3]); 8461 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 8462 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 8463 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 8464 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 8465 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 8466 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 8467 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 8468 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 8469 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 8470 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 8471 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 8472 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 8473 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 8474 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 8475 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 8476 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 8477 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 8478 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 8479 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 8480 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 8481 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 8482 } else { 8483 sbuf_printf(sb, " channel 0 channel 1\n"); 8484 sbuf_printf(sb, "macInErrs: %10u %10u\n", 8485 stats.mac_in_errs[0], stats.mac_in_errs[1]); 8486 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 8487 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 8488 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 8489 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 8490 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 8491 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 8492 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 8493 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 8494 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 8495 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 8496 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 8497 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 8498 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 8499 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 8500 } 8501 8502 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 8503 stats.ofld_no_neigh, stats.ofld_cong_defer); 8504 8505 rc = sbuf_finish(sb); 8506 sbuf_delete(sb); 8507 8508 return (rc); 8509} 8510 8511static int 8512sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 8513{ 8514 struct adapter *sc = arg1; 8515 struct tp_params *tpp = &sc->params.tp; 8516 u_int mask; 8517 int rc; 8518 8519 mask = tpp->la_mask >> 16; 8520 rc = sysctl_handle_int(oidp, &mask, 0, req); 8521 if (rc != 0 || req->newptr == NULL) 8522 return (rc); 8523 if (mask > 0xffff) 8524 return (EINVAL); 8525 tpp->la_mask = mask << 16; 8526 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 8527 8528 return (0); 8529} 8530 8531struct field_desc { 8532 const char *name; 8533 u_int start; 8534 u_int width; 8535}; 8536 8537static void 8538field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 8539{ 8540 char buf[32]; 8541 int line_size = 0; 8542 8543 while (f->name) { 8544 uint64_t mask = (1ULL << f->width) - 1; 8545 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 8546 ((uintmax_t)v >> f->start) & mask); 8547 8548 if (line_size + len >= 79) { 8549 line_size = 8; 8550 sbuf_printf(sb, "\n "); 8551 } 8552 sbuf_printf(sb, "%s ", buf); 8553 line_size += len + 1; 8554 f++; 8555 } 8556 sbuf_printf(sb, "\n"); 8557} 8558 8559static const struct field_desc tp_la0[] = { 8560 { "RcfOpCodeOut", 60, 4 }, 8561 { "State", 56, 4 }, 8562 { "WcfState", 52, 4 }, 8563 { "RcfOpcSrcOut", 50, 2 }, 8564 { "CRxError", 49, 1 }, 8565 { "ERxError", 48, 1 }, 8566 { "SanityFailed", 47, 1 }, 8567 { "SpuriousMsg", 46, 1 }, 8568 { "FlushInputMsg", 45, 1 }, 8569 { "FlushInputCpl", 44, 1 }, 8570 { "RssUpBit", 43, 1 }, 8571 { "RssFilterHit", 42, 1 }, 8572 { "Tid", 32, 10 }, 8573 { "InitTcb", 31, 1 }, 8574 { "LineNumber", 24, 7 }, 8575 { "Emsg", 23, 1 }, 8576 { "EdataOut", 22, 1 }, 8577 { "Cmsg", 21, 1 }, 8578 { "CdataOut", 20, 1 }, 8579 { "EreadPdu", 19, 1 }, 8580 { "CreadPdu", 18, 1 }, 8581 { "TunnelPkt", 17, 1 }, 8582 { "RcfPeerFin", 16, 1 }, 8583 { "RcfReasonOut", 12, 4 }, 8584 { "TxCchannel", 10, 2 }, 8585 { "RcfTxChannel", 8, 2 }, 8586 { "RxEchannel", 6, 2 }, 8587 { "RcfRxChannel", 5, 1 }, 8588 { "RcfDataOutSrdy", 4, 1 }, 8589 { "RxDvld", 3, 1 }, 8590 { "RxOoDvld", 2, 1 }, 8591 { "RxCongestion", 1, 1 }, 8592 { "TxCongestion", 0, 1 }, 8593 { NULL } 8594}; 8595 8596static const struct field_desc tp_la1[] = { 8597 { "CplCmdIn", 56, 8 }, 8598 { "CplCmdOut", 48, 8 }, 8599 { "ESynOut", 47, 1 }, 8600 { "EAckOut", 46, 1 }, 8601 { "EFinOut", 45, 1 }, 8602 { "ERstOut", 44, 1 }, 8603 { "SynIn", 43, 1 }, 8604 { "AckIn", 42, 1 }, 8605 { "FinIn", 41, 1 }, 8606 { "RstIn", 40, 1 }, 8607 { "DataIn", 39, 1 }, 8608 { "DataInVld", 38, 1 }, 8609 { "PadIn", 37, 1 }, 8610 { "RxBufEmpty", 36, 1 }, 8611 { "RxDdp", 35, 1 }, 8612 { "RxFbCongestion", 34, 1 }, 8613 { "TxFbCongestion", 33, 1 }, 8614 { "TxPktSumSrdy", 32, 1 }, 8615 { "RcfUlpType", 28, 4 }, 8616 { "Eread", 27, 1 }, 8617 { "Ebypass", 26, 1 }, 8618 { "Esave", 25, 1 }, 8619 { "Static0", 24, 1 }, 8620 { "Cread", 23, 1 }, 8621 { "Cbypass", 22, 1 }, 8622 { "Csave", 21, 1 }, 8623 { "CPktOut", 20, 1 }, 8624 { "RxPagePoolFull", 18, 2 }, 8625 { "RxLpbkPkt", 17, 1 }, 8626 { "TxLpbkPkt", 16, 1 }, 8627 { "RxVfValid", 15, 1 }, 8628 { "SynLearned", 14, 1 }, 8629 { "SetDelEntry", 13, 1 }, 8630 { "SetInvEntry", 12, 1 }, 8631 { "CpcmdDvld", 11, 1 }, 8632 { "CpcmdSave", 10, 1 }, 8633 { "RxPstructsFull", 8, 2 }, 8634 { "EpcmdDvld", 7, 1 }, 8635 { "EpcmdFlush", 6, 1 }, 8636 { "EpcmdTrimPrefix", 5, 1 }, 8637 { "EpcmdTrimPostfix", 4, 1 }, 8638 { "ERssIp4Pkt", 3, 1 }, 8639 { "ERssIp6Pkt", 2, 1 }, 8640 { "ERssTcpUdpPkt", 1, 1 }, 8641 { "ERssFceFipPkt", 0, 1 }, 8642 { NULL } 8643}; 8644 8645static const struct field_desc tp_la2[] = { 8646 { "CplCmdIn", 56, 8 }, 8647 { "MpsVfVld", 55, 1 }, 8648 { "MpsPf", 52, 3 }, 8649 { "MpsVf", 44, 8 }, 8650 { "SynIn", 43, 1 }, 8651 { "AckIn", 42, 1 }, 8652 { "FinIn", 41, 1 }, 8653 { "RstIn", 40, 1 }, 8654 { "DataIn", 39, 1 }, 8655 { "DataInVld", 38, 1 }, 8656 { "PadIn", 37, 1 }, 8657 { "RxBufEmpty", 36, 1 }, 8658 { "RxDdp", 35, 1 }, 8659 { "RxFbCongestion", 34, 1 }, 8660 { "TxFbCongestion", 33, 1 }, 8661 { "TxPktSumSrdy", 32, 1 }, 8662 { "RcfUlpType", 28, 4 }, 8663 { "Eread", 27, 1 }, 8664 { "Ebypass", 26, 1 }, 8665 { "Esave", 25, 1 }, 8666 { "Static0", 24, 1 }, 8667 { "Cread", 23, 1 }, 8668 { "Cbypass", 22, 1 }, 8669 { "Csave", 21, 1 }, 8670 { "CPktOut", 20, 1 }, 8671 { "RxPagePoolFull", 18, 2 }, 8672 { "RxLpbkPkt", 17, 1 }, 8673 { "TxLpbkPkt", 16, 1 }, 8674 { "RxVfValid", 15, 1 }, 8675 { "SynLearned", 14, 1 }, 8676 { "SetDelEntry", 13, 1 }, 8677 { "SetInvEntry", 12, 1 }, 8678 { "CpcmdDvld", 11, 1 }, 8679 { "CpcmdSave", 10, 1 }, 8680 { "RxPstructsFull", 8, 2 }, 8681 { "EpcmdDvld", 7, 1 }, 8682 { "EpcmdFlush", 6, 1 }, 8683 { "EpcmdTrimPrefix", 5, 1 }, 8684 { "EpcmdTrimPostfix", 4, 1 }, 8685 { "ERssIp4Pkt", 3, 1 }, 8686 { "ERssIp6Pkt", 2, 1 }, 8687 { "ERssTcpUdpPkt", 1, 1 }, 8688 { "ERssFceFipPkt", 0, 1 }, 8689 { NULL } 8690}; 8691 8692static void 8693tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 8694{ 8695 8696 field_desc_show(sb, *p, tp_la0); 8697} 8698 8699static void 8700tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 8701{ 8702 8703 if (idx) 8704 sbuf_printf(sb, "\n"); 8705 field_desc_show(sb, p[0], tp_la0); 8706 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 8707 field_desc_show(sb, p[1], tp_la0); 8708} 8709 8710static void 8711tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 8712{ 8713 8714 if (idx) 8715 sbuf_printf(sb, "\n"); 8716 field_desc_show(sb, p[0], tp_la0); 8717 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 8718 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 8719} 8720 8721static int 8722sysctl_tp_la(SYSCTL_HANDLER_ARGS) 8723{ 8724 struct adapter *sc = arg1; 8725 struct sbuf *sb; 8726 uint64_t *buf, *p; 8727 int rc; 8728 u_int i, inc; 8729 void (*show_func)(struct sbuf *, uint64_t *, int); 8730 8731 rc = sysctl_wire_old_buffer(req, 0); 8732 if (rc != 0) 8733 return (rc); 8734 8735 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8736 if (sb == NULL) 8737 return (ENOMEM); 8738 8739 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 8740 8741 t4_tp_read_la(sc, buf, NULL); 8742 p = buf; 8743 8744 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 8745 case 2: 8746 inc = 2; 8747 show_func = tp_la_show2; 8748 break; 8749 case 3: 8750 inc = 2; 8751 show_func = tp_la_show3; 8752 break; 8753 default: 8754 inc = 1; 8755 show_func = tp_la_show; 8756 } 8757 8758 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 8759 (*show_func)(sb, p, i); 8760 8761 rc = sbuf_finish(sb); 8762 sbuf_delete(sb); 8763 free(buf, M_CXGBE); 8764 return (rc); 8765} 8766 8767static int 8768sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 8769{ 8770 struct adapter *sc = arg1; 8771 struct sbuf *sb; 8772 int rc; 8773 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 8774 8775 rc = sysctl_wire_old_buffer(req, 0); 8776 if (rc != 0) 8777 return (rc); 8778 8779 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8780 if (sb == NULL) 8781 return (ENOMEM); 8782 8783 t4_get_chan_txrate(sc, nrate, orate); 8784 8785 if (sc->chip_params->nchan > 2) { 8786 sbuf_printf(sb, " channel 0 channel 1" 8787 " channel 2 channel 3\n"); 8788 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 8789 nrate[0], nrate[1], nrate[2], nrate[3]); 8790 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 8791 orate[0], orate[1], orate[2], orate[3]); 8792 } else { 8793 sbuf_printf(sb, " channel 0 channel 1\n"); 8794 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 8795 nrate[0], nrate[1]); 8796 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 8797 orate[0], orate[1]); 8798 } 8799 8800 rc = sbuf_finish(sb); 8801 sbuf_delete(sb); 8802 8803 return (rc); 8804} 8805 8806static int 8807sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 8808{ 8809 struct adapter *sc = arg1; 8810 struct sbuf *sb; 8811 uint32_t *buf, *p; 8812 int rc, i; 8813 8814 rc = sysctl_wire_old_buffer(req, 0); 8815 if (rc != 0) 8816 return (rc); 8817 8818 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8819 if (sb == NULL) 8820 return (ENOMEM); 8821 8822 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 8823 M_ZERO | M_WAITOK); 8824 8825 t4_ulprx_read_la(sc, buf); 8826 p = buf; 8827 8828 sbuf_printf(sb, " Pcmd Type Message" 8829 " Data"); 8830 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 8831 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 8832 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 8833 } 8834 8835 rc = sbuf_finish(sb); 8836 sbuf_delete(sb); 8837 free(buf, M_CXGBE); 8838 return (rc); 8839} 8840 8841static int 8842sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 8843{ 8844 struct adapter *sc = arg1; 8845 struct sbuf *sb; 8846 int rc, v; 8847 8848 MPASS(chip_id(sc) >= CHELSIO_T5); 8849 8850 rc = sysctl_wire_old_buffer(req, 0); 8851 if (rc != 0) 8852 return (rc); 8853 8854 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8855 if (sb == NULL) 8856 return (ENOMEM); 8857 8858 v = t4_read_reg(sc, A_SGE_STAT_CFG); 8859 if (G_STATSOURCE_T5(v) == 7) { 8860 int mode; 8861 8862 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 8863 if (mode == 0) { 8864 sbuf_printf(sb, "total %d, incomplete %d", 8865 t4_read_reg(sc, A_SGE_STAT_TOTAL), 8866 t4_read_reg(sc, A_SGE_STAT_MATCH)); 8867 } else if (mode == 1) { 8868 sbuf_printf(sb, "total %d, data overflow %d", 8869 t4_read_reg(sc, A_SGE_STAT_TOTAL), 8870 t4_read_reg(sc, A_SGE_STAT_MATCH)); 8871 } else { 8872 sbuf_printf(sb, "unknown mode %d", mode); 8873 } 8874 } 8875 rc = sbuf_finish(sb); 8876 sbuf_delete(sb); 8877 8878 return (rc); 8879} 8880 8881static int 8882sysctl_cpus(SYSCTL_HANDLER_ARGS) 8883{ 8884 struct adapter *sc = arg1; 8885 enum cpu_sets op = arg2; 8886 cpuset_t cpuset; 8887 struct sbuf *sb; 8888 int i, rc; 8889 8890 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 8891 8892 CPU_ZERO(&cpuset); 8893 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 8894 if (rc != 0) 8895 return (rc); 8896 8897 rc = sysctl_wire_old_buffer(req, 0); 8898 if (rc != 0) 8899 return (rc); 8900 8901 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8902 if (sb == NULL) 8903 return (ENOMEM); 8904 8905 CPU_FOREACH(i) 8906 sbuf_printf(sb, "%d ", i); 8907 rc = sbuf_finish(sb); 8908 sbuf_delete(sb); 8909 8910 return (rc); 8911 8912} 8913 8914#ifdef TCP_OFFLOAD 8915static int 8916sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS) 8917{ 8918 struct adapter *sc = arg1; 8919 int *old_ports, *new_ports; 8920 int i, new_count, rc; 8921 8922 if (req->newptr == NULL && req->oldptr == NULL) 8923 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) * 8924 sizeof(sc->tt.tls_rx_ports[0]))); 8925 8926 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx"); 8927 if (rc) 8928 return (rc); 8929 8930 if (sc->tt.num_tls_rx_ports == 0) { 8931 i = -1; 8932 rc = SYSCTL_OUT(req, &i, sizeof(i)); 8933 } else 8934 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports, 8935 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0])); 8936 if (rc == 0 && req->newptr != NULL) { 8937 new_count = req->newlen / sizeof(new_ports[0]); 8938 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE, 8939 M_WAITOK); 8940 rc = SYSCTL_IN(req, new_ports, new_count * 8941 sizeof(new_ports[0])); 8942 if (rc) 8943 goto err; 8944 8945 /* Allow setting to a single '-1' to clear the list. */ 8946 if (new_count == 1 && new_ports[0] == -1) { 8947 ADAPTER_LOCK(sc); 8948 old_ports = sc->tt.tls_rx_ports; 8949 sc->tt.tls_rx_ports = NULL; 8950 sc->tt.num_tls_rx_ports = 0; 8951 ADAPTER_UNLOCK(sc); 8952 free(old_ports, M_CXGBE); 8953 } else { 8954 for (i = 0; i < new_count; i++) { 8955 if (new_ports[i] < 1 || 8956 new_ports[i] > IPPORT_MAX) { 8957 rc = EINVAL; 8958 goto err; 8959 } 8960 } 8961 8962 ADAPTER_LOCK(sc); 8963 old_ports = sc->tt.tls_rx_ports; 8964 sc->tt.tls_rx_ports = new_ports; 8965 sc->tt.num_tls_rx_ports = new_count; 8966 ADAPTER_UNLOCK(sc); 8967 free(old_ports, M_CXGBE); 8968 new_ports = NULL; 8969 } 8970 err: 8971 free(new_ports, M_CXGBE); 8972 } 8973 end_synchronized_op(sc, 0); 8974 return (rc); 8975} 8976 8977static void 8978unit_conv(char *buf, size_t len, u_int val, u_int factor) 8979{ 8980 u_int rem = val % factor; 8981 8982 if (rem == 0) 8983 snprintf(buf, len, "%u", val / factor); 8984 else { 8985 while (rem % 10 == 0) 8986 rem /= 10; 8987 snprintf(buf, len, "%u.%u", val / factor, rem); 8988 } 8989} 8990 8991static int 8992sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 8993{ 8994 struct adapter *sc = arg1; 8995 char buf[16]; 8996 u_int res, re; 8997 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 8998 8999 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9000 switch (arg2) { 9001 case 0: 9002 /* timer_tick */ 9003 re = G_TIMERRESOLUTION(res); 9004 break; 9005 case 1: 9006 /* TCP timestamp tick */ 9007 re = G_TIMESTAMPRESOLUTION(res); 9008 break; 9009 case 2: 9010 /* DACK tick */ 9011 re = G_DELAYEDACKRESOLUTION(res); 9012 break; 9013 default: 9014 return (EDOOFUS); 9015 } 9016 9017 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 9018 9019 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 9020} 9021 9022static int 9023sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 9024{ 9025 struct adapter *sc = arg1; 9026 u_int res, dack_re, v; 9027 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9028 9029 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9030 dack_re = G_DELAYEDACKRESOLUTION(res); 9031 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 9032 9033 return (sysctl_handle_int(oidp, &v, 0, req)); 9034} 9035 9036static int 9037sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 9038{ 9039 struct adapter *sc = arg1; 9040 int reg = arg2; 9041 u_int tre; 9042 u_long tp_tick_us, v; 9043 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9044 9045 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 9046 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 9047 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 9048 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 9049 9050 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 9051 tp_tick_us = (cclk_ps << tre) / 1000000; 9052 9053 if (reg == A_TP_INIT_SRTT) 9054 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 9055 else 9056 v = tp_tick_us * t4_read_reg(sc, reg); 9057 9058 return (sysctl_handle_long(oidp, &v, 0, req)); 9059} 9060 9061/* 9062 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 9063 * passed to this function. 9064 */ 9065static int 9066sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 9067{ 9068 struct adapter *sc = arg1; 9069 int idx = arg2; 9070 u_int v; 9071 9072 MPASS(idx >= 0 && idx <= 24); 9073 9074 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 9075 9076 return (sysctl_handle_int(oidp, &v, 0, req)); 9077} 9078 9079static int 9080sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 9081{ 9082 struct adapter *sc = arg1; 9083 int idx = arg2; 9084 u_int shift, v, r; 9085 9086 MPASS(idx >= 0 && idx < 16); 9087 9088 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 9089 shift = (idx & 3) << 3; 9090 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 9091 9092 return (sysctl_handle_int(oidp, &v, 0, req)); 9093} 9094 9095static int 9096sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 9097{ 9098 struct vi_info *vi = arg1; 9099 struct adapter *sc = vi->pi->adapter; 9100 int idx, rc, i; 9101 struct sge_ofld_rxq *ofld_rxq; 9102 uint8_t v; 9103 9104 idx = vi->ofld_tmr_idx; 9105 9106 rc = sysctl_handle_int(oidp, &idx, 0, req); 9107 if (rc != 0 || req->newptr == NULL) 9108 return (rc); 9109 9110 if (idx < 0 || idx >= SGE_NTIMERS) 9111 return (EINVAL); 9112 9113 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 9114 "t4otmr"); 9115 if (rc) 9116 return (rc); 9117 9118 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 9119 for_each_ofld_rxq(vi, i, ofld_rxq) { 9120#ifdef atomic_store_rel_8 9121 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 9122#else 9123 ofld_rxq->iq.intr_params = v; 9124#endif 9125 } 9126 vi->ofld_tmr_idx = idx; 9127 9128 end_synchronized_op(sc, LOCK_HELD); 9129 return (0); 9130} 9131 9132static int 9133sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 9134{ 9135 struct vi_info *vi = arg1; 9136 struct adapter *sc = vi->pi->adapter; 9137 int idx, rc; 9138 9139 idx = vi->ofld_pktc_idx; 9140 9141 rc = sysctl_handle_int(oidp, &idx, 0, req); 9142 if (rc != 0 || req->newptr == NULL) 9143 return (rc); 9144 9145 if (idx < -1 || idx >= SGE_NCOUNTERS) 9146 return (EINVAL); 9147 9148 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 9149 "t4opktc"); 9150 if (rc) 9151 return (rc); 9152 9153 if (vi->flags & VI_INIT_DONE) 9154 rc = EBUSY; /* cannot be changed once the queues are created */ 9155 else 9156 vi->ofld_pktc_idx = idx; 9157 9158 end_synchronized_op(sc, LOCK_HELD); 9159 return (rc); 9160} 9161#endif 9162 9163static int 9164get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 9165{ 9166 int rc; 9167 9168 if (cntxt->cid > M_CTXTQID) 9169 return (EINVAL); 9170 9171 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 9172 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 9173 return (EINVAL); 9174 9175 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 9176 if (rc) 9177 return (rc); 9178 9179 if (sc->flags & FW_OK) { 9180 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 9181 &cntxt->data[0]); 9182 if (rc == 0) 9183 goto done; 9184 } 9185 9186 /* 9187 * Read via firmware failed or wasn't even attempted. Read directly via 9188 * the backdoor. 9189 */ 9190 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 9191done: 9192 end_synchronized_op(sc, 0); 9193 return (rc); 9194} 9195 9196static int 9197load_fw(struct adapter *sc, struct t4_data *fw) 9198{ 9199 int rc; 9200 uint8_t *fw_data; 9201 9202 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 9203 if (rc) 9204 return (rc); 9205 9206 /* 9207 * The firmware, with the sole exception of the memory parity error 9208 * handler, runs from memory and not flash. It is almost always safe to 9209 * install a new firmware on a running system. Just set bit 1 in 9210 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 9211 */ 9212 if (sc->flags & FULL_INIT_DONE && 9213 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 9214 rc = EBUSY; 9215 goto done; 9216 } 9217 9218 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 9219 if (fw_data == NULL) { 9220 rc = ENOMEM; 9221 goto done; 9222 } 9223 9224 rc = copyin(fw->data, fw_data, fw->len); 9225 if (rc == 0) 9226 rc = -t4_load_fw(sc, fw_data, fw->len); 9227 9228 free(fw_data, M_CXGBE); 9229done: 9230 end_synchronized_op(sc, 0); 9231 return (rc); 9232} 9233 9234static int 9235load_cfg(struct adapter *sc, struct t4_data *cfg) 9236{ 9237 int rc; 9238 uint8_t *cfg_data = NULL; 9239 9240 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9241 if (rc) 9242 return (rc); 9243 9244 if (cfg->len == 0) { 9245 /* clear */ 9246 rc = -t4_load_cfg(sc, NULL, 0); 9247 goto done; 9248 } 9249 9250 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 9251 if (cfg_data == NULL) { 9252 rc = ENOMEM; 9253 goto done; 9254 } 9255 9256 rc = copyin(cfg->data, cfg_data, cfg->len); 9257 if (rc == 0) 9258 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 9259 9260 free(cfg_data, M_CXGBE); 9261done: 9262 end_synchronized_op(sc, 0); 9263 return (rc); 9264} 9265 9266static int 9267load_boot(struct adapter *sc, struct t4_bootrom *br) 9268{ 9269 int rc; 9270 uint8_t *br_data = NULL; 9271 u_int offset; 9272 9273 if (br->len > 1024 * 1024) 9274 return (EFBIG); 9275 9276 if (br->pf_offset == 0) { 9277 /* pfidx */ 9278 if (br->pfidx_addr > 7) 9279 return (EINVAL); 9280 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 9281 A_PCIE_PF_EXPROM_OFST))); 9282 } else if (br->pf_offset == 1) { 9283 /* offset */ 9284 offset = G_OFFSET(br->pfidx_addr); 9285 } else { 9286 return (EINVAL); 9287 } 9288 9289 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 9290 if (rc) 9291 return (rc); 9292 9293 if (br->len == 0) { 9294 /* clear */ 9295 rc = -t4_load_boot(sc, NULL, offset, 0); 9296 goto done; 9297 } 9298 9299 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 9300 if (br_data == NULL) { 9301 rc = ENOMEM; 9302 goto done; 9303 } 9304 9305 rc = copyin(br->data, br_data, br->len); 9306 if (rc == 0) 9307 rc = -t4_load_boot(sc, br_data, offset, br->len); 9308 9309 free(br_data, M_CXGBE); 9310done: 9311 end_synchronized_op(sc, 0); 9312 return (rc); 9313} 9314 9315static int 9316load_bootcfg(struct adapter *sc, struct t4_data *bc) 9317{ 9318 int rc; 9319 uint8_t *bc_data = NULL; 9320 9321 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9322 if (rc) 9323 return (rc); 9324 9325 if (bc->len == 0) { 9326 /* clear */ 9327 rc = -t4_load_bootcfg(sc, NULL, 0); 9328 goto done; 9329 } 9330 9331 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 9332 if (bc_data == NULL) { 9333 rc = ENOMEM; 9334 goto done; 9335 } 9336 9337 rc = copyin(bc->data, bc_data, bc->len); 9338 if (rc == 0) 9339 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 9340 9341 free(bc_data, M_CXGBE); 9342done: 9343 end_synchronized_op(sc, 0); 9344 return (rc); 9345} 9346 9347static int 9348cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 9349{ 9350 int rc; 9351 struct cudbg_init *cudbg; 9352 void *handle, *buf; 9353 9354 /* buf is large, don't block if no memory is available */ 9355 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 9356 if (buf == NULL) 9357 return (ENOMEM); 9358 9359 handle = cudbg_alloc_handle(); 9360 if (handle == NULL) { 9361 rc = ENOMEM; 9362 goto done; 9363 } 9364 9365 cudbg = cudbg_get_init(handle); 9366 cudbg->adap = sc; 9367 cudbg->print = (cudbg_print_cb)printf; 9368 9369#ifndef notyet 9370 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 9371 __func__, dump->wr_flash, dump->len, dump->data); 9372#endif 9373 9374 if (dump->wr_flash) 9375 cudbg->use_flash = 1; 9376 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 9377 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 9378 9379 rc = cudbg_collect(handle, buf, &dump->len); 9380 if (rc != 0) 9381 goto done; 9382 9383 rc = copyout(buf, dump->data, dump->len); 9384done: 9385 cudbg_free_handle(handle); 9386 free(buf, M_CXGBE); 9387 return (rc); 9388} 9389 9390static void 9391free_offload_policy(struct t4_offload_policy *op) 9392{ 9393 struct offload_rule *r; 9394 int i; 9395 9396 if (op == NULL) 9397 return; 9398 9399 r = &op->rule[0]; 9400 for (i = 0; i < op->nrules; i++, r++) { 9401 free(r->bpf_prog.bf_insns, M_CXGBE); 9402 } 9403 free(op->rule, M_CXGBE); 9404 free(op, M_CXGBE); 9405} 9406 9407static int 9408set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 9409{ 9410 int i, rc, len; 9411 struct t4_offload_policy *op, *old; 9412 struct bpf_program *bf; 9413 const struct offload_settings *s; 9414 struct offload_rule *r; 9415 void *u; 9416 9417 if (!is_offload(sc)) 9418 return (ENODEV); 9419 9420 if (uop->nrules == 0) { 9421 /* Delete installed policies. */ 9422 op = NULL; 9423 goto set_policy; 9424 } if (uop->nrules > 256) { /* arbitrary */ 9425 return (E2BIG); 9426 } 9427 9428 /* Copy userspace offload policy to kernel */ 9429 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 9430 op->nrules = uop->nrules; 9431 len = op->nrules * sizeof(struct offload_rule); 9432 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9433 rc = copyin(uop->rule, op->rule, len); 9434 if (rc) { 9435 free(op->rule, M_CXGBE); 9436 free(op, M_CXGBE); 9437 return (rc); 9438 } 9439 9440 r = &op->rule[0]; 9441 for (i = 0; i < op->nrules; i++, r++) { 9442 9443 /* Validate open_type */ 9444 if (r->open_type != OPEN_TYPE_LISTEN && 9445 r->open_type != OPEN_TYPE_ACTIVE && 9446 r->open_type != OPEN_TYPE_PASSIVE && 9447 r->open_type != OPEN_TYPE_DONTCARE) { 9448error: 9449 /* 9450 * Rules 0 to i have malloc'd filters that need to be 9451 * freed. Rules i+1 to nrules have userspace pointers 9452 * and should be left alone. 9453 */ 9454 op->nrules = i; 9455 free_offload_policy(op); 9456 return (rc); 9457 } 9458 9459 /* Validate settings */ 9460 s = &r->settings; 9461 if ((s->offload != 0 && s->offload != 1) || 9462 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 9463 s->sched_class < -1 || 9464 s->sched_class >= sc->chip_params->nsched_cls) { 9465 rc = EINVAL; 9466 goto error; 9467 } 9468 9469 bf = &r->bpf_prog; 9470 u = bf->bf_insns; /* userspace ptr */ 9471 bf->bf_insns = NULL; 9472 if (bf->bf_len == 0) { 9473 /* legal, matches everything */ 9474 continue; 9475 } 9476 len = bf->bf_len * sizeof(*bf->bf_insns); 9477 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9478 rc = copyin(u, bf->bf_insns, len); 9479 if (rc != 0) 9480 goto error; 9481 9482 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 9483 rc = EINVAL; 9484 goto error; 9485 } 9486 } 9487set_policy: 9488 rw_wlock(&sc->policy_lock); 9489 old = sc->policy; 9490 sc->policy = op; 9491 rw_wunlock(&sc->policy_lock); 9492 free_offload_policy(old); 9493 9494 return (0); 9495} 9496 9497#define MAX_READ_BUF_SIZE (128 * 1024) 9498static int 9499read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 9500{ 9501 uint32_t addr, remaining, n; 9502 uint32_t *buf; 9503 int rc; 9504 uint8_t *dst; 9505 9506 rc = validate_mem_range(sc, mr->addr, mr->len); 9507 if (rc != 0) 9508 return (rc); 9509 9510 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 9511 addr = mr->addr; 9512 remaining = mr->len; 9513 dst = (void *)mr->data; 9514 9515 while (remaining) { 9516 n = min(remaining, MAX_READ_BUF_SIZE); 9517 read_via_memwin(sc, 2, addr, buf, n); 9518 9519 rc = copyout(buf, dst, n); 9520 if (rc != 0) 9521 break; 9522 9523 dst += n; 9524 remaining -= n; 9525 addr += n; 9526 } 9527 9528 free(buf, M_CXGBE); 9529 return (rc); 9530} 9531#undef MAX_READ_BUF_SIZE 9532 9533static int 9534read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 9535{ 9536 int rc; 9537 9538 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 9539 return (EINVAL); 9540 9541 if (i2cd->len > sizeof(i2cd->data)) 9542 return (EFBIG); 9543 9544 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 9545 if (rc) 9546 return (rc); 9547 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 9548 i2cd->offset, i2cd->len, &i2cd->data[0]); 9549 end_synchronized_op(sc, 0); 9550 9551 return (rc); 9552} 9553 9554int 9555t4_os_find_pci_capability(struct adapter *sc, int cap) 9556{ 9557 int i; 9558 9559 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 9560} 9561 9562int 9563t4_os_pci_save_state(struct adapter *sc) 9564{ 9565 device_t dev; 9566 struct pci_devinfo *dinfo; 9567 9568 dev = sc->dev; 9569 dinfo = device_get_ivars(dev); 9570 9571 pci_cfg_save(dev, dinfo, 0); 9572 return (0); 9573} 9574 9575int 9576t4_os_pci_restore_state(struct adapter *sc) 9577{ 9578 device_t dev; 9579 struct pci_devinfo *dinfo; 9580 9581 dev = sc->dev; 9582 dinfo = device_get_ivars(dev); 9583 9584 pci_cfg_restore(dev, dinfo); 9585 return (0); 9586} 9587 9588void 9589t4_os_portmod_changed(struct port_info *pi) 9590{ 9591 struct adapter *sc = pi->adapter; 9592 struct vi_info *vi; 9593 struct ifnet *ifp; 9594 static const char *mod_str[] = { 9595 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 9596 }; 9597 9598 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 9599 ("%s: port_type %u", __func__, pi->port_type)); 9600 9601 vi = &pi->vi[0]; 9602 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 9603 PORT_LOCK(pi); 9604 build_medialist(pi); 9605 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 9606 fixup_link_config(pi); 9607 apply_link_config(pi); 9608 } 9609 PORT_UNLOCK(pi); 9610 end_synchronized_op(sc, LOCK_HELD); 9611 } 9612 9613 ifp = vi->ifp; 9614 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 9615 if_printf(ifp, "transceiver unplugged.\n"); 9616 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 9617 if_printf(ifp, "unknown transceiver inserted.\n"); 9618 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 9619 if_printf(ifp, "unsupported transceiver inserted.\n"); 9620 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 9621 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 9622 port_top_speed(pi), mod_str[pi->mod_type]); 9623 } else { 9624 if_printf(ifp, "transceiver (type %d) inserted.\n", 9625 pi->mod_type); 9626 } 9627} 9628 9629void 9630t4_os_link_changed(struct port_info *pi) 9631{ 9632 struct vi_info *vi; 9633 struct ifnet *ifp; 9634 struct link_config *lc; 9635 int v; 9636 9637 PORT_LOCK_ASSERT_OWNED(pi); 9638 9639 for_each_vi(pi, v, vi) { 9640 ifp = vi->ifp; 9641 if (ifp == NULL) 9642 continue; 9643 9644 lc = &pi->link_cfg; 9645 if (lc->link_ok) { 9646 ifp->if_baudrate = IF_Mbps(lc->speed); 9647 if_link_state_change(ifp, LINK_STATE_UP); 9648 } else { 9649 if_link_state_change(ifp, LINK_STATE_DOWN); 9650 } 9651 } 9652} 9653 9654void 9655t4_iterate(void (*func)(struct adapter *, void *), void *arg) 9656{ 9657 struct adapter *sc; 9658 9659 sx_slock(&t4_list_lock); 9660 SLIST_FOREACH(sc, &t4_list, link) { 9661 /* 9662 * func should not make any assumptions about what state sc is 9663 * in - the only guarantee is that sc->sc_lock is a valid lock. 9664 */ 9665 func(sc, arg); 9666 } 9667 sx_sunlock(&t4_list_lock); 9668} 9669 9670static int 9671t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 9672 struct thread *td) 9673{ 9674 int rc; 9675 struct adapter *sc = dev->si_drv1; 9676 9677 rc = priv_check(td, PRIV_DRIVER); 9678 if (rc != 0) 9679 return (rc); 9680 9681 switch (cmd) { 9682 case CHELSIO_T4_GETREG: { 9683 struct t4_reg *edata = (struct t4_reg *)data; 9684 9685 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9686 return (EFAULT); 9687 9688 if (edata->size == 4) 9689 edata->val = t4_read_reg(sc, edata->addr); 9690 else if (edata->size == 8) 9691 edata->val = t4_read_reg64(sc, edata->addr); 9692 else 9693 return (EINVAL); 9694 9695 break; 9696 } 9697 case CHELSIO_T4_SETREG: { 9698 struct t4_reg *edata = (struct t4_reg *)data; 9699 9700 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9701 return (EFAULT); 9702 9703 if (edata->size == 4) { 9704 if (edata->val & 0xffffffff00000000) 9705 return (EINVAL); 9706 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 9707 } else if (edata->size == 8) 9708 t4_write_reg64(sc, edata->addr, edata->val); 9709 else 9710 return (EINVAL); 9711 break; 9712 } 9713 case CHELSIO_T4_REGDUMP: { 9714 struct t4_regdump *regs = (struct t4_regdump *)data; 9715 int reglen = t4_get_regs_len(sc); 9716 uint8_t *buf; 9717 9718 if (regs->len < reglen) { 9719 regs->len = reglen; /* hint to the caller */ 9720 return (ENOBUFS); 9721 } 9722 9723 regs->len = reglen; 9724 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 9725 get_regs(sc, regs, buf); 9726 rc = copyout(buf, regs->data, reglen); 9727 free(buf, M_CXGBE); 9728 break; 9729 } 9730 case CHELSIO_T4_GET_FILTER_MODE: 9731 rc = get_filter_mode(sc, (uint32_t *)data); 9732 break; 9733 case CHELSIO_T4_SET_FILTER_MODE: 9734 rc = set_filter_mode(sc, *(uint32_t *)data); 9735 break; 9736 case CHELSIO_T4_GET_FILTER: 9737 rc = get_filter(sc, (struct t4_filter *)data); 9738 break; 9739 case CHELSIO_T4_SET_FILTER: 9740 rc = set_filter(sc, (struct t4_filter *)data); 9741 break; 9742 case CHELSIO_T4_DEL_FILTER: 9743 rc = del_filter(sc, (struct t4_filter *)data); 9744 break; 9745 case CHELSIO_T4_GET_SGE_CONTEXT: 9746 rc = get_sge_context(sc, (struct t4_sge_context *)data); 9747 break; 9748 case CHELSIO_T4_LOAD_FW: 9749 rc = load_fw(sc, (struct t4_data *)data); 9750 break; 9751 case CHELSIO_T4_GET_MEM: 9752 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 9753 break; 9754 case CHELSIO_T4_GET_I2C: 9755 rc = read_i2c(sc, (struct t4_i2c_data *)data); 9756 break; 9757 case CHELSIO_T4_CLEAR_STATS: { 9758 int i, v, bg_map; 9759 u_int port_id = *(uint32_t *)data; 9760 struct port_info *pi; 9761 struct vi_info *vi; 9762 9763 if (port_id >= sc->params.nports) 9764 return (EINVAL); 9765 pi = sc->port[port_id]; 9766 if (pi == NULL) 9767 return (EIO); 9768 9769 /* MAC stats */ 9770 t4_clr_port_stats(sc, pi->tx_chan); 9771 pi->tx_parse_error = 0; 9772 pi->tnl_cong_drops = 0; 9773 mtx_lock(&sc->reg_lock); 9774 for_each_vi(pi, v, vi) { 9775 if (vi->flags & VI_INIT_DONE) 9776 t4_clr_vi_stats(sc, vi->viid); 9777 } 9778 bg_map = pi->mps_bg_map; 9779 v = 0; /* reuse */ 9780 while (bg_map) { 9781 i = ffs(bg_map) - 1; 9782 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 9783 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 9784 bg_map &= ~(1 << i); 9785 } 9786 mtx_unlock(&sc->reg_lock); 9787 9788 /* 9789 * Since this command accepts a port, clear stats for 9790 * all VIs on this port. 9791 */ 9792 for_each_vi(pi, v, vi) { 9793 if (vi->flags & VI_INIT_DONE) { 9794 struct sge_rxq *rxq; 9795 struct sge_txq *txq; 9796 struct sge_wrq *wrq; 9797 9798 for_each_rxq(vi, i, rxq) { 9799#if defined(INET) || defined(INET6) 9800 rxq->lro.lro_queued = 0; 9801 rxq->lro.lro_flushed = 0; 9802#endif 9803 rxq->rxcsum = 0; 9804 rxq->vlan_extraction = 0; 9805 } 9806 9807 for_each_txq(vi, i, txq) { 9808 txq->txcsum = 0; 9809 txq->tso_wrs = 0; 9810 txq->vlan_insertion = 0; 9811 txq->imm_wrs = 0; 9812 txq->sgl_wrs = 0; 9813 txq->txpkt_wrs = 0; 9814 txq->txpkts0_wrs = 0; 9815 txq->txpkts1_wrs = 0; 9816 txq->txpkts0_pkts = 0; 9817 txq->txpkts1_pkts = 0; 9818 mp_ring_reset_stats(txq->r); 9819 } 9820 9821#ifdef TCP_OFFLOAD 9822 /* nothing to clear for each ofld_rxq */ 9823 9824 for_each_ofld_txq(vi, i, wrq) { 9825 wrq->tx_wrs_direct = 0; 9826 wrq->tx_wrs_copied = 0; 9827 } 9828#endif 9829 9830 if (IS_MAIN_VI(vi)) { 9831 wrq = &sc->sge.ctrlq[pi->port_id]; 9832 wrq->tx_wrs_direct = 0; 9833 wrq->tx_wrs_copied = 0; 9834 } 9835 } 9836 } 9837 break; 9838 } 9839 case CHELSIO_T4_SCHED_CLASS: 9840 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 9841 break; 9842 case CHELSIO_T4_SCHED_QUEUE: 9843 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 9844 break; 9845 case CHELSIO_T4_GET_TRACER: 9846 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 9847 break; 9848 case CHELSIO_T4_SET_TRACER: 9849 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 9850 break; 9851 case CHELSIO_T4_LOAD_CFG: 9852 rc = load_cfg(sc, (struct t4_data *)data); 9853 break; 9854 case CHELSIO_T4_LOAD_BOOT: 9855 rc = load_boot(sc, (struct t4_bootrom *)data); 9856 break; 9857 case CHELSIO_T4_LOAD_BOOTCFG: 9858 rc = load_bootcfg(sc, (struct t4_data *)data); 9859 break; 9860 case CHELSIO_T4_CUDBG_DUMP: 9861 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 9862 break; 9863 case CHELSIO_T4_SET_OFLD_POLICY: 9864 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 9865 break; 9866 default: 9867 rc = ENOTTY; 9868 } 9869 9870 return (rc); 9871} 9872 9873void 9874t4_db_full(struct adapter *sc) 9875{ 9876 9877 CXGBE_UNIMPLEMENTED(__func__); 9878} 9879 9880void 9881t4_db_dropped(struct adapter *sc) 9882{ 9883 9884 CXGBE_UNIMPLEMENTED(__func__); 9885} 9886 9887#ifdef TCP_OFFLOAD 9888void 9889t4_iscsi_init(struct adapter *sc, u_int tag_mask, const u_int *pgsz_order) 9890{ 9891 9892 t4_write_reg(sc, A_ULP_RX_ISCSI_TAGMASK, tag_mask); 9893 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, V_HPZ0(pgsz_order[0]) | 9894 V_HPZ1(pgsz_order[1]) | V_HPZ2(pgsz_order[2]) | 9895 V_HPZ3(pgsz_order[3])); 9896} 9897 9898static int 9899toe_capability(struct vi_info *vi, int enable) 9900{ 9901 int rc; 9902 struct port_info *pi = vi->pi; 9903 struct adapter *sc = pi->adapter; 9904 9905 ASSERT_SYNCHRONIZED_OP(sc); 9906 9907 if (!is_offload(sc)) 9908 return (ENODEV); 9909 9910 if (enable) { 9911 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 9912 /* TOE is already enabled. */ 9913 return (0); 9914 } 9915 9916 /* 9917 * We need the port's queues around so that we're able to send 9918 * and receive CPLs to/from the TOE even if the ifnet for this 9919 * port has never been UP'd administratively. 9920 */ 9921 if (!(vi->flags & VI_INIT_DONE)) { 9922 rc = vi_full_init(vi); 9923 if (rc) 9924 return (rc); 9925 } 9926 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 9927 rc = vi_full_init(&pi->vi[0]); 9928 if (rc) 9929 return (rc); 9930 } 9931 9932 if (isset(&sc->offload_map, pi->port_id)) { 9933 /* TOE is enabled on another VI of this port. */ 9934 pi->uld_vis++; 9935 return (0); 9936 } 9937 9938 if (!uld_active(sc, ULD_TOM)) { 9939 rc = t4_activate_uld(sc, ULD_TOM); 9940 if (rc == EAGAIN) { 9941 log(LOG_WARNING, 9942 "You must kldload t4_tom.ko before trying " 9943 "to enable TOE on a cxgbe interface.\n"); 9944 } 9945 if (rc != 0) 9946 return (rc); 9947 KASSERT(sc->tom_softc != NULL, 9948 ("%s: TOM activated but softc NULL", __func__)); 9949 KASSERT(uld_active(sc, ULD_TOM), 9950 ("%s: TOM activated but flag not set", __func__)); 9951 } 9952 9953 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 9954 if (!uld_active(sc, ULD_IWARP)) 9955 (void) t4_activate_uld(sc, ULD_IWARP); 9956 if (!uld_active(sc, ULD_ISCSI)) 9957 (void) t4_activate_uld(sc, ULD_ISCSI); 9958 9959 pi->uld_vis++; 9960 setbit(&sc->offload_map, pi->port_id); 9961 } else { 9962 pi->uld_vis--; 9963 9964 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 9965 return (0); 9966 9967 KASSERT(uld_active(sc, ULD_TOM), 9968 ("%s: TOM never initialized?", __func__)); 9969 clrbit(&sc->offload_map, pi->port_id); 9970 } 9971 9972 return (0); 9973} 9974 9975/* 9976 * Add an upper layer driver to the global list. 9977 */ 9978int 9979t4_register_uld(struct uld_info *ui) 9980{ 9981 int rc = 0; 9982 struct uld_info *u; 9983 9984 sx_xlock(&t4_uld_list_lock); 9985 SLIST_FOREACH(u, &t4_uld_list, link) { 9986 if (u->uld_id == ui->uld_id) { 9987 rc = EEXIST; 9988 goto done; 9989 } 9990 } 9991 9992 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 9993 ui->refcount = 0; 9994done: 9995 sx_xunlock(&t4_uld_list_lock); 9996 return (rc); 9997} 9998 9999int 10000t4_unregister_uld(struct uld_info *ui) 10001{ 10002 int rc = EINVAL; 10003 struct uld_info *u; 10004 10005 sx_xlock(&t4_uld_list_lock); 10006 10007 SLIST_FOREACH(u, &t4_uld_list, link) { 10008 if (u == ui) { 10009 if (ui->refcount > 0) { 10010 rc = EBUSY; 10011 goto done; 10012 } 10013 10014 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 10015 rc = 0; 10016 goto done; 10017 } 10018 } 10019done: 10020 sx_xunlock(&t4_uld_list_lock); 10021 return (rc); 10022} 10023 10024int 10025t4_activate_uld(struct adapter *sc, int id) 10026{ 10027 int rc; 10028 struct uld_info *ui; 10029 10030 ASSERT_SYNCHRONIZED_OP(sc); 10031 10032 if (id < 0 || id > ULD_MAX) 10033 return (EINVAL); 10034 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 10035 10036 sx_slock(&t4_uld_list_lock); 10037 10038 SLIST_FOREACH(ui, &t4_uld_list, link) { 10039 if (ui->uld_id == id) { 10040 if (!(sc->flags & FULL_INIT_DONE)) { 10041 rc = adapter_full_init(sc); 10042 if (rc != 0) 10043 break; 10044 } 10045 10046 rc = ui->activate(sc); 10047 if (rc == 0) { 10048 setbit(&sc->active_ulds, id); 10049 ui->refcount++; 10050 } 10051 break; 10052 } 10053 } 10054 10055 sx_sunlock(&t4_uld_list_lock); 10056 10057 return (rc); 10058} 10059 10060int 10061t4_deactivate_uld(struct adapter *sc, int id) 10062{ 10063 int rc; 10064 struct uld_info *ui; 10065 10066 ASSERT_SYNCHRONIZED_OP(sc); 10067 10068 if (id < 0 || id > ULD_MAX) 10069 return (EINVAL); 10070 rc = ENXIO; 10071 10072 sx_slock(&t4_uld_list_lock); 10073 10074 SLIST_FOREACH(ui, &t4_uld_list, link) { 10075 if (ui->uld_id == id) { 10076 rc = ui->deactivate(sc); 10077 if (rc == 0) { 10078 clrbit(&sc->active_ulds, id); 10079 ui->refcount--; 10080 } 10081 break; 10082 } 10083 } 10084 10085 sx_sunlock(&t4_uld_list_lock); 10086 10087 return (rc); 10088} 10089 10090int 10091uld_active(struct adapter *sc, int uld_id) 10092{ 10093 10094 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 10095 10096 return (isset(&sc->active_ulds, uld_id)); 10097} 10098#endif 10099 10100/* 10101 * t = ptr to tunable. 10102 * nc = number of CPUs. 10103 * c = compiled in default for that tunable. 10104 */ 10105static void 10106calculate_nqueues(int *t, int nc, const int c) 10107{ 10108 int nq; 10109 10110 if (*t > 0) 10111 return; 10112 nq = *t < 0 ? -*t : c; 10113 *t = min(nc, nq); 10114} 10115 10116/* 10117 * Come up with reasonable defaults for some of the tunables, provided they're 10118 * not set by the user (in which case we'll use the values as is). 10119 */ 10120static void 10121tweak_tunables(void) 10122{ 10123 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 10124 10125 if (t4_ntxq < 1) { 10126#ifdef RSS 10127 t4_ntxq = rss_getnumbuckets(); 10128#else 10129 calculate_nqueues(&t4_ntxq, nc, NTXQ); 10130#endif 10131 } 10132 10133 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 10134 10135 if (t4_nrxq < 1) { 10136#ifdef RSS 10137 t4_nrxq = rss_getnumbuckets(); 10138#else 10139 calculate_nqueues(&t4_nrxq, nc, NRXQ); 10140#endif 10141 } 10142 10143 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 10144 10145#ifdef TCP_OFFLOAD 10146 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 10147 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 10148 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 10149 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 10150 10151 if (t4_toecaps_allowed == -1) 10152 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 10153 10154 if (t4_rdmacaps_allowed == -1) { 10155 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 10156 FW_CAPS_CONFIG_RDMA_RDMAC; 10157 } 10158 10159 if (t4_iscsicaps_allowed == -1) { 10160 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 10161 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 10162 FW_CAPS_CONFIG_ISCSI_T10DIF; 10163 } 10164 10165 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 10166 t4_tmr_idx_ofld = TMR_IDX_OFLD; 10167 10168 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 10169 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 10170#else 10171 if (t4_toecaps_allowed == -1) 10172 t4_toecaps_allowed = 0; 10173 10174 if (t4_rdmacaps_allowed == -1) 10175 t4_rdmacaps_allowed = 0; 10176 10177 if (t4_iscsicaps_allowed == -1) 10178 t4_iscsicaps_allowed = 0; 10179#endif 10180 10181#ifdef DEV_NETMAP 10182 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 10183 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 10184#endif 10185 10186 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 10187 t4_tmr_idx = TMR_IDX; 10188 10189 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 10190 t4_pktc_idx = PKTC_IDX; 10191 10192 if (t4_qsize_txq < 128) 10193 t4_qsize_txq = 128; 10194 10195 if (t4_qsize_rxq < 128) 10196 t4_qsize_rxq = 128; 10197 while (t4_qsize_rxq & 7) 10198 t4_qsize_rxq++; 10199 10200 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 10201 10202 /* 10203 * Number of VIs to create per-port. The first VI is the "main" regular 10204 * VI for the port. The rest are additional virtual interfaces on the 10205 * same physical port. Note that the main VI does not have native 10206 * netmap support but the extra VIs do. 10207 * 10208 * Limit the number of VIs per port to the number of available 10209 * MAC addresses per port. 10210 */ 10211 if (t4_num_vis < 1) 10212 t4_num_vis = 1; 10213 if (t4_num_vis > nitems(vi_mac_funcs)) { 10214 t4_num_vis = nitems(vi_mac_funcs); 10215 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 10216 } 10217 10218 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 10219 pcie_relaxed_ordering = 1; 10220#if defined(__i386__) || defined(__amd64__) 10221 if (cpu_vendor_id == CPU_VENDOR_INTEL) 10222 pcie_relaxed_ordering = 0; 10223#endif 10224 } 10225} 10226 10227#ifdef DDB 10228static void 10229t4_dump_tcb(struct adapter *sc, int tid) 10230{ 10231 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 10232 10233 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 10234 save = t4_read_reg(sc, reg); 10235 base = sc->memwin[2].mw_base; 10236 10237 /* Dump TCB for the tid */ 10238 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 10239 tcb_addr += tid * TCB_SIZE; 10240 10241 if (is_t4(sc)) { 10242 pf = 0; 10243 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 10244 } else { 10245 pf = V_PFNUM(sc->pf); 10246 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 10247 } 10248 t4_write_reg(sc, reg, win_pos | pf); 10249 t4_read_reg(sc, reg); 10250 10251 off = tcb_addr - win_pos; 10252 for (i = 0; i < 4; i++) { 10253 uint32_t buf[8]; 10254 for (j = 0; j < 8; j++, off += 4) 10255 buf[j] = htonl(t4_read_reg(sc, base + off)); 10256 10257 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 10258 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 10259 buf[7]); 10260 } 10261 10262 t4_write_reg(sc, reg, save); 10263 t4_read_reg(sc, reg); 10264} 10265 10266static void 10267t4_dump_devlog(struct adapter *sc) 10268{ 10269 struct devlog_params *dparams = &sc->params.devlog; 10270 struct fw_devlog_e e; 10271 int i, first, j, m, nentries, rc; 10272 uint64_t ftstamp = UINT64_MAX; 10273 10274 if (dparams->start == 0) { 10275 db_printf("devlog params not valid\n"); 10276 return; 10277 } 10278 10279 nentries = dparams->size / sizeof(struct fw_devlog_e); 10280 m = fwmtype_to_hwmtype(dparams->memtype); 10281 10282 /* Find the first entry. */ 10283 first = -1; 10284 for (i = 0; i < nentries && !db_pager_quit; i++) { 10285 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10286 sizeof(e), (void *)&e); 10287 if (rc != 0) 10288 break; 10289 10290 if (e.timestamp == 0) 10291 break; 10292 10293 e.timestamp = be64toh(e.timestamp); 10294 if (e.timestamp < ftstamp) { 10295 ftstamp = e.timestamp; 10296 first = i; 10297 } 10298 } 10299 10300 if (first == -1) 10301 return; 10302 10303 i = first; 10304 do { 10305 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10306 sizeof(e), (void *)&e); 10307 if (rc != 0) 10308 return; 10309 10310 if (e.timestamp == 0) 10311 return; 10312 10313 e.timestamp = be64toh(e.timestamp); 10314 e.seqno = be32toh(e.seqno); 10315 for (j = 0; j < 8; j++) 10316 e.params[j] = be32toh(e.params[j]); 10317 10318 db_printf("%10d %15ju %8s %8s ", 10319 e.seqno, e.timestamp, 10320 (e.level < nitems(devlog_level_strings) ? 10321 devlog_level_strings[e.level] : "UNKNOWN"), 10322 (e.facility < nitems(devlog_facility_strings) ? 10323 devlog_facility_strings[e.facility] : "UNKNOWN")); 10324 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 10325 e.params[3], e.params[4], e.params[5], e.params[6], 10326 e.params[7]); 10327 10328 if (++i == nentries) 10329 i = 0; 10330 } while (i != first && !db_pager_quit); 10331} 10332 10333static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 10334_DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 10335 10336DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 10337{ 10338 device_t dev; 10339 int t; 10340 bool valid; 10341 10342 valid = false; 10343 t = db_read_token(); 10344 if (t == tIDENT) { 10345 dev = device_lookup_by_name(db_tok_string); 10346 valid = true; 10347 } 10348 db_skip_to_eol(); 10349 if (!valid) { 10350 db_printf("usage: show t4 devlog <nexus>\n"); 10351 return; 10352 } 10353 10354 if (dev == NULL) { 10355 db_printf("device not found\n"); 10356 return; 10357 } 10358 10359 t4_dump_devlog(device_get_softc(dev)); 10360} 10361 10362DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 10363{ 10364 device_t dev; 10365 int radix, tid, t; 10366 bool valid; 10367 10368 valid = false; 10369 radix = db_radix; 10370 db_radix = 10; 10371 t = db_read_token(); 10372 if (t == tIDENT) { 10373 dev = device_lookup_by_name(db_tok_string); 10374 t = db_read_token(); 10375 if (t == tNUMBER) { 10376 tid = db_tok_number; 10377 valid = true; 10378 } 10379 } 10380 db_radix = radix; 10381 db_skip_to_eol(); 10382 if (!valid) { 10383 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 10384 return; 10385 } 10386 10387 if (dev == NULL) { 10388 db_printf("device not found\n"); 10389 return; 10390 } 10391 if (tid < 0) { 10392 db_printf("invalid tid\n"); 10393 return; 10394 } 10395 10396 t4_dump_tcb(device_get_softc(dev), tid); 10397} 10398#endif 10399 10400/* 10401 * Borrowed from cesa_prep_aes_key(). 10402 * 10403 * NB: The crypto engine wants the words in the decryption key in reverse 10404 * order. 10405 */ 10406void 10407t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits) 10408{ 10409 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 10410 uint32_t *dkey; 10411 int i; 10412 10413 rijndaelKeySetupEnc(ek, enc_key, kbits); 10414 dkey = dec_key; 10415 dkey += (kbits / 8) / 4; 10416 10417 switch (kbits) { 10418 case 128: 10419 for (i = 0; i < 4; i++) 10420 *--dkey = htobe32(ek[4 * 10 + i]); 10421 break; 10422 case 192: 10423 for (i = 0; i < 2; i++) 10424 *--dkey = htobe32(ek[4 * 11 + 2 + i]); 10425 for (i = 0; i < 4; i++) 10426 *--dkey = htobe32(ek[4 * 12 + i]); 10427 break; 10428 case 256: 10429 for (i = 0; i < 4; i++) 10430 *--dkey = htobe32(ek[4 * 13 + i]); 10431 for (i = 0; i < 4; i++) 10432 *--dkey = htobe32(ek[4 * 14 + i]); 10433 break; 10434 } 10435 MPASS(dkey == dec_key); 10436} 10437 10438static struct sx mlu; /* mod load unload */ 10439SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 10440 10441static int 10442mod_event(module_t mod, int cmd, void *arg) 10443{ 10444 int rc = 0; 10445 static int loaded = 0; 10446 10447 switch (cmd) { 10448 case MOD_LOAD: 10449 sx_xlock(&mlu); 10450 if (loaded++ == 0) { 10451 t4_sge_modload(); 10452 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10453 t4_filter_rpl, CPL_COOKIE_FILTER); 10454 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 10455 do_l2t_write_rpl, CPL_COOKIE_FILTER); 10456 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 10457 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 10458 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10459 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 10460 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 10461 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 10462 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 10463 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 10464 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 10465 do_smt_write_rpl); 10466 sx_init(&t4_list_lock, "T4/T5 adapters"); 10467 SLIST_INIT(&t4_list); 10468#ifdef TCP_OFFLOAD 10469 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 10470 SLIST_INIT(&t4_uld_list); 10471#endif 10472 t4_tracer_modload(); 10473 tweak_tunables(); 10474 } 10475 sx_xunlock(&mlu); 10476 break; 10477 10478 case MOD_UNLOAD: 10479 sx_xlock(&mlu); 10480 if (--loaded == 0) { 10481 int tries; 10482 10483 sx_slock(&t4_list_lock); 10484 if (!SLIST_EMPTY(&t4_list)) { 10485 rc = EBUSY; 10486 sx_sunlock(&t4_list_lock); 10487 goto done_unload; 10488 } 10489#ifdef TCP_OFFLOAD 10490 sx_slock(&t4_uld_list_lock); 10491 if (!SLIST_EMPTY(&t4_uld_list)) { 10492 rc = EBUSY; 10493 sx_sunlock(&t4_uld_list_lock); 10494 sx_sunlock(&t4_list_lock); 10495 goto done_unload; 10496 } 10497#endif 10498 tries = 0; 10499 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 10500 uprintf("%ju clusters with custom free routine " 10501 "still is use.\n", t4_sge_extfree_refs()); 10502 pause("t4unload", 2 * hz); 10503 } 10504#ifdef TCP_OFFLOAD 10505 sx_sunlock(&t4_uld_list_lock); 10506#endif 10507 sx_sunlock(&t4_list_lock); 10508 10509 if (t4_sge_extfree_refs() == 0) { 10510 t4_tracer_modunload(); 10511#ifdef TCP_OFFLOAD 10512 sx_destroy(&t4_uld_list_lock); 10513#endif 10514 sx_destroy(&t4_list_lock); 10515 t4_sge_modunload(); 10516 loaded = 0; 10517 } else { 10518 rc = EBUSY; 10519 loaded++; /* undo earlier decrement */ 10520 } 10521 } 10522done_unload: 10523 sx_xunlock(&mlu); 10524 break; 10525 } 10526 10527 return (rc); 10528} 10529 10530static devclass_t t4_devclass, t5_devclass, t6_devclass; 10531static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 10532static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 10533 10534DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 10535MODULE_VERSION(t4nex, 1); 10536MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 10537#ifdef DEV_NETMAP 10538MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 10539#endif /* DEV_NETMAP */ 10540 10541DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 10542MODULE_VERSION(t5nex, 1); 10543MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 10544#ifdef DEV_NETMAP 10545MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 10546#endif /* DEV_NETMAP */ 10547 10548DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 10549MODULE_VERSION(t6nex, 1); 10550MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 10551#ifdef DEV_NETMAP 10552MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 10553#endif /* DEV_NETMAP */ 10554 10555DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 10556MODULE_VERSION(cxgbe, 1); 10557 10558DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 10559MODULE_VERSION(cxl, 1); 10560 10561DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 10562MODULE_VERSION(cc, 1); 10563 10564DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 10565MODULE_VERSION(vcxgbe, 1); 10566 10567DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 10568MODULE_VERSION(vcxl, 1); 10569 10570DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 10571MODULE_VERSION(vcc, 1); 10572