t4_main.c revision 346876
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/11/sys/dev/cxgbe/t4_main.c 346876 2019-04-29 04:42:18Z np $"); 30 31#include "opt_ddb.h" 32#include "opt_inet.h" 33#include "opt_inet6.h" 34#include "opt_rss.h" 35 36#include <sys/param.h> 37#include <sys/conf.h> 38#include <sys/priv.h> 39#include <sys/kernel.h> 40#include <sys/bus.h> 41#include <sys/module.h> 42#include <sys/malloc.h> 43#include <sys/queue.h> 44#include <sys/taskqueue.h> 45#include <sys/pciio.h> 46#include <dev/pci/pcireg.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pci_private.h> 49#include <sys/firmware.h> 50#include <sys/sbuf.h> 51#include <sys/smp.h> 52#include <sys/socket.h> 53#include <sys/sockio.h> 54#include <sys/sysctl.h> 55#include <net/ethernet.h> 56#include <net/if.h> 57#include <net/if_types.h> 58#include <net/if_dl.h> 59#include <net/if_vlan_var.h> 60#ifdef RSS 61#include <net/rss_config.h> 62#endif 63#if defined(__i386__) || defined(__amd64__) 64#include <machine/md_var.h> 65#include <machine/cputypes.h> 66#include <vm/vm.h> 67#include <vm/pmap.h> 68#endif 69#include <crypto/rijndael/rijndael.h> 70#ifdef DDB 71#include <ddb/ddb.h> 72#include <ddb/db_lex.h> 73#endif 74 75#include "common/common.h" 76#include "common/t4_msg.h" 77#include "common/t4_regs.h" 78#include "common/t4_regs_values.h" 79#include "cudbg/cudbg.h" 80#include "t4_ioctl.h" 81#include "t4_l2t.h" 82#include "t4_mp_ring.h" 83#include "t4_if.h" 84#include "t4_smt.h" 85 86/* T4 bus driver interface */ 87static int t4_probe(device_t); 88static int t4_attach(device_t); 89static int t4_detach(device_t); 90static int t4_child_location_str(device_t, device_t, char *, size_t); 91static int t4_ready(device_t); 92static int t4_read_port_device(device_t, int, device_t *); 93static device_method_t t4_methods[] = { 94 DEVMETHOD(device_probe, t4_probe), 95 DEVMETHOD(device_attach, t4_attach), 96 DEVMETHOD(device_detach, t4_detach), 97 98 DEVMETHOD(bus_child_location_str, t4_child_location_str), 99 100 DEVMETHOD(t4_is_main_ready, t4_ready), 101 DEVMETHOD(t4_read_port_device, t4_read_port_device), 102 103 DEVMETHOD_END 104}; 105static driver_t t4_driver = { 106 "t4nex", 107 t4_methods, 108 sizeof(struct adapter) 109}; 110 111 112/* T4 port (cxgbe) interface */ 113static int cxgbe_probe(device_t); 114static int cxgbe_attach(device_t); 115static int cxgbe_detach(device_t); 116device_method_t cxgbe_methods[] = { 117 DEVMETHOD(device_probe, cxgbe_probe), 118 DEVMETHOD(device_attach, cxgbe_attach), 119 DEVMETHOD(device_detach, cxgbe_detach), 120 { 0, 0 } 121}; 122static driver_t cxgbe_driver = { 123 "cxgbe", 124 cxgbe_methods, 125 sizeof(struct port_info) 126}; 127 128/* T4 VI (vcxgbe) interface */ 129static int vcxgbe_probe(device_t); 130static int vcxgbe_attach(device_t); 131static int vcxgbe_detach(device_t); 132static device_method_t vcxgbe_methods[] = { 133 DEVMETHOD(device_probe, vcxgbe_probe), 134 DEVMETHOD(device_attach, vcxgbe_attach), 135 DEVMETHOD(device_detach, vcxgbe_detach), 136 { 0, 0 } 137}; 138static driver_t vcxgbe_driver = { 139 "vcxgbe", 140 vcxgbe_methods, 141 sizeof(struct vi_info) 142}; 143 144static d_ioctl_t t4_ioctl; 145 146static struct cdevsw t4_cdevsw = { 147 .d_version = D_VERSION, 148 .d_ioctl = t4_ioctl, 149 .d_name = "t4nex", 150}; 151 152/* T5 bus driver interface */ 153static int t5_probe(device_t); 154static device_method_t t5_methods[] = { 155 DEVMETHOD(device_probe, t5_probe), 156 DEVMETHOD(device_attach, t4_attach), 157 DEVMETHOD(device_detach, t4_detach), 158 159 DEVMETHOD(bus_child_location_str, t4_child_location_str), 160 161 DEVMETHOD(t4_is_main_ready, t4_ready), 162 DEVMETHOD(t4_read_port_device, t4_read_port_device), 163 164 DEVMETHOD_END 165}; 166static driver_t t5_driver = { 167 "t5nex", 168 t5_methods, 169 sizeof(struct adapter) 170}; 171 172 173/* T5 port (cxl) interface */ 174static driver_t cxl_driver = { 175 "cxl", 176 cxgbe_methods, 177 sizeof(struct port_info) 178}; 179 180/* T5 VI (vcxl) interface */ 181static driver_t vcxl_driver = { 182 "vcxl", 183 vcxgbe_methods, 184 sizeof(struct vi_info) 185}; 186 187/* T6 bus driver interface */ 188static int t6_probe(device_t); 189static device_method_t t6_methods[] = { 190 DEVMETHOD(device_probe, t6_probe), 191 DEVMETHOD(device_attach, t4_attach), 192 DEVMETHOD(device_detach, t4_detach), 193 194 DEVMETHOD(bus_child_location_str, t4_child_location_str), 195 196 DEVMETHOD(t4_is_main_ready, t4_ready), 197 DEVMETHOD(t4_read_port_device, t4_read_port_device), 198 199 DEVMETHOD_END 200}; 201static driver_t t6_driver = { 202 "t6nex", 203 t6_methods, 204 sizeof(struct adapter) 205}; 206 207 208/* T6 port (cc) interface */ 209static driver_t cc_driver = { 210 "cc", 211 cxgbe_methods, 212 sizeof(struct port_info) 213}; 214 215/* T6 VI (vcc) interface */ 216static driver_t vcc_driver = { 217 "vcc", 218 vcxgbe_methods, 219 sizeof(struct vi_info) 220}; 221 222/* ifnet + media interface */ 223static void cxgbe_init(void *); 224static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 225static int cxgbe_transmit(struct ifnet *, struct mbuf *); 226static void cxgbe_qflush(struct ifnet *); 227static int cxgbe_media_change(struct ifnet *); 228static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 229 230MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 231 232/* 233 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 234 * then ADAPTER_LOCK, then t4_uld_list_lock. 235 */ 236static struct sx t4_list_lock; 237SLIST_HEAD(, adapter) t4_list; 238#ifdef TCP_OFFLOAD 239static struct sx t4_uld_list_lock; 240SLIST_HEAD(, uld_info) t4_uld_list; 241#endif 242 243/* 244 * Tunables. See tweak_tunables() too. 245 * 246 * Each tunable is set to a default value here if it's known at compile-time. 247 * Otherwise it is set to -n as an indication to tweak_tunables() that it should 248 * provide a reasonable default (upto n) when the driver is loaded. 249 * 250 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 251 * T5 are under hw.cxl. 252 */ 253SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe(4) parameters"); 254SYSCTL_NODE(_hw, OID_AUTO, cxl, CTLFLAG_RD, 0, "cxgbe(4) T5+ parameters"); 255SYSCTL_NODE(_hw_cxgbe, OID_AUTO, toe, CTLFLAG_RD, 0, "cxgbe(4) TOE parameters"); 256 257/* 258 * Number of queues for tx and rx, NIC and offload. 259 */ 260#define NTXQ 16 261int t4_ntxq = -NTXQ; 262SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq, CTLFLAG_RDTUN, &t4_ntxq, 0, 263 "Number of TX queues per port"); 264TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq); /* Old name, undocumented */ 265 266#define NRXQ 8 267int t4_nrxq = -NRXQ; 268SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq, CTLFLAG_RDTUN, &t4_nrxq, 0, 269 "Number of RX queues per port"); 270TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq); /* Old name, undocumented */ 271 272#define NTXQ_VI 1 273static int t4_ntxq_vi = -NTXQ_VI; 274SYSCTL_INT(_hw_cxgbe, OID_AUTO, ntxq_vi, CTLFLAG_RDTUN, &t4_ntxq_vi, 0, 275 "Number of TX queues per VI"); 276 277#define NRXQ_VI 1 278static int t4_nrxq_vi = -NRXQ_VI; 279SYSCTL_INT(_hw_cxgbe, OID_AUTO, nrxq_vi, CTLFLAG_RDTUN, &t4_nrxq_vi, 0, 280 "Number of RX queues per VI"); 281 282static int t4_rsrv_noflowq = 0; 283SYSCTL_INT(_hw_cxgbe, OID_AUTO, rsrv_noflowq, CTLFLAG_RDTUN, &t4_rsrv_noflowq, 284 0, "Reserve TX queue 0 of each VI for non-flowid packets"); 285 286#ifdef TCP_OFFLOAD 287#define NOFLDTXQ 8 288static int t4_nofldtxq = -NOFLDTXQ; 289SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq, CTLFLAG_RDTUN, &t4_nofldtxq, 0, 290 "Number of offload TX queues per port"); 291 292#define NOFLDRXQ 2 293static int t4_nofldrxq = -NOFLDRXQ; 294SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq, CTLFLAG_RDTUN, &t4_nofldrxq, 0, 295 "Number of offload RX queues per port"); 296 297#define NOFLDTXQ_VI 1 298static int t4_nofldtxq_vi = -NOFLDTXQ_VI; 299SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldtxq_vi, CTLFLAG_RDTUN, &t4_nofldtxq_vi, 0, 300 "Number of offload TX queues per VI"); 301 302#define NOFLDRXQ_VI 1 303static int t4_nofldrxq_vi = -NOFLDRXQ_VI; 304SYSCTL_INT(_hw_cxgbe, OID_AUTO, nofldrxq_vi, CTLFLAG_RDTUN, &t4_nofldrxq_vi, 0, 305 "Number of offload RX queues per VI"); 306 307#define TMR_IDX_OFLD 1 308int t4_tmr_idx_ofld = TMR_IDX_OFLD; 309SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx_ofld, CTLFLAG_RDTUN, 310 &t4_tmr_idx_ofld, 0, "Holdoff timer index for offload queues"); 311 312#define PKTC_IDX_OFLD (-1) 313int t4_pktc_idx_ofld = PKTC_IDX_OFLD; 314SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx_ofld, CTLFLAG_RDTUN, 315 &t4_pktc_idx_ofld, 0, "holdoff packet counter index for offload queues"); 316 317/* 0 means chip/fw default, non-zero number is value in microseconds */ 318static u_long t4_toe_keepalive_idle = 0; 319SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_idle, CTLFLAG_RDTUN, 320 &t4_toe_keepalive_idle, 0, "TOE keepalive idle timer (us)"); 321 322/* 0 means chip/fw default, non-zero number is value in microseconds */ 323static u_long t4_toe_keepalive_interval = 0; 324SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, keepalive_interval, CTLFLAG_RDTUN, 325 &t4_toe_keepalive_interval, 0, "TOE keepalive interval timer (us)"); 326 327/* 0 means chip/fw default, non-zero number is # of keepalives before abort */ 328static int t4_toe_keepalive_count = 0; 329SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, keepalive_count, CTLFLAG_RDTUN, 330 &t4_toe_keepalive_count, 0, "Number of TOE keepalive probes before abort"); 331 332/* 0 means chip/fw default, non-zero number is value in microseconds */ 333static u_long t4_toe_rexmt_min = 0; 334SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_min, CTLFLAG_RDTUN, 335 &t4_toe_rexmt_min, 0, "Minimum TOE retransmit interval (us)"); 336 337/* 0 means chip/fw default, non-zero number is value in microseconds */ 338static u_long t4_toe_rexmt_max = 0; 339SYSCTL_ULONG(_hw_cxgbe_toe, OID_AUTO, rexmt_max, CTLFLAG_RDTUN, 340 &t4_toe_rexmt_max, 0, "Maximum TOE retransmit interval (us)"); 341 342/* 0 means chip/fw default, non-zero number is # of rexmt before abort */ 343static int t4_toe_rexmt_count = 0; 344SYSCTL_INT(_hw_cxgbe_toe, OID_AUTO, rexmt_count, CTLFLAG_RDTUN, 345 &t4_toe_rexmt_count, 0, "Number of TOE retransmissions before abort"); 346 347/* -1 means chip/fw default, other values are raw backoff values to use */ 348static int t4_toe_rexmt_backoff[16] = { 349 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 350}; 351SYSCTL_NODE(_hw_cxgbe_toe, OID_AUTO, rexmt_backoff, CTLFLAG_RD, 0, 352 "cxgbe(4) TOE retransmit backoff values"); 353SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 0, CTLFLAG_RDTUN, 354 &t4_toe_rexmt_backoff[0], 0, ""); 355SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 1, CTLFLAG_RDTUN, 356 &t4_toe_rexmt_backoff[1], 0, ""); 357SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 2, CTLFLAG_RDTUN, 358 &t4_toe_rexmt_backoff[2], 0, ""); 359SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 3, CTLFLAG_RDTUN, 360 &t4_toe_rexmt_backoff[3], 0, ""); 361SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 4, CTLFLAG_RDTUN, 362 &t4_toe_rexmt_backoff[4], 0, ""); 363SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 5, CTLFLAG_RDTUN, 364 &t4_toe_rexmt_backoff[5], 0, ""); 365SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 6, CTLFLAG_RDTUN, 366 &t4_toe_rexmt_backoff[6], 0, ""); 367SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 7, CTLFLAG_RDTUN, 368 &t4_toe_rexmt_backoff[7], 0, ""); 369SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 8, CTLFLAG_RDTUN, 370 &t4_toe_rexmt_backoff[8], 0, ""); 371SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 9, CTLFLAG_RDTUN, 372 &t4_toe_rexmt_backoff[9], 0, ""); 373SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 10, CTLFLAG_RDTUN, 374 &t4_toe_rexmt_backoff[10], 0, ""); 375SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 11, CTLFLAG_RDTUN, 376 &t4_toe_rexmt_backoff[11], 0, ""); 377SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 12, CTLFLAG_RDTUN, 378 &t4_toe_rexmt_backoff[12], 0, ""); 379SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 13, CTLFLAG_RDTUN, 380 &t4_toe_rexmt_backoff[13], 0, ""); 381SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 14, CTLFLAG_RDTUN, 382 &t4_toe_rexmt_backoff[14], 0, ""); 383SYSCTL_INT(_hw_cxgbe_toe_rexmt_backoff, OID_AUTO, 15, CTLFLAG_RDTUN, 384 &t4_toe_rexmt_backoff[15], 0, ""); 385#endif 386 387#ifdef DEV_NETMAP 388#define NNMTXQ_VI 2 389static int t4_nnmtxq_vi = -NNMTXQ_VI; 390SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmtxq_vi, CTLFLAG_RDTUN, &t4_nnmtxq_vi, 0, 391 "Number of netmap TX queues per VI"); 392 393#define NNMRXQ_VI 2 394static int t4_nnmrxq_vi = -NNMRXQ_VI; 395SYSCTL_INT(_hw_cxgbe, OID_AUTO, nnmrxq_vi, CTLFLAG_RDTUN, &t4_nnmrxq_vi, 0, 396 "Number of netmap RX queues per VI"); 397#endif 398 399/* 400 * Holdoff parameters for ports. 401 */ 402#define TMR_IDX 1 403int t4_tmr_idx = TMR_IDX; 404SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_timer_idx, CTLFLAG_RDTUN, &t4_tmr_idx, 405 0, "Holdoff timer index"); 406TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx); /* Old name */ 407 408#define PKTC_IDX (-1) 409int t4_pktc_idx = PKTC_IDX; 410SYSCTL_INT(_hw_cxgbe, OID_AUTO, holdoff_pktc_idx, CTLFLAG_RDTUN, &t4_pktc_idx, 411 0, "Holdoff packet counter index"); 412TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx); /* Old name */ 413 414/* 415 * Size (# of entries) of each tx and rx queue. 416 */ 417unsigned int t4_qsize_txq = TX_EQ_QSIZE; 418SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_txq, CTLFLAG_RDTUN, &t4_qsize_txq, 0, 419 "Number of descriptors in each TX queue"); 420 421unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 422SYSCTL_INT(_hw_cxgbe, OID_AUTO, qsize_rxq, CTLFLAG_RDTUN, &t4_qsize_rxq, 0, 423 "Number of descriptors in each RX queue"); 424 425/* 426 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 427 */ 428int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 429SYSCTL_INT(_hw_cxgbe, OID_AUTO, interrupt_types, CTLFLAG_RDTUN, &t4_intr_types, 430 0, "Interrupt types allowed (bit 0 = INTx, 1 = MSI, 2 = MSI-X)"); 431 432/* 433 * Configuration file. All the _CF names here are special. 434 */ 435#define DEFAULT_CF "default" 436#define BUILTIN_CF "built-in" 437#define FLASH_CF "flash" 438#define UWIRE_CF "uwire" 439#define FPGA_CF "fpga" 440static char t4_cfg_file[32] = DEFAULT_CF; 441SYSCTL_STRING(_hw_cxgbe, OID_AUTO, config_file, CTLFLAG_RDTUN, t4_cfg_file, 442 sizeof(t4_cfg_file), "Firmware configuration file"); 443 444/* 445 * PAUSE settings (bit 0, 1, 2 = rx_pause, tx_pause, pause_autoneg respectively). 446 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 447 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 448 * mark or when signalled to do so, 0 to never emit PAUSE. 449 * pause_autoneg = 1 means PAUSE will be negotiated if possible and the 450 * negotiated settings will override rx_pause/tx_pause. 451 * Otherwise rx_pause/tx_pause are applied forcibly. 452 */ 453static int t4_pause_settings = PAUSE_RX | PAUSE_TX | PAUSE_AUTONEG; 454SYSCTL_INT(_hw_cxgbe, OID_AUTO, pause_settings, CTLFLAG_RDTUN, 455 &t4_pause_settings, 0, 456 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 457 458/* 459 * Forward Error Correction settings (bit 0, 1 = RS, BASER respectively). 460 * -1 to run with the firmware default. Same as FEC_AUTO (bit 5) 461 * 0 to disable FEC. 462 */ 463static int t4_fec = -1; 464SYSCTL_INT(_hw_cxgbe, OID_AUTO, fec, CTLFLAG_RDTUN, &t4_fec, 0, 465 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 466 467/* 468 * Link autonegotiation. 469 * -1 to run with the firmware default. 470 * 0 to disable. 471 * 1 to enable. 472 */ 473static int t4_autoneg = -1; 474SYSCTL_INT(_hw_cxgbe, OID_AUTO, autoneg, CTLFLAG_RDTUN, &t4_autoneg, 0, 475 "Link autonegotiation"); 476 477/* 478 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 479 * encouraged respectively). 480 */ 481static unsigned int t4_fw_install = 1; 482SYSCTL_INT(_hw_cxgbe, OID_AUTO, fw_install, CTLFLAG_RDTUN, &t4_fw_install, 0, 483 "Firmware auto-install (0 = prohibited, 1 = allowed, 2 = encouraged)"); 484 485/* 486 * ASIC features that will be used. Disable the ones you don't want so that the 487 * chip resources aren't wasted on features that will not be used. 488 */ 489static int t4_nbmcaps_allowed = 0; 490SYSCTL_INT(_hw_cxgbe, OID_AUTO, nbmcaps_allowed, CTLFLAG_RDTUN, 491 &t4_nbmcaps_allowed, 0, "Default NBM capabilities"); 492 493static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 494SYSCTL_INT(_hw_cxgbe, OID_AUTO, linkcaps_allowed, CTLFLAG_RDTUN, 495 &t4_linkcaps_allowed, 0, "Default link capabilities"); 496 497static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 498 FW_CAPS_CONFIG_SWITCH_EGRESS; 499SYSCTL_INT(_hw_cxgbe, OID_AUTO, switchcaps_allowed, CTLFLAG_RDTUN, 500 &t4_switchcaps_allowed, 0, "Default switch capabilities"); 501 502static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC | 503 FW_CAPS_CONFIG_NIC_HASHFILTER; 504SYSCTL_INT(_hw_cxgbe, OID_AUTO, niccaps_allowed, CTLFLAG_RDTUN, 505 &t4_niccaps_allowed, 0, "Default NIC capabilities"); 506 507static int t4_toecaps_allowed = -1; 508SYSCTL_INT(_hw_cxgbe, OID_AUTO, toecaps_allowed, CTLFLAG_RDTUN, 509 &t4_toecaps_allowed, 0, "Default TCP offload capabilities"); 510 511static int t4_rdmacaps_allowed = -1; 512SYSCTL_INT(_hw_cxgbe, OID_AUTO, rdmacaps_allowed, CTLFLAG_RDTUN, 513 &t4_rdmacaps_allowed, 0, "Default RDMA capabilities"); 514 515static int t4_cryptocaps_allowed = -1; 516SYSCTL_INT(_hw_cxgbe, OID_AUTO, cryptocaps_allowed, CTLFLAG_RDTUN, 517 &t4_cryptocaps_allowed, 0, "Default crypto capabilities"); 518 519static int t4_iscsicaps_allowed = -1; 520SYSCTL_INT(_hw_cxgbe, OID_AUTO, iscsicaps_allowed, CTLFLAG_RDTUN, 521 &t4_iscsicaps_allowed, 0, "Default iSCSI capabilities"); 522 523static int t4_fcoecaps_allowed = 0; 524SYSCTL_INT(_hw_cxgbe, OID_AUTO, fcoecaps_allowed, CTLFLAG_RDTUN, 525 &t4_fcoecaps_allowed, 0, "Default FCoE capabilities"); 526 527static int t5_write_combine = 0; 528SYSCTL_INT(_hw_cxl, OID_AUTO, write_combine, CTLFLAG_RDTUN, &t5_write_combine, 529 0, "Use WC instead of UC for BAR2"); 530 531static int t4_num_vis = 1; 532SYSCTL_INT(_hw_cxgbe, OID_AUTO, num_vis, CTLFLAG_RDTUN, &t4_num_vis, 0, 533 "Number of VIs per port"); 534 535/* 536 * PCIe Relaxed Ordering. 537 * -1: driver should figure out a good value. 538 * 0: disable RO. 539 * 1: enable RO. 540 * 2: leave RO alone. 541 */ 542static int pcie_relaxed_ordering = -1; 543SYSCTL_INT(_hw_cxgbe, OID_AUTO, pcie_relaxed_ordering, CTLFLAG_RDTUN, 544 &pcie_relaxed_ordering, 0, 545 "PCIe Relaxed Ordering: 0 = disable, 1 = enable, 2 = leave alone"); 546 547static int t4_panic_on_fatal_err = 0; 548TUNABLE_INT("hw.cxgbe.panic_on_fatal_err", &t4_panic_on_fatal_err); 549 550#ifdef TCP_OFFLOAD 551/* 552 * TOE tunables. 553 */ 554static int t4_cop_managed_offloading = 0; 555TUNABLE_INT("hw.cxgbe.cop_managed_offloading", &t4_cop_managed_offloading); 556#endif 557 558/* Functions used by VIs to obtain unique MAC addresses for each VI. */ 559static int vi_mac_funcs[] = { 560 FW_VI_FUNC_ETH, 561 FW_VI_FUNC_OFLD, 562 FW_VI_FUNC_IWARP, 563 FW_VI_FUNC_OPENISCSI, 564 FW_VI_FUNC_OPENFCOE, 565 FW_VI_FUNC_FOISCSI, 566 FW_VI_FUNC_FOFCOE, 567}; 568 569struct intrs_and_queues { 570 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 571 uint16_t num_vis; /* number of VIs for each port */ 572 uint16_t nirq; /* Total # of vectors */ 573 uint16_t ntxq; /* # of NIC txq's for each port */ 574 uint16_t nrxq; /* # of NIC rxq's for each port */ 575 uint16_t nofldtxq; /* # of TOE txq's for each port */ 576 uint16_t nofldrxq; /* # of TOE rxq's for each port */ 577 578 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 579 uint16_t ntxq_vi; /* # of NIC txq's */ 580 uint16_t nrxq_vi; /* # of NIC rxq's */ 581 uint16_t nofldtxq_vi; /* # of TOE txq's */ 582 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 583 uint16_t nnmtxq_vi; /* # of netmap txq's */ 584 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 585}; 586 587static void setup_memwin(struct adapter *); 588static void position_memwin(struct adapter *, int, uint32_t); 589static int validate_mem_range(struct adapter *, uint32_t, uint32_t); 590static int fwmtype_to_hwmtype(int); 591static int validate_mt_off_len(struct adapter *, int, uint32_t, uint32_t, 592 uint32_t *); 593static int fixup_devlog_params(struct adapter *); 594static int cfg_itype_and_nqueues(struct adapter *, struct intrs_and_queues *); 595static int prep_firmware(struct adapter *); 596static int partition_resources(struct adapter *, const struct firmware *, 597 const char *); 598static int get_params__pre_init(struct adapter *); 599static int get_params__post_init(struct adapter *); 600static int set_params__post_init(struct adapter *); 601static void t4_set_desc(struct adapter *); 602static bool fixed_ifmedia(struct port_info *); 603static void build_medialist(struct port_info *); 604static void init_link_config(struct port_info *); 605static int fixup_link_config(struct port_info *); 606static int apply_link_config(struct port_info *); 607static int cxgbe_init_synchronized(struct vi_info *); 608static int cxgbe_uninit_synchronized(struct vi_info *); 609static void quiesce_txq(struct adapter *, struct sge_txq *); 610static void quiesce_wrq(struct adapter *, struct sge_wrq *); 611static void quiesce_iq(struct adapter *, struct sge_iq *); 612static void quiesce_fl(struct adapter *, struct sge_fl *); 613static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 614 driver_intr_t *, void *, char *); 615static int t4_free_irq(struct adapter *, struct irq *); 616static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 617static void vi_refresh_stats(struct adapter *, struct vi_info *); 618static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 619static void cxgbe_tick(void *); 620static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t); 621static void cxgbe_sysctls(struct port_info *); 622static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 623static int sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS); 624static int sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS); 625static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 626static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 627static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 628static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 629static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 630static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 631static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 632static int sysctl_fec(SYSCTL_HANDLER_ARGS); 633static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 634static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 635static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 636static int sysctl_loadavg(SYSCTL_HANDLER_ARGS); 637static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 638static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 639static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 640static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS); 641static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 642static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 643static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 644static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 645static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 646static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 647static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 648static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 649static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 650static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 651static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 652static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 653static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 654static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 655static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 656static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 657static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 658static int sysctl_tids(SYSCTL_HANDLER_ARGS); 659static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 660static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 661static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 662static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 663static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 664static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 665static int sysctl_cpus(SYSCTL_HANDLER_ARGS); 666#ifdef TCP_OFFLOAD 667static int sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS); 668static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 669static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 670static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 671static int sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS); 672static int sysctl_tp_backoff(SYSCTL_HANDLER_ARGS); 673static int sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS); 674static int sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS); 675#endif 676static int get_sge_context(struct adapter *, struct t4_sge_context *); 677static int load_fw(struct adapter *, struct t4_data *); 678static int load_cfg(struct adapter *, struct t4_data *); 679static int load_boot(struct adapter *, struct t4_bootrom *); 680static int load_bootcfg(struct adapter *, struct t4_data *); 681static int cudbg_dump(struct adapter *, struct t4_cudbg_dump *); 682static void free_offload_policy(struct t4_offload_policy *); 683static int set_offload_policy(struct adapter *, struct t4_offload_policy *); 684static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 685static int read_i2c(struct adapter *, struct t4_i2c_data *); 686#ifdef TCP_OFFLOAD 687static int toe_capability(struct vi_info *, int); 688#endif 689static int mod_event(module_t, int, void *); 690static int notify_siblings(device_t, int); 691 692struct { 693 uint16_t device; 694 char *desc; 695} t4_pciids[] = { 696 {0xa000, "Chelsio Terminator 4 FPGA"}, 697 {0x4400, "Chelsio T440-dbg"}, 698 {0x4401, "Chelsio T420-CR"}, 699 {0x4402, "Chelsio T422-CR"}, 700 {0x4403, "Chelsio T440-CR"}, 701 {0x4404, "Chelsio T420-BCH"}, 702 {0x4405, "Chelsio T440-BCH"}, 703 {0x4406, "Chelsio T440-CH"}, 704 {0x4407, "Chelsio T420-SO"}, 705 {0x4408, "Chelsio T420-CX"}, 706 {0x4409, "Chelsio T420-BT"}, 707 {0x440a, "Chelsio T404-BT"}, 708 {0x440e, "Chelsio T440-LP-CR"}, 709}, t5_pciids[] = { 710 {0xb000, "Chelsio Terminator 5 FPGA"}, 711 {0x5400, "Chelsio T580-dbg"}, 712 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 713 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 714 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 715 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 716 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 717 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 718 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 719 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 720 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 721 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 722 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 723 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 724 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 725 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */ 726 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */ 727 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */ 728 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */ 729 730 /* Custom */ 731 {0x5483, "Custom T540-CR"}, 732 {0x5484, "Custom T540-BT"}, 733}, t6_pciids[] = { 734 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 735 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */ 736 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 737 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 738 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */ 739 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */ 740 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */ 741 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */ 742 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 743 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 744 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */ 745 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 746 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */ 747 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */ 748 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */ 749 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */ 750 751 /* Custom */ 752 {0x6480, "Custom T6225-CR"}, 753 {0x6481, "Custom T62100-CR"}, 754 {0x6482, "Custom T6225-CR"}, 755 {0x6483, "Custom T62100-CR"}, 756 {0x6484, "Custom T64100-CR"}, 757 {0x6485, "Custom T6240-SO"}, 758 {0x6486, "Custom T6225-SO-CR"}, 759 {0x6487, "Custom T6225-CR"}, 760}; 761 762#ifdef TCP_OFFLOAD 763/* 764 * service_iq_fl() has an iq and needs the fl. Offset of fl from the iq should 765 * be exactly the same for both rxq and ofld_rxq. 766 */ 767CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 768CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 769#endif 770CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 771 772static int 773t4_probe(device_t dev) 774{ 775 int i; 776 uint16_t v = pci_get_vendor(dev); 777 uint16_t d = pci_get_device(dev); 778 uint8_t f = pci_get_function(dev); 779 780 if (v != PCI_VENDOR_ID_CHELSIO) 781 return (ENXIO); 782 783 /* Attach only to PF0 of the FPGA */ 784 if (d == 0xa000 && f != 0) 785 return (ENXIO); 786 787 for (i = 0; i < nitems(t4_pciids); i++) { 788 if (d == t4_pciids[i].device) { 789 device_set_desc(dev, t4_pciids[i].desc); 790 return (BUS_PROBE_DEFAULT); 791 } 792 } 793 794 return (ENXIO); 795} 796 797static int 798t5_probe(device_t dev) 799{ 800 int i; 801 uint16_t v = pci_get_vendor(dev); 802 uint16_t d = pci_get_device(dev); 803 uint8_t f = pci_get_function(dev); 804 805 if (v != PCI_VENDOR_ID_CHELSIO) 806 return (ENXIO); 807 808 /* Attach only to PF0 of the FPGA */ 809 if (d == 0xb000 && f != 0) 810 return (ENXIO); 811 812 for (i = 0; i < nitems(t5_pciids); i++) { 813 if (d == t5_pciids[i].device) { 814 device_set_desc(dev, t5_pciids[i].desc); 815 return (BUS_PROBE_DEFAULT); 816 } 817 } 818 819 return (ENXIO); 820} 821 822static int 823t6_probe(device_t dev) 824{ 825 int i; 826 uint16_t v = pci_get_vendor(dev); 827 uint16_t d = pci_get_device(dev); 828 829 if (v != PCI_VENDOR_ID_CHELSIO) 830 return (ENXIO); 831 832 for (i = 0; i < nitems(t6_pciids); i++) { 833 if (d == t6_pciids[i].device) { 834 device_set_desc(dev, t6_pciids[i].desc); 835 return (BUS_PROBE_DEFAULT); 836 } 837 } 838 839 return (ENXIO); 840} 841 842static void 843t5_attribute_workaround(device_t dev) 844{ 845 device_t root_port; 846 uint32_t v; 847 848 /* 849 * The T5 chips do not properly echo the No Snoop and Relaxed 850 * Ordering attributes when replying to a TLP from a Root 851 * Port. As a workaround, find the parent Root Port and 852 * disable No Snoop and Relaxed Ordering. Note that this 853 * affects all devices under this root port. 854 */ 855 root_port = pci_find_pcie_root_port(dev); 856 if (root_port == NULL) { 857 device_printf(dev, "Unable to find parent root port\n"); 858 return; 859 } 860 861 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 862 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 863 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 864 0) 865 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 866 device_get_nameunit(root_port)); 867} 868 869static const struct devnames devnames[] = { 870 { 871 .nexus_name = "t4nex", 872 .ifnet_name = "cxgbe", 873 .vi_ifnet_name = "vcxgbe", 874 .pf03_drv_name = "t4iov", 875 .vf_nexus_name = "t4vf", 876 .vf_ifnet_name = "cxgbev" 877 }, { 878 .nexus_name = "t5nex", 879 .ifnet_name = "cxl", 880 .vi_ifnet_name = "vcxl", 881 .pf03_drv_name = "t5iov", 882 .vf_nexus_name = "t5vf", 883 .vf_ifnet_name = "cxlv" 884 }, { 885 .nexus_name = "t6nex", 886 .ifnet_name = "cc", 887 .vi_ifnet_name = "vcc", 888 .pf03_drv_name = "t6iov", 889 .vf_nexus_name = "t6vf", 890 .vf_ifnet_name = "ccv" 891 } 892}; 893 894void 895t4_init_devnames(struct adapter *sc) 896{ 897 int id; 898 899 id = chip_id(sc); 900 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 901 sc->names = &devnames[id - CHELSIO_T4]; 902 else { 903 device_printf(sc->dev, "chip id %d is not supported.\n", id); 904 sc->names = NULL; 905 } 906} 907 908static int 909t4_ifnet_unit(struct adapter *sc, struct port_info *pi) 910{ 911 const char *parent, *name; 912 long value; 913 int line, unit; 914 915 line = 0; 916 parent = device_get_nameunit(sc->dev); 917 name = sc->names->ifnet_name; 918 while (resource_find_dev(&line, name, &unit, "at", parent) == 0) { 919 if (resource_long_value(name, unit, "port", &value) == 0 && 920 value == pi->port_id) 921 return (unit); 922 } 923 return (-1); 924} 925 926static int 927t4_attach(device_t dev) 928{ 929 struct adapter *sc; 930 int rc = 0, i, j, rqidx, tqidx, nports; 931 struct make_dev_args mda; 932 struct intrs_and_queues iaq; 933 struct sge *s; 934 uint32_t *buf; 935#ifdef TCP_OFFLOAD 936 int ofld_rqidx, ofld_tqidx; 937#endif 938#ifdef DEV_NETMAP 939 int nm_rqidx, nm_tqidx; 940#endif 941 int num_vis; 942 943 sc = device_get_softc(dev); 944 sc->dev = dev; 945 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 946 947 if ((pci_get_device(dev) & 0xff00) == 0x5400) 948 t5_attribute_workaround(dev); 949 pci_enable_busmaster(dev); 950 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 951 uint32_t v; 952 953 pci_set_max_read_req(dev, 4096); 954 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 955 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 956 if (pcie_relaxed_ordering == 0 && 957 (v | PCIEM_CTL_RELAXED_ORD_ENABLE) != 0) { 958 v &= ~PCIEM_CTL_RELAXED_ORD_ENABLE; 959 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 960 } else if (pcie_relaxed_ordering == 1 && 961 (v & PCIEM_CTL_RELAXED_ORD_ENABLE) == 0) { 962 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 963 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 964 } 965 } 966 967 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 968 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 969 sc->traceq = -1; 970 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 971 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 972 device_get_nameunit(dev)); 973 974 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 975 device_get_nameunit(dev)); 976 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 977 t4_add_adapter(sc); 978 979 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 980 TAILQ_INIT(&sc->sfl); 981 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 982 983 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 984 985 sc->policy = NULL; 986 rw_init(&sc->policy_lock, "connection offload policy"); 987 988 rc = t4_map_bars_0_and_4(sc); 989 if (rc != 0) 990 goto done; /* error message displayed already */ 991 992 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 993 994 /* Prepare the adapter for operation. */ 995 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 996 rc = -t4_prep_adapter(sc, buf); 997 free(buf, M_CXGBE); 998 if (rc != 0) { 999 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 1000 goto done; 1001 } 1002 1003 /* 1004 * This is the real PF# to which we're attaching. Works from within PCI 1005 * passthrough environments too, where pci_get_function() could return a 1006 * different PF# depending on the passthrough configuration. We need to 1007 * use the real PF# in all our communication with the firmware. 1008 */ 1009 j = t4_read_reg(sc, A_PL_WHOAMI); 1010 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 1011 sc->mbox = sc->pf; 1012 1013 t4_init_devnames(sc); 1014 if (sc->names == NULL) { 1015 rc = ENOTSUP; 1016 goto done; /* error message displayed already */ 1017 } 1018 1019 /* 1020 * Do this really early, with the memory windows set up even before the 1021 * character device. The userland tool's register i/o and mem read 1022 * will work even in "recovery mode". 1023 */ 1024 setup_memwin(sc); 1025 if (t4_init_devlog_params(sc, 0) == 0) 1026 fixup_devlog_params(sc); 1027 make_dev_args_init(&mda); 1028 mda.mda_devsw = &t4_cdevsw; 1029 mda.mda_uid = UID_ROOT; 1030 mda.mda_gid = GID_WHEEL; 1031 mda.mda_mode = 0600; 1032 mda.mda_si_drv1 = sc; 1033 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 1034 if (rc != 0) 1035 device_printf(dev, "failed to create nexus char device: %d.\n", 1036 rc); 1037 1038 /* Go no further if recovery mode has been requested. */ 1039 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 1040 device_printf(dev, "recovery mode.\n"); 1041 goto done; 1042 } 1043 1044#if defined(__i386__) 1045 if ((cpu_feature & CPUID_CX8) == 0) { 1046 device_printf(dev, "64 bit atomics not available.\n"); 1047 rc = ENOTSUP; 1048 goto done; 1049 } 1050#endif 1051 1052 /* Prepare the firmware for operation */ 1053 rc = prep_firmware(sc); 1054 if (rc != 0) 1055 goto done; /* error message displayed already */ 1056 1057 rc = get_params__post_init(sc); 1058 if (rc != 0) 1059 goto done; /* error message displayed already */ 1060 1061 rc = set_params__post_init(sc); 1062 if (rc != 0) 1063 goto done; /* error message displayed already */ 1064 1065 rc = t4_map_bar_2(sc); 1066 if (rc != 0) 1067 goto done; /* error message displayed already */ 1068 1069 rc = t4_create_dma_tag(sc); 1070 if (rc != 0) 1071 goto done; /* error message displayed already */ 1072 1073 /* 1074 * First pass over all the ports - allocate VIs and initialize some 1075 * basic parameters like mac address, port type, etc. 1076 */ 1077 for_each_port(sc, i) { 1078 struct port_info *pi; 1079 1080 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 1081 sc->port[i] = pi; 1082 1083 /* These must be set before t4_port_init */ 1084 pi->adapter = sc; 1085 pi->port_id = i; 1086 /* 1087 * XXX: vi[0] is special so we can't delay this allocation until 1088 * pi->nvi's final value is known. 1089 */ 1090 pi->vi = malloc(sizeof(struct vi_info) * t4_num_vis, M_CXGBE, 1091 M_ZERO | M_WAITOK); 1092 1093 /* 1094 * Allocate the "main" VI and initialize parameters 1095 * like mac addr. 1096 */ 1097 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 1098 if (rc != 0) { 1099 device_printf(dev, "unable to initialize port %d: %d\n", 1100 i, rc); 1101 free(pi->vi, M_CXGBE); 1102 free(pi, M_CXGBE); 1103 sc->port[i] = NULL; 1104 goto done; 1105 } 1106 1107 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 1108 device_get_nameunit(dev), i); 1109 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 1110 sc->chan_map[pi->tx_chan] = i; 1111 1112 /* All VIs on this port share this media. */ 1113 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change, 1114 cxgbe_media_status); 1115 1116 PORT_LOCK(pi); 1117 init_link_config(pi); 1118 fixup_link_config(pi); 1119 build_medialist(pi); 1120 if (fixed_ifmedia(pi)) 1121 pi->flags |= FIXED_IFMEDIA; 1122 PORT_UNLOCK(pi); 1123 1124 pi->dev = device_add_child(dev, sc->names->ifnet_name, 1125 t4_ifnet_unit(sc, pi)); 1126 if (pi->dev == NULL) { 1127 device_printf(dev, 1128 "failed to add device for port %d.\n", i); 1129 rc = ENXIO; 1130 goto done; 1131 } 1132 pi->vi[0].dev = pi->dev; 1133 device_set_softc(pi->dev, pi); 1134 } 1135 1136 /* 1137 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1138 */ 1139 nports = sc->params.nports; 1140 rc = cfg_itype_and_nqueues(sc, &iaq); 1141 if (rc != 0) 1142 goto done; /* error message displayed already */ 1143 1144 num_vis = iaq.num_vis; 1145 sc->intr_type = iaq.intr_type; 1146 sc->intr_count = iaq.nirq; 1147 1148 s = &sc->sge; 1149 s->nrxq = nports * iaq.nrxq; 1150 s->ntxq = nports * iaq.ntxq; 1151 if (num_vis > 1) { 1152 s->nrxq += nports * (num_vis - 1) * iaq.nrxq_vi; 1153 s->ntxq += nports * (num_vis - 1) * iaq.ntxq_vi; 1154 } 1155 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1156 s->neq += nports; /* ctrl queues: 1 per port */ 1157 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1158#ifdef TCP_OFFLOAD 1159 if (is_offload(sc)) { 1160 s->nofldrxq = nports * iaq.nofldrxq; 1161 s->nofldtxq = nports * iaq.nofldtxq; 1162 if (num_vis > 1) { 1163 s->nofldrxq += nports * (num_vis - 1) * iaq.nofldrxq_vi; 1164 s->nofldtxq += nports * (num_vis - 1) * iaq.nofldtxq_vi; 1165 } 1166 s->neq += s->nofldtxq + s->nofldrxq; 1167 s->niq += s->nofldrxq; 1168 1169 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1170 M_CXGBE, M_ZERO | M_WAITOK); 1171 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1172 M_CXGBE, M_ZERO | M_WAITOK); 1173 } 1174#endif 1175#ifdef DEV_NETMAP 1176 if (num_vis > 1) { 1177 s->nnmrxq = nports * (num_vis - 1) * iaq.nnmrxq_vi; 1178 s->nnmtxq = nports * (num_vis - 1) * iaq.nnmtxq_vi; 1179 } 1180 s->neq += s->nnmtxq + s->nnmrxq; 1181 s->niq += s->nnmrxq; 1182 1183 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1184 M_CXGBE, M_ZERO | M_WAITOK); 1185 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1186 M_CXGBE, M_ZERO | M_WAITOK); 1187#endif 1188 1189 s->ctrlq = malloc(nports * sizeof(struct sge_wrq), M_CXGBE, 1190 M_ZERO | M_WAITOK); 1191 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1192 M_ZERO | M_WAITOK); 1193 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1194 M_ZERO | M_WAITOK); 1195 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1196 M_ZERO | M_WAITOK); 1197 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1198 M_ZERO | M_WAITOK); 1199 1200 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1201 M_ZERO | M_WAITOK); 1202 1203 t4_init_l2t(sc, M_WAITOK); 1204 t4_init_smt(sc, M_WAITOK); 1205 t4_init_tx_sched(sc); 1206 if (sc->vres.key.size != 0) 1207 sc->key_map = vmem_create("T4TLS key map", sc->vres.key.start, 1208 sc->vres.key.size, 32, 0, M_FIRSTFIT | M_WAITOK); 1209 1210 /* 1211 * Second pass over the ports. This time we know the number of rx and 1212 * tx queues that each port should get. 1213 */ 1214 rqidx = tqidx = 0; 1215#ifdef TCP_OFFLOAD 1216 ofld_rqidx = ofld_tqidx = 0; 1217#endif 1218#ifdef DEV_NETMAP 1219 nm_rqidx = nm_tqidx = 0; 1220#endif 1221 for_each_port(sc, i) { 1222 struct port_info *pi = sc->port[i]; 1223 struct vi_info *vi; 1224 1225 if (pi == NULL) 1226 continue; 1227 1228 pi->nvi = num_vis; 1229 for_each_vi(pi, j, vi) { 1230 vi->pi = pi; 1231 vi->qsize_rxq = t4_qsize_rxq; 1232 vi->qsize_txq = t4_qsize_txq; 1233 1234 vi->first_rxq = rqidx; 1235 vi->first_txq = tqidx; 1236 vi->tmr_idx = t4_tmr_idx; 1237 vi->pktc_idx = t4_pktc_idx; 1238 vi->nrxq = j == 0 ? iaq.nrxq : iaq.nrxq_vi; 1239 vi->ntxq = j == 0 ? iaq.ntxq : iaq.ntxq_vi; 1240 1241 rqidx += vi->nrxq; 1242 tqidx += vi->ntxq; 1243 1244 if (j == 0 && vi->ntxq > 1) 1245 vi->rsrv_noflowq = t4_rsrv_noflowq ? 1 : 0; 1246 else 1247 vi->rsrv_noflowq = 0; 1248 1249#ifdef TCP_OFFLOAD 1250 vi->ofld_tmr_idx = t4_tmr_idx_ofld; 1251 vi->ofld_pktc_idx = t4_pktc_idx_ofld; 1252 vi->first_ofld_rxq = ofld_rqidx; 1253 vi->first_ofld_txq = ofld_tqidx; 1254 vi->nofldrxq = j == 0 ? iaq.nofldrxq : iaq.nofldrxq_vi; 1255 vi->nofldtxq = j == 0 ? iaq.nofldtxq : iaq.nofldtxq_vi; 1256 1257 ofld_rqidx += vi->nofldrxq; 1258 ofld_tqidx += vi->nofldtxq; 1259#endif 1260#ifdef DEV_NETMAP 1261 if (j > 0) { 1262 vi->first_nm_rxq = nm_rqidx; 1263 vi->first_nm_txq = nm_tqidx; 1264 vi->nnmrxq = iaq.nnmrxq_vi; 1265 vi->nnmtxq = iaq.nnmtxq_vi; 1266 nm_rqidx += vi->nnmrxq; 1267 nm_tqidx += vi->nnmtxq; 1268 } 1269#endif 1270 } 1271 } 1272 1273 rc = t4_setup_intr_handlers(sc); 1274 if (rc != 0) { 1275 device_printf(dev, 1276 "failed to setup interrupt handlers: %d\n", rc); 1277 goto done; 1278 } 1279 1280 rc = bus_generic_probe(dev); 1281 if (rc != 0) { 1282 device_printf(dev, "failed to probe child drivers: %d\n", rc); 1283 goto done; 1284 } 1285 1286 /* 1287 * Ensure thread-safe mailbox access (in debug builds). 1288 * 1289 * So far this was the only thread accessing the mailbox but various 1290 * ifnets and sysctls are about to be created and their handlers/ioctls 1291 * will access the mailbox from different threads. 1292 */ 1293 sc->flags |= CHK_MBOX_ACCESS; 1294 1295 rc = bus_generic_attach(dev); 1296 if (rc != 0) { 1297 device_printf(dev, 1298 "failed to attach all child ports: %d\n", rc); 1299 goto done; 1300 } 1301 1302 device_printf(dev, 1303 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1304 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1305 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1306 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1307 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1308 1309 t4_set_desc(sc); 1310 1311 notify_siblings(dev, 0); 1312 1313done: 1314 if (rc != 0 && sc->cdev) { 1315 /* cdev was created and so cxgbetool works; recover that way. */ 1316 device_printf(dev, 1317 "error during attach, adapter is now in recovery mode.\n"); 1318 rc = 0; 1319 } 1320 1321 if (rc != 0) 1322 t4_detach_common(dev); 1323 else 1324 t4_sysctls(sc); 1325 1326 return (rc); 1327} 1328 1329static int 1330t4_child_location_str(device_t bus, device_t dev, char *buf, size_t buflen) 1331{ 1332 struct adapter *sc; 1333 struct port_info *pi; 1334 int i; 1335 1336 sc = device_get_softc(bus); 1337 buf[0] = '\0'; 1338 for_each_port(sc, i) { 1339 pi = sc->port[i]; 1340 if (pi != NULL && pi->dev == dev) { 1341 snprintf(buf, buflen, "port=%d", pi->port_id); 1342 break; 1343 } 1344 } 1345 return (0); 1346} 1347 1348static int 1349t4_ready(device_t dev) 1350{ 1351 struct adapter *sc; 1352 1353 sc = device_get_softc(dev); 1354 if (sc->flags & FW_OK) 1355 return (0); 1356 return (ENXIO); 1357} 1358 1359static int 1360t4_read_port_device(device_t dev, int port, device_t *child) 1361{ 1362 struct adapter *sc; 1363 struct port_info *pi; 1364 1365 sc = device_get_softc(dev); 1366 if (port < 0 || port >= MAX_NPORTS) 1367 return (EINVAL); 1368 pi = sc->port[port]; 1369 if (pi == NULL || pi->dev == NULL) 1370 return (ENXIO); 1371 *child = pi->dev; 1372 return (0); 1373} 1374 1375static int 1376notify_siblings(device_t dev, int detaching) 1377{ 1378 device_t sibling; 1379 int error, i; 1380 1381 error = 0; 1382 for (i = 0; i < PCI_FUNCMAX; i++) { 1383 if (i == pci_get_function(dev)) 1384 continue; 1385 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1386 pci_get_slot(dev), i); 1387 if (sibling == NULL || !device_is_attached(sibling)) 1388 continue; 1389 if (detaching) 1390 error = T4_DETACH_CHILD(sibling); 1391 else 1392 (void)T4_ATTACH_CHILD(sibling); 1393 if (error) 1394 break; 1395 } 1396 return (error); 1397} 1398 1399/* 1400 * Idempotent 1401 */ 1402static int 1403t4_detach(device_t dev) 1404{ 1405 struct adapter *sc; 1406 int rc; 1407 1408 sc = device_get_softc(dev); 1409 1410 rc = notify_siblings(dev, 1); 1411 if (rc) { 1412 device_printf(dev, 1413 "failed to detach sibling devices: %d\n", rc); 1414 return (rc); 1415 } 1416 1417 return (t4_detach_common(dev)); 1418} 1419 1420int 1421t4_detach_common(device_t dev) 1422{ 1423 struct adapter *sc; 1424 struct port_info *pi; 1425 int i, rc; 1426 1427 sc = device_get_softc(dev); 1428 1429 if (sc->cdev) { 1430 destroy_dev(sc->cdev); 1431 sc->cdev = NULL; 1432 } 1433 1434 sc->flags &= ~CHK_MBOX_ACCESS; 1435 if (sc->flags & FULL_INIT_DONE) { 1436 if (!(sc->flags & IS_VF)) 1437 t4_intr_disable(sc); 1438 } 1439 1440 if (device_is_attached(dev)) { 1441 rc = bus_generic_detach(dev); 1442 if (rc) { 1443 device_printf(dev, 1444 "failed to detach child devices: %d\n", rc); 1445 return (rc); 1446 } 1447 } 1448 1449 for (i = 0; i < sc->intr_count; i++) 1450 t4_free_irq(sc, &sc->irq[i]); 1451 1452 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1453 t4_free_tx_sched(sc); 1454 1455 for (i = 0; i < MAX_NPORTS; i++) { 1456 pi = sc->port[i]; 1457 if (pi) { 1458 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1459 if (pi->dev) 1460 device_delete_child(dev, pi->dev); 1461 1462 mtx_destroy(&pi->pi_lock); 1463 free(pi->vi, M_CXGBE); 1464 free(pi, M_CXGBE); 1465 } 1466 } 1467 1468 device_delete_children(dev); 1469 1470 if (sc->flags & FULL_INIT_DONE) 1471 adapter_full_uninit(sc); 1472 1473 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1474 t4_fw_bye(sc, sc->mbox); 1475 1476 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1477 pci_release_msi(dev); 1478 1479 if (sc->regs_res) 1480 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1481 sc->regs_res); 1482 1483 if (sc->udbs_res) 1484 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1485 sc->udbs_res); 1486 1487 if (sc->msix_res) 1488 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1489 sc->msix_res); 1490 1491 if (sc->l2t) 1492 t4_free_l2t(sc->l2t); 1493 if (sc->key_map) 1494 vmem_destroy(sc->key_map); 1495 if (sc->smt) 1496 t4_free_smt(sc->smt); 1497 1498#ifdef TCP_OFFLOAD 1499 free(sc->sge.ofld_rxq, M_CXGBE); 1500 free(sc->sge.ofld_txq, M_CXGBE); 1501#endif 1502#ifdef DEV_NETMAP 1503 free(sc->sge.nm_rxq, M_CXGBE); 1504 free(sc->sge.nm_txq, M_CXGBE); 1505#endif 1506 free(sc->irq, M_CXGBE); 1507 free(sc->sge.rxq, M_CXGBE); 1508 free(sc->sge.txq, M_CXGBE); 1509 free(sc->sge.ctrlq, M_CXGBE); 1510 free(sc->sge.iqmap, M_CXGBE); 1511 free(sc->sge.eqmap, M_CXGBE); 1512 free(sc->tids.ftid_tab, M_CXGBE); 1513 free(sc->tids.hpftid_tab, M_CXGBE); 1514 if (sc->tids.hftid_tab) 1515 free_hftid_tab(&sc->tids); 1516 free(sc->tids.atid_tab, M_CXGBE); 1517 free(sc->tids.tid_tab, M_CXGBE); 1518 free(sc->tt.tls_rx_ports, M_CXGBE); 1519 t4_destroy_dma_tag(sc); 1520 if (mtx_initialized(&sc->sc_lock)) { 1521 sx_xlock(&t4_list_lock); 1522 SLIST_REMOVE(&t4_list, sc, adapter, link); 1523 sx_xunlock(&t4_list_lock); 1524 mtx_destroy(&sc->sc_lock); 1525 } 1526 1527 callout_drain(&sc->sfl_callout); 1528 if (mtx_initialized(&sc->tids.ftid_lock)) { 1529 mtx_destroy(&sc->tids.ftid_lock); 1530 cv_destroy(&sc->tids.ftid_cv); 1531 } 1532 if (mtx_initialized(&sc->tids.atid_lock)) 1533 mtx_destroy(&sc->tids.atid_lock); 1534 if (mtx_initialized(&sc->sfl_lock)) 1535 mtx_destroy(&sc->sfl_lock); 1536 if (mtx_initialized(&sc->ifp_lock)) 1537 mtx_destroy(&sc->ifp_lock); 1538 if (mtx_initialized(&sc->reg_lock)) 1539 mtx_destroy(&sc->reg_lock); 1540 1541 if (rw_initialized(&sc->policy_lock)) { 1542 rw_destroy(&sc->policy_lock); 1543#ifdef TCP_OFFLOAD 1544 if (sc->policy != NULL) 1545 free_offload_policy(sc->policy); 1546#endif 1547 } 1548 1549 for (i = 0; i < NUM_MEMWIN; i++) { 1550 struct memwin *mw = &sc->memwin[i]; 1551 1552 if (rw_initialized(&mw->mw_lock)) 1553 rw_destroy(&mw->mw_lock); 1554 } 1555 1556 bzero(sc, sizeof(*sc)); 1557 1558 return (0); 1559} 1560 1561static int 1562cxgbe_probe(device_t dev) 1563{ 1564 char buf[128]; 1565 struct port_info *pi = device_get_softc(dev); 1566 1567 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1568 device_set_desc_copy(dev, buf); 1569 1570 return (BUS_PROBE_DEFAULT); 1571} 1572 1573#define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1574 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1575 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS) 1576#define T4_CAP_ENABLE (T4_CAP) 1577 1578static int 1579cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1580{ 1581 struct ifnet *ifp; 1582 struct sbuf *sb; 1583 1584 vi->xact_addr_filt = -1; 1585 callout_init(&vi->tick, 1); 1586 1587 /* Allocate an ifnet and set it up */ 1588 ifp = if_alloc(IFT_ETHER); 1589 if (ifp == NULL) { 1590 device_printf(dev, "Cannot allocate ifnet\n"); 1591 return (ENOMEM); 1592 } 1593 vi->ifp = ifp; 1594 ifp->if_softc = vi; 1595 1596 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1597 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1598 1599 ifp->if_init = cxgbe_init; 1600 ifp->if_ioctl = cxgbe_ioctl; 1601 ifp->if_transmit = cxgbe_transmit; 1602 ifp->if_qflush = cxgbe_qflush; 1603 ifp->if_get_counter = cxgbe_get_counter; 1604 1605 ifp->if_capabilities = T4_CAP; 1606#ifdef TCP_OFFLOAD 1607 if (vi->nofldrxq != 0) 1608 ifp->if_capabilities |= IFCAP_TOE; 1609#endif 1610 ifp->if_capenable = T4_CAP_ENABLE; 1611 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1612 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1613 1614 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 1615 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS; 1616 ifp->if_hw_tsomaxsegsize = 65536; 1617 1618 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp, 1619 EVENTHANDLER_PRI_ANY); 1620 1621 ether_ifattach(ifp, vi->hw_addr); 1622#ifdef DEV_NETMAP 1623 if (vi->nnmrxq != 0) 1624 cxgbe_nm_attach(vi); 1625#endif 1626 sb = sbuf_new_auto(); 1627 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1628#ifdef TCP_OFFLOAD 1629 if (ifp->if_capabilities & IFCAP_TOE) 1630 sbuf_printf(sb, "; %d txq, %d rxq (TOE)", 1631 vi->nofldtxq, vi->nofldrxq); 1632#endif 1633#ifdef DEV_NETMAP 1634 if (ifp->if_capabilities & IFCAP_NETMAP) 1635 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1636 vi->nnmtxq, vi->nnmrxq); 1637#endif 1638 sbuf_finish(sb); 1639 device_printf(dev, "%s\n", sbuf_data(sb)); 1640 sbuf_delete(sb); 1641 1642 vi_sysctls(vi); 1643 1644 return (0); 1645} 1646 1647static int 1648cxgbe_attach(device_t dev) 1649{ 1650 struct port_info *pi = device_get_softc(dev); 1651 struct adapter *sc = pi->adapter; 1652 struct vi_info *vi; 1653 int i, rc; 1654 1655 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1656 1657 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1658 if (rc) 1659 return (rc); 1660 1661 for_each_vi(pi, i, vi) { 1662 if (i == 0) 1663 continue; 1664 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1665 if (vi->dev == NULL) { 1666 device_printf(dev, "failed to add VI %d\n", i); 1667 continue; 1668 } 1669 device_set_softc(vi->dev, vi); 1670 } 1671 1672 cxgbe_sysctls(pi); 1673 1674 bus_generic_attach(dev); 1675 1676 return (0); 1677} 1678 1679static void 1680cxgbe_vi_detach(struct vi_info *vi) 1681{ 1682 struct ifnet *ifp = vi->ifp; 1683 1684 ether_ifdetach(ifp); 1685 1686 if (vi->vlan_c) 1687 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c); 1688 1689 /* Let detach proceed even if these fail. */ 1690#ifdef DEV_NETMAP 1691 if (ifp->if_capabilities & IFCAP_NETMAP) 1692 cxgbe_nm_detach(vi); 1693#endif 1694 cxgbe_uninit_synchronized(vi); 1695 callout_drain(&vi->tick); 1696 vi_full_uninit(vi); 1697 1698 if_free(vi->ifp); 1699 vi->ifp = NULL; 1700} 1701 1702static int 1703cxgbe_detach(device_t dev) 1704{ 1705 struct port_info *pi = device_get_softc(dev); 1706 struct adapter *sc = pi->adapter; 1707 int rc; 1708 1709 /* Detach the extra VIs first. */ 1710 rc = bus_generic_detach(dev); 1711 if (rc) 1712 return (rc); 1713 device_delete_children(dev); 1714 1715 doom_vi(sc, &pi->vi[0]); 1716 1717 if (pi->flags & HAS_TRACEQ) { 1718 sc->traceq = -1; /* cloner should not create ifnet */ 1719 t4_tracer_port_detach(sc); 1720 } 1721 1722 cxgbe_vi_detach(&pi->vi[0]); 1723 callout_drain(&pi->tick); 1724 ifmedia_removeall(&pi->media); 1725 1726 end_synchronized_op(sc, 0); 1727 1728 return (0); 1729} 1730 1731static void 1732cxgbe_init(void *arg) 1733{ 1734 struct vi_info *vi = arg; 1735 struct adapter *sc = vi->pi->adapter; 1736 1737 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1738 return; 1739 cxgbe_init_synchronized(vi); 1740 end_synchronized_op(sc, 0); 1741} 1742 1743static int 1744cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1745{ 1746 int rc = 0, mtu, can_sleep, if_flags, if_drv_flags, vi_if_flags; 1747 struct vi_info *vi = ifp->if_softc; 1748 struct port_info *pi = vi->pi; 1749 struct adapter *sc = pi->adapter; 1750 struct ifreq *ifr = (struct ifreq *)data; 1751 uint32_t mask; 1752 1753 switch (cmd) { 1754 case SIOCSIFMTU: 1755 mtu = ifr->ifr_mtu; 1756 if (mtu < ETHERMIN || mtu > MAX_MTU) 1757 return (EINVAL); 1758 1759 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1760 if (rc) 1761 return (rc); 1762 ifp->if_mtu = mtu; 1763 if (vi->flags & VI_INIT_DONE) { 1764 t4_update_fl_bufsize(ifp); 1765 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1766 rc = update_mac_settings(ifp, XGMAC_MTU); 1767 } 1768 end_synchronized_op(sc, 0); 1769 break; 1770 1771 case SIOCSIFFLAGS: 1772 /* 1773 * Decide what to do, with the port lock held. 1774 */ 1775 PORT_LOCK(pi); 1776 if_flags = ifp->if_flags; 1777 if_drv_flags = ifp->if_drv_flags; 1778 vi_if_flags = vi->if_flags; 1779 if (if_flags & IFF_UP && if_drv_flags & IFF_DRV_RUNNING && 1780 (vi_if_flags ^ if_flags) & (IFF_PROMISC | IFF_ALLMULTI)) { 1781 can_sleep = 0; 1782 } else { 1783 can_sleep = 1; 1784 } 1785 PORT_UNLOCK(pi); 1786 1787 /* 1788 * ifp/vi flags may change here but we'll just do what our local 1789 * copy of the flags indicates and then update the driver owned 1790 * ifp/vi flags (in a synch-op and with the port lock held) to 1791 * reflect what we did. 1792 */ 1793 1794 rc = begin_synchronized_op(sc, vi, 1795 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg"); 1796 if (rc) { 1797 if_printf(ifp, "%ssleepable synch operation failed: %d." 1798 " if_flags 0x%08x, if_drv_flags 0x%08x\n", 1799 can_sleep ? "" : "non-", rc, if_flags, 1800 if_drv_flags); 1801 return (rc); 1802 } 1803 1804 if (if_flags & IFF_UP) { 1805 if (if_drv_flags & IFF_DRV_RUNNING) { 1806 if ((if_flags ^ vi_if_flags) & 1807 (IFF_PROMISC | IFF_ALLMULTI)) { 1808 MPASS(can_sleep == 0); 1809 rc = update_mac_settings(ifp, 1810 XGMAC_PROMISC | XGMAC_ALLMULTI); 1811 } 1812 } else { 1813 MPASS(can_sleep == 1); 1814 rc = cxgbe_init_synchronized(vi); 1815 } 1816 } else if (if_drv_flags & IFF_DRV_RUNNING) { 1817 MPASS(can_sleep == 1); 1818 rc = cxgbe_uninit_synchronized(vi); 1819 } 1820 PORT_LOCK(pi); 1821 vi->if_flags = if_flags; 1822 PORT_UNLOCK(pi); 1823 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD); 1824 break; 1825 1826 case SIOCADDMULTI: 1827 case SIOCDELMULTI: /* these two are called with a mutex held :-( */ 1828 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi"); 1829 if (rc) 1830 return (rc); 1831 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1832 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1833 end_synchronized_op(sc, LOCK_HELD); 1834 break; 1835 1836 case SIOCSIFCAP: 1837 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1838 if (rc) 1839 return (rc); 1840 1841 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1842 if (mask & IFCAP_TXCSUM) { 1843 ifp->if_capenable ^= IFCAP_TXCSUM; 1844 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1845 1846 if (IFCAP_TSO4 & ifp->if_capenable && 1847 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1848 ifp->if_capenable &= ~IFCAP_TSO4; 1849 if_printf(ifp, 1850 "tso4 disabled due to -txcsum.\n"); 1851 } 1852 } 1853 if (mask & IFCAP_TXCSUM_IPV6) { 1854 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1855 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1856 1857 if (IFCAP_TSO6 & ifp->if_capenable && 1858 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1859 ifp->if_capenable &= ~IFCAP_TSO6; 1860 if_printf(ifp, 1861 "tso6 disabled due to -txcsum6.\n"); 1862 } 1863 } 1864 if (mask & IFCAP_RXCSUM) 1865 ifp->if_capenable ^= IFCAP_RXCSUM; 1866 if (mask & IFCAP_RXCSUM_IPV6) 1867 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1868 1869 /* 1870 * Note that we leave CSUM_TSO alone (it is always set). The 1871 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1872 * sending a TSO request our way, so it's sufficient to toggle 1873 * IFCAP_TSOx only. 1874 */ 1875 if (mask & IFCAP_TSO4) { 1876 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1877 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1878 if_printf(ifp, "enable txcsum first.\n"); 1879 rc = EAGAIN; 1880 goto fail; 1881 } 1882 ifp->if_capenable ^= IFCAP_TSO4; 1883 } 1884 if (mask & IFCAP_TSO6) { 1885 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1886 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1887 if_printf(ifp, "enable txcsum6 first.\n"); 1888 rc = EAGAIN; 1889 goto fail; 1890 } 1891 ifp->if_capenable ^= IFCAP_TSO6; 1892 } 1893 if (mask & IFCAP_LRO) { 1894#if defined(INET) || defined(INET6) 1895 int i; 1896 struct sge_rxq *rxq; 1897 1898 ifp->if_capenable ^= IFCAP_LRO; 1899 for_each_rxq(vi, i, rxq) { 1900 if (ifp->if_capenable & IFCAP_LRO) 1901 rxq->iq.flags |= IQ_LRO_ENABLED; 1902 else 1903 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1904 } 1905#endif 1906 } 1907#ifdef TCP_OFFLOAD 1908 if (mask & IFCAP_TOE) { 1909 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1910 1911 rc = toe_capability(vi, enable); 1912 if (rc != 0) 1913 goto fail; 1914 1915 ifp->if_capenable ^= mask; 1916 } 1917#endif 1918 if (mask & IFCAP_VLAN_HWTAGGING) { 1919 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1920 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1921 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1922 } 1923 if (mask & IFCAP_VLAN_MTU) { 1924 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1925 1926 /* Need to find out how to disable auto-mtu-inflation */ 1927 } 1928 if (mask & IFCAP_VLAN_HWTSO) 1929 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1930 if (mask & IFCAP_VLAN_HWCSUM) 1931 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1932 1933#ifdef VLAN_CAPABILITIES 1934 VLAN_CAPABILITIES(ifp); 1935#endif 1936fail: 1937 end_synchronized_op(sc, 0); 1938 break; 1939 1940 case SIOCSIFMEDIA: 1941 case SIOCGIFMEDIA: 1942 case SIOCGIFXMEDIA: 1943 ifmedia_ioctl(ifp, ifr, &pi->media, cmd); 1944 break; 1945 1946 case SIOCGI2C: { 1947 struct ifi2creq i2c; 1948 1949 rc = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c)); 1950 if (rc != 0) 1951 break; 1952 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 1953 rc = EPERM; 1954 break; 1955 } 1956 if (i2c.len > sizeof(i2c.data)) { 1957 rc = EINVAL; 1958 break; 1959 } 1960 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 1961 if (rc) 1962 return (rc); 1963 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr, 1964 i2c.offset, i2c.len, &i2c.data[0]); 1965 end_synchronized_op(sc, 0); 1966 if (rc == 0) 1967 rc = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c)); 1968 break; 1969 } 1970 1971 default: 1972 rc = ether_ioctl(ifp, cmd, data); 1973 } 1974 1975 return (rc); 1976} 1977 1978static int 1979cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 1980{ 1981 struct vi_info *vi = ifp->if_softc; 1982 struct port_info *pi = vi->pi; 1983 struct adapter *sc = pi->adapter; 1984 struct sge_txq *txq; 1985 void *items[1]; 1986 int rc; 1987 1988 M_ASSERTPKTHDR(m); 1989 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 1990 1991 if (__predict_false(pi->link_cfg.link_ok == false)) { 1992 m_freem(m); 1993 return (ENETDOWN); 1994 } 1995 1996 rc = parse_pkt(sc, &m); 1997 if (__predict_false(rc != 0)) { 1998 MPASS(m == NULL); /* was freed already */ 1999 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 2000 return (rc); 2001 } 2002 2003 /* Select a txq. */ 2004 txq = &sc->sge.txq[vi->first_txq]; 2005 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2006 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 2007 vi->rsrv_noflowq); 2008 2009 items[0] = m; 2010 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 2011 if (__predict_false(rc != 0)) 2012 m_freem(m); 2013 2014 return (rc); 2015} 2016 2017static void 2018cxgbe_qflush(struct ifnet *ifp) 2019{ 2020 struct vi_info *vi = ifp->if_softc; 2021 struct sge_txq *txq; 2022 int i; 2023 2024 /* queues do not exist if !VI_INIT_DONE. */ 2025 if (vi->flags & VI_INIT_DONE) { 2026 for_each_txq(vi, i, txq) { 2027 TXQ_LOCK(txq); 2028 txq->eq.flags |= EQ_QFLUSH; 2029 TXQ_UNLOCK(txq); 2030 while (!mp_ring_is_idle(txq->r)) { 2031 mp_ring_check_drainage(txq->r, 0); 2032 pause("qflush", 1); 2033 } 2034 TXQ_LOCK(txq); 2035 txq->eq.flags &= ~EQ_QFLUSH; 2036 TXQ_UNLOCK(txq); 2037 } 2038 } 2039 if_qflush(ifp); 2040} 2041 2042static uint64_t 2043vi_get_counter(struct ifnet *ifp, ift_counter c) 2044{ 2045 struct vi_info *vi = ifp->if_softc; 2046 struct fw_vi_stats_vf *s = &vi->stats; 2047 2048 vi_refresh_stats(vi->pi->adapter, vi); 2049 2050 switch (c) { 2051 case IFCOUNTER_IPACKETS: 2052 return (s->rx_bcast_frames + s->rx_mcast_frames + 2053 s->rx_ucast_frames); 2054 case IFCOUNTER_IERRORS: 2055 return (s->rx_err_frames); 2056 case IFCOUNTER_OPACKETS: 2057 return (s->tx_bcast_frames + s->tx_mcast_frames + 2058 s->tx_ucast_frames + s->tx_offload_frames); 2059 case IFCOUNTER_OERRORS: 2060 return (s->tx_drop_frames); 2061 case IFCOUNTER_IBYTES: 2062 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 2063 s->rx_ucast_bytes); 2064 case IFCOUNTER_OBYTES: 2065 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 2066 s->tx_ucast_bytes + s->tx_offload_bytes); 2067 case IFCOUNTER_IMCASTS: 2068 return (s->rx_mcast_frames); 2069 case IFCOUNTER_OMCASTS: 2070 return (s->tx_mcast_frames); 2071 case IFCOUNTER_OQDROPS: { 2072 uint64_t drops; 2073 2074 drops = 0; 2075 if (vi->flags & VI_INIT_DONE) { 2076 int i; 2077 struct sge_txq *txq; 2078 2079 for_each_txq(vi, i, txq) 2080 drops += counter_u64_fetch(txq->r->drops); 2081 } 2082 2083 return (drops); 2084 2085 } 2086 2087 default: 2088 return (if_get_counter_default(ifp, c)); 2089 } 2090} 2091 2092uint64_t 2093cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 2094{ 2095 struct vi_info *vi = ifp->if_softc; 2096 struct port_info *pi = vi->pi; 2097 struct adapter *sc = pi->adapter; 2098 struct port_stats *s = &pi->stats; 2099 2100 if (pi->nvi > 1 || sc->flags & IS_VF) 2101 return (vi_get_counter(ifp, c)); 2102 2103 cxgbe_refresh_stats(sc, pi); 2104 2105 switch (c) { 2106 case IFCOUNTER_IPACKETS: 2107 return (s->rx_frames); 2108 2109 case IFCOUNTER_IERRORS: 2110 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 2111 s->rx_fcs_err + s->rx_len_err); 2112 2113 case IFCOUNTER_OPACKETS: 2114 return (s->tx_frames); 2115 2116 case IFCOUNTER_OERRORS: 2117 return (s->tx_error_frames); 2118 2119 case IFCOUNTER_IBYTES: 2120 return (s->rx_octets); 2121 2122 case IFCOUNTER_OBYTES: 2123 return (s->tx_octets); 2124 2125 case IFCOUNTER_IMCASTS: 2126 return (s->rx_mcast_frames); 2127 2128 case IFCOUNTER_OMCASTS: 2129 return (s->tx_mcast_frames); 2130 2131 case IFCOUNTER_IQDROPS: 2132 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 2133 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 2134 s->rx_trunc3 + pi->tnl_cong_drops); 2135 2136 case IFCOUNTER_OQDROPS: { 2137 uint64_t drops; 2138 2139 drops = s->tx_drop; 2140 if (vi->flags & VI_INIT_DONE) { 2141 int i; 2142 struct sge_txq *txq; 2143 2144 for_each_txq(vi, i, txq) 2145 drops += counter_u64_fetch(txq->r->drops); 2146 } 2147 2148 return (drops); 2149 2150 } 2151 2152 default: 2153 return (if_get_counter_default(ifp, c)); 2154 } 2155} 2156 2157/* 2158 * The kernel picks a media from the list we had provided but we still validate 2159 * the requeste. 2160 */ 2161static int 2162cxgbe_media_change(struct ifnet *ifp) 2163{ 2164 struct vi_info *vi = ifp->if_softc; 2165 struct port_info *pi = vi->pi; 2166 struct ifmedia *ifm = &pi->media; 2167 struct link_config *lc = &pi->link_cfg; 2168 struct adapter *sc = pi->adapter; 2169 int rc; 2170 2171 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec"); 2172 if (rc != 0) 2173 return (rc); 2174 PORT_LOCK(pi); 2175 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 2176 /* ifconfig .. media autoselect */ 2177 if (!(lc->supported & FW_PORT_CAP32_ANEG)) { 2178 rc = ENOTSUP; /* AN not supported by transceiver */ 2179 goto done; 2180 } 2181 lc->requested_aneg = AUTONEG_ENABLE; 2182 lc->requested_speed = 0; 2183 lc->requested_fc |= PAUSE_AUTONEG; 2184 } else { 2185 lc->requested_aneg = AUTONEG_DISABLE; 2186 lc->requested_speed = 2187 ifmedia_baudrate(ifm->ifm_media) / 1000000; 2188 lc->requested_fc = 0; 2189 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE) 2190 lc->requested_fc |= PAUSE_RX; 2191 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE) 2192 lc->requested_fc |= PAUSE_TX; 2193 } 2194 if (pi->up_vis > 0) { 2195 fixup_link_config(pi); 2196 rc = apply_link_config(pi); 2197 } 2198done: 2199 PORT_UNLOCK(pi); 2200 end_synchronized_op(sc, 0); 2201 return (rc); 2202} 2203 2204/* 2205 * Base media word (without ETHER, pause, link active, etc.) for the port at the 2206 * given speed. 2207 */ 2208static int 2209port_mword(struct port_info *pi, uint32_t speed) 2210{ 2211 2212 MPASS(speed & M_FW_PORT_CAP32_SPEED); 2213 MPASS(powerof2(speed)); 2214 2215 switch(pi->port_type) { 2216 case FW_PORT_TYPE_BT_SGMII: 2217 case FW_PORT_TYPE_BT_XFI: 2218 case FW_PORT_TYPE_BT_XAUI: 2219 /* BaseT */ 2220 switch (speed) { 2221 case FW_PORT_CAP32_SPEED_100M: 2222 return (IFM_100_T); 2223 case FW_PORT_CAP32_SPEED_1G: 2224 return (IFM_1000_T); 2225 case FW_PORT_CAP32_SPEED_10G: 2226 return (IFM_10G_T); 2227 } 2228 break; 2229 case FW_PORT_TYPE_KX4: 2230 if (speed == FW_PORT_CAP32_SPEED_10G) 2231 return (IFM_10G_KX4); 2232 break; 2233 case FW_PORT_TYPE_CX4: 2234 if (speed == FW_PORT_CAP32_SPEED_10G) 2235 return (IFM_10G_CX4); 2236 break; 2237 case FW_PORT_TYPE_KX: 2238 if (speed == FW_PORT_CAP32_SPEED_1G) 2239 return (IFM_1000_KX); 2240 break; 2241 case FW_PORT_TYPE_KR: 2242 case FW_PORT_TYPE_BP_AP: 2243 case FW_PORT_TYPE_BP4_AP: 2244 case FW_PORT_TYPE_BP40_BA: 2245 case FW_PORT_TYPE_KR4_100G: 2246 case FW_PORT_TYPE_KR_SFP28: 2247 case FW_PORT_TYPE_KR_XLAUI: 2248 switch (speed) { 2249 case FW_PORT_CAP32_SPEED_1G: 2250 return (IFM_1000_KX); 2251 case FW_PORT_CAP32_SPEED_10G: 2252 return (IFM_10G_KR); 2253 case FW_PORT_CAP32_SPEED_25G: 2254 return (IFM_25G_KR); 2255 case FW_PORT_CAP32_SPEED_40G: 2256 return (IFM_40G_KR4); 2257 case FW_PORT_CAP32_SPEED_50G: 2258 return (IFM_50G_KR2); 2259 case FW_PORT_CAP32_SPEED_100G: 2260 return (IFM_100G_KR4); 2261 } 2262 break; 2263 case FW_PORT_TYPE_FIBER_XFI: 2264 case FW_PORT_TYPE_FIBER_XAUI: 2265 case FW_PORT_TYPE_SFP: 2266 case FW_PORT_TYPE_QSFP_10G: 2267 case FW_PORT_TYPE_QSA: 2268 case FW_PORT_TYPE_QSFP: 2269 case FW_PORT_TYPE_CR4_QSFP: 2270 case FW_PORT_TYPE_CR_QSFP: 2271 case FW_PORT_TYPE_CR2_QSFP: 2272 case FW_PORT_TYPE_SFP28: 2273 /* Pluggable transceiver */ 2274 switch (pi->mod_type) { 2275 case FW_PORT_MOD_TYPE_LR: 2276 switch (speed) { 2277 case FW_PORT_CAP32_SPEED_1G: 2278 return (IFM_1000_LX); 2279 case FW_PORT_CAP32_SPEED_10G: 2280 return (IFM_10G_LR); 2281 case FW_PORT_CAP32_SPEED_25G: 2282 return (IFM_25G_LR); 2283 case FW_PORT_CAP32_SPEED_40G: 2284 return (IFM_40G_LR4); 2285 case FW_PORT_CAP32_SPEED_50G: 2286 return (IFM_50G_LR2); 2287 case FW_PORT_CAP32_SPEED_100G: 2288 return (IFM_100G_LR4); 2289 } 2290 break; 2291 case FW_PORT_MOD_TYPE_SR: 2292 switch (speed) { 2293 case FW_PORT_CAP32_SPEED_1G: 2294 return (IFM_1000_SX); 2295 case FW_PORT_CAP32_SPEED_10G: 2296 return (IFM_10G_SR); 2297 case FW_PORT_CAP32_SPEED_25G: 2298 return (IFM_25G_SR); 2299 case FW_PORT_CAP32_SPEED_40G: 2300 return (IFM_40G_SR4); 2301 case FW_PORT_CAP32_SPEED_50G: 2302 return (IFM_50G_SR2); 2303 case FW_PORT_CAP32_SPEED_100G: 2304 return (IFM_100G_SR4); 2305 } 2306 break; 2307 case FW_PORT_MOD_TYPE_ER: 2308 if (speed == FW_PORT_CAP32_SPEED_10G) 2309 return (IFM_10G_ER); 2310 break; 2311 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 2312 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 2313 switch (speed) { 2314 case FW_PORT_CAP32_SPEED_1G: 2315 return (IFM_1000_CX); 2316 case FW_PORT_CAP32_SPEED_10G: 2317 return (IFM_10G_TWINAX); 2318 case FW_PORT_CAP32_SPEED_25G: 2319 return (IFM_25G_CR); 2320 case FW_PORT_CAP32_SPEED_40G: 2321 return (IFM_40G_CR4); 2322 case FW_PORT_CAP32_SPEED_50G: 2323 return (IFM_50G_CR2); 2324 case FW_PORT_CAP32_SPEED_100G: 2325 return (IFM_100G_CR4); 2326 } 2327 break; 2328 case FW_PORT_MOD_TYPE_LRM: 2329 if (speed == FW_PORT_CAP32_SPEED_10G) 2330 return (IFM_10G_LRM); 2331 break; 2332 case FW_PORT_MOD_TYPE_NA: 2333 MPASS(0); /* Not pluggable? */ 2334 /* fall throough */ 2335 case FW_PORT_MOD_TYPE_ERROR: 2336 case FW_PORT_MOD_TYPE_UNKNOWN: 2337 case FW_PORT_MOD_TYPE_NOTSUPPORTED: 2338 break; 2339 case FW_PORT_MOD_TYPE_NONE: 2340 return (IFM_NONE); 2341 } 2342 break; 2343 case FW_PORT_TYPE_NONE: 2344 return (IFM_NONE); 2345 } 2346 2347 return (IFM_UNKNOWN); 2348} 2349 2350static void 2351cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 2352{ 2353 struct vi_info *vi = ifp->if_softc; 2354 struct port_info *pi = vi->pi; 2355 struct adapter *sc = pi->adapter; 2356 struct link_config *lc = &pi->link_cfg; 2357 2358 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0) 2359 return; 2360 PORT_LOCK(pi); 2361 2362 if (pi->up_vis == 0) { 2363 /* 2364 * If all the interfaces are administratively down the firmware 2365 * does not report transceiver changes. Refresh port info here 2366 * so that ifconfig displays accurate ifmedia at all times. 2367 * This is the only reason we have a synchronized op in this 2368 * function. Just PORT_LOCK would have been enough otherwise. 2369 */ 2370 t4_update_port_info(pi); 2371 build_medialist(pi); 2372 } 2373 2374 /* ifm_status */ 2375 ifmr->ifm_status = IFM_AVALID; 2376 if (lc->link_ok == false) 2377 goto done; 2378 ifmr->ifm_status |= IFM_ACTIVE; 2379 2380 /* ifm_active */ 2381 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2382 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE); 2383 if (lc->fc & PAUSE_RX) 2384 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 2385 if (lc->fc & PAUSE_TX) 2386 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 2387 ifmr->ifm_active |= port_mword(pi, speed_to_fwcap(lc->speed)); 2388done: 2389 PORT_UNLOCK(pi); 2390 end_synchronized_op(sc, 0); 2391} 2392 2393static int 2394vcxgbe_probe(device_t dev) 2395{ 2396 char buf[128]; 2397 struct vi_info *vi = device_get_softc(dev); 2398 2399 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2400 vi - vi->pi->vi); 2401 device_set_desc_copy(dev, buf); 2402 2403 return (BUS_PROBE_DEFAULT); 2404} 2405 2406static int 2407alloc_extra_vi(struct adapter *sc, struct port_info *pi, struct vi_info *vi) 2408{ 2409 int func, index, rc; 2410 uint32_t param, val; 2411 2412 ASSERT_SYNCHRONIZED_OP(sc); 2413 2414 index = vi - pi->vi; 2415 MPASS(index > 0); /* This function deals with _extra_ VIs only */ 2416 KASSERT(index < nitems(vi_mac_funcs), 2417 ("%s: VI %s doesn't have a MAC func", __func__, 2418 device_get_nameunit(vi->dev))); 2419 func = vi_mac_funcs[index]; 2420 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2421 vi->hw_addr, &vi->rss_size, func, 0); 2422 if (rc < 0) { 2423 device_printf(vi->dev, "failed to allocate virtual interface %d" 2424 "for port %d: %d\n", index, pi->port_id, -rc); 2425 return (-rc); 2426 } 2427 vi->viid = rc; 2428 if (chip_id(sc) <= CHELSIO_T5) 2429 vi->smt_idx = (rc & 0x7f) << 1; 2430 else 2431 vi->smt_idx = (rc & 0x7f); 2432 2433 if (vi->rss_size == 1) { 2434 /* 2435 * This VI didn't get a slice of the RSS table. Reduce the 2436 * number of VIs being created (hw.cxgbe.num_vis) or modify the 2437 * configuration file (nvi, rssnvi for this PF) if this is a 2438 * problem. 2439 */ 2440 device_printf(vi->dev, "RSS table not available.\n"); 2441 vi->rss_base = 0xffff; 2442 2443 return (0); 2444 } 2445 2446 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2447 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2448 V_FW_PARAMS_PARAM_YZ(vi->viid); 2449 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2450 if (rc) 2451 vi->rss_base = 0xffff; 2452 else { 2453 MPASS((val >> 16) == vi->rss_size); 2454 vi->rss_base = val & 0xffff; 2455 } 2456 2457 return (0); 2458} 2459 2460static int 2461vcxgbe_attach(device_t dev) 2462{ 2463 struct vi_info *vi; 2464 struct port_info *pi; 2465 struct adapter *sc; 2466 int rc; 2467 2468 vi = device_get_softc(dev); 2469 pi = vi->pi; 2470 sc = pi->adapter; 2471 2472 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4via"); 2473 if (rc) 2474 return (rc); 2475 rc = alloc_extra_vi(sc, pi, vi); 2476 end_synchronized_op(sc, 0); 2477 if (rc) 2478 return (rc); 2479 2480 rc = cxgbe_vi_attach(dev, vi); 2481 if (rc) { 2482 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2483 return (rc); 2484 } 2485 return (0); 2486} 2487 2488static int 2489vcxgbe_detach(device_t dev) 2490{ 2491 struct vi_info *vi; 2492 struct adapter *sc; 2493 2494 vi = device_get_softc(dev); 2495 sc = vi->pi->adapter; 2496 2497 doom_vi(sc, vi); 2498 2499 cxgbe_vi_detach(vi); 2500 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2501 2502 end_synchronized_op(sc, 0); 2503 2504 return (0); 2505} 2506 2507void 2508t4_fatal_err(struct adapter *sc) 2509{ 2510 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 2511 t4_intr_disable(sc); 2512 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n", 2513 device_get_nameunit(sc->dev)); 2514 if (t4_panic_on_fatal_err) 2515 panic("panic requested on fatal error"); 2516} 2517 2518void 2519t4_add_adapter(struct adapter *sc) 2520{ 2521 sx_xlock(&t4_list_lock); 2522 SLIST_INSERT_HEAD(&t4_list, sc, link); 2523 sx_xunlock(&t4_list_lock); 2524} 2525 2526int 2527t4_map_bars_0_and_4(struct adapter *sc) 2528{ 2529 sc->regs_rid = PCIR_BAR(0); 2530 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2531 &sc->regs_rid, RF_ACTIVE); 2532 if (sc->regs_res == NULL) { 2533 device_printf(sc->dev, "cannot map registers.\n"); 2534 return (ENXIO); 2535 } 2536 sc->bt = rman_get_bustag(sc->regs_res); 2537 sc->bh = rman_get_bushandle(sc->regs_res); 2538 sc->mmio_len = rman_get_size(sc->regs_res); 2539 setbit(&sc->doorbells, DOORBELL_KDB); 2540 2541 sc->msix_rid = PCIR_BAR(4); 2542 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2543 &sc->msix_rid, RF_ACTIVE); 2544 if (sc->msix_res == NULL) { 2545 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2546 return (ENXIO); 2547 } 2548 2549 return (0); 2550} 2551 2552int 2553t4_map_bar_2(struct adapter *sc) 2554{ 2555 2556 /* 2557 * T4: only iWARP driver uses the userspace doorbells. There is no need 2558 * to map it if RDMA is disabled. 2559 */ 2560 if (is_t4(sc) && sc->rdmacaps == 0) 2561 return (0); 2562 2563 sc->udbs_rid = PCIR_BAR(2); 2564 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2565 &sc->udbs_rid, RF_ACTIVE); 2566 if (sc->udbs_res == NULL) { 2567 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2568 return (ENXIO); 2569 } 2570 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2571 2572 if (chip_id(sc) >= CHELSIO_T5) { 2573 setbit(&sc->doorbells, DOORBELL_UDB); 2574#if defined(__i386__) || defined(__amd64__) 2575 if (t5_write_combine) { 2576 int rc, mode; 2577 2578 /* 2579 * Enable write combining on BAR2. This is the 2580 * userspace doorbell BAR and is split into 128B 2581 * (UDBS_SEG_SIZE) doorbell regions, each associated 2582 * with an egress queue. The first 64B has the doorbell 2583 * and the second 64B can be used to submit a tx work 2584 * request with an implicit doorbell. 2585 */ 2586 2587 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2588 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2589 if (rc == 0) { 2590 clrbit(&sc->doorbells, DOORBELL_UDB); 2591 setbit(&sc->doorbells, DOORBELL_WCWR); 2592 setbit(&sc->doorbells, DOORBELL_UDBWC); 2593 } else { 2594 device_printf(sc->dev, 2595 "couldn't enable write combining: %d\n", 2596 rc); 2597 } 2598 2599 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2600 t4_write_reg(sc, A_SGE_STAT_CFG, 2601 V_STATSOURCE_T5(7) | mode); 2602 } 2603#endif 2604 } 2605 sc->iwt.wc_en = isset(&sc->doorbells, DOORBELL_UDBWC) ? 1 : 0; 2606 2607 return (0); 2608} 2609 2610struct memwin_init { 2611 uint32_t base; 2612 uint32_t aperture; 2613}; 2614 2615static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2616 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2617 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2618 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2619}; 2620 2621static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2622 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2623 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2624 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2625}; 2626 2627static void 2628setup_memwin(struct adapter *sc) 2629{ 2630 const struct memwin_init *mw_init; 2631 struct memwin *mw; 2632 int i; 2633 uint32_t bar0; 2634 2635 if (is_t4(sc)) { 2636 /* 2637 * Read low 32b of bar0 indirectly via the hardware backdoor 2638 * mechanism. Works from within PCI passthrough environments 2639 * too, where rman_get_start() can return a different value. We 2640 * need to program the T4 memory window decoders with the actual 2641 * addresses that will be coming across the PCIe link. 2642 */ 2643 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2644 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2645 2646 mw_init = &t4_memwin[0]; 2647 } else { 2648 /* T5+ use the relative offset inside the PCIe BAR */ 2649 bar0 = 0; 2650 2651 mw_init = &t5_memwin[0]; 2652 } 2653 2654 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2655 rw_init(&mw->mw_lock, "memory window access"); 2656 mw->mw_base = mw_init->base; 2657 mw->mw_aperture = mw_init->aperture; 2658 mw->mw_curpos = 0; 2659 t4_write_reg(sc, 2660 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2661 (mw->mw_base + bar0) | V_BIR(0) | 2662 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2663 rw_wlock(&mw->mw_lock); 2664 position_memwin(sc, i, 0); 2665 rw_wunlock(&mw->mw_lock); 2666 } 2667 2668 /* flush */ 2669 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2670} 2671 2672/* 2673 * Positions the memory window at the given address in the card's address space. 2674 * There are some alignment requirements and the actual position may be at an 2675 * address prior to the requested address. mw->mw_curpos always has the actual 2676 * position of the window. 2677 */ 2678static void 2679position_memwin(struct adapter *sc, int idx, uint32_t addr) 2680{ 2681 struct memwin *mw; 2682 uint32_t pf; 2683 uint32_t reg; 2684 2685 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2686 mw = &sc->memwin[idx]; 2687 rw_assert(&mw->mw_lock, RA_WLOCKED); 2688 2689 if (is_t4(sc)) { 2690 pf = 0; 2691 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2692 } else { 2693 pf = V_PFNUM(sc->pf); 2694 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2695 } 2696 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2697 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2698 t4_read_reg(sc, reg); /* flush */ 2699} 2700 2701int 2702rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2703 int len, int rw) 2704{ 2705 struct memwin *mw; 2706 uint32_t mw_end, v; 2707 2708 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2709 2710 /* Memory can only be accessed in naturally aligned 4 byte units */ 2711 if (addr & 3 || len & 3 || len <= 0) 2712 return (EINVAL); 2713 2714 mw = &sc->memwin[idx]; 2715 while (len > 0) { 2716 rw_rlock(&mw->mw_lock); 2717 mw_end = mw->mw_curpos + mw->mw_aperture; 2718 if (addr >= mw_end || addr < mw->mw_curpos) { 2719 /* Will need to reposition the window */ 2720 if (!rw_try_upgrade(&mw->mw_lock)) { 2721 rw_runlock(&mw->mw_lock); 2722 rw_wlock(&mw->mw_lock); 2723 } 2724 rw_assert(&mw->mw_lock, RA_WLOCKED); 2725 position_memwin(sc, idx, addr); 2726 rw_downgrade(&mw->mw_lock); 2727 mw_end = mw->mw_curpos + mw->mw_aperture; 2728 } 2729 rw_assert(&mw->mw_lock, RA_RLOCKED); 2730 while (addr < mw_end && len > 0) { 2731 if (rw == 0) { 2732 v = t4_read_reg(sc, mw->mw_base + addr - 2733 mw->mw_curpos); 2734 *val++ = le32toh(v); 2735 } else { 2736 v = *val++; 2737 t4_write_reg(sc, mw->mw_base + addr - 2738 mw->mw_curpos, htole32(v)); 2739 } 2740 addr += 4; 2741 len -= 4; 2742 } 2743 rw_runlock(&mw->mw_lock); 2744 } 2745 2746 return (0); 2747} 2748 2749int 2750alloc_atid_tab(struct tid_info *t, int flags) 2751{ 2752 int i; 2753 2754 MPASS(t->natids > 0); 2755 MPASS(t->atid_tab == NULL); 2756 2757 t->atid_tab = malloc(t->natids * sizeof(*t->atid_tab), M_CXGBE, 2758 M_ZERO | flags); 2759 if (t->atid_tab == NULL) 2760 return (ENOMEM); 2761 mtx_init(&t->atid_lock, "atid lock", NULL, MTX_DEF); 2762 t->afree = t->atid_tab; 2763 t->atids_in_use = 0; 2764 for (i = 1; i < t->natids; i++) 2765 t->atid_tab[i - 1].next = &t->atid_tab[i]; 2766 t->atid_tab[t->natids - 1].next = NULL; 2767 2768 return (0); 2769} 2770 2771void 2772free_atid_tab(struct tid_info *t) 2773{ 2774 2775 KASSERT(t->atids_in_use == 0, 2776 ("%s: %d atids still in use.", __func__, t->atids_in_use)); 2777 2778 if (mtx_initialized(&t->atid_lock)) 2779 mtx_destroy(&t->atid_lock); 2780 free(t->atid_tab, M_CXGBE); 2781 t->atid_tab = NULL; 2782} 2783 2784int 2785alloc_atid(struct adapter *sc, void *ctx) 2786{ 2787 struct tid_info *t = &sc->tids; 2788 int atid = -1; 2789 2790 mtx_lock(&t->atid_lock); 2791 if (t->afree) { 2792 union aopen_entry *p = t->afree; 2793 2794 atid = p - t->atid_tab; 2795 MPASS(atid <= M_TID_TID); 2796 t->afree = p->next; 2797 p->data = ctx; 2798 t->atids_in_use++; 2799 } 2800 mtx_unlock(&t->atid_lock); 2801 return (atid); 2802} 2803 2804void * 2805lookup_atid(struct adapter *sc, int atid) 2806{ 2807 struct tid_info *t = &sc->tids; 2808 2809 return (t->atid_tab[atid].data); 2810} 2811 2812void 2813free_atid(struct adapter *sc, int atid) 2814{ 2815 struct tid_info *t = &sc->tids; 2816 union aopen_entry *p = &t->atid_tab[atid]; 2817 2818 mtx_lock(&t->atid_lock); 2819 p->next = t->afree; 2820 t->afree = p; 2821 t->atids_in_use--; 2822 mtx_unlock(&t->atid_lock); 2823} 2824 2825static void 2826queue_tid_release(struct adapter *sc, int tid) 2827{ 2828 2829 CXGBE_UNIMPLEMENTED("deferred tid release"); 2830} 2831 2832void 2833release_tid(struct adapter *sc, int tid, struct sge_wrq *ctrlq) 2834{ 2835 struct wrqe *wr; 2836 struct cpl_tid_release *req; 2837 2838 wr = alloc_wrqe(sizeof(*req), ctrlq); 2839 if (wr == NULL) { 2840 queue_tid_release(sc, tid); /* defer */ 2841 return; 2842 } 2843 req = wrtod(wr); 2844 2845 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid); 2846 2847 t4_wrq_tx(sc, wr); 2848} 2849 2850static int 2851t4_range_cmp(const void *a, const void *b) 2852{ 2853 return ((const struct t4_range *)a)->start - 2854 ((const struct t4_range *)b)->start; 2855} 2856 2857/* 2858 * Verify that the memory range specified by the addr/len pair is valid within 2859 * the card's address space. 2860 */ 2861static int 2862validate_mem_range(struct adapter *sc, uint32_t addr, uint32_t len) 2863{ 2864 struct t4_range mem_ranges[4], *r, *next; 2865 uint32_t em, addr_len; 2866 int i, n, remaining; 2867 2868 /* Memory can only be accessed in naturally aligned 4 byte units */ 2869 if (addr & 3 || len & 3 || len == 0) 2870 return (EINVAL); 2871 2872 /* Enabled memories */ 2873 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2874 2875 r = &mem_ranges[0]; 2876 n = 0; 2877 bzero(r, sizeof(mem_ranges)); 2878 if (em & F_EDRAM0_ENABLE) { 2879 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2880 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2881 if (r->size > 0) { 2882 r->start = G_EDRAM0_BASE(addr_len) << 20; 2883 if (addr >= r->start && 2884 addr + len <= r->start + r->size) 2885 return (0); 2886 r++; 2887 n++; 2888 } 2889 } 2890 if (em & F_EDRAM1_ENABLE) { 2891 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2892 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2893 if (r->size > 0) { 2894 r->start = G_EDRAM1_BASE(addr_len) << 20; 2895 if (addr >= r->start && 2896 addr + len <= r->start + r->size) 2897 return (0); 2898 r++; 2899 n++; 2900 } 2901 } 2902 if (em & F_EXT_MEM_ENABLE) { 2903 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2904 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2905 if (r->size > 0) { 2906 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2907 if (addr >= r->start && 2908 addr + len <= r->start + r->size) 2909 return (0); 2910 r++; 2911 n++; 2912 } 2913 } 2914 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 2915 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2916 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 2917 if (r->size > 0) { 2918 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 2919 if (addr >= r->start && 2920 addr + len <= r->start + r->size) 2921 return (0); 2922 r++; 2923 n++; 2924 } 2925 } 2926 MPASS(n <= nitems(mem_ranges)); 2927 2928 if (n > 1) { 2929 /* Sort and merge the ranges. */ 2930 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 2931 2932 /* Start from index 0 and examine the next n - 1 entries. */ 2933 r = &mem_ranges[0]; 2934 for (remaining = n - 1; remaining > 0; remaining--, r++) { 2935 2936 MPASS(r->size > 0); /* r is a valid entry. */ 2937 next = r + 1; 2938 MPASS(next->size > 0); /* and so is the next one. */ 2939 2940 while (r->start + r->size >= next->start) { 2941 /* Merge the next one into the current entry. */ 2942 r->size = max(r->start + r->size, 2943 next->start + next->size) - r->start; 2944 n--; /* One fewer entry in total. */ 2945 if (--remaining == 0) 2946 goto done; /* short circuit */ 2947 next++; 2948 } 2949 if (next != r + 1) { 2950 /* 2951 * Some entries were merged into r and next 2952 * points to the first valid entry that couldn't 2953 * be merged. 2954 */ 2955 MPASS(next->size > 0); /* must be valid */ 2956 memcpy(r + 1, next, remaining * sizeof(*r)); 2957#ifdef INVARIANTS 2958 /* 2959 * This so that the foo->size assertion in the 2960 * next iteration of the loop do the right 2961 * thing for entries that were pulled up and are 2962 * no longer valid. 2963 */ 2964 MPASS(n < nitems(mem_ranges)); 2965 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 2966 sizeof(struct t4_range)); 2967#endif 2968 } 2969 } 2970done: 2971 /* Done merging the ranges. */ 2972 MPASS(n > 0); 2973 r = &mem_ranges[0]; 2974 for (i = 0; i < n; i++, r++) { 2975 if (addr >= r->start && 2976 addr + len <= r->start + r->size) 2977 return (0); 2978 } 2979 } 2980 2981 return (EFAULT); 2982} 2983 2984static int 2985fwmtype_to_hwmtype(int mtype) 2986{ 2987 2988 switch (mtype) { 2989 case FW_MEMTYPE_EDC0: 2990 return (MEM_EDC0); 2991 case FW_MEMTYPE_EDC1: 2992 return (MEM_EDC1); 2993 case FW_MEMTYPE_EXTMEM: 2994 return (MEM_MC0); 2995 case FW_MEMTYPE_EXTMEM1: 2996 return (MEM_MC1); 2997 default: 2998 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 2999 } 3000} 3001 3002/* 3003 * Verify that the memory range specified by the memtype/offset/len pair is 3004 * valid and lies entirely within the memtype specified. The global address of 3005 * the start of the range is returned in addr. 3006 */ 3007static int 3008validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, uint32_t len, 3009 uint32_t *addr) 3010{ 3011 uint32_t em, addr_len, maddr; 3012 3013 /* Memory can only be accessed in naturally aligned 4 byte units */ 3014 if (off & 3 || len & 3 || len == 0) 3015 return (EINVAL); 3016 3017 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 3018 switch (fwmtype_to_hwmtype(mtype)) { 3019 case MEM_EDC0: 3020 if (!(em & F_EDRAM0_ENABLE)) 3021 return (EINVAL); 3022 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 3023 maddr = G_EDRAM0_BASE(addr_len) << 20; 3024 break; 3025 case MEM_EDC1: 3026 if (!(em & F_EDRAM1_ENABLE)) 3027 return (EINVAL); 3028 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 3029 maddr = G_EDRAM1_BASE(addr_len) << 20; 3030 break; 3031 case MEM_MC: 3032 if (!(em & F_EXT_MEM_ENABLE)) 3033 return (EINVAL); 3034 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 3035 maddr = G_EXT_MEM_BASE(addr_len) << 20; 3036 break; 3037 case MEM_MC1: 3038 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 3039 return (EINVAL); 3040 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 3041 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 3042 break; 3043 default: 3044 return (EINVAL); 3045 } 3046 3047 *addr = maddr + off; /* global address */ 3048 return (validate_mem_range(sc, *addr, len)); 3049} 3050 3051static int 3052fixup_devlog_params(struct adapter *sc) 3053{ 3054 struct devlog_params *dparams = &sc->params.devlog; 3055 int rc; 3056 3057 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 3058 dparams->size, &dparams->addr); 3059 3060 return (rc); 3061} 3062 3063static void 3064update_nirq(struct intrs_and_queues *iaq, int nports) 3065{ 3066 int extra = T4_EXTRA_INTR; 3067 3068 iaq->nirq = extra; 3069 iaq->nirq += nports * (iaq->nrxq + iaq->nofldrxq); 3070 iaq->nirq += nports * (iaq->num_vis - 1) * 3071 max(iaq->nrxq_vi, iaq->nnmrxq_vi); 3072 iaq->nirq += nports * (iaq->num_vis - 1) * iaq->nofldrxq_vi; 3073} 3074 3075/* 3076 * Adjust requirements to fit the number of interrupts available. 3077 */ 3078static void 3079calculate_iaq(struct adapter *sc, struct intrs_and_queues *iaq, int itype, 3080 int navail) 3081{ 3082 int old_nirq; 3083 const int nports = sc->params.nports; 3084 3085 MPASS(nports > 0); 3086 MPASS(navail > 0); 3087 3088 bzero(iaq, sizeof(*iaq)); 3089 iaq->intr_type = itype; 3090 iaq->num_vis = t4_num_vis; 3091 iaq->ntxq = t4_ntxq; 3092 iaq->ntxq_vi = t4_ntxq_vi; 3093 iaq->nrxq = t4_nrxq; 3094 iaq->nrxq_vi = t4_nrxq_vi; 3095#ifdef TCP_OFFLOAD 3096 if (is_offload(sc)) { 3097 iaq->nofldtxq = t4_nofldtxq; 3098 iaq->nofldtxq_vi = t4_nofldtxq_vi; 3099 iaq->nofldrxq = t4_nofldrxq; 3100 iaq->nofldrxq_vi = t4_nofldrxq_vi; 3101 } 3102#endif 3103#ifdef DEV_NETMAP 3104 iaq->nnmtxq_vi = t4_nnmtxq_vi; 3105 iaq->nnmrxq_vi = t4_nnmrxq_vi; 3106#endif 3107 3108 update_nirq(iaq, nports); 3109 if (iaq->nirq <= navail && 3110 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3111 /* 3112 * This is the normal case -- there are enough interrupts for 3113 * everything. 3114 */ 3115 goto done; 3116 } 3117 3118 /* 3119 * If extra VIs have been configured try reducing their count and see if 3120 * that works. 3121 */ 3122 while (iaq->num_vis > 1) { 3123 iaq->num_vis--; 3124 update_nirq(iaq, nports); 3125 if (iaq->nirq <= navail && 3126 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3127 device_printf(sc->dev, "virtual interfaces per port " 3128 "reduced to %d from %d. nrxq=%u, nofldrxq=%u, " 3129 "nrxq_vi=%u nofldrxq_vi=%u, nnmrxq_vi=%u. " 3130 "itype %d, navail %u, nirq %d.\n", 3131 iaq->num_vis, t4_num_vis, iaq->nrxq, iaq->nofldrxq, 3132 iaq->nrxq_vi, iaq->nofldrxq_vi, iaq->nnmrxq_vi, 3133 itype, navail, iaq->nirq); 3134 goto done; 3135 } 3136 } 3137 3138 /* 3139 * Extra VIs will not be created. Log a message if they were requested. 3140 */ 3141 MPASS(iaq->num_vis == 1); 3142 iaq->ntxq_vi = iaq->nrxq_vi = 0; 3143 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 3144 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 3145 if (iaq->num_vis != t4_num_vis) { 3146 device_printf(sc->dev, "extra virtual interfaces disabled. " 3147 "nrxq=%u, nofldrxq=%u, nrxq_vi=%u nofldrxq_vi=%u, " 3148 "nnmrxq_vi=%u. itype %d, navail %u, nirq %d.\n", 3149 iaq->nrxq, iaq->nofldrxq, iaq->nrxq_vi, iaq->nofldrxq_vi, 3150 iaq->nnmrxq_vi, itype, navail, iaq->nirq); 3151 } 3152 3153 /* 3154 * Keep reducing the number of NIC rx queues to the next lower power of 3155 * 2 (for even RSS distribution) and halving the TOE rx queues and see 3156 * if that works. 3157 */ 3158 do { 3159 if (iaq->nrxq > 1) { 3160 do { 3161 iaq->nrxq--; 3162 } while (!powerof2(iaq->nrxq)); 3163 } 3164 if (iaq->nofldrxq > 1) 3165 iaq->nofldrxq >>= 1; 3166 3167 old_nirq = iaq->nirq; 3168 update_nirq(iaq, nports); 3169 if (iaq->nirq <= navail && 3170 (itype != INTR_MSI || powerof2(iaq->nirq))) { 3171 device_printf(sc->dev, "running with reduced number of " 3172 "rx queues because of shortage of interrupts. " 3173 "nrxq=%u, nofldrxq=%u. " 3174 "itype %d, navail %u, nirq %d.\n", iaq->nrxq, 3175 iaq->nofldrxq, itype, navail, iaq->nirq); 3176 goto done; 3177 } 3178 } while (old_nirq != iaq->nirq); 3179 3180 /* One interrupt for everything. Ugh. */ 3181 device_printf(sc->dev, "running with minimal number of queues. " 3182 "itype %d, navail %u.\n", itype, navail); 3183 iaq->nirq = 1; 3184 MPASS(iaq->nrxq == 1); 3185 iaq->ntxq = 1; 3186 if (iaq->nofldrxq > 1) 3187 iaq->nofldtxq = 1; 3188done: 3189 MPASS(iaq->num_vis > 0); 3190 if (iaq->num_vis > 1) { 3191 MPASS(iaq->nrxq_vi > 0); 3192 MPASS(iaq->ntxq_vi > 0); 3193 } 3194 MPASS(iaq->nirq > 0); 3195 MPASS(iaq->nrxq > 0); 3196 MPASS(iaq->ntxq > 0); 3197 if (itype == INTR_MSI) { 3198 MPASS(powerof2(iaq->nirq)); 3199 } 3200} 3201 3202static int 3203cfg_itype_and_nqueues(struct adapter *sc, struct intrs_and_queues *iaq) 3204{ 3205 int rc, itype, navail, nalloc; 3206 3207 for (itype = INTR_MSIX; itype; itype >>= 1) { 3208 3209 if ((itype & t4_intr_types) == 0) 3210 continue; /* not allowed */ 3211 3212 if (itype == INTR_MSIX) 3213 navail = pci_msix_count(sc->dev); 3214 else if (itype == INTR_MSI) 3215 navail = pci_msi_count(sc->dev); 3216 else 3217 navail = 1; 3218restart: 3219 if (navail == 0) 3220 continue; 3221 3222 calculate_iaq(sc, iaq, itype, navail); 3223 nalloc = iaq->nirq; 3224 rc = 0; 3225 if (itype == INTR_MSIX) 3226 rc = pci_alloc_msix(sc->dev, &nalloc); 3227 else if (itype == INTR_MSI) 3228 rc = pci_alloc_msi(sc->dev, &nalloc); 3229 3230 if (rc == 0 && nalloc > 0) { 3231 if (nalloc == iaq->nirq) 3232 return (0); 3233 3234 /* 3235 * Didn't get the number requested. Use whatever number 3236 * the kernel is willing to allocate. 3237 */ 3238 device_printf(sc->dev, "fewer vectors than requested, " 3239 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 3240 itype, iaq->nirq, nalloc); 3241 pci_release_msi(sc->dev); 3242 navail = nalloc; 3243 goto restart; 3244 } 3245 3246 device_printf(sc->dev, 3247 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 3248 itype, rc, iaq->nirq, nalloc); 3249 } 3250 3251 device_printf(sc->dev, 3252 "failed to find a usable interrupt type. " 3253 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 3254 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 3255 3256 return (ENXIO); 3257} 3258 3259#define FW_VERSION(chip) ( \ 3260 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 3261 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 3262 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 3263 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 3264#define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 3265 3266struct fw_info { 3267 uint8_t chip; 3268 char *kld_name; 3269 char *fw_mod_name; 3270 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ 3271} fw_info[] = { 3272 { 3273 .chip = CHELSIO_T4, 3274 .kld_name = "t4fw_cfg", 3275 .fw_mod_name = "t4fw", 3276 .fw_hdr = { 3277 .chip = FW_HDR_CHIP_T4, 3278 .fw_ver = htobe32(FW_VERSION(T4)), 3279 .intfver_nic = FW_INTFVER(T4, NIC), 3280 .intfver_vnic = FW_INTFVER(T4, VNIC), 3281 .intfver_ofld = FW_INTFVER(T4, OFLD), 3282 .intfver_ri = FW_INTFVER(T4, RI), 3283 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 3284 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3285 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 3286 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3287 }, 3288 }, { 3289 .chip = CHELSIO_T5, 3290 .kld_name = "t5fw_cfg", 3291 .fw_mod_name = "t5fw", 3292 .fw_hdr = { 3293 .chip = FW_HDR_CHIP_T5, 3294 .fw_ver = htobe32(FW_VERSION(T5)), 3295 .intfver_nic = FW_INTFVER(T5, NIC), 3296 .intfver_vnic = FW_INTFVER(T5, VNIC), 3297 .intfver_ofld = FW_INTFVER(T5, OFLD), 3298 .intfver_ri = FW_INTFVER(T5, RI), 3299 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 3300 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3301 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 3302 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3303 }, 3304 }, { 3305 .chip = CHELSIO_T6, 3306 .kld_name = "t6fw_cfg", 3307 .fw_mod_name = "t6fw", 3308 .fw_hdr = { 3309 .chip = FW_HDR_CHIP_T6, 3310 .fw_ver = htobe32(FW_VERSION(T6)), 3311 .intfver_nic = FW_INTFVER(T6, NIC), 3312 .intfver_vnic = FW_INTFVER(T6, VNIC), 3313 .intfver_ofld = FW_INTFVER(T6, OFLD), 3314 .intfver_ri = FW_INTFVER(T6, RI), 3315 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3316 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3317 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3318 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3319 }, 3320 } 3321}; 3322 3323static struct fw_info * 3324find_fw_info(int chip) 3325{ 3326 int i; 3327 3328 for (i = 0; i < nitems(fw_info); i++) { 3329 if (fw_info[i].chip == chip) 3330 return (&fw_info[i]); 3331 } 3332 return (NULL); 3333} 3334 3335/* 3336 * Is the given firmware API compatible with the one the driver was compiled 3337 * with? 3338 */ 3339static int 3340fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) 3341{ 3342 3343 /* short circuit if it's the exact same firmware version */ 3344 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 3345 return (1); 3346 3347 /* 3348 * XXX: Is this too conservative? Perhaps I should limit this to the 3349 * features that are supported in the driver. 3350 */ 3351#define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 3352 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 3353 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 3354 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 3355 return (1); 3356#undef SAME_INTF 3357 3358 return (0); 3359} 3360 3361/* 3362 * The firmware in the KLD is usable, but should it be installed? This routine 3363 * explains itself in detail if it indicates the KLD firmware should be 3364 * installed. 3365 */ 3366static int 3367should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c) 3368{ 3369 const char *reason; 3370 3371 if (!card_fw_usable) { 3372 reason = "incompatible or unusable"; 3373 goto install; 3374 } 3375 3376 if (k > c) { 3377 reason = "older than the version bundled with this driver"; 3378 goto install; 3379 } 3380 3381 if (t4_fw_install == 2 && k != c) { 3382 reason = "different than the version bundled with this driver"; 3383 goto install; 3384 } 3385 3386 return (0); 3387 3388install: 3389 if (t4_fw_install == 0) { 3390 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3391 "but the driver is prohibited from installing a different " 3392 "firmware on the card.\n", 3393 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3394 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 3395 3396 return (0); 3397 } 3398 3399 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 3400 "installing firmware %u.%u.%u.%u on card.\n", 3401 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3402 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 3403 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3404 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3405 3406 return (1); 3407} 3408 3409/* 3410 * Establish contact with the firmware and determine if we are the master driver 3411 * or not, and whether we are responsible for chip initialization. 3412 */ 3413static int 3414prep_firmware(struct adapter *sc) 3415{ 3416 const struct firmware *fw = NULL, *default_cfg; 3417 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1; 3418 enum dev_state state; 3419 struct fw_info *fw_info; 3420 struct fw_hdr *card_fw; /* fw on the card */ 3421 const struct fw_hdr *kld_fw; /* fw in the KLD */ 3422 const struct fw_hdr *drv_fw; /* fw header the driver was compiled 3423 against */ 3424 3425 /* This is the firmware whose headers the driver was compiled against */ 3426 fw_info = find_fw_info(chip_id(sc)); 3427 if (fw_info == NULL) { 3428 device_printf(sc->dev, 3429 "unable to look up firmware information for chip %d.\n", 3430 chip_id(sc)); 3431 return (EINVAL); 3432 } 3433 drv_fw = &fw_info->fw_hdr; 3434 3435 /* 3436 * The firmware KLD contains many modules. The KLD name is also the 3437 * name of the module that contains the default config file. 3438 */ 3439 default_cfg = firmware_get(fw_info->kld_name); 3440 3441 /* This is the firmware in the KLD */ 3442 fw = firmware_get(fw_info->fw_mod_name); 3443 if (fw != NULL) { 3444 kld_fw = (const void *)fw->data; 3445 kld_fw_usable = fw_compatible(drv_fw, kld_fw); 3446 } else { 3447 kld_fw = NULL; 3448 kld_fw_usable = 0; 3449 } 3450 3451 /* Read the header of the firmware on the card */ 3452 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 3453 rc = -t4_read_flash(sc, FLASH_FW_START, 3454 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1); 3455 if (rc == 0) { 3456 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw); 3457 if (card_fw->fw_ver == be32toh(0xffffffff)) { 3458 uint32_t d = be32toh(kld_fw->fw_ver); 3459 3460 if (!kld_fw_usable) { 3461 device_printf(sc->dev, 3462 "no firmware on the card and no usable " 3463 "firmware bundled with the driver.\n"); 3464 rc = EIO; 3465 goto done; 3466 } else if (t4_fw_install == 0) { 3467 device_printf(sc->dev, 3468 "no firmware on the card and the driver " 3469 "is prohibited from installing new " 3470 "firmware.\n"); 3471 rc = EIO; 3472 goto done; 3473 } 3474 3475 device_printf(sc->dev, "no firmware on the card, " 3476 "installing firmware %d.%d.%d.%d\n", 3477 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3478 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d)); 3479 rc = t4_fw_forceinstall(sc, fw->data, fw->datasize); 3480 if (rc < 0) { 3481 rc = -rc; 3482 device_printf(sc->dev, 3483 "firmware install failed: %d.\n", rc); 3484 goto done; 3485 } 3486 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3487 card_fw_usable = 1; 3488 need_fw_reset = 0; 3489 } 3490 } else { 3491 device_printf(sc->dev, 3492 "Unable to read card's firmware header: %d\n", rc); 3493 card_fw_usable = 0; 3494 } 3495 3496 /* Contact firmware. */ 3497 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 3498 if (rc < 0 || state == DEV_STATE_ERR) { 3499 rc = -rc; 3500 device_printf(sc->dev, 3501 "failed to connect to the firmware: %d, %d.\n", rc, state); 3502 goto done; 3503 } 3504 pf = rc; 3505 if (pf == sc->mbox) 3506 sc->flags |= MASTER_PF; 3507 else if (state == DEV_STATE_UNINIT) { 3508 /* 3509 * We didn't get to be the master so we definitely won't be 3510 * configuring the chip. It's a bug if someone else hasn't 3511 * configured it already. 3512 */ 3513 device_printf(sc->dev, "couldn't be master(%d), " 3514 "device not already initialized either(%d).\n", rc, state); 3515 rc = EPROTO; 3516 goto done; 3517 } 3518 3519 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && 3520 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) { 3521 /* 3522 * Common case: the firmware on the card is an exact match and 3523 * the KLD is an exact match too, or the KLD is 3524 * absent/incompatible. Note that t4_fw_install = 2 is ignored 3525 * here -- use cxgbetool loadfw if you want to reinstall the 3526 * same firmware as the one on the card. 3527 */ 3528 } else if (kld_fw_usable && state == DEV_STATE_UNINIT && 3529 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver), 3530 be32toh(card_fw->fw_ver))) { 3531 3532 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3533 if (rc != 0) { 3534 device_printf(sc->dev, 3535 "failed to install firmware: %d\n", rc); 3536 goto done; 3537 } 3538 3539 /* Installed successfully, update the cached header too. */ 3540 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3541 card_fw_usable = 1; 3542 need_fw_reset = 0; /* already reset as part of load_fw */ 3543 } 3544 3545 if (!card_fw_usable) { 3546 uint32_t d, c, k; 3547 3548 d = ntohl(drv_fw->fw_ver); 3549 c = ntohl(card_fw->fw_ver); 3550 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0; 3551 3552 device_printf(sc->dev, "Cannot find a usable firmware: " 3553 "fw_install %d, chip state %d, " 3554 "driver compiled with %d.%d.%d.%d, " 3555 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n", 3556 t4_fw_install, state, 3557 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3558 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d), 3559 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3560 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), 3561 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3562 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3563 rc = EINVAL; 3564 goto done; 3565 } 3566 3567 /* Reset device */ 3568 if (need_fw_reset && 3569 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) { 3570 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 3571 if (rc != ETIMEDOUT && rc != EIO) 3572 t4_fw_bye(sc, sc->mbox); 3573 goto done; 3574 } 3575 sc->flags |= FW_OK; 3576 3577 rc = get_params__pre_init(sc); 3578 if (rc != 0) 3579 goto done; /* error message displayed already */ 3580 3581 /* Partition adapter resources as specified in the config file. */ 3582 if (state == DEV_STATE_UNINIT) { 3583 3584 KASSERT(sc->flags & MASTER_PF, 3585 ("%s: trying to change chip settings when not master.", 3586 __func__)); 3587 3588 rc = partition_resources(sc, default_cfg, fw_info->kld_name); 3589 if (rc != 0) 3590 goto done; /* error message displayed already */ 3591 3592 t4_tweak_chip_settings(sc); 3593 3594 /* get basic stuff going */ 3595 rc = -t4_fw_initialize(sc, sc->mbox); 3596 if (rc != 0) { 3597 device_printf(sc->dev, "fw init failed: %d.\n", rc); 3598 goto done; 3599 } 3600 } else { 3601 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf); 3602 sc->cfcsum = 0; 3603 } 3604 3605done: 3606 free(card_fw, M_CXGBE); 3607 if (fw != NULL) 3608 firmware_put(fw, FIRMWARE_UNLOAD); 3609 if (default_cfg != NULL) 3610 firmware_put(default_cfg, FIRMWARE_UNLOAD); 3611 3612 return (rc); 3613} 3614 3615#define FW_PARAM_DEV(param) \ 3616 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 3617 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 3618#define FW_PARAM_PFVF(param) \ 3619 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 3620 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 3621 3622/* 3623 * Partition chip resources for use between various PFs, VFs, etc. 3624 */ 3625static int 3626partition_resources(struct adapter *sc, const struct firmware *default_cfg, 3627 const char *name_prefix) 3628{ 3629 const struct firmware *cfg = NULL; 3630 int rc = 0; 3631 struct fw_caps_config_cmd caps; 3632 uint32_t mtype, moff, finicsum, cfcsum; 3633 3634 /* 3635 * Figure out what configuration file to use. Pick the default config 3636 * file for the card if the user hasn't specified one explicitly. 3637 */ 3638 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file); 3639 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3640 /* Card specific overrides go here. */ 3641 if (pci_get_device(sc->dev) == 0x440a) 3642 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF); 3643 if (is_fpga(sc)) 3644 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF); 3645 } else if (strncmp(t4_cfg_file, BUILTIN_CF, sizeof(t4_cfg_file)) == 0) 3646 goto use_built_in_config; /* go straight to config. */ 3647 3648 /* 3649 * We need to load another module if the profile is anything except 3650 * "default" or "flash". 3651 */ 3652 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 && 3653 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3654 char s[32]; 3655 3656 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file); 3657 cfg = firmware_get(s); 3658 if (cfg == NULL) { 3659 if (default_cfg != NULL) { 3660 device_printf(sc->dev, 3661 "unable to load module \"%s\" for " 3662 "configuration profile \"%s\", will use " 3663 "the default config file instead.\n", 3664 s, sc->cfg_file); 3665 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3666 "%s", DEFAULT_CF); 3667 } else { 3668 device_printf(sc->dev, 3669 "unable to load module \"%s\" for " 3670 "configuration profile \"%s\", will use " 3671 "the config file on the card's flash " 3672 "instead.\n", s, sc->cfg_file); 3673 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3674 "%s", FLASH_CF); 3675 } 3676 } 3677 } 3678 3679 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 && 3680 default_cfg == NULL) { 3681 device_printf(sc->dev, 3682 "default config file not available, will use the config " 3683 "file on the card's flash instead.\n"); 3684 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF); 3685 } 3686 3687 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3688 u_int cflen; 3689 const uint32_t *cfdata; 3690 uint32_t param, val, addr; 3691 3692 KASSERT(cfg != NULL || default_cfg != NULL, 3693 ("%s: no config to upload", __func__)); 3694 3695 /* 3696 * Ask the firmware where it wants us to upload the config file. 3697 */ 3698 param = FW_PARAM_DEV(CF); 3699 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3700 if (rc != 0) { 3701 /* No support for config file? Shouldn't happen. */ 3702 device_printf(sc->dev, 3703 "failed to query config file location: %d.\n", rc); 3704 goto done; 3705 } 3706 mtype = G_FW_PARAMS_PARAM_Y(val); 3707 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3708 3709 /* 3710 * XXX: sheer laziness. We deliberately added 4 bytes of 3711 * useless stuffing/comments at the end of the config file so 3712 * it's ok to simply throw away the last remaining bytes when 3713 * the config file is not an exact multiple of 4. This also 3714 * helps with the validate_mt_off_len check. 3715 */ 3716 if (cfg != NULL) { 3717 cflen = cfg->datasize & ~3; 3718 cfdata = cfg->data; 3719 } else { 3720 cflen = default_cfg->datasize & ~3; 3721 cfdata = default_cfg->data; 3722 } 3723 3724 if (cflen > FLASH_CFG_MAX_SIZE) { 3725 device_printf(sc->dev, 3726 "config file too long (%d, max allowed is %d). " 3727 "Will try to use the config on the card, if any.\n", 3728 cflen, FLASH_CFG_MAX_SIZE); 3729 goto use_config_on_flash; 3730 } 3731 3732 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3733 if (rc != 0) { 3734 device_printf(sc->dev, 3735 "%s: addr (%d/0x%x) or len %d is not valid: %d. " 3736 "Will try to use the config on the card, if any.\n", 3737 __func__, mtype, moff, cflen, rc); 3738 goto use_config_on_flash; 3739 } 3740 write_via_memwin(sc, 2, addr, cfdata, cflen); 3741 } else { 3742use_config_on_flash: 3743 mtype = FW_MEMTYPE_FLASH; 3744 moff = t4_flash_cfg_addr(sc); 3745 } 3746 3747 bzero(&caps, sizeof(caps)); 3748 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3749 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3750 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3751 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3752 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps)); 3753 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3754 if (rc != 0) { 3755 device_printf(sc->dev, 3756 "failed to pre-process config file: %d " 3757 "(mtype %d, moff 0x%x). Will reset the firmware and retry " 3758 "with the built-in configuration.\n", rc, mtype, moff); 3759 3760 rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST); 3761 if (rc != 0) { 3762 device_printf(sc->dev, 3763 "firmware reset failed: %d.\n", rc); 3764 if (rc != ETIMEDOUT && rc != EIO) { 3765 t4_fw_bye(sc, sc->mbox); 3766 sc->flags &= ~FW_OK; 3767 } 3768 goto done; 3769 } 3770 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", "built-in"); 3771use_built_in_config: 3772 bzero(&caps, sizeof(caps)); 3773 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3774 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3775 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3776 rc = t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3777 if (rc != 0) { 3778 device_printf(sc->dev, 3779 "built-in configuration failed: %d.\n", rc); 3780 goto done; 3781 } 3782 } 3783 3784 finicsum = be32toh(caps.finicsum); 3785 cfcsum = be32toh(caps.cfcsum); 3786 if (finicsum != cfcsum) { 3787 device_printf(sc->dev, 3788 "WARNING: config file checksum mismatch: %08x %08x\n", 3789 finicsum, cfcsum); 3790 } 3791 sc->cfcsum = cfcsum; 3792 3793#define LIMIT_CAPS(x) do { \ 3794 caps.x &= htobe16(t4_##x##_allowed); \ 3795} while (0) 3796 3797 /* 3798 * Let the firmware know what features will (not) be used so it can tune 3799 * things accordingly. 3800 */ 3801 LIMIT_CAPS(nbmcaps); 3802 LIMIT_CAPS(linkcaps); 3803 LIMIT_CAPS(switchcaps); 3804 LIMIT_CAPS(niccaps); 3805 LIMIT_CAPS(toecaps); 3806 LIMIT_CAPS(rdmacaps); 3807 LIMIT_CAPS(cryptocaps); 3808 LIMIT_CAPS(iscsicaps); 3809 LIMIT_CAPS(fcoecaps); 3810#undef LIMIT_CAPS 3811 3812 if (caps.niccaps & htobe16(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 3813 /* 3814 * TOE and hashfilters are mutually exclusive. It is a config 3815 * file or firmware bug if both are reported as available. Try 3816 * to cope with the situation in non-debug builds by disabling 3817 * TOE. 3818 */ 3819 MPASS(caps.toecaps == 0); 3820 3821 caps.toecaps = 0; 3822 caps.rdmacaps = 0; 3823 caps.iscsicaps = 0; 3824 } 3825 3826 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3827 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3828 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3829 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3830 if (rc != 0) { 3831 device_printf(sc->dev, 3832 "failed to process config file: %d.\n", rc); 3833 } 3834done: 3835 if (cfg != NULL) 3836 firmware_put(cfg, FIRMWARE_UNLOAD); 3837 return (rc); 3838} 3839 3840/* 3841 * Retrieve parameters that are needed (or nice to have) very early. 3842 */ 3843static int 3844get_params__pre_init(struct adapter *sc) 3845{ 3846 int rc; 3847 uint32_t param[2], val[2]; 3848 3849 t4_get_version_info(sc); 3850 3851 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 3852 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 3853 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 3854 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 3855 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 3856 3857 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 3858 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 3859 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 3860 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 3861 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 3862 3863 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 3864 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 3865 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 3866 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 3867 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 3868 3869 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 3870 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 3871 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 3872 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 3873 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 3874 3875 param[0] = FW_PARAM_DEV(PORTVEC); 3876 param[1] = FW_PARAM_DEV(CCLK); 3877 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3878 if (rc != 0) { 3879 device_printf(sc->dev, 3880 "failed to query parameters (pre_init): %d.\n", rc); 3881 return (rc); 3882 } 3883 3884 sc->params.portvec = val[0]; 3885 sc->params.nports = bitcount32(val[0]); 3886 sc->params.vpd.cclk = val[1]; 3887 3888 /* Read device log parameters. */ 3889 rc = -t4_init_devlog_params(sc, 1); 3890 if (rc == 0) 3891 fixup_devlog_params(sc); 3892 else { 3893 device_printf(sc->dev, 3894 "failed to get devlog parameters: %d.\n", rc); 3895 rc = 0; /* devlog isn't critical for device operation */ 3896 } 3897 3898 return (rc); 3899} 3900 3901/* 3902 * Retrieve various parameters that are of interest to the driver. The device 3903 * has been initialized by the firmware at this point. 3904 */ 3905static int 3906get_params__post_init(struct adapter *sc) 3907{ 3908 int rc; 3909 uint32_t param[7], val[7]; 3910 struct fw_caps_config_cmd caps; 3911 3912 param[0] = FW_PARAM_PFVF(IQFLINT_START); 3913 param[1] = FW_PARAM_PFVF(EQ_START); 3914 param[2] = FW_PARAM_PFVF(FILTER_START); 3915 param[3] = FW_PARAM_PFVF(FILTER_END); 3916 param[4] = FW_PARAM_PFVF(L2T_START); 3917 param[5] = FW_PARAM_PFVF(L2T_END); 3918 param[6] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3919 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 3920 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_VDD); 3921 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 7, param, val); 3922 if (rc != 0) { 3923 device_printf(sc->dev, 3924 "failed to query parameters (post_init): %d.\n", rc); 3925 return (rc); 3926 } 3927 3928 sc->sge.iq_start = val[0]; 3929 sc->sge.eq_start = val[1]; 3930 if (val[3] > val[2]) { 3931 sc->tids.ftid_base = val[2]; 3932 sc->tids.ftid_end = val[3]; 3933 sc->tids.nftids = val[3] - val[2] + 1; 3934 } 3935 sc->vres.l2t.start = val[4]; 3936 sc->vres.l2t.size = val[5] - val[4] + 1; 3937 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 3938 ("%s: L2 table size (%u) larger than expected (%u)", 3939 __func__, sc->vres.l2t.size, L2T_SIZE)); 3940 sc->params.core_vdd = val[6]; 3941 3942 if (chip_id(sc) >= CHELSIO_T6) { 3943 3944#ifdef INVARIANTS 3945 if (sc->params.fw_vers >= 3946 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 3947 V_FW_HDR_FW_VER_MICRO(1) | V_FW_HDR_FW_VER_BUILD(0))) { 3948 /* 3949 * Note that the code to enable the region should run 3950 * before t4_fw_initialize and not here. This is just a 3951 * reminder to add said code. 3952 */ 3953 device_printf(sc->dev, 3954 "hpfilter region not enabled.\n"); 3955 } 3956#endif 3957 3958 sc->tids.tid_base = t4_read_reg(sc, 3959 A_LE_DB_ACTIVE_TABLE_START_INDEX); 3960 3961 param[0] = FW_PARAM_PFVF(HPFILTER_START); 3962 param[1] = FW_PARAM_PFVF(HPFILTER_END); 3963 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3964 if (rc != 0) { 3965 device_printf(sc->dev, 3966 "failed to query hpfilter parameters: %d.\n", rc); 3967 return (rc); 3968 } 3969 if ((int)val[1] > (int)val[0]) { 3970 sc->tids.hpftid_base = val[0]; 3971 sc->tids.hpftid_end = val[1]; 3972 sc->tids.nhpftids = val[1] - val[0] + 1; 3973 3974 /* 3975 * These should go off if the layout changes and the 3976 * driver needs to catch up. 3977 */ 3978 MPASS(sc->tids.hpftid_base == 0); 3979 MPASS(sc->tids.tid_base == sc->tids.nhpftids); 3980 } 3981 } 3982 3983 /* 3984 * MPSBGMAP is queried separately because only recent firmwares support 3985 * it as a parameter and we don't want the compound query above to fail 3986 * on older firmwares. 3987 */ 3988 param[0] = FW_PARAM_DEV(MPSBGMAP); 3989 val[0] = 0; 3990 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 3991 if (rc == 0) 3992 sc->params.mps_bg_map = val[0]; 3993 else 3994 sc->params.mps_bg_map = 0; 3995 3996 /* 3997 * Determine whether the firmware supports the filter2 work request. 3998 * This is queried separately for the same reason as MPSBGMAP above. 3999 */ 4000 param[0] = FW_PARAM_DEV(FILTER2_WR); 4001 val[0] = 0; 4002 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); 4003 if (rc == 0) 4004 sc->params.filter2_wr_support = val[0] != 0; 4005 else 4006 sc->params.filter2_wr_support = 0; 4007 4008 /* get capabilites */ 4009 bzero(&caps, sizeof(caps)); 4010 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 4011 F_FW_CMD_REQUEST | F_FW_CMD_READ); 4012 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 4013 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 4014 if (rc != 0) { 4015 device_printf(sc->dev, 4016 "failed to get card capabilities: %d.\n", rc); 4017 return (rc); 4018 } 4019 4020#define READ_CAPS(x) do { \ 4021 sc->x = htobe16(caps.x); \ 4022} while (0) 4023 READ_CAPS(nbmcaps); 4024 READ_CAPS(linkcaps); 4025 READ_CAPS(switchcaps); 4026 READ_CAPS(niccaps); 4027 READ_CAPS(toecaps); 4028 READ_CAPS(rdmacaps); 4029 READ_CAPS(cryptocaps); 4030 READ_CAPS(iscsicaps); 4031 READ_CAPS(fcoecaps); 4032 4033 if (sc->niccaps & FW_CAPS_CONFIG_NIC_HASHFILTER) { 4034 MPASS(chip_id(sc) > CHELSIO_T4); 4035 MPASS(sc->toecaps == 0); 4036 sc->toecaps = 0; 4037 4038 param[0] = FW_PARAM_DEV(NTID); 4039 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4040 if (rc != 0) { 4041 device_printf(sc->dev, 4042 "failed to query HASHFILTER parameters: %d.\n", rc); 4043 return (rc); 4044 } 4045 sc->tids.ntids = val[0]; 4046 if (sc->params.fw_vers < 4047 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4048 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) { 4049 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4050 sc->tids.ntids -= sc->tids.nhpftids; 4051 } 4052 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4053 sc->params.hash_filter = 1; 4054 } 4055 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 4056 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 4057 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 4058 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4059 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 4060 if (rc != 0) { 4061 device_printf(sc->dev, 4062 "failed to query NIC parameters: %d.\n", rc); 4063 return (rc); 4064 } 4065 if (val[1] > val[0]) { 4066 sc->tids.etid_base = val[0]; 4067 sc->tids.etid_end = val[1]; 4068 sc->tids.netids = val[1] - val[0] + 1; 4069 sc->params.eo_wr_cred = val[2]; 4070 sc->params.ethoffload = 1; 4071 } 4072 } 4073 if (sc->toecaps) { 4074 /* query offload-related parameters */ 4075 param[0] = FW_PARAM_DEV(NTID); 4076 param[1] = FW_PARAM_PFVF(SERVER_START); 4077 param[2] = FW_PARAM_PFVF(SERVER_END); 4078 param[3] = FW_PARAM_PFVF(TDDP_START); 4079 param[4] = FW_PARAM_PFVF(TDDP_END); 4080 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4081 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4082 if (rc != 0) { 4083 device_printf(sc->dev, 4084 "failed to query TOE parameters: %d.\n", rc); 4085 return (rc); 4086 } 4087 sc->tids.ntids = val[0]; 4088 if (sc->params.fw_vers < 4089 (V_FW_HDR_FW_VER_MAJOR(1) | V_FW_HDR_FW_VER_MINOR(20) | 4090 V_FW_HDR_FW_VER_MICRO(5) | V_FW_HDR_FW_VER_BUILD(0))) { 4091 MPASS(sc->tids.ntids >= sc->tids.nhpftids); 4092 sc->tids.ntids -= sc->tids.nhpftids; 4093 } 4094 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 4095 if (val[2] > val[1]) { 4096 sc->tids.stid_base = val[1]; 4097 sc->tids.nstids = val[2] - val[1] + 1; 4098 } 4099 sc->vres.ddp.start = val[3]; 4100 sc->vres.ddp.size = val[4] - val[3] + 1; 4101 sc->params.ofldq_wr_cred = val[5]; 4102 sc->params.offload = 1; 4103 } else { 4104 /* 4105 * The firmware attempts memfree TOE configuration for -SO cards 4106 * and will report toecaps=0 if it runs out of resources (this 4107 * depends on the config file). It may not report 0 for other 4108 * capabilities dependent on the TOE in this case. Set them to 4109 * 0 here so that the driver doesn't bother tracking resources 4110 * that will never be used. 4111 */ 4112 sc->iscsicaps = 0; 4113 sc->rdmacaps = 0; 4114 } 4115 if (sc->rdmacaps) { 4116 param[0] = FW_PARAM_PFVF(STAG_START); 4117 param[1] = FW_PARAM_PFVF(STAG_END); 4118 param[2] = FW_PARAM_PFVF(RQ_START); 4119 param[3] = FW_PARAM_PFVF(RQ_END); 4120 param[4] = FW_PARAM_PFVF(PBL_START); 4121 param[5] = FW_PARAM_PFVF(PBL_END); 4122 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4123 if (rc != 0) { 4124 device_printf(sc->dev, 4125 "failed to query RDMA parameters(1): %d.\n", rc); 4126 return (rc); 4127 } 4128 sc->vres.stag.start = val[0]; 4129 sc->vres.stag.size = val[1] - val[0] + 1; 4130 sc->vres.rq.start = val[2]; 4131 sc->vres.rq.size = val[3] - val[2] + 1; 4132 sc->vres.pbl.start = val[4]; 4133 sc->vres.pbl.size = val[5] - val[4] + 1; 4134 4135 param[0] = FW_PARAM_PFVF(SQRQ_START); 4136 param[1] = FW_PARAM_PFVF(SQRQ_END); 4137 param[2] = FW_PARAM_PFVF(CQ_START); 4138 param[3] = FW_PARAM_PFVF(CQ_END); 4139 param[4] = FW_PARAM_PFVF(OCQ_START); 4140 param[5] = FW_PARAM_PFVF(OCQ_END); 4141 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 4142 if (rc != 0) { 4143 device_printf(sc->dev, 4144 "failed to query RDMA parameters(2): %d.\n", rc); 4145 return (rc); 4146 } 4147 sc->vres.qp.start = val[0]; 4148 sc->vres.qp.size = val[1] - val[0] + 1; 4149 sc->vres.cq.start = val[2]; 4150 sc->vres.cq.size = val[3] - val[2] + 1; 4151 sc->vres.ocq.start = val[4]; 4152 sc->vres.ocq.size = val[5] - val[4] + 1; 4153 4154 param[0] = FW_PARAM_PFVF(SRQ_START); 4155 param[1] = FW_PARAM_PFVF(SRQ_END); 4156 param[2] = FW_PARAM_DEV(MAXORDIRD_QP); 4157 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4158 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); 4159 if (rc != 0) { 4160 device_printf(sc->dev, 4161 "failed to query RDMA parameters(3): %d.\n", rc); 4162 return (rc); 4163 } 4164 sc->vres.srq.start = val[0]; 4165 sc->vres.srq.size = val[1] - val[0] + 1; 4166 sc->params.max_ordird_qp = val[2]; 4167 sc->params.max_ird_adapter = val[3]; 4168 } 4169 if (sc->iscsicaps) { 4170 param[0] = FW_PARAM_PFVF(ISCSI_START); 4171 param[1] = FW_PARAM_PFVF(ISCSI_END); 4172 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4173 if (rc != 0) { 4174 device_printf(sc->dev, 4175 "failed to query iSCSI parameters: %d.\n", rc); 4176 return (rc); 4177 } 4178 sc->vres.iscsi.start = val[0]; 4179 sc->vres.iscsi.size = val[1] - val[0] + 1; 4180 } 4181 if (sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS) { 4182 param[0] = FW_PARAM_PFVF(TLS_START); 4183 param[1] = FW_PARAM_PFVF(TLS_END); 4184 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 4185 if (rc != 0) { 4186 device_printf(sc->dev, 4187 "failed to query TLS parameters: %d.\n", rc); 4188 return (rc); 4189 } 4190 sc->vres.key.start = val[0]; 4191 sc->vres.key.size = val[1] - val[0] + 1; 4192 } 4193 4194 t4_init_sge_params(sc); 4195 4196 /* 4197 * We've got the params we wanted to query via the firmware. Now grab 4198 * some others directly from the chip. 4199 */ 4200 rc = t4_read_chip_settings(sc); 4201 4202 return (rc); 4203} 4204 4205static int 4206set_params__post_init(struct adapter *sc) 4207{ 4208 uint32_t param, val; 4209#ifdef TCP_OFFLOAD 4210 int i, v, shift; 4211#endif 4212 4213 /* ask for encapsulated CPLs */ 4214 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 4215 val = 1; 4216 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 4217 4218 /* Enable 32b port caps if the firmware supports it. */ 4219 param = FW_PARAM_PFVF(PORT_CAPS32); 4220 val = 1; 4221 if (t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val) == 0) 4222 sc->params.port_caps32 = 1; 4223 4224#ifdef TCP_OFFLOAD 4225 /* 4226 * Override the TOE timers with user provided tunables. This is not the 4227 * recommended way to change the timers (the firmware config file is) so 4228 * these tunables are not documented. 4229 * 4230 * All the timer tunables are in microseconds. 4231 */ 4232 if (t4_toe_keepalive_idle != 0) { 4233 v = us_to_tcp_ticks(sc, t4_toe_keepalive_idle); 4234 v &= M_KEEPALIVEIDLE; 4235 t4_set_reg_field(sc, A_TP_KEEP_IDLE, 4236 V_KEEPALIVEIDLE(M_KEEPALIVEIDLE), V_KEEPALIVEIDLE(v)); 4237 } 4238 if (t4_toe_keepalive_interval != 0) { 4239 v = us_to_tcp_ticks(sc, t4_toe_keepalive_interval); 4240 v &= M_KEEPALIVEINTVL; 4241 t4_set_reg_field(sc, A_TP_KEEP_INTVL, 4242 V_KEEPALIVEINTVL(M_KEEPALIVEINTVL), V_KEEPALIVEINTVL(v)); 4243 } 4244 if (t4_toe_keepalive_count != 0) { 4245 v = t4_toe_keepalive_count & M_KEEPALIVEMAXR2; 4246 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4247 V_KEEPALIVEMAXR1(M_KEEPALIVEMAXR1) | 4248 V_KEEPALIVEMAXR2(M_KEEPALIVEMAXR2), 4249 V_KEEPALIVEMAXR1(1) | V_KEEPALIVEMAXR2(v)); 4250 } 4251 if (t4_toe_rexmt_min != 0) { 4252 v = us_to_tcp_ticks(sc, t4_toe_rexmt_min); 4253 v &= M_RXTMIN; 4254 t4_set_reg_field(sc, A_TP_RXT_MIN, 4255 V_RXTMIN(M_RXTMIN), V_RXTMIN(v)); 4256 } 4257 if (t4_toe_rexmt_max != 0) { 4258 v = us_to_tcp_ticks(sc, t4_toe_rexmt_max); 4259 v &= M_RXTMAX; 4260 t4_set_reg_field(sc, A_TP_RXT_MAX, 4261 V_RXTMAX(M_RXTMAX), V_RXTMAX(v)); 4262 } 4263 if (t4_toe_rexmt_count != 0) { 4264 v = t4_toe_rexmt_count & M_RXTSHIFTMAXR2; 4265 t4_set_reg_field(sc, A_TP_SHIFT_CNT, 4266 V_RXTSHIFTMAXR1(M_RXTSHIFTMAXR1) | 4267 V_RXTSHIFTMAXR2(M_RXTSHIFTMAXR2), 4268 V_RXTSHIFTMAXR1(1) | V_RXTSHIFTMAXR2(v)); 4269 } 4270 for (i = 0; i < nitems(t4_toe_rexmt_backoff); i++) { 4271 if (t4_toe_rexmt_backoff[i] != -1) { 4272 v = t4_toe_rexmt_backoff[i] & M_TIMERBACKOFFINDEX0; 4273 shift = (i & 3) << 3; 4274 t4_set_reg_field(sc, A_TP_TCP_BACKOFF_REG0 + (i & ~3), 4275 M_TIMERBACKOFFINDEX0 << shift, v << shift); 4276 } 4277 } 4278#endif 4279 return (0); 4280} 4281 4282#undef FW_PARAM_PFVF 4283#undef FW_PARAM_DEV 4284 4285static void 4286t4_set_desc(struct adapter *sc) 4287{ 4288 char buf[128]; 4289 struct adapter_params *p = &sc->params; 4290 4291 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 4292 4293 device_set_desc_copy(sc->dev, buf); 4294} 4295 4296static inline void 4297ifmedia_add4(struct ifmedia *ifm, int m) 4298{ 4299 4300 ifmedia_add(ifm, m, 0, NULL); 4301 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL); 4302 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL); 4303 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL); 4304} 4305 4306/* 4307 * This is the selected media, which is not quite the same as the active media. 4308 * The media line in ifconfig is "media: Ethernet selected (active)" if selected 4309 * and active are not the same, and "media: Ethernet selected" otherwise. 4310 */ 4311static void 4312set_current_media(struct port_info *pi) 4313{ 4314 struct link_config *lc; 4315 struct ifmedia *ifm; 4316 int mword; 4317 u_int speed; 4318 4319 PORT_LOCK_ASSERT_OWNED(pi); 4320 4321 /* Leave current media alone if it's already set to IFM_NONE. */ 4322 ifm = &pi->media; 4323 if (ifm->ifm_cur != NULL && 4324 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE) 4325 return; 4326 4327 lc = &pi->link_cfg; 4328 if (lc->requested_aneg != AUTONEG_DISABLE && 4329 lc->supported & FW_PORT_CAP32_ANEG) { 4330 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO); 4331 return; 4332 } 4333 mword = IFM_ETHER | IFM_FDX; 4334 if (lc->requested_fc & PAUSE_TX) 4335 mword |= IFM_ETH_TXPAUSE; 4336 if (lc->requested_fc & PAUSE_RX) 4337 mword |= IFM_ETH_RXPAUSE; 4338 if (lc->requested_speed == 0) 4339 speed = port_top_speed(pi) * 1000; /* Gbps -> Mbps */ 4340 else 4341 speed = lc->requested_speed; 4342 mword |= port_mword(pi, speed_to_fwcap(speed)); 4343 ifmedia_set(ifm, mword); 4344} 4345 4346/* 4347 * Returns true if the ifmedia list for the port cannot change. 4348 */ 4349static bool 4350fixed_ifmedia(struct port_info *pi) 4351{ 4352 4353 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 4354 pi->port_type == FW_PORT_TYPE_BT_XFI || 4355 pi->port_type == FW_PORT_TYPE_BT_XAUI || 4356 pi->port_type == FW_PORT_TYPE_KX4 || 4357 pi->port_type == FW_PORT_TYPE_KX || 4358 pi->port_type == FW_PORT_TYPE_KR || 4359 pi->port_type == FW_PORT_TYPE_BP_AP || 4360 pi->port_type == FW_PORT_TYPE_BP4_AP || 4361 pi->port_type == FW_PORT_TYPE_BP40_BA || 4362 pi->port_type == FW_PORT_TYPE_KR4_100G || 4363 pi->port_type == FW_PORT_TYPE_KR_SFP28 || 4364 pi->port_type == FW_PORT_TYPE_KR_XLAUI); 4365} 4366 4367static void 4368build_medialist(struct port_info *pi) 4369{ 4370 uint32_t ss, speed; 4371 int unknown, mword, bit; 4372 struct link_config *lc; 4373 struct ifmedia *ifm; 4374 4375 PORT_LOCK_ASSERT_OWNED(pi); 4376 4377 if (pi->flags & FIXED_IFMEDIA) 4378 return; 4379 4380 /* 4381 * Rebuild the ifmedia list. 4382 */ 4383 ifm = &pi->media; 4384 ifmedia_removeall(ifm); 4385 lc = &pi->link_cfg; 4386 ss = G_FW_PORT_CAP32_SPEED(lc->supported); /* Supported Speeds */ 4387 if (__predict_false(ss == 0)) { /* not supposed to happen. */ 4388 MPASS(ss != 0); 4389no_media: 4390 MPASS(LIST_EMPTY(&ifm->ifm_list)); 4391 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 4392 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 4393 return; 4394 } 4395 4396 unknown = 0; 4397 for (bit = S_FW_PORT_CAP32_SPEED; bit < fls(ss); bit++) { 4398 speed = 1 << bit; 4399 MPASS(speed & M_FW_PORT_CAP32_SPEED); 4400 if (ss & speed) { 4401 mword = port_mword(pi, speed); 4402 if (mword == IFM_NONE) { 4403 goto no_media; 4404 } else if (mword == IFM_UNKNOWN) 4405 unknown++; 4406 else 4407 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword); 4408 } 4409 } 4410 if (unknown > 0) /* Add one unknown for all unknown media types. */ 4411 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN); 4412 if (lc->supported & FW_PORT_CAP32_ANEG) 4413 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL); 4414 4415 set_current_media(pi); 4416} 4417 4418/* 4419 * Initialize the requested fields in the link config based on driver tunables. 4420 */ 4421static void 4422init_link_config(struct port_info *pi) 4423{ 4424 struct link_config *lc = &pi->link_cfg; 4425 4426 PORT_LOCK_ASSERT_OWNED(pi); 4427 4428 lc->requested_speed = 0; 4429 4430 if (t4_autoneg == 0) 4431 lc->requested_aneg = AUTONEG_DISABLE; 4432 else if (t4_autoneg == 1) 4433 lc->requested_aneg = AUTONEG_ENABLE; 4434 else 4435 lc->requested_aneg = AUTONEG_AUTO; 4436 4437 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX | 4438 PAUSE_AUTONEG); 4439 4440 if (t4_fec == -1 || t4_fec & FEC_AUTO) 4441 lc->requested_fec = FEC_AUTO; 4442 else { 4443 lc->requested_fec = FEC_NONE; 4444 if (t4_fec & FEC_RS) 4445 lc->requested_fec |= FEC_RS; 4446 if (t4_fec & FEC_BASER_RS) 4447 lc->requested_fec |= FEC_BASER_RS; 4448 } 4449} 4450 4451/* 4452 * Makes sure that all requested settings comply with what's supported by the 4453 * port. Returns the number of settings that were invalid and had to be fixed. 4454 */ 4455static int 4456fixup_link_config(struct port_info *pi) 4457{ 4458 int n = 0; 4459 struct link_config *lc = &pi->link_cfg; 4460 uint32_t fwspeed; 4461 4462 PORT_LOCK_ASSERT_OWNED(pi); 4463 4464 /* Speed (when not autonegotiating) */ 4465 if (lc->requested_speed != 0) { 4466 fwspeed = speed_to_fwcap(lc->requested_speed); 4467 if ((fwspeed & lc->supported) == 0) { 4468 n++; 4469 lc->requested_speed = 0; 4470 } 4471 } 4472 4473 /* Link autonegotiation */ 4474 MPASS(lc->requested_aneg == AUTONEG_ENABLE || 4475 lc->requested_aneg == AUTONEG_DISABLE || 4476 lc->requested_aneg == AUTONEG_AUTO); 4477 if (lc->requested_aneg == AUTONEG_ENABLE && 4478 !(lc->supported & FW_PORT_CAP32_ANEG)) { 4479 n++; 4480 lc->requested_aneg = AUTONEG_AUTO; 4481 } 4482 4483 /* Flow control */ 4484 MPASS((lc->requested_fc & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) == 0); 4485 if (lc->requested_fc & PAUSE_TX && 4486 !(lc->supported & FW_PORT_CAP32_FC_TX)) { 4487 n++; 4488 lc->requested_fc &= ~PAUSE_TX; 4489 } 4490 if (lc->requested_fc & PAUSE_RX && 4491 !(lc->supported & FW_PORT_CAP32_FC_RX)) { 4492 n++; 4493 lc->requested_fc &= ~PAUSE_RX; 4494 } 4495 if (!(lc->requested_fc & PAUSE_AUTONEG) && 4496 !(lc->supported & FW_PORT_CAP32_FORCE_PAUSE)) { 4497 n++; 4498 lc->requested_fc |= PAUSE_AUTONEG; 4499 } 4500 4501 /* FEC */ 4502 if ((lc->requested_fec & FEC_RS && 4503 !(lc->supported & FW_PORT_CAP32_FEC_RS)) || 4504 (lc->requested_fec & FEC_BASER_RS && 4505 !(lc->supported & FW_PORT_CAP32_FEC_BASER_RS))) { 4506 n++; 4507 lc->requested_fec = FEC_AUTO; 4508 } 4509 4510 return (n); 4511} 4512 4513/* 4514 * Apply the requested L1 settings, which are expected to be valid, to the 4515 * hardware. 4516 */ 4517static int 4518apply_link_config(struct port_info *pi) 4519{ 4520 struct adapter *sc = pi->adapter; 4521 struct link_config *lc = &pi->link_cfg; 4522 int rc; 4523 4524#ifdef INVARIANTS 4525 ASSERT_SYNCHRONIZED_OP(sc); 4526 PORT_LOCK_ASSERT_OWNED(pi); 4527 4528 if (lc->requested_aneg == AUTONEG_ENABLE) 4529 MPASS(lc->supported & FW_PORT_CAP32_ANEG); 4530 if (!(lc->requested_fc & PAUSE_AUTONEG)) 4531 MPASS(lc->supported & FW_PORT_CAP32_FORCE_PAUSE); 4532 if (lc->requested_fc & PAUSE_TX) 4533 MPASS(lc->supported & FW_PORT_CAP32_FC_TX); 4534 if (lc->requested_fc & PAUSE_RX) 4535 MPASS(lc->supported & FW_PORT_CAP32_FC_RX); 4536 if (lc->requested_fec & FEC_RS) 4537 MPASS(lc->supported & FW_PORT_CAP32_FEC_RS); 4538 if (lc->requested_fec & FEC_BASER_RS) 4539 MPASS(lc->supported & FW_PORT_CAP32_FEC_BASER_RS); 4540#endif 4541 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 4542 if (rc != 0) { 4543 device_printf(pi->dev, "l1cfg failed: %d\n", rc); 4544 } else { 4545 /* 4546 * An L1_CFG will almost always result in a link-change event if 4547 * the link is up, and the driver will refresh the actual 4548 * fec/fc/etc. when the notification is processed. If the link 4549 * is down then the actual settings are meaningless. 4550 * 4551 * This takes care of the case where a change in the L1 settings 4552 * may not result in a notification. 4553 */ 4554 if (lc->link_ok && !(lc->requested_fc & PAUSE_AUTONEG)) 4555 lc->fc = lc->requested_fc & (PAUSE_TX | PAUSE_RX); 4556 } 4557 return (rc); 4558} 4559 4560#define FW_MAC_EXACT_CHUNK 7 4561 4562/* 4563 * Program the port's XGMAC based on parameters in ifnet. The caller also 4564 * indicates which parameters should be programmed (the rest are left alone). 4565 */ 4566int 4567update_mac_settings(struct ifnet *ifp, int flags) 4568{ 4569 int rc = 0; 4570 struct vi_info *vi = ifp->if_softc; 4571 struct port_info *pi = vi->pi; 4572 struct adapter *sc = pi->adapter; 4573 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 4574 4575 ASSERT_SYNCHRONIZED_OP(sc); 4576 KASSERT(flags, ("%s: not told what to update.", __func__)); 4577 4578 if (flags & XGMAC_MTU) 4579 mtu = ifp->if_mtu; 4580 4581 if (flags & XGMAC_PROMISC) 4582 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 4583 4584 if (flags & XGMAC_ALLMULTI) 4585 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 4586 4587 if (flags & XGMAC_VLANEX) 4588 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 4589 4590 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 4591 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 4592 allmulti, 1, vlanex, false); 4593 if (rc) { 4594 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 4595 rc); 4596 return (rc); 4597 } 4598 } 4599 4600 if (flags & XGMAC_UCADDR) { 4601 uint8_t ucaddr[ETHER_ADDR_LEN]; 4602 4603 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 4604 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 4605 ucaddr, true, true); 4606 if (rc < 0) { 4607 rc = -rc; 4608 if_printf(ifp, "change_mac failed: %d\n", rc); 4609 return (rc); 4610 } else { 4611 vi->xact_addr_filt = rc; 4612 rc = 0; 4613 } 4614 } 4615 4616 if (flags & XGMAC_MCADDRS) { 4617 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 4618 int del = 1; 4619 uint64_t hash = 0; 4620 struct ifmultiaddr *ifma; 4621 int i = 0, j; 4622 4623 if_maddr_rlock(ifp); 4624 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 4625 if (ifma->ifma_addr->sa_family != AF_LINK) 4626 continue; 4627 mcaddr[i] = 4628 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 4629 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 4630 i++; 4631 4632 if (i == FW_MAC_EXACT_CHUNK) { 4633 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 4634 del, i, mcaddr, NULL, &hash, 0); 4635 if (rc < 0) { 4636 rc = -rc; 4637 for (j = 0; j < i; j++) { 4638 if_printf(ifp, 4639 "failed to add mc address" 4640 " %02x:%02x:%02x:" 4641 "%02x:%02x:%02x rc=%d\n", 4642 mcaddr[j][0], mcaddr[j][1], 4643 mcaddr[j][2], mcaddr[j][3], 4644 mcaddr[j][4], mcaddr[j][5], 4645 rc); 4646 } 4647 goto mcfail; 4648 } 4649 del = 0; 4650 i = 0; 4651 } 4652 } 4653 if (i > 0) { 4654 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 4655 mcaddr, NULL, &hash, 0); 4656 if (rc < 0) { 4657 rc = -rc; 4658 for (j = 0; j < i; j++) { 4659 if_printf(ifp, 4660 "failed to add mc address" 4661 " %02x:%02x:%02x:" 4662 "%02x:%02x:%02x rc=%d\n", 4663 mcaddr[j][0], mcaddr[j][1], 4664 mcaddr[j][2], mcaddr[j][3], 4665 mcaddr[j][4], mcaddr[j][5], 4666 rc); 4667 } 4668 goto mcfail; 4669 } 4670 } 4671 4672 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 4673 if (rc != 0) 4674 if_printf(ifp, "failed to set mc address hash: %d", rc); 4675mcfail: 4676 if_maddr_runlock(ifp); 4677 } 4678 4679 return (rc); 4680} 4681 4682/* 4683 * {begin|end}_synchronized_op must be called from the same thread. 4684 */ 4685int 4686begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 4687 char *wmesg) 4688{ 4689 int rc, pri; 4690 4691#ifdef WITNESS 4692 /* the caller thinks it's ok to sleep, but is it really? */ 4693 if (flags & SLEEP_OK) 4694 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 4695 "begin_synchronized_op"); 4696#endif 4697 4698 if (INTR_OK) 4699 pri = PCATCH; 4700 else 4701 pri = 0; 4702 4703 ADAPTER_LOCK(sc); 4704 for (;;) { 4705 4706 if (vi && IS_DOOMED(vi)) { 4707 rc = ENXIO; 4708 goto done; 4709 } 4710 4711 if (!IS_BUSY(sc)) { 4712 rc = 0; 4713 break; 4714 } 4715 4716 if (!(flags & SLEEP_OK)) { 4717 rc = EBUSY; 4718 goto done; 4719 } 4720 4721 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 4722 rc = EINTR; 4723 goto done; 4724 } 4725 } 4726 4727 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 4728 SET_BUSY(sc); 4729#ifdef INVARIANTS 4730 sc->last_op = wmesg; 4731 sc->last_op_thr = curthread; 4732 sc->last_op_flags = flags; 4733#endif 4734 4735done: 4736 if (!(flags & HOLD_LOCK) || rc) 4737 ADAPTER_UNLOCK(sc); 4738 4739 return (rc); 4740} 4741 4742/* 4743 * Tell if_ioctl and if_init that the VI is going away. This is 4744 * special variant of begin_synchronized_op and must be paired with a 4745 * call to end_synchronized_op. 4746 */ 4747void 4748doom_vi(struct adapter *sc, struct vi_info *vi) 4749{ 4750 4751 ADAPTER_LOCK(sc); 4752 SET_DOOMED(vi); 4753 wakeup(&sc->flags); 4754 while (IS_BUSY(sc)) 4755 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 4756 SET_BUSY(sc); 4757#ifdef INVARIANTS 4758 sc->last_op = "t4detach"; 4759 sc->last_op_thr = curthread; 4760 sc->last_op_flags = 0; 4761#endif 4762 ADAPTER_UNLOCK(sc); 4763} 4764 4765/* 4766 * {begin|end}_synchronized_op must be called from the same thread. 4767 */ 4768void 4769end_synchronized_op(struct adapter *sc, int flags) 4770{ 4771 4772 if (flags & LOCK_HELD) 4773 ADAPTER_LOCK_ASSERT_OWNED(sc); 4774 else 4775 ADAPTER_LOCK(sc); 4776 4777 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 4778 CLR_BUSY(sc); 4779 wakeup(&sc->flags); 4780 ADAPTER_UNLOCK(sc); 4781} 4782 4783static int 4784cxgbe_init_synchronized(struct vi_info *vi) 4785{ 4786 struct port_info *pi = vi->pi; 4787 struct adapter *sc = pi->adapter; 4788 struct ifnet *ifp = vi->ifp; 4789 int rc = 0, i; 4790 struct sge_txq *txq; 4791 4792 ASSERT_SYNCHRONIZED_OP(sc); 4793 4794 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4795 return (0); /* already running */ 4796 4797 if (!(sc->flags & FULL_INIT_DONE) && 4798 ((rc = adapter_full_init(sc)) != 0)) 4799 return (rc); /* error message displayed already */ 4800 4801 if (!(vi->flags & VI_INIT_DONE) && 4802 ((rc = vi_full_init(vi)) != 0)) 4803 return (rc); /* error message displayed already */ 4804 4805 rc = update_mac_settings(ifp, XGMAC_ALL); 4806 if (rc) 4807 goto done; /* error message displayed already */ 4808 4809 PORT_LOCK(pi); 4810 if (pi->up_vis == 0) { 4811 t4_update_port_info(pi); 4812 fixup_link_config(pi); 4813 build_medialist(pi); 4814 apply_link_config(pi); 4815 } 4816 4817 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 4818 if (rc != 0) { 4819 if_printf(ifp, "enable_vi failed: %d\n", rc); 4820 PORT_UNLOCK(pi); 4821 goto done; 4822 } 4823 4824 /* 4825 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 4826 * if this changes. 4827 */ 4828 4829 for_each_txq(vi, i, txq) { 4830 TXQ_LOCK(txq); 4831 txq->eq.flags |= EQ_ENABLED; 4832 TXQ_UNLOCK(txq); 4833 } 4834 4835 /* 4836 * The first iq of the first port to come up is used for tracing. 4837 */ 4838 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 4839 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 4840 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 4841 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 4842 V_QUEUENUMBER(sc->traceq)); 4843 pi->flags |= HAS_TRACEQ; 4844 } 4845 4846 /* all ok */ 4847 pi->up_vis++; 4848 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4849 4850 if (pi->nvi > 1 || sc->flags & IS_VF) 4851 callout_reset(&vi->tick, hz, vi_tick, vi); 4852 else 4853 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 4854 PORT_UNLOCK(pi); 4855done: 4856 if (rc != 0) 4857 cxgbe_uninit_synchronized(vi); 4858 4859 return (rc); 4860} 4861 4862/* 4863 * Idempotent. 4864 */ 4865static int 4866cxgbe_uninit_synchronized(struct vi_info *vi) 4867{ 4868 struct port_info *pi = vi->pi; 4869 struct adapter *sc = pi->adapter; 4870 struct ifnet *ifp = vi->ifp; 4871 int rc, i; 4872 struct sge_txq *txq; 4873 4874 ASSERT_SYNCHRONIZED_OP(sc); 4875 4876 if (!(vi->flags & VI_INIT_DONE)) { 4877 if (__predict_false(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4878 KASSERT(0, ("uninited VI is running")); 4879 if_printf(ifp, "uninited VI with running ifnet. " 4880 "vi->flags 0x%016lx, if_flags 0x%08x, " 4881 "if_drv_flags 0x%08x\n", vi->flags, ifp->if_flags, 4882 ifp->if_drv_flags); 4883 } 4884 return (0); 4885 } 4886 4887 /* 4888 * Disable the VI so that all its data in either direction is discarded 4889 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 4890 * tick) intact as the TP can deliver negative advice or data that it's 4891 * holding in its RAM (for an offloaded connection) even after the VI is 4892 * disabled. 4893 */ 4894 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 4895 if (rc) { 4896 if_printf(ifp, "disable_vi failed: %d\n", rc); 4897 return (rc); 4898 } 4899 4900 for_each_txq(vi, i, txq) { 4901 TXQ_LOCK(txq); 4902 txq->eq.flags &= ~EQ_ENABLED; 4903 TXQ_UNLOCK(txq); 4904 } 4905 4906 PORT_LOCK(pi); 4907 if (pi->nvi > 1 || sc->flags & IS_VF) 4908 callout_stop(&vi->tick); 4909 else 4910 callout_stop(&pi->tick); 4911 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4912 PORT_UNLOCK(pi); 4913 return (0); 4914 } 4915 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4916 pi->up_vis--; 4917 if (pi->up_vis > 0) { 4918 PORT_UNLOCK(pi); 4919 return (0); 4920 } 4921 4922 pi->link_cfg.link_ok = false; 4923 pi->link_cfg.speed = 0; 4924 pi->link_cfg.link_down_rc = 255; 4925 t4_os_link_changed(pi); 4926 PORT_UNLOCK(pi); 4927 4928 return (0); 4929} 4930 4931/* 4932 * It is ok for this function to fail midway and return right away. t4_detach 4933 * will walk the entire sc->irq list and clean up whatever is valid. 4934 */ 4935int 4936t4_setup_intr_handlers(struct adapter *sc) 4937{ 4938 int rc, rid, p, q, v; 4939 char s[8]; 4940 struct irq *irq; 4941 struct port_info *pi; 4942 struct vi_info *vi; 4943 struct sge *sge = &sc->sge; 4944 struct sge_rxq *rxq; 4945#ifdef TCP_OFFLOAD 4946 struct sge_ofld_rxq *ofld_rxq; 4947#endif 4948#ifdef DEV_NETMAP 4949 struct sge_nm_rxq *nm_rxq; 4950#endif 4951#ifdef RSS 4952 int nbuckets = rss_getnumbuckets(); 4953#endif 4954 4955 /* 4956 * Setup interrupts. 4957 */ 4958 irq = &sc->irq[0]; 4959 rid = sc->intr_type == INTR_INTX ? 0 : 1; 4960 if (forwarding_intr_to_fwq(sc)) 4961 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 4962 4963 /* Multiple interrupts. */ 4964 if (sc->flags & IS_VF) 4965 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 4966 ("%s: too few intr.", __func__)); 4967 else 4968 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 4969 ("%s: too few intr.", __func__)); 4970 4971 /* The first one is always error intr on PFs */ 4972 if (!(sc->flags & IS_VF)) { 4973 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 4974 if (rc != 0) 4975 return (rc); 4976 irq++; 4977 rid++; 4978 } 4979 4980 /* The second one is always the firmware event queue (first on VFs) */ 4981 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 4982 if (rc != 0) 4983 return (rc); 4984 irq++; 4985 rid++; 4986 4987 for_each_port(sc, p) { 4988 pi = sc->port[p]; 4989 for_each_vi(pi, v, vi) { 4990 vi->first_intr = rid - 1; 4991 4992 if (vi->nnmrxq > 0) { 4993 int n = max(vi->nrxq, vi->nnmrxq); 4994 4995 rxq = &sge->rxq[vi->first_rxq]; 4996#ifdef DEV_NETMAP 4997 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 4998#endif 4999 for (q = 0; q < n; q++) { 5000 snprintf(s, sizeof(s), "%x%c%x", p, 5001 'a' + v, q); 5002 if (q < vi->nrxq) 5003 irq->rxq = rxq++; 5004#ifdef DEV_NETMAP 5005 if (q < vi->nnmrxq) 5006 irq->nm_rxq = nm_rxq++; 5007 5008 if (irq->nm_rxq != NULL && 5009 irq->rxq == NULL) { 5010 /* Netmap rx only */ 5011 rc = t4_alloc_irq(sc, irq, rid, 5012 t4_nm_intr, irq->nm_rxq, s); 5013 } 5014 if (irq->nm_rxq != NULL && 5015 irq->rxq != NULL) { 5016 /* NIC and Netmap rx */ 5017 rc = t4_alloc_irq(sc, irq, rid, 5018 t4_vi_intr, irq, s); 5019 } 5020#endif 5021 if (irq->rxq != NULL && 5022 irq->nm_rxq == NULL) { 5023 /* NIC rx only */ 5024 rc = t4_alloc_irq(sc, irq, rid, 5025 t4_intr, irq->rxq, s); 5026 } 5027 if (rc != 0) 5028 return (rc); 5029#ifdef RSS 5030 if (q < vi->nrxq) { 5031 bus_bind_intr(sc->dev, irq->res, 5032 rss_getcpu(q % nbuckets)); 5033 } 5034#endif 5035 irq++; 5036 rid++; 5037 vi->nintr++; 5038 } 5039 } else { 5040 for_each_rxq(vi, q, rxq) { 5041 snprintf(s, sizeof(s), "%x%c%x", p, 5042 'a' + v, q); 5043 rc = t4_alloc_irq(sc, irq, rid, 5044 t4_intr, rxq, s); 5045 if (rc != 0) 5046 return (rc); 5047#ifdef RSS 5048 bus_bind_intr(sc->dev, irq->res, 5049 rss_getcpu(q % nbuckets)); 5050#endif 5051 irq++; 5052 rid++; 5053 vi->nintr++; 5054 } 5055 } 5056#ifdef TCP_OFFLOAD 5057 for_each_ofld_rxq(vi, q, ofld_rxq) { 5058 snprintf(s, sizeof(s), "%x%c%x", p, 'A' + v, q); 5059 rc = t4_alloc_irq(sc, irq, rid, t4_intr, 5060 ofld_rxq, s); 5061 if (rc != 0) 5062 return (rc); 5063 irq++; 5064 rid++; 5065 vi->nintr++; 5066 } 5067#endif 5068 } 5069 } 5070 MPASS(irq == &sc->irq[sc->intr_count]); 5071 5072 return (0); 5073} 5074 5075int 5076adapter_full_init(struct adapter *sc) 5077{ 5078 int rc, i; 5079#ifdef RSS 5080 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5081 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 5082#endif 5083 5084 ASSERT_SYNCHRONIZED_OP(sc); 5085 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5086 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 5087 ("%s: FULL_INIT_DONE already", __func__)); 5088 5089 /* 5090 * queues that belong to the adapter (not any particular port). 5091 */ 5092 rc = t4_setup_adapter_queues(sc); 5093 if (rc != 0) 5094 goto done; 5095 5096 for (i = 0; i < nitems(sc->tq); i++) { 5097 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 5098 taskqueue_thread_enqueue, &sc->tq[i]); 5099 if (sc->tq[i] == NULL) { 5100 device_printf(sc->dev, 5101 "failed to allocate task queue %d\n", i); 5102 rc = ENOMEM; 5103 goto done; 5104 } 5105 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 5106 device_get_nameunit(sc->dev), i); 5107 } 5108#ifdef RSS 5109 MPASS(RSS_KEYSIZE == 40); 5110 rss_getkey((void *)&raw_rss_key[0]); 5111 for (i = 0; i < nitems(rss_key); i++) { 5112 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 5113 } 5114 t4_write_rss_key(sc, &rss_key[0], -1, 1); 5115#endif 5116 5117 if (!(sc->flags & IS_VF)) 5118 t4_intr_enable(sc); 5119 sc->flags |= FULL_INIT_DONE; 5120done: 5121 if (rc != 0) 5122 adapter_full_uninit(sc); 5123 5124 return (rc); 5125} 5126 5127int 5128adapter_full_uninit(struct adapter *sc) 5129{ 5130 int i; 5131 5132 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 5133 5134 t4_teardown_adapter_queues(sc); 5135 5136 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 5137 taskqueue_free(sc->tq[i]); 5138 sc->tq[i] = NULL; 5139 } 5140 5141 sc->flags &= ~FULL_INIT_DONE; 5142 5143 return (0); 5144} 5145 5146#ifdef RSS 5147#define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 5148 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 5149 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 5150 RSS_HASHTYPE_RSS_UDP_IPV6) 5151 5152/* Translates kernel hash types to hardware. */ 5153static int 5154hashconfig_to_hashen(int hashconfig) 5155{ 5156 int hashen = 0; 5157 5158 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 5159 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 5160 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 5161 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 5162 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 5163 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5164 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5165 } 5166 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 5167 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 5168 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5169 } 5170 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 5171 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 5172 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 5173 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 5174 5175 return (hashen); 5176} 5177 5178/* Translates hardware hash types to kernel. */ 5179static int 5180hashen_to_hashconfig(int hashen) 5181{ 5182 int hashconfig = 0; 5183 5184 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 5185 /* 5186 * If UDP hashing was enabled it must have been enabled for 5187 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 5188 * enabling any 4-tuple hash is nonsense configuration. 5189 */ 5190 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5191 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 5192 5193 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5194 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 5195 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5196 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 5197 } 5198 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 5199 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 5200 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 5201 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 5202 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 5203 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 5204 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 5205 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 5206 5207 return (hashconfig); 5208} 5209#endif 5210 5211int 5212vi_full_init(struct vi_info *vi) 5213{ 5214 struct adapter *sc = vi->pi->adapter; 5215 struct ifnet *ifp = vi->ifp; 5216 uint16_t *rss; 5217 struct sge_rxq *rxq; 5218 int rc, i, j, hashen; 5219#ifdef RSS 5220 int nbuckets = rss_getnumbuckets(); 5221 int hashconfig = rss_gethashconfig(); 5222 int extra; 5223#endif 5224 5225 ASSERT_SYNCHRONIZED_OP(sc); 5226 KASSERT((vi->flags & VI_INIT_DONE) == 0, 5227 ("%s: VI_INIT_DONE already", __func__)); 5228 5229 sysctl_ctx_init(&vi->ctx); 5230 vi->flags |= VI_SYSCTL_CTX; 5231 5232 /* 5233 * Allocate tx/rx/fl queues for this VI. 5234 */ 5235 rc = t4_setup_vi_queues(vi); 5236 if (rc != 0) 5237 goto done; /* error message displayed already */ 5238 5239 /* 5240 * Setup RSS for this VI. Save a copy of the RSS table for later use. 5241 */ 5242 if (vi->nrxq > vi->rss_size) { 5243 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 5244 "some queues will never receive traffic.\n", vi->nrxq, 5245 vi->rss_size); 5246 } else if (vi->rss_size % vi->nrxq) { 5247 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 5248 "expect uneven traffic distribution.\n", vi->nrxq, 5249 vi->rss_size); 5250 } 5251#ifdef RSS 5252 if (vi->nrxq != nbuckets) { 5253 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 5254 "performance will be impacted.\n", vi->nrxq, nbuckets); 5255 } 5256#endif 5257 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 5258 for (i = 0; i < vi->rss_size;) { 5259#ifdef RSS 5260 j = rss_get_indirection_to_bucket(i); 5261 j %= vi->nrxq; 5262 rxq = &sc->sge.rxq[vi->first_rxq + j]; 5263 rss[i++] = rxq->iq.abs_id; 5264#else 5265 for_each_rxq(vi, j, rxq) { 5266 rss[i++] = rxq->iq.abs_id; 5267 if (i == vi->rss_size) 5268 break; 5269 } 5270#endif 5271 } 5272 5273 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 5274 vi->rss_size); 5275 if (rc != 0) { 5276 if_printf(ifp, "rss_config failed: %d\n", rc); 5277 goto done; 5278 } 5279 5280#ifdef RSS 5281 hashen = hashconfig_to_hashen(hashconfig); 5282 5283 /* 5284 * We may have had to enable some hashes even though the global config 5285 * wants them disabled. This is a potential problem that must be 5286 * reported to the user. 5287 */ 5288 extra = hashen_to_hashconfig(hashen) ^ hashconfig; 5289 5290 /* 5291 * If we consider only the supported hash types, then the enabled hashes 5292 * are a superset of the requested hashes. In other words, there cannot 5293 * be any supported hash that was requested but not enabled, but there 5294 * can be hashes that were not requested but had to be enabled. 5295 */ 5296 extra &= SUPPORTED_RSS_HASHTYPES; 5297 MPASS((extra & hashconfig) == 0); 5298 5299 if (extra) { 5300 if_printf(ifp, 5301 "global RSS config (0x%x) cannot be accommodated.\n", 5302 hashconfig); 5303 } 5304 if (extra & RSS_HASHTYPE_RSS_IPV4) 5305 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 5306 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 5307 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 5308 if (extra & RSS_HASHTYPE_RSS_IPV6) 5309 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 5310 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 5311 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 5312 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 5313 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 5314 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 5315 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 5316#else 5317 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 5318 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 5319 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 5320 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 5321#endif 5322 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0); 5323 if (rc != 0) { 5324 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 5325 goto done; 5326 } 5327 5328 vi->rss = rss; 5329 vi->flags |= VI_INIT_DONE; 5330done: 5331 if (rc != 0) 5332 vi_full_uninit(vi); 5333 5334 return (rc); 5335} 5336 5337/* 5338 * Idempotent. 5339 */ 5340int 5341vi_full_uninit(struct vi_info *vi) 5342{ 5343 struct port_info *pi = vi->pi; 5344 struct adapter *sc = pi->adapter; 5345 int i; 5346 struct sge_rxq *rxq; 5347 struct sge_txq *txq; 5348#ifdef TCP_OFFLOAD 5349 struct sge_ofld_rxq *ofld_rxq; 5350 struct sge_wrq *ofld_txq; 5351#endif 5352 5353 if (vi->flags & VI_INIT_DONE) { 5354 5355 /* Need to quiesce queues. */ 5356 5357 /* XXX: Only for the first VI? */ 5358 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 5359 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 5360 5361 for_each_txq(vi, i, txq) { 5362 quiesce_txq(sc, txq); 5363 } 5364 5365#ifdef TCP_OFFLOAD 5366 for_each_ofld_txq(vi, i, ofld_txq) { 5367 quiesce_wrq(sc, ofld_txq); 5368 } 5369#endif 5370 5371 for_each_rxq(vi, i, rxq) { 5372 quiesce_iq(sc, &rxq->iq); 5373 quiesce_fl(sc, &rxq->fl); 5374 } 5375 5376#ifdef TCP_OFFLOAD 5377 for_each_ofld_rxq(vi, i, ofld_rxq) { 5378 quiesce_iq(sc, &ofld_rxq->iq); 5379 quiesce_fl(sc, &ofld_rxq->fl); 5380 } 5381#endif 5382 free(vi->rss, M_CXGBE); 5383 free(vi->nm_rss, M_CXGBE); 5384 } 5385 5386 t4_teardown_vi_queues(vi); 5387 vi->flags &= ~VI_INIT_DONE; 5388 5389 return (0); 5390} 5391 5392static void 5393quiesce_txq(struct adapter *sc, struct sge_txq *txq) 5394{ 5395 struct sge_eq *eq = &txq->eq; 5396 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 5397 5398 (void) sc; /* unused */ 5399 5400#ifdef INVARIANTS 5401 TXQ_LOCK(txq); 5402 MPASS((eq->flags & EQ_ENABLED) == 0); 5403 TXQ_UNLOCK(txq); 5404#endif 5405 5406 /* Wait for the mp_ring to empty. */ 5407 while (!mp_ring_is_idle(txq->r)) { 5408 mp_ring_check_drainage(txq->r, 0); 5409 pause("rquiesce", 1); 5410 } 5411 5412 /* Then wait for the hardware to finish. */ 5413 while (spg->cidx != htobe16(eq->pidx)) 5414 pause("equiesce", 1); 5415 5416 /* Finally, wait for the driver to reclaim all descriptors. */ 5417 while (eq->cidx != eq->pidx) 5418 pause("dquiesce", 1); 5419} 5420 5421static void 5422quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 5423{ 5424 5425 /* XXXTX */ 5426} 5427 5428static void 5429quiesce_iq(struct adapter *sc, struct sge_iq *iq) 5430{ 5431 (void) sc; /* unused */ 5432 5433 /* Synchronize with the interrupt handler */ 5434 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 5435 pause("iqfree", 1); 5436} 5437 5438static void 5439quiesce_fl(struct adapter *sc, struct sge_fl *fl) 5440{ 5441 mtx_lock(&sc->sfl_lock); 5442 FL_LOCK(fl); 5443 fl->flags |= FL_DOOMED; 5444 FL_UNLOCK(fl); 5445 callout_stop(&sc->sfl_callout); 5446 mtx_unlock(&sc->sfl_lock); 5447 5448 KASSERT((fl->flags & FL_STARVING) == 0, 5449 ("%s: still starving", __func__)); 5450} 5451 5452static int 5453t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 5454 driver_intr_t *handler, void *arg, char *name) 5455{ 5456 int rc; 5457 5458 irq->rid = rid; 5459 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 5460 RF_SHAREABLE | RF_ACTIVE); 5461 if (irq->res == NULL) { 5462 device_printf(sc->dev, 5463 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 5464 return (ENOMEM); 5465 } 5466 5467 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 5468 NULL, handler, arg, &irq->tag); 5469 if (rc != 0) { 5470 device_printf(sc->dev, 5471 "failed to setup interrupt for rid %d, name %s: %d\n", 5472 rid, name, rc); 5473 } else if (name) 5474 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 5475 5476 return (rc); 5477} 5478 5479static int 5480t4_free_irq(struct adapter *sc, struct irq *irq) 5481{ 5482 if (irq->tag) 5483 bus_teardown_intr(sc->dev, irq->res, irq->tag); 5484 if (irq->res) 5485 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 5486 5487 bzero(irq, sizeof(*irq)); 5488 5489 return (0); 5490} 5491 5492static void 5493get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 5494{ 5495 5496 regs->version = chip_id(sc) | chip_rev(sc) << 10; 5497 t4_get_regs(sc, buf, regs->len); 5498} 5499 5500#define A_PL_INDIR_CMD 0x1f8 5501 5502#define S_PL_AUTOINC 31 5503#define M_PL_AUTOINC 0x1U 5504#define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 5505#define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 5506 5507#define S_PL_VFID 20 5508#define M_PL_VFID 0xffU 5509#define V_PL_VFID(x) ((x) << S_PL_VFID) 5510#define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 5511 5512#define S_PL_ADDR 0 5513#define M_PL_ADDR 0xfffffU 5514#define V_PL_ADDR(x) ((x) << S_PL_ADDR) 5515#define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 5516 5517#define A_PL_INDIR_DATA 0x1fc 5518 5519static uint64_t 5520read_vf_stat(struct adapter *sc, unsigned int viid, int reg) 5521{ 5522 u32 stats[2]; 5523 5524 mtx_assert(&sc->reg_lock, MA_OWNED); 5525 if (sc->flags & IS_VF) { 5526 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 5527 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 5528 } else { 5529 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5530 V_PL_VFID(G_FW_VIID_VIN(viid)) | 5531 V_PL_ADDR(VF_MPS_REG(reg))); 5532 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 5533 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 5534 } 5535 return (((uint64_t)stats[1]) << 32 | stats[0]); 5536} 5537 5538static void 5539t4_get_vi_stats(struct adapter *sc, unsigned int viid, 5540 struct fw_vi_stats_vf *stats) 5541{ 5542 5543#define GET_STAT(name) \ 5544 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L) 5545 5546 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 5547 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 5548 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 5549 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 5550 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 5551 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 5552 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 5553 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 5554 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 5555 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 5556 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 5557 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 5558 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 5559 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 5560 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 5561 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 5562 5563#undef GET_STAT 5564} 5565 5566static void 5567t4_clr_vi_stats(struct adapter *sc, unsigned int viid) 5568{ 5569 int reg; 5570 5571 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 5572 V_PL_VFID(G_FW_VIID_VIN(viid)) | 5573 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 5574 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 5575 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 5576 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 5577} 5578 5579static void 5580vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 5581{ 5582 struct timeval tv; 5583 const struct timeval interval = {0, 250000}; /* 250ms */ 5584 5585 if (!(vi->flags & VI_INIT_DONE)) 5586 return; 5587 5588 getmicrotime(&tv); 5589 timevalsub(&tv, &interval); 5590 if (timevalcmp(&tv, &vi->last_refreshed, <)) 5591 return; 5592 5593 mtx_lock(&sc->reg_lock); 5594 t4_get_vi_stats(sc, vi->viid, &vi->stats); 5595 getmicrotime(&vi->last_refreshed); 5596 mtx_unlock(&sc->reg_lock); 5597} 5598 5599static void 5600cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 5601{ 5602 u_int i, v, tnl_cong_drops, bg_map; 5603 struct timeval tv; 5604 const struct timeval interval = {0, 250000}; /* 250ms */ 5605 5606 getmicrotime(&tv); 5607 timevalsub(&tv, &interval); 5608 if (timevalcmp(&tv, &pi->last_refreshed, <)) 5609 return; 5610 5611 tnl_cong_drops = 0; 5612 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 5613 bg_map = pi->mps_bg_map; 5614 while (bg_map) { 5615 i = ffs(bg_map) - 1; 5616 mtx_lock(&sc->reg_lock); 5617 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 1, 5618 A_TP_MIB_TNL_CNG_DROP_0 + i); 5619 mtx_unlock(&sc->reg_lock); 5620 tnl_cong_drops += v; 5621 bg_map &= ~(1 << i); 5622 } 5623 pi->tnl_cong_drops = tnl_cong_drops; 5624 getmicrotime(&pi->last_refreshed); 5625} 5626 5627static void 5628cxgbe_tick(void *arg) 5629{ 5630 struct port_info *pi = arg; 5631 struct adapter *sc = pi->adapter; 5632 5633 PORT_LOCK_ASSERT_OWNED(pi); 5634 cxgbe_refresh_stats(sc, pi); 5635 5636 callout_schedule(&pi->tick, hz); 5637} 5638 5639void 5640vi_tick(void *arg) 5641{ 5642 struct vi_info *vi = arg; 5643 struct adapter *sc = vi->pi->adapter; 5644 5645 vi_refresh_stats(sc, vi); 5646 5647 callout_schedule(&vi->tick, hz); 5648} 5649 5650static void 5651cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid) 5652{ 5653 struct ifnet *vlan; 5654 5655 if (arg != ifp || ifp->if_type != IFT_ETHER) 5656 return; 5657 5658 vlan = VLAN_DEVAT(ifp, vid); 5659 VLAN_SETCOOKIE(vlan, ifp); 5660} 5661 5662/* 5663 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 5664 */ 5665static char *caps_decoder[] = { 5666 "\20\001IPMI\002NCSI", /* 0: NBM */ 5667 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 5668 "\20\001INGRESS\002EGRESS", /* 2: switch */ 5669 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 5670 "\006HASHFILTER\007ETHOFLD", 5671 "\20\001TOE", /* 4: TOE */ 5672 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 5673 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 5674 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 5675 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 5676 "\007T10DIF" 5677 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 5678 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 5679 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 5680 "\004PO_INITIATOR\005PO_TARGET", 5681}; 5682 5683void 5684t4_sysctls(struct adapter *sc) 5685{ 5686 struct sysctl_ctx_list *ctx; 5687 struct sysctl_oid *oid; 5688 struct sysctl_oid_list *children, *c0; 5689 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 5690 5691 ctx = device_get_sysctl_ctx(sc->dev); 5692 5693 /* 5694 * dev.t4nex.X. 5695 */ 5696 oid = device_get_sysctl_tree(sc->dev); 5697 c0 = children = SYSCTL_CHILDREN(oid); 5698 5699 sc->sc_do_rxcopy = 1; 5700 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 5701 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 5702 5703 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 5704 sc->params.nports, "# of ports"); 5705 5706 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 5707 CTLTYPE_STRING | CTLFLAG_RD, doorbells, (uintptr_t)&sc->doorbells, 5708 sysctl_bitfield_8b, "A", "available doorbells"); 5709 5710 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 5711 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 5712 5713 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 5714 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 5715 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 5716 "interrupt holdoff timer values (us)"); 5717 5718 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 5719 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 5720 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 5721 "interrupt holdoff packet counter values"); 5722 5723 t4_sge_sysctls(sc, ctx, children); 5724 5725 sc->lro_timeout = 100; 5726 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 5727 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 5728 5729 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 5730 &sc->debug_flags, 0, "flags to enable runtime debugging"); 5731 5732 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 5733 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 5734 5735 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 5736 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 5737 5738 if (sc->flags & IS_VF) 5739 return; 5740 5741 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 5742 NULL, chip_rev(sc), "chip hardware revision"); 5743 5744 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 5745 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 5746 5747 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 5748 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 5749 5750 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 5751 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 5752 5753 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "md_version", 5754 CTLFLAG_RD, sc->params.vpd.md, 0, "manufacturing diags version"); 5755 5756 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 5757 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 5758 5759 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 5760 sc->er_version, 0, "expansion ROM version"); 5761 5762 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 5763 sc->bs_version, 0, "bootstrap firmware version"); 5764 5765 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 5766 NULL, sc->params.scfg_vers, "serial config version"); 5767 5768 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 5769 NULL, sc->params.vpd_vers, "VPD version"); 5770 5771 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 5772 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 5773 5774 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 5775 sc->cfcsum, "config file checksum"); 5776 5777#define SYSCTL_CAP(name, n, text) \ 5778 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 5779 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], (uintptr_t)&sc->name, \ 5780 sysctl_bitfield_16b, "A", "available " text " capabilities") 5781 5782 SYSCTL_CAP(nbmcaps, 0, "NBM"); 5783 SYSCTL_CAP(linkcaps, 1, "link"); 5784 SYSCTL_CAP(switchcaps, 2, "switch"); 5785 SYSCTL_CAP(niccaps, 3, "NIC"); 5786 SYSCTL_CAP(toecaps, 4, "TCP offload"); 5787 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 5788 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 5789 SYSCTL_CAP(cryptocaps, 7, "crypto"); 5790 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 5791#undef SYSCTL_CAP 5792 5793 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 5794 NULL, sc->tids.nftids, "number of filters"); 5795 5796 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 5797 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 5798 "chip temperature (in Celsius)"); 5799 5800 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "loadavg", CTLTYPE_STRING | 5801 CTLFLAG_RD, sc, 0, sysctl_loadavg, "A", 5802 "microprocessor load averages (debug firmwares only)"); 5803 5804 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_vdd", CTLFLAG_RD, 5805 &sc->params.core_vdd, 0, "core Vdd (in mV)"); 5806 5807 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "local_cpus", 5808 CTLTYPE_STRING | CTLFLAG_RD, sc, LOCAL_CPUS, 5809 sysctl_cpus, "A", "local CPUs"); 5810 5811 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_cpus", 5812 CTLTYPE_STRING | CTLFLAG_RD, sc, INTR_CPUS, 5813 sysctl_cpus, "A", "preferred CPUs for interrupts"); 5814 5815 /* 5816 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 5817 */ 5818 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 5819 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 5820 "logs and miscellaneous information"); 5821 children = SYSCTL_CHILDREN(oid); 5822 5823 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 5824 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5825 sysctl_cctrl, "A", "congestion control"); 5826 5827 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 5828 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5829 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 5830 5831 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 5832 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 5833 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 5834 5835 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 5836 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 5837 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 5838 5839 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 5840 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 5841 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 5842 5843 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 5844 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 5845 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 5846 5847 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 5848 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 5849 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 5850 5851 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 5852 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5853 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6, 5854 "A", "CIM logic analyzer"); 5855 5856 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 5857 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5858 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 5859 5860 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 5861 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 5862 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 5863 5864 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 5865 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 5866 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 5867 5868 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 5869 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 5870 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 5871 5872 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 5873 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 5874 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 5875 5876 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 5877 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 5878 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 5879 5880 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 5881 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 5882 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 5883 5884 if (chip_id(sc) > CHELSIO_T4) { 5885 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 5886 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 5887 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 5888 5889 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 5890 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 5891 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 5892 } 5893 5894 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 5895 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5896 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 5897 5898 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 5899 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5900 sysctl_cim_qcfg, "A", "CIM queue configuration"); 5901 5902 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 5903 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5904 sysctl_cpl_stats, "A", "CPL statistics"); 5905 5906 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 5907 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5908 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 5909 5910 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 5911 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5912 sysctl_devlog, "A", "firmware's device log"); 5913 5914 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 5915 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5916 sysctl_fcoe_stats, "A", "FCoE statistics"); 5917 5918 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 5919 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5920 sysctl_hw_sched, "A", "hardware scheduler "); 5921 5922 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 5923 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5924 sysctl_l2t, "A", "hardware L2 table"); 5925 5926 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "smt", 5927 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5928 sysctl_smt, "A", "hardware source MAC table"); 5929 5930 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 5931 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5932 sysctl_lb_stats, "A", "loopback statistics"); 5933 5934 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 5935 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5936 sysctl_meminfo, "A", "memory regions"); 5937 5938 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 5939 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5940 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 5941 "A", "MPS TCAM entries"); 5942 5943 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 5944 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5945 sysctl_path_mtus, "A", "path MTUs"); 5946 5947 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 5948 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5949 sysctl_pm_stats, "A", "PM statistics"); 5950 5951 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 5952 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5953 sysctl_rdma_stats, "A", "RDMA statistics"); 5954 5955 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 5956 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5957 sysctl_tcp_stats, "A", "TCP statistics"); 5958 5959 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 5960 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5961 sysctl_tids, "A", "TID information"); 5962 5963 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 5964 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5965 sysctl_tp_err_stats, "A", "TP error statistics"); 5966 5967 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 5968 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 5969 "TP logic analyzer event capture mask"); 5970 5971 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 5972 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5973 sysctl_tp_la, "A", "TP logic analyzer"); 5974 5975 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 5976 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5977 sysctl_tx_rate, "A", "Tx rate"); 5978 5979 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 5980 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5981 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 5982 5983 if (chip_id(sc) >= CHELSIO_T5) { 5984 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 5985 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5986 sysctl_wcwr_stats, "A", "write combined work requests"); 5987 } 5988 5989#ifdef TCP_OFFLOAD 5990 if (is_offload(sc)) { 5991 int i; 5992 char s[4]; 5993 5994 /* 5995 * dev.t4nex.X.toe. 5996 */ 5997 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 5998 NULL, "TOE parameters"); 5999 children = SYSCTL_CHILDREN(oid); 6000 6001 sc->tt.cong_algorithm = -1; 6002 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_algorithm", 6003 CTLFLAG_RW, &sc->tt.cong_algorithm, 0, "congestion control " 6004 "(-1 = default, 0 = reno, 1 = tahoe, 2 = newreno, " 6005 "3 = highspeed)"); 6006 6007 sc->tt.sndbuf = 256 * 1024; 6008 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 6009 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 6010 6011 sc->tt.ddp = 0; 6012 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 6013 &sc->tt.ddp, 0, "DDP allowed"); 6014 6015 sc->tt.rx_coalesce = 1; 6016 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 6017 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 6018 6019 sc->tt.tls = 0; 6020 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tls", CTLFLAG_RW, 6021 &sc->tt.tls, 0, "Inline TLS allowed"); 6022 6023 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tls_rx_ports", 6024 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tls_rx_ports, 6025 "I", "TCP ports that use inline TLS+TOE RX"); 6026 6027 sc->tt.tx_align = 1; 6028 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 6029 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 6030 6031 sc->tt.tx_zcopy = 0; 6032 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 6033 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 6034 "Enable zero-copy aio_write(2)"); 6035 6036 sc->tt.cop_managed_offloading = !!t4_cop_managed_offloading; 6037 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6038 "cop_managed_offloading", CTLFLAG_RW, 6039 &sc->tt.cop_managed_offloading, 0, 6040 "COP (Connection Offload Policy) controls all TOE offload"); 6041 6042 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 6043 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 6044 "TP timer tick (us)"); 6045 6046 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 6047 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 6048 "TCP timestamp tick (us)"); 6049 6050 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 6051 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 6052 "DACK tick (us)"); 6053 6054 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 6055 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 6056 "IU", "DACK timer (us)"); 6057 6058 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 6059 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 6060 sysctl_tp_timer, "LU", "Minimum retransmit interval (us)"); 6061 6062 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 6063 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 6064 sysctl_tp_timer, "LU", "Maximum retransmit interval (us)"); 6065 6066 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 6067 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 6068 sysctl_tp_timer, "LU", "Persist timer min (us)"); 6069 6070 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 6071 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 6072 sysctl_tp_timer, "LU", "Persist timer max (us)"); 6073 6074 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 6075 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 6076 sysctl_tp_timer, "LU", "Keepalive idle timer (us)"); 6077 6078 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_interval", 6079 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 6080 sysctl_tp_timer, "LU", "Keepalive interval timer (us)"); 6081 6082 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 6083 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 6084 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 6085 6086 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 6087 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 6088 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 6089 6090 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "syn_rexmt_count", 6091 CTLTYPE_UINT | CTLFLAG_RD, sc, S_SYNSHIFTMAX, 6092 sysctl_tp_shift_cnt, "IU", 6093 "Number of SYN retransmissions before abort"); 6094 6095 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_count", 6096 CTLTYPE_UINT | CTLFLAG_RD, sc, S_RXTSHIFTMAXR2, 6097 sysctl_tp_shift_cnt, "IU", 6098 "Number of retransmissions before abort"); 6099 6100 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_count", 6101 CTLTYPE_UINT | CTLFLAG_RD, sc, S_KEEPALIVEMAXR2, 6102 sysctl_tp_shift_cnt, "IU", 6103 "Number of keepalive probes before abort"); 6104 6105 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rexmt_backoff", 6106 CTLFLAG_RD, NULL, "TOE retransmit backoffs"); 6107 children = SYSCTL_CHILDREN(oid); 6108 for (i = 0; i < 16; i++) { 6109 snprintf(s, sizeof(s), "%u", i); 6110 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, s, 6111 CTLTYPE_UINT | CTLFLAG_RD, sc, i, sysctl_tp_backoff, 6112 "IU", "TOE retransmit backoff"); 6113 } 6114 } 6115#endif 6116} 6117 6118void 6119vi_sysctls(struct vi_info *vi) 6120{ 6121 struct sysctl_ctx_list *ctx; 6122 struct sysctl_oid *oid; 6123 struct sysctl_oid_list *children; 6124 6125 ctx = device_get_sysctl_ctx(vi->dev); 6126 6127 /* 6128 * dev.v?(cxgbe|cxl).X. 6129 */ 6130 oid = device_get_sysctl_tree(vi->dev); 6131 children = SYSCTL_CHILDREN(oid); 6132 6133 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 6134 vi->viid, "VI identifer"); 6135 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 6136 &vi->nrxq, 0, "# of rx queues"); 6137 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 6138 &vi->ntxq, 0, "# of tx queues"); 6139 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 6140 &vi->first_rxq, 0, "index of first rx queue"); 6141 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 6142 &vi->first_txq, 0, "index of first tx queue"); 6143 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 6144 vi->rss_size, "size of RSS indirection table"); 6145 6146 if (IS_MAIN_VI(vi)) { 6147 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 6148 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 6149 "Reserve queue 0 for non-flowid packets"); 6150 } 6151 6152#ifdef TCP_OFFLOAD 6153 if (vi->nofldrxq != 0) { 6154 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 6155 &vi->nofldrxq, 0, 6156 "# of rx queues for offloaded TCP connections"); 6157 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 6158 &vi->nofldtxq, 0, 6159 "# of tx queues for offloaded TCP connections"); 6160 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 6161 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 6162 "index of first TOE rx queue"); 6163 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 6164 CTLFLAG_RD, &vi->first_ofld_txq, 0, 6165 "index of first TOE tx queue"); 6166 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx_ofld", 6167 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 6168 sysctl_holdoff_tmr_idx_ofld, "I", 6169 "holdoff timer index for TOE queues"); 6170 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx_ofld", 6171 CTLTYPE_INT | CTLFLAG_RW, vi, 0, 6172 sysctl_holdoff_pktc_idx_ofld, "I", 6173 "holdoff packet counter index for TOE queues"); 6174 } 6175#endif 6176#ifdef DEV_NETMAP 6177 if (vi->nnmrxq != 0) { 6178 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 6179 &vi->nnmrxq, 0, "# of netmap rx queues"); 6180 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 6181 &vi->nnmtxq, 0, "# of netmap tx queues"); 6182 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 6183 CTLFLAG_RD, &vi->first_nm_rxq, 0, 6184 "index of first netmap rx queue"); 6185 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 6186 CTLFLAG_RD, &vi->first_nm_txq, 0, 6187 "index of first netmap tx queue"); 6188 } 6189#endif 6190 6191 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 6192 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 6193 "holdoff timer index"); 6194 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 6195 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 6196 "holdoff packet counter index"); 6197 6198 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 6199 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 6200 "rx queue size"); 6201 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 6202 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 6203 "tx queue size"); 6204} 6205 6206static void 6207cxgbe_sysctls(struct port_info *pi) 6208{ 6209 struct sysctl_ctx_list *ctx; 6210 struct sysctl_oid *oid; 6211 struct sysctl_oid_list *children, *children2; 6212 struct adapter *sc = pi->adapter; 6213 int i; 6214 char name[16]; 6215 static char *tc_flags = {"\20\1USER\2SYNC\3ASYNC\4ERR"}; 6216 6217 ctx = device_get_sysctl_ctx(pi->dev); 6218 6219 /* 6220 * dev.cxgbe.X. 6221 */ 6222 oid = device_get_sysctl_tree(pi->dev); 6223 children = SYSCTL_CHILDREN(oid); 6224 6225 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 6226 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 6227 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 6228 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 6229 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 6230 "PHY temperature (in Celsius)"); 6231 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 6232 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 6233 "PHY firmware version"); 6234 } 6235 6236 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 6237 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A", 6238 "PAUSE settings (bit 0 = rx_pause, 1 = tx_pause, 2 = pause_autoneg)"); 6239 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 6240 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A", 6241 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 6242 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 6243 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I", 6244 "autonegotiation (-1 = not supported)"); 6245 6246 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 6247 port_top_speed(pi), "max speed (in Gbps)"); 6248 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "mps_bg_map", CTLFLAG_RD, NULL, 6249 pi->mps_bg_map, "MPS buffer group map"); 6250 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_e_chan_map", CTLFLAG_RD, 6251 NULL, pi->rx_e_chan_map, "TP rx e-channel map"); 6252 6253 if (sc->flags & IS_VF) 6254 return; 6255 6256 /* 6257 * dev.(cxgbe|cxl).X.tc. 6258 */ 6259 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 6260 "Tx scheduler traffic classes (cl_rl)"); 6261 children2 = SYSCTL_CHILDREN(oid); 6262 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "pktsize", 6263 CTLFLAG_RW, &pi->sched_params->pktsize, 0, 6264 "pktsize for per-flow cl-rl (0 means up to the driver )"); 6265 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "burstsize", 6266 CTLFLAG_RW, &pi->sched_params->burstsize, 0, 6267 "burstsize for per-flow cl-rl (0 means up to the driver)"); 6268 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 6269 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i]; 6270 6271 snprintf(name, sizeof(name), "%d", i); 6272 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 6273 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 6274 "traffic class")); 6275 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "flags", 6276 CTLTYPE_STRING | CTLFLAG_RD, tc_flags, (uintptr_t)&tc->flags, 6277 sysctl_bitfield_8b, "A", "flags"); 6278 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 6279 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 6280 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 6281 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 6282 sysctl_tc_params, "A", "traffic class parameters"); 6283 } 6284 6285 /* 6286 * dev.cxgbe.X.stats. 6287 */ 6288 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 6289 NULL, "port statistics"); 6290 children = SYSCTL_CHILDREN(oid); 6291 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 6292 &pi->tx_parse_error, 0, 6293 "# of tx packets with invalid length or # of segments"); 6294 6295#define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 6296 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 6297 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 6298 sysctl_handle_t4_reg64, "QU", desc) 6299 6300 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 6301 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 6302 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 6303 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 6304 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 6305 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 6306 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 6307 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 6308 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 6309 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 6310 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 6311 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 6312 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 6313 "# of tx frames in this range", 6314 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 6315 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 6316 "# of tx frames in this range", 6317 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 6318 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 6319 "# of tx frames in this range", 6320 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 6321 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 6322 "# of tx frames in this range", 6323 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 6324 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 6325 "# of tx frames in this range", 6326 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 6327 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 6328 "# of tx frames in this range", 6329 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 6330 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 6331 "# of tx frames in this range", 6332 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 6333 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 6334 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 6335 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 6336 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 6337 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 6338 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 6339 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 6340 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 6341 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 6342 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 6343 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 6344 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 6345 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 6346 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 6347 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 6348 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 6349 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 6350 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 6351 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 6352 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 6353 6354 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 6355 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 6356 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 6357 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 6358 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 6359 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 6360 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 6361 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 6362 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 6363 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 6364 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 6365 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 6366 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 6367 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 6368 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 6369 "# of frames received with bad FCS", 6370 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 6371 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 6372 "# of frames received with length error", 6373 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 6374 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 6375 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 6376 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 6377 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 6378 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 6379 "# of rx frames in this range", 6380 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 6381 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 6382 "# of rx frames in this range", 6383 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 6384 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 6385 "# of rx frames in this range", 6386 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 6387 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 6388 "# of rx frames in this range", 6389 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 6390 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 6391 "# of rx frames in this range", 6392 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 6393 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 6394 "# of rx frames in this range", 6395 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 6396 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 6397 "# of rx frames in this range", 6398 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 6399 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 6400 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 6401 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 6402 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 6403 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 6404 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 6405 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 6406 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 6407 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 6408 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 6409 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 6410 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 6411 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 6412 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 6413 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 6414 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 6415 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 6416 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 6417 6418#undef SYSCTL_ADD_T4_REG64 6419 6420#define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 6421 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 6422 &pi->stats.name, desc) 6423 6424 /* We get these from port_stats and they may be stale by up to 1s */ 6425 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 6426 "# drops due to buffer-group 0 overflows"); 6427 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 6428 "# drops due to buffer-group 1 overflows"); 6429 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 6430 "# drops due to buffer-group 2 overflows"); 6431 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 6432 "# drops due to buffer-group 3 overflows"); 6433 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 6434 "# of buffer-group 0 truncated packets"); 6435 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 6436 "# of buffer-group 1 truncated packets"); 6437 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 6438 "# of buffer-group 2 truncated packets"); 6439 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 6440 "# of buffer-group 3 truncated packets"); 6441 6442#undef SYSCTL_ADD_T4_PORTSTAT 6443 6444 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_records", 6445 CTLFLAG_RD, &pi->tx_tls_records, 6446 "# of TLS records transmitted"); 6447 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "tx_tls_octets", 6448 CTLFLAG_RD, &pi->tx_tls_octets, 6449 "# of payload octets in transmitted TLS records"); 6450 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_records", 6451 CTLFLAG_RD, &pi->rx_tls_records, 6452 "# of TLS records received"); 6453 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "rx_tls_octets", 6454 CTLFLAG_RD, &pi->rx_tls_octets, 6455 "# of payload octets in received TLS records"); 6456} 6457 6458static int 6459sysctl_int_array(SYSCTL_HANDLER_ARGS) 6460{ 6461 int rc, *i, space = 0; 6462 struct sbuf sb; 6463 6464 sbuf_new_for_sysctl(&sb, NULL, 64, req); 6465 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 6466 if (space) 6467 sbuf_printf(&sb, " "); 6468 sbuf_printf(&sb, "%d", *i); 6469 space = 1; 6470 } 6471 rc = sbuf_finish(&sb); 6472 sbuf_delete(&sb); 6473 return (rc); 6474} 6475 6476static int 6477sysctl_bitfield_8b(SYSCTL_HANDLER_ARGS) 6478{ 6479 int rc; 6480 struct sbuf *sb; 6481 6482 rc = sysctl_wire_old_buffer(req, 0); 6483 if (rc != 0) 6484 return(rc); 6485 6486 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6487 if (sb == NULL) 6488 return (ENOMEM); 6489 6490 sbuf_printf(sb, "%b", *(uint8_t *)(uintptr_t)arg2, (char *)arg1); 6491 rc = sbuf_finish(sb); 6492 sbuf_delete(sb); 6493 6494 return (rc); 6495} 6496 6497static int 6498sysctl_bitfield_16b(SYSCTL_HANDLER_ARGS) 6499{ 6500 int rc; 6501 struct sbuf *sb; 6502 6503 rc = sysctl_wire_old_buffer(req, 0); 6504 if (rc != 0) 6505 return(rc); 6506 6507 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6508 if (sb == NULL) 6509 return (ENOMEM); 6510 6511 sbuf_printf(sb, "%b", *(uint16_t *)(uintptr_t)arg2, (char *)arg1); 6512 rc = sbuf_finish(sb); 6513 sbuf_delete(sb); 6514 6515 return (rc); 6516} 6517 6518static int 6519sysctl_btphy(SYSCTL_HANDLER_ARGS) 6520{ 6521 struct port_info *pi = arg1; 6522 int op = arg2; 6523 struct adapter *sc = pi->adapter; 6524 u_int v; 6525 int rc; 6526 6527 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 6528 if (rc) 6529 return (rc); 6530 /* XXX: magic numbers */ 6531 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 6532 &v); 6533 end_synchronized_op(sc, 0); 6534 if (rc) 6535 return (rc); 6536 if (op == 0) 6537 v /= 256; 6538 6539 rc = sysctl_handle_int(oidp, &v, 0, req); 6540 return (rc); 6541} 6542 6543static int 6544sysctl_noflowq(SYSCTL_HANDLER_ARGS) 6545{ 6546 struct vi_info *vi = arg1; 6547 int rc, val; 6548 6549 val = vi->rsrv_noflowq; 6550 rc = sysctl_handle_int(oidp, &val, 0, req); 6551 if (rc != 0 || req->newptr == NULL) 6552 return (rc); 6553 6554 if ((val >= 1) && (vi->ntxq > 1)) 6555 vi->rsrv_noflowq = 1; 6556 else 6557 vi->rsrv_noflowq = 0; 6558 6559 return (rc); 6560} 6561 6562static int 6563sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 6564{ 6565 struct vi_info *vi = arg1; 6566 struct adapter *sc = vi->pi->adapter; 6567 int idx, rc, i; 6568 struct sge_rxq *rxq; 6569 uint8_t v; 6570 6571 idx = vi->tmr_idx; 6572 6573 rc = sysctl_handle_int(oidp, &idx, 0, req); 6574 if (rc != 0 || req->newptr == NULL) 6575 return (rc); 6576 6577 if (idx < 0 || idx >= SGE_NTIMERS) 6578 return (EINVAL); 6579 6580 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6581 "t4tmr"); 6582 if (rc) 6583 return (rc); 6584 6585 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 6586 for_each_rxq(vi, i, rxq) { 6587#ifdef atomic_store_rel_8 6588 atomic_store_rel_8(&rxq->iq.intr_params, v); 6589#else 6590 rxq->iq.intr_params = v; 6591#endif 6592 } 6593 vi->tmr_idx = idx; 6594 6595 end_synchronized_op(sc, LOCK_HELD); 6596 return (0); 6597} 6598 6599static int 6600sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 6601{ 6602 struct vi_info *vi = arg1; 6603 struct adapter *sc = vi->pi->adapter; 6604 int idx, rc; 6605 6606 idx = vi->pktc_idx; 6607 6608 rc = sysctl_handle_int(oidp, &idx, 0, req); 6609 if (rc != 0 || req->newptr == NULL) 6610 return (rc); 6611 6612 if (idx < -1 || idx >= SGE_NCOUNTERS) 6613 return (EINVAL); 6614 6615 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6616 "t4pktc"); 6617 if (rc) 6618 return (rc); 6619 6620 if (vi->flags & VI_INIT_DONE) 6621 rc = EBUSY; /* cannot be changed once the queues are created */ 6622 else 6623 vi->pktc_idx = idx; 6624 6625 end_synchronized_op(sc, LOCK_HELD); 6626 return (rc); 6627} 6628 6629static int 6630sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 6631{ 6632 struct vi_info *vi = arg1; 6633 struct adapter *sc = vi->pi->adapter; 6634 int qsize, rc; 6635 6636 qsize = vi->qsize_rxq; 6637 6638 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6639 if (rc != 0 || req->newptr == NULL) 6640 return (rc); 6641 6642 if (qsize < 128 || (qsize & 7)) 6643 return (EINVAL); 6644 6645 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6646 "t4rxqs"); 6647 if (rc) 6648 return (rc); 6649 6650 if (vi->flags & VI_INIT_DONE) 6651 rc = EBUSY; /* cannot be changed once the queues are created */ 6652 else 6653 vi->qsize_rxq = qsize; 6654 6655 end_synchronized_op(sc, LOCK_HELD); 6656 return (rc); 6657} 6658 6659static int 6660sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 6661{ 6662 struct vi_info *vi = arg1; 6663 struct adapter *sc = vi->pi->adapter; 6664 int qsize, rc; 6665 6666 qsize = vi->qsize_txq; 6667 6668 rc = sysctl_handle_int(oidp, &qsize, 0, req); 6669 if (rc != 0 || req->newptr == NULL) 6670 return (rc); 6671 6672 if (qsize < 128 || qsize > 65536) 6673 return (EINVAL); 6674 6675 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 6676 "t4txqs"); 6677 if (rc) 6678 return (rc); 6679 6680 if (vi->flags & VI_INIT_DONE) 6681 rc = EBUSY; /* cannot be changed once the queues are created */ 6682 else 6683 vi->qsize_txq = qsize; 6684 6685 end_synchronized_op(sc, LOCK_HELD); 6686 return (rc); 6687} 6688 6689static int 6690sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 6691{ 6692 struct port_info *pi = arg1; 6693 struct adapter *sc = pi->adapter; 6694 struct link_config *lc = &pi->link_cfg; 6695 int rc; 6696 6697 if (req->newptr == NULL) { 6698 struct sbuf *sb; 6699 static char *bits = "\20\1RX\2TX\3AUTO"; 6700 6701 rc = sysctl_wire_old_buffer(req, 0); 6702 if (rc != 0) 6703 return(rc); 6704 6705 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6706 if (sb == NULL) 6707 return (ENOMEM); 6708 6709 if (lc->link_ok) { 6710 sbuf_printf(sb, "%b", (lc->fc & (PAUSE_TX | PAUSE_RX)) | 6711 (lc->requested_fc & PAUSE_AUTONEG), bits); 6712 } else { 6713 sbuf_printf(sb, "%b", lc->requested_fc & (PAUSE_TX | 6714 PAUSE_RX | PAUSE_AUTONEG), bits); 6715 } 6716 rc = sbuf_finish(sb); 6717 sbuf_delete(sb); 6718 } else { 6719 char s[2]; 6720 int n; 6721 6722 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX | 6723 PAUSE_AUTONEG)); 6724 s[1] = 0; 6725 6726 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6727 if (rc != 0) 6728 return(rc); 6729 6730 if (s[1] != 0) 6731 return (EINVAL); 6732 if (s[0] < '0' || s[0] > '9') 6733 return (EINVAL); /* not a number */ 6734 n = s[0] - '0'; 6735 if (n & ~(PAUSE_TX | PAUSE_RX | PAUSE_AUTONEG)) 6736 return (EINVAL); /* some other bit is set too */ 6737 6738 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6739 "t4PAUSE"); 6740 if (rc) 6741 return (rc); 6742 PORT_LOCK(pi); 6743 lc->requested_fc = n; 6744 fixup_link_config(pi); 6745 if (pi->up_vis > 0) 6746 rc = apply_link_config(pi); 6747 set_current_media(pi); 6748 PORT_UNLOCK(pi); 6749 end_synchronized_op(sc, 0); 6750 } 6751 6752 return (rc); 6753} 6754 6755static int 6756sysctl_fec(SYSCTL_HANDLER_ARGS) 6757{ 6758 struct port_info *pi = arg1; 6759 struct adapter *sc = pi->adapter; 6760 struct link_config *lc = &pi->link_cfg; 6761 int rc; 6762 int8_t old; 6763 6764 if (req->newptr == NULL) { 6765 struct sbuf *sb; 6766 static char *bits = "\20\1RS\2BASE-R\3RSVD1\4RSVD2\5RSVD3\6AUTO"; 6767 6768 rc = sysctl_wire_old_buffer(req, 0); 6769 if (rc != 0) 6770 return(rc); 6771 6772 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 6773 if (sb == NULL) 6774 return (ENOMEM); 6775 6776 /* 6777 * Display the requested_fec when the link is down -- the actual 6778 * FEC makes sense only when the link is up. 6779 */ 6780 if (lc->link_ok) { 6781 sbuf_printf(sb, "%b", (lc->fec & M_FW_PORT_CAP32_FEC) | 6782 (lc->requested_fec & FEC_AUTO), bits); 6783 } else { 6784 sbuf_printf(sb, "%b", lc->requested_fec, bits); 6785 } 6786 rc = sbuf_finish(sb); 6787 sbuf_delete(sb); 6788 } else { 6789 char s[3]; 6790 int n; 6791 6792 snprintf(s, sizeof(s), "%d", 6793 lc->requested_fec == FEC_AUTO ? -1 : 6794 lc->requested_fec & M_FW_PORT_CAP32_FEC); 6795 6796 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 6797 if (rc != 0) 6798 return(rc); 6799 6800 n = strtol(&s[0], NULL, 0); 6801 if (n < 0 || n & FEC_AUTO) 6802 n = FEC_AUTO; 6803 else { 6804 if (n & ~M_FW_PORT_CAP32_FEC) 6805 return (EINVAL);/* some other bit is set too */ 6806 if (!powerof2(n)) 6807 return (EINVAL);/* one bit can be set at most */ 6808 } 6809 6810 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6811 "t4fec"); 6812 if (rc) 6813 return (rc); 6814 PORT_LOCK(pi); 6815 old = lc->requested_fec; 6816 if (n == FEC_AUTO) 6817 lc->requested_fec = FEC_AUTO; 6818 else if (n == 0) 6819 lc->requested_fec = FEC_NONE; 6820 else { 6821 if ((lc->supported | V_FW_PORT_CAP32_FEC(n)) != 6822 lc->supported) { 6823 rc = ENOTSUP; 6824 goto done; 6825 } 6826 lc->requested_fec = n; 6827 } 6828 fixup_link_config(pi); 6829 if (pi->up_vis > 0) { 6830 rc = apply_link_config(pi); 6831 if (rc != 0) { 6832 lc->requested_fec = old; 6833 if (rc == FW_EPROTO) 6834 rc = ENOTSUP; 6835 } 6836 } 6837done: 6838 PORT_UNLOCK(pi); 6839 end_synchronized_op(sc, 0); 6840 } 6841 6842 return (rc); 6843} 6844 6845static int 6846sysctl_autoneg(SYSCTL_HANDLER_ARGS) 6847{ 6848 struct port_info *pi = arg1; 6849 struct adapter *sc = pi->adapter; 6850 struct link_config *lc = &pi->link_cfg; 6851 int rc, val; 6852 6853 if (lc->supported & FW_PORT_CAP32_ANEG) 6854 val = lc->requested_aneg == AUTONEG_DISABLE ? 0 : 1; 6855 else 6856 val = -1; 6857 rc = sysctl_handle_int(oidp, &val, 0, req); 6858 if (rc != 0 || req->newptr == NULL) 6859 return (rc); 6860 if (val == 0) 6861 val = AUTONEG_DISABLE; 6862 else if (val == 1) 6863 val = AUTONEG_ENABLE; 6864 else 6865 val = AUTONEG_AUTO; 6866 6867 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 6868 "t4aneg"); 6869 if (rc) 6870 return (rc); 6871 PORT_LOCK(pi); 6872 if (val == AUTONEG_ENABLE && !(lc->supported & FW_PORT_CAP32_ANEG)) { 6873 rc = ENOTSUP; 6874 goto done; 6875 } 6876 lc->requested_aneg = val; 6877 fixup_link_config(pi); 6878 if (pi->up_vis > 0) 6879 rc = apply_link_config(pi); 6880 set_current_media(pi); 6881done: 6882 PORT_UNLOCK(pi); 6883 end_synchronized_op(sc, 0); 6884 return (rc); 6885} 6886 6887static int 6888sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 6889{ 6890 struct adapter *sc = arg1; 6891 int reg = arg2; 6892 uint64_t val; 6893 6894 val = t4_read_reg64(sc, reg); 6895 6896 return (sysctl_handle_64(oidp, &val, 0, req)); 6897} 6898 6899static int 6900sysctl_temperature(SYSCTL_HANDLER_ARGS) 6901{ 6902 struct adapter *sc = arg1; 6903 int rc, t; 6904 uint32_t param, val; 6905 6906 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 6907 if (rc) 6908 return (rc); 6909 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6910 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 6911 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 6912 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 6913 end_synchronized_op(sc, 0); 6914 if (rc) 6915 return (rc); 6916 6917 /* unknown is returned as 0 but we display -1 in that case */ 6918 t = val == 0 ? -1 : val; 6919 6920 rc = sysctl_handle_int(oidp, &t, 0, req); 6921 return (rc); 6922} 6923 6924static int 6925sysctl_loadavg(SYSCTL_HANDLER_ARGS) 6926{ 6927 struct adapter *sc = arg1; 6928 struct sbuf *sb; 6929 int rc; 6930 uint32_t param, val; 6931 6932 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4lavg"); 6933 if (rc) 6934 return (rc); 6935 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6936 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_LOAD); 6937 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 6938 end_synchronized_op(sc, 0); 6939 if (rc) 6940 return (rc); 6941 6942 rc = sysctl_wire_old_buffer(req, 0); 6943 if (rc != 0) 6944 return (rc); 6945 6946 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6947 if (sb == NULL) 6948 return (ENOMEM); 6949 6950 if (val == 0xffffffff) { 6951 /* Only debug and custom firmwares report load averages. */ 6952 sbuf_printf(sb, "not available"); 6953 } else { 6954 sbuf_printf(sb, "%d %d %d", val & 0xff, (val >> 8) & 0xff, 6955 (val >> 16) & 0xff); 6956 } 6957 rc = sbuf_finish(sb); 6958 sbuf_delete(sb); 6959 6960 return (rc); 6961} 6962 6963static int 6964sysctl_cctrl(SYSCTL_HANDLER_ARGS) 6965{ 6966 struct adapter *sc = arg1; 6967 struct sbuf *sb; 6968 int rc, i; 6969 uint16_t incr[NMTUS][NCCTRL_WIN]; 6970 static const char *dec_fac[] = { 6971 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 6972 "0.9375" 6973 }; 6974 6975 rc = sysctl_wire_old_buffer(req, 0); 6976 if (rc != 0) 6977 return (rc); 6978 6979 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6980 if (sb == NULL) 6981 return (ENOMEM); 6982 6983 t4_read_cong_tbl(sc, incr); 6984 6985 for (i = 0; i < NCCTRL_WIN; ++i) { 6986 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 6987 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 6988 incr[5][i], incr[6][i], incr[7][i]); 6989 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 6990 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 6991 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 6992 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 6993 } 6994 6995 rc = sbuf_finish(sb); 6996 sbuf_delete(sb); 6997 6998 return (rc); 6999} 7000 7001static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 7002 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 7003 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 7004 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 7005}; 7006 7007static int 7008sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 7009{ 7010 struct adapter *sc = arg1; 7011 struct sbuf *sb; 7012 int rc, i, n, qid = arg2; 7013 uint32_t *buf, *p; 7014 char *qtype; 7015 u_int cim_num_obq = sc->chip_params->cim_num_obq; 7016 7017 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 7018 ("%s: bad qid %d\n", __func__, qid)); 7019 7020 if (qid < CIM_NUM_IBQ) { 7021 /* inbound queue */ 7022 qtype = "IBQ"; 7023 n = 4 * CIM_IBQ_SIZE; 7024 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7025 rc = t4_read_cim_ibq(sc, qid, buf, n); 7026 } else { 7027 /* outbound queue */ 7028 qtype = "OBQ"; 7029 qid -= CIM_NUM_IBQ; 7030 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 7031 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 7032 rc = t4_read_cim_obq(sc, qid, buf, n); 7033 } 7034 7035 if (rc < 0) { 7036 rc = -rc; 7037 goto done; 7038 } 7039 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 7040 7041 rc = sysctl_wire_old_buffer(req, 0); 7042 if (rc != 0) 7043 goto done; 7044 7045 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7046 if (sb == NULL) { 7047 rc = ENOMEM; 7048 goto done; 7049 } 7050 7051 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 7052 for (i = 0, p = buf; i < n; i += 16, p += 4) 7053 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 7054 p[2], p[3]); 7055 7056 rc = sbuf_finish(sb); 7057 sbuf_delete(sb); 7058done: 7059 free(buf, M_CXGBE); 7060 return (rc); 7061} 7062 7063static int 7064sysctl_cim_la(SYSCTL_HANDLER_ARGS) 7065{ 7066 struct adapter *sc = arg1; 7067 u_int cfg; 7068 struct sbuf *sb; 7069 uint32_t *buf, *p; 7070 int rc; 7071 7072 MPASS(chip_id(sc) <= CHELSIO_T5); 7073 7074 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 7075 if (rc != 0) 7076 return (rc); 7077 7078 rc = sysctl_wire_old_buffer(req, 0); 7079 if (rc != 0) 7080 return (rc); 7081 7082 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7083 if (sb == NULL) 7084 return (ENOMEM); 7085 7086 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 7087 M_ZERO | M_WAITOK); 7088 7089 rc = -t4_cim_read_la(sc, buf, NULL); 7090 if (rc != 0) 7091 goto done; 7092 7093 sbuf_printf(sb, "Status Data PC%s", 7094 cfg & F_UPDBGLACAPTPCONLY ? "" : 7095 " LS0Stat LS0Addr LS0Data"); 7096 7097 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 7098 if (cfg & F_UPDBGLACAPTPCONLY) { 7099 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 7100 p[6], p[7]); 7101 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 7102 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 7103 p[4] & 0xff, p[5] >> 8); 7104 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 7105 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7106 p[1] & 0xf, p[2] >> 4); 7107 } else { 7108 sbuf_printf(sb, 7109 "\n %02x %x%07x %x%07x %08x %08x " 7110 "%08x%08x%08x%08x", 7111 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 7112 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 7113 p[6], p[7]); 7114 } 7115 } 7116 7117 rc = sbuf_finish(sb); 7118 sbuf_delete(sb); 7119done: 7120 free(buf, M_CXGBE); 7121 return (rc); 7122} 7123 7124static int 7125sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS) 7126{ 7127 struct adapter *sc = arg1; 7128 u_int cfg; 7129 struct sbuf *sb; 7130 uint32_t *buf, *p; 7131 int rc; 7132 7133 MPASS(chip_id(sc) > CHELSIO_T5); 7134 7135 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 7136 if (rc != 0) 7137 return (rc); 7138 7139 rc = sysctl_wire_old_buffer(req, 0); 7140 if (rc != 0) 7141 return (rc); 7142 7143 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7144 if (sb == NULL) 7145 return (ENOMEM); 7146 7147 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 7148 M_ZERO | M_WAITOK); 7149 7150 rc = -t4_cim_read_la(sc, buf, NULL); 7151 if (rc != 0) 7152 goto done; 7153 7154 sbuf_printf(sb, "Status Inst Data PC%s", 7155 cfg & F_UPDBGLACAPTPCONLY ? "" : 7156 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 7157 7158 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 7159 if (cfg & F_UPDBGLACAPTPCONLY) { 7160 sbuf_printf(sb, "\n %02x %08x %08x %08x", 7161 p[3] & 0xff, p[2], p[1], p[0]); 7162 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 7163 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 7164 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 7165 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 7166 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 7167 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 7168 p[6] >> 16); 7169 } else { 7170 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 7171 "%08x %08x %08x %08x %08x %08x", 7172 (p[9] >> 16) & 0xff, 7173 p[9] & 0xffff, p[8] >> 16, 7174 p[8] & 0xffff, p[7] >> 16, 7175 p[7] & 0xffff, p[6] >> 16, 7176 p[2], p[1], p[0], p[5], p[4], p[3]); 7177 } 7178 } 7179 7180 rc = sbuf_finish(sb); 7181 sbuf_delete(sb); 7182done: 7183 free(buf, M_CXGBE); 7184 return (rc); 7185} 7186 7187static int 7188sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 7189{ 7190 struct adapter *sc = arg1; 7191 u_int i; 7192 struct sbuf *sb; 7193 uint32_t *buf, *p; 7194 int rc; 7195 7196 rc = sysctl_wire_old_buffer(req, 0); 7197 if (rc != 0) 7198 return (rc); 7199 7200 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7201 if (sb == NULL) 7202 return (ENOMEM); 7203 7204 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 7205 M_ZERO | M_WAITOK); 7206 7207 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 7208 p = buf; 7209 7210 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 7211 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 7212 p[1], p[0]); 7213 } 7214 7215 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 7216 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 7217 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 7218 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 7219 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 7220 (p[1] >> 2) | ((p[2] & 3) << 30), 7221 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 7222 p[0] & 1); 7223 } 7224 7225 rc = sbuf_finish(sb); 7226 sbuf_delete(sb); 7227 free(buf, M_CXGBE); 7228 return (rc); 7229} 7230 7231static int 7232sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 7233{ 7234 struct adapter *sc = arg1; 7235 u_int i; 7236 struct sbuf *sb; 7237 uint32_t *buf, *p; 7238 int rc; 7239 7240 rc = sysctl_wire_old_buffer(req, 0); 7241 if (rc != 0) 7242 return (rc); 7243 7244 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7245 if (sb == NULL) 7246 return (ENOMEM); 7247 7248 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 7249 M_ZERO | M_WAITOK); 7250 7251 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 7252 p = buf; 7253 7254 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 7255 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 7256 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 7257 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 7258 p[4], p[3], p[2], p[1], p[0]); 7259 } 7260 7261 sbuf_printf(sb, "\n\nCntl ID Data"); 7262 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 7263 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 7264 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 7265 } 7266 7267 rc = sbuf_finish(sb); 7268 sbuf_delete(sb); 7269 free(buf, M_CXGBE); 7270 return (rc); 7271} 7272 7273static int 7274sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 7275{ 7276 struct adapter *sc = arg1; 7277 struct sbuf *sb; 7278 int rc, i; 7279 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 7280 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 7281 uint16_t thres[CIM_NUM_IBQ]; 7282 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 7283 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 7284 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 7285 7286 cim_num_obq = sc->chip_params->cim_num_obq; 7287 if (is_t4(sc)) { 7288 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 7289 obq_rdaddr = A_UP_OBQ_0_REALADDR; 7290 } else { 7291 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 7292 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 7293 } 7294 nq = CIM_NUM_IBQ + cim_num_obq; 7295 7296 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 7297 if (rc == 0) 7298 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 7299 if (rc != 0) 7300 return (rc); 7301 7302 t4_read_cimq_cfg(sc, base, size, thres); 7303 7304 rc = sysctl_wire_old_buffer(req, 0); 7305 if (rc != 0) 7306 return (rc); 7307 7308 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 7309 if (sb == NULL) 7310 return (ENOMEM); 7311 7312 sbuf_printf(sb, 7313 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 7314 7315 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 7316 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 7317 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 7318 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7319 G_QUEREMFLITS(p[2]) * 16); 7320 for ( ; i < nq; i++, p += 4, wr += 2) 7321 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 7322 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 7323 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 7324 G_QUEREMFLITS(p[2]) * 16); 7325 7326 rc = sbuf_finish(sb); 7327 sbuf_delete(sb); 7328 7329 return (rc); 7330} 7331 7332static int 7333sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 7334{ 7335 struct adapter *sc = arg1; 7336 struct sbuf *sb; 7337 int rc; 7338 struct tp_cpl_stats stats; 7339 7340 rc = sysctl_wire_old_buffer(req, 0); 7341 if (rc != 0) 7342 return (rc); 7343 7344 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7345 if (sb == NULL) 7346 return (ENOMEM); 7347 7348 mtx_lock(&sc->reg_lock); 7349 t4_tp_get_cpl_stats(sc, &stats, 0); 7350 mtx_unlock(&sc->reg_lock); 7351 7352 if (sc->chip_params->nchan > 2) { 7353 sbuf_printf(sb, " channel 0 channel 1" 7354 " channel 2 channel 3"); 7355 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 7356 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 7357 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 7358 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 7359 } else { 7360 sbuf_printf(sb, " channel 0 channel 1"); 7361 sbuf_printf(sb, "\nCPL requests: %10u %10u", 7362 stats.req[0], stats.req[1]); 7363 sbuf_printf(sb, "\nCPL responses: %10u %10u", 7364 stats.rsp[0], stats.rsp[1]); 7365 } 7366 7367 rc = sbuf_finish(sb); 7368 sbuf_delete(sb); 7369 7370 return (rc); 7371} 7372 7373static int 7374sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 7375{ 7376 struct adapter *sc = arg1; 7377 struct sbuf *sb; 7378 int rc; 7379 struct tp_usm_stats stats; 7380 7381 rc = sysctl_wire_old_buffer(req, 0); 7382 if (rc != 0) 7383 return(rc); 7384 7385 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7386 if (sb == NULL) 7387 return (ENOMEM); 7388 7389 t4_get_usm_stats(sc, &stats, 1); 7390 7391 sbuf_printf(sb, "Frames: %u\n", stats.frames); 7392 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 7393 sbuf_printf(sb, "Drops: %u", stats.drops); 7394 7395 rc = sbuf_finish(sb); 7396 sbuf_delete(sb); 7397 7398 return (rc); 7399} 7400 7401static const char * const devlog_level_strings[] = { 7402 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 7403 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 7404 [FW_DEVLOG_LEVEL_ERR] = "ERR", 7405 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 7406 [FW_DEVLOG_LEVEL_INFO] = "INFO", 7407 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 7408}; 7409 7410static const char * const devlog_facility_strings[] = { 7411 [FW_DEVLOG_FACILITY_CORE] = "CORE", 7412 [FW_DEVLOG_FACILITY_CF] = "CF", 7413 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 7414 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 7415 [FW_DEVLOG_FACILITY_RES] = "RES", 7416 [FW_DEVLOG_FACILITY_HW] = "HW", 7417 [FW_DEVLOG_FACILITY_FLR] = "FLR", 7418 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 7419 [FW_DEVLOG_FACILITY_PHY] = "PHY", 7420 [FW_DEVLOG_FACILITY_MAC] = "MAC", 7421 [FW_DEVLOG_FACILITY_PORT] = "PORT", 7422 [FW_DEVLOG_FACILITY_VI] = "VI", 7423 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 7424 [FW_DEVLOG_FACILITY_ACL] = "ACL", 7425 [FW_DEVLOG_FACILITY_TM] = "TM", 7426 [FW_DEVLOG_FACILITY_QFC] = "QFC", 7427 [FW_DEVLOG_FACILITY_DCB] = "DCB", 7428 [FW_DEVLOG_FACILITY_ETH] = "ETH", 7429 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 7430 [FW_DEVLOG_FACILITY_RI] = "RI", 7431 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 7432 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 7433 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 7434 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 7435 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 7436}; 7437 7438static int 7439sysctl_devlog(SYSCTL_HANDLER_ARGS) 7440{ 7441 struct adapter *sc = arg1; 7442 struct devlog_params *dparams = &sc->params.devlog; 7443 struct fw_devlog_e *buf, *e; 7444 int i, j, rc, nentries, first = 0; 7445 struct sbuf *sb; 7446 uint64_t ftstamp = UINT64_MAX; 7447 7448 if (dparams->addr == 0) 7449 return (ENXIO); 7450 7451 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT); 7452 if (buf == NULL) 7453 return (ENOMEM); 7454 7455 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 7456 if (rc != 0) 7457 goto done; 7458 7459 nentries = dparams->size / sizeof(struct fw_devlog_e); 7460 for (i = 0; i < nentries; i++) { 7461 e = &buf[i]; 7462 7463 if (e->timestamp == 0) 7464 break; /* end */ 7465 7466 e->timestamp = be64toh(e->timestamp); 7467 e->seqno = be32toh(e->seqno); 7468 for (j = 0; j < 8; j++) 7469 e->params[j] = be32toh(e->params[j]); 7470 7471 if (e->timestamp < ftstamp) { 7472 ftstamp = e->timestamp; 7473 first = i; 7474 } 7475 } 7476 7477 if (buf[first].timestamp == 0) 7478 goto done; /* nothing in the log */ 7479 7480 rc = sysctl_wire_old_buffer(req, 0); 7481 if (rc != 0) 7482 goto done; 7483 7484 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7485 if (sb == NULL) { 7486 rc = ENOMEM; 7487 goto done; 7488 } 7489 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 7490 "Seq#", "Tstamp", "Level", "Facility", "Message"); 7491 7492 i = first; 7493 do { 7494 e = &buf[i]; 7495 if (e->timestamp == 0) 7496 break; /* end */ 7497 7498 sbuf_printf(sb, "%10d %15ju %8s %8s ", 7499 e->seqno, e->timestamp, 7500 (e->level < nitems(devlog_level_strings) ? 7501 devlog_level_strings[e->level] : "UNKNOWN"), 7502 (e->facility < nitems(devlog_facility_strings) ? 7503 devlog_facility_strings[e->facility] : "UNKNOWN")); 7504 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 7505 e->params[2], e->params[3], e->params[4], 7506 e->params[5], e->params[6], e->params[7]); 7507 7508 if (++i == nentries) 7509 i = 0; 7510 } while (i != first); 7511 7512 rc = sbuf_finish(sb); 7513 sbuf_delete(sb); 7514done: 7515 free(buf, M_CXGBE); 7516 return (rc); 7517} 7518 7519static int 7520sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 7521{ 7522 struct adapter *sc = arg1; 7523 struct sbuf *sb; 7524 int rc; 7525 struct tp_fcoe_stats stats[MAX_NCHAN]; 7526 int i, nchan = sc->chip_params->nchan; 7527 7528 rc = sysctl_wire_old_buffer(req, 0); 7529 if (rc != 0) 7530 return (rc); 7531 7532 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7533 if (sb == NULL) 7534 return (ENOMEM); 7535 7536 for (i = 0; i < nchan; i++) 7537 t4_get_fcoe_stats(sc, i, &stats[i], 1); 7538 7539 if (nchan > 2) { 7540 sbuf_printf(sb, " channel 0 channel 1" 7541 " channel 2 channel 3"); 7542 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 7543 stats[0].octets_ddp, stats[1].octets_ddp, 7544 stats[2].octets_ddp, stats[3].octets_ddp); 7545 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 7546 stats[0].frames_ddp, stats[1].frames_ddp, 7547 stats[2].frames_ddp, stats[3].frames_ddp); 7548 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 7549 stats[0].frames_drop, stats[1].frames_drop, 7550 stats[2].frames_drop, stats[3].frames_drop); 7551 } else { 7552 sbuf_printf(sb, " channel 0 channel 1"); 7553 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 7554 stats[0].octets_ddp, stats[1].octets_ddp); 7555 sbuf_printf(sb, "\nframesDDP: %16u %16u", 7556 stats[0].frames_ddp, stats[1].frames_ddp); 7557 sbuf_printf(sb, "\nframesDrop: %16u %16u", 7558 stats[0].frames_drop, stats[1].frames_drop); 7559 } 7560 7561 rc = sbuf_finish(sb); 7562 sbuf_delete(sb); 7563 7564 return (rc); 7565} 7566 7567static int 7568sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 7569{ 7570 struct adapter *sc = arg1; 7571 struct sbuf *sb; 7572 int rc, i; 7573 unsigned int map, kbps, ipg, mode; 7574 unsigned int pace_tab[NTX_SCHED]; 7575 7576 rc = sysctl_wire_old_buffer(req, 0); 7577 if (rc != 0) 7578 return (rc); 7579 7580 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7581 if (sb == NULL) 7582 return (ENOMEM); 7583 7584 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 7585 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 7586 t4_read_pace_tbl(sc, pace_tab); 7587 7588 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 7589 "Class IPG (0.1 ns) Flow IPG (us)"); 7590 7591 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 7592 t4_get_tx_sched(sc, i, &kbps, &ipg, 1); 7593 sbuf_printf(sb, "\n %u %-5s %u ", i, 7594 (mode & (1 << i)) ? "flow" : "class", map & 3); 7595 if (kbps) 7596 sbuf_printf(sb, "%9u ", kbps); 7597 else 7598 sbuf_printf(sb, " disabled "); 7599 7600 if (ipg) 7601 sbuf_printf(sb, "%13u ", ipg); 7602 else 7603 sbuf_printf(sb, " disabled "); 7604 7605 if (pace_tab[i]) 7606 sbuf_printf(sb, "%10u", pace_tab[i]); 7607 else 7608 sbuf_printf(sb, " disabled"); 7609 } 7610 7611 rc = sbuf_finish(sb); 7612 sbuf_delete(sb); 7613 7614 return (rc); 7615} 7616 7617static int 7618sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 7619{ 7620 struct adapter *sc = arg1; 7621 struct sbuf *sb; 7622 int rc, i, j; 7623 uint64_t *p0, *p1; 7624 struct lb_port_stats s[2]; 7625 static const char *stat_name[] = { 7626 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 7627 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 7628 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 7629 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 7630 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 7631 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 7632 "BG2FramesTrunc:", "BG3FramesTrunc:" 7633 }; 7634 7635 rc = sysctl_wire_old_buffer(req, 0); 7636 if (rc != 0) 7637 return (rc); 7638 7639 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7640 if (sb == NULL) 7641 return (ENOMEM); 7642 7643 memset(s, 0, sizeof(s)); 7644 7645 for (i = 0; i < sc->chip_params->nchan; i += 2) { 7646 t4_get_lb_stats(sc, i, &s[0]); 7647 t4_get_lb_stats(sc, i + 1, &s[1]); 7648 7649 p0 = &s[0].octets; 7650 p1 = &s[1].octets; 7651 sbuf_printf(sb, "%s Loopback %u" 7652 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 7653 7654 for (j = 0; j < nitems(stat_name); j++) 7655 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 7656 *p0++, *p1++); 7657 } 7658 7659 rc = sbuf_finish(sb); 7660 sbuf_delete(sb); 7661 7662 return (rc); 7663} 7664 7665static int 7666sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 7667{ 7668 int rc = 0; 7669 struct port_info *pi = arg1; 7670 struct link_config *lc = &pi->link_cfg; 7671 struct sbuf *sb; 7672 7673 rc = sysctl_wire_old_buffer(req, 0); 7674 if (rc != 0) 7675 return(rc); 7676 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 7677 if (sb == NULL) 7678 return (ENOMEM); 7679 7680 if (lc->link_ok || lc->link_down_rc == 255) 7681 sbuf_printf(sb, "n/a"); 7682 else 7683 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 7684 7685 rc = sbuf_finish(sb); 7686 sbuf_delete(sb); 7687 7688 return (rc); 7689} 7690 7691struct mem_desc { 7692 unsigned int base; 7693 unsigned int limit; 7694 unsigned int idx; 7695}; 7696 7697static int 7698mem_desc_cmp(const void *a, const void *b) 7699{ 7700 return ((const struct mem_desc *)a)->base - 7701 ((const struct mem_desc *)b)->base; 7702} 7703 7704static void 7705mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 7706 unsigned int to) 7707{ 7708 unsigned int size; 7709 7710 if (from == to) 7711 return; 7712 7713 size = to - from + 1; 7714 if (size == 0) 7715 return; 7716 7717 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 7718 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 7719} 7720 7721static int 7722sysctl_meminfo(SYSCTL_HANDLER_ARGS) 7723{ 7724 struct adapter *sc = arg1; 7725 struct sbuf *sb; 7726 int rc, i, n; 7727 uint32_t lo, hi, used, alloc; 7728 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 7729 static const char *region[] = { 7730 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 7731 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 7732 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 7733 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 7734 "RQUDP region:", "PBL region:", "TXPBL region:", 7735 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 7736 "On-chip queues:", "TLS keys:", 7737 }; 7738 struct mem_desc avail[4]; 7739 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 7740 struct mem_desc *md = mem; 7741 7742 rc = sysctl_wire_old_buffer(req, 0); 7743 if (rc != 0) 7744 return (rc); 7745 7746 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7747 if (sb == NULL) 7748 return (ENOMEM); 7749 7750 for (i = 0; i < nitems(mem); i++) { 7751 mem[i].limit = 0; 7752 mem[i].idx = i; 7753 } 7754 7755 /* Find and sort the populated memory ranges */ 7756 i = 0; 7757 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 7758 if (lo & F_EDRAM0_ENABLE) { 7759 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 7760 avail[i].base = G_EDRAM0_BASE(hi) << 20; 7761 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 7762 avail[i].idx = 0; 7763 i++; 7764 } 7765 if (lo & F_EDRAM1_ENABLE) { 7766 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 7767 avail[i].base = G_EDRAM1_BASE(hi) << 20; 7768 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 7769 avail[i].idx = 1; 7770 i++; 7771 } 7772 if (lo & F_EXT_MEM_ENABLE) { 7773 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 7774 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 7775 avail[i].limit = avail[i].base + 7776 (G_EXT_MEM_SIZE(hi) << 20); 7777 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 7778 i++; 7779 } 7780 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 7781 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 7782 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 7783 avail[i].limit = avail[i].base + 7784 (G_EXT_MEM1_SIZE(hi) << 20); 7785 avail[i].idx = 4; 7786 i++; 7787 } 7788 if (!i) /* no memory available */ 7789 return 0; 7790 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 7791 7792 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 7793 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 7794 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 7795 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 7796 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 7797 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 7798 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 7799 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 7800 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 7801 7802 /* the next few have explicit upper bounds */ 7803 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 7804 md->limit = md->base - 1 + 7805 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 7806 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 7807 md++; 7808 7809 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 7810 md->limit = md->base - 1 + 7811 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 7812 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 7813 md++; 7814 7815 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 7816 if (chip_id(sc) <= CHELSIO_T5) 7817 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 7818 else 7819 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 7820 md->limit = 0; 7821 } else { 7822 md->base = 0; 7823 md->idx = nitems(region); /* hide it */ 7824 } 7825 md++; 7826 7827#define ulp_region(reg) \ 7828 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 7829 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 7830 7831 ulp_region(RX_ISCSI); 7832 ulp_region(RX_TDDP); 7833 ulp_region(TX_TPT); 7834 ulp_region(RX_STAG); 7835 ulp_region(RX_RQ); 7836 ulp_region(RX_RQUDP); 7837 ulp_region(RX_PBL); 7838 ulp_region(TX_PBL); 7839#undef ulp_region 7840 7841 md->base = 0; 7842 md->idx = nitems(region); 7843 if (!is_t4(sc)) { 7844 uint32_t size = 0; 7845 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 7846 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 7847 7848 if (is_t5(sc)) { 7849 if (sge_ctrl & F_VFIFO_ENABLE) 7850 size = G_DBVFIFO_SIZE(fifo_size); 7851 } else 7852 size = G_T6_DBVFIFO_SIZE(fifo_size); 7853 7854 if (size) { 7855 md->base = G_BASEADDR(t4_read_reg(sc, 7856 A_SGE_DBVFIFO_BADDR)); 7857 md->limit = md->base + (size << 2) - 1; 7858 } 7859 } 7860 md++; 7861 7862 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 7863 md->limit = 0; 7864 md++; 7865 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 7866 md->limit = 0; 7867 md++; 7868 7869 md->base = sc->vres.ocq.start; 7870 if (sc->vres.ocq.size) 7871 md->limit = md->base + sc->vres.ocq.size - 1; 7872 else 7873 md->idx = nitems(region); /* hide it */ 7874 md++; 7875 7876 md->base = sc->vres.key.start; 7877 if (sc->vres.key.size) 7878 md->limit = md->base + sc->vres.key.size - 1; 7879 else 7880 md->idx = nitems(region); /* hide it */ 7881 md++; 7882 7883 /* add any address-space holes, there can be up to 3 */ 7884 for (n = 0; n < i - 1; n++) 7885 if (avail[n].limit < avail[n + 1].base) 7886 (md++)->base = avail[n].limit; 7887 if (avail[n].limit) 7888 (md++)->base = avail[n].limit; 7889 7890 n = md - mem; 7891 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 7892 7893 for (lo = 0; lo < i; lo++) 7894 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 7895 avail[lo].limit - 1); 7896 7897 sbuf_printf(sb, "\n"); 7898 for (i = 0; i < n; i++) { 7899 if (mem[i].idx >= nitems(region)) 7900 continue; /* skip holes */ 7901 if (!mem[i].limit) 7902 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 7903 mem_region_show(sb, region[mem[i].idx], mem[i].base, 7904 mem[i].limit); 7905 } 7906 7907 sbuf_printf(sb, "\n"); 7908 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 7909 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 7910 mem_region_show(sb, "uP RAM:", lo, hi); 7911 7912 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 7913 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 7914 mem_region_show(sb, "uP Extmem2:", lo, hi); 7915 7916 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 7917 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 7918 G_PMRXMAXPAGE(lo), 7919 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 7920 (lo & F_PMRXNUMCHN) ? 2 : 1); 7921 7922 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 7923 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 7924 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 7925 G_PMTXMAXPAGE(lo), 7926 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 7927 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 7928 sbuf_printf(sb, "%u p-structs\n", 7929 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 7930 7931 for (i = 0; i < 4; i++) { 7932 if (chip_id(sc) > CHELSIO_T5) 7933 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 7934 else 7935 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 7936 if (is_t5(sc)) { 7937 used = G_T5_USED(lo); 7938 alloc = G_T5_ALLOC(lo); 7939 } else { 7940 used = G_USED(lo); 7941 alloc = G_ALLOC(lo); 7942 } 7943 /* For T6 these are MAC buffer groups */ 7944 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 7945 i, used, alloc); 7946 } 7947 for (i = 0; i < sc->chip_params->nchan; i++) { 7948 if (chip_id(sc) > CHELSIO_T5) 7949 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 7950 else 7951 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 7952 if (is_t5(sc)) { 7953 used = G_T5_USED(lo); 7954 alloc = G_T5_ALLOC(lo); 7955 } else { 7956 used = G_USED(lo); 7957 alloc = G_ALLOC(lo); 7958 } 7959 /* For T6 these are MAC buffer groups */ 7960 sbuf_printf(sb, 7961 "\nLoopback %d using %u pages out of %u allocated", 7962 i, used, alloc); 7963 } 7964 7965 rc = sbuf_finish(sb); 7966 sbuf_delete(sb); 7967 7968 return (rc); 7969} 7970 7971static inline void 7972tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 7973{ 7974 *mask = x | y; 7975 y = htobe64(y); 7976 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 7977} 7978 7979static int 7980sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 7981{ 7982 struct adapter *sc = arg1; 7983 struct sbuf *sb; 7984 int rc, i; 7985 7986 MPASS(chip_id(sc) <= CHELSIO_T5); 7987 7988 rc = sysctl_wire_old_buffer(req, 0); 7989 if (rc != 0) 7990 return (rc); 7991 7992 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7993 if (sb == NULL) 7994 return (ENOMEM); 7995 7996 sbuf_printf(sb, 7997 "Idx Ethernet address Mask Vld Ports PF" 7998 " VF Replication P0 P1 P2 P3 ML"); 7999 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8000 uint64_t tcamx, tcamy, mask; 8001 uint32_t cls_lo, cls_hi; 8002 uint8_t addr[ETHER_ADDR_LEN]; 8003 8004 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 8005 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 8006 if (tcamx & tcamy) 8007 continue; 8008 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8009 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8010 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8011 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 8012 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 8013 addr[3], addr[4], addr[5], (uintmax_t)mask, 8014 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 8015 G_PORTMAP(cls_hi), G_PF(cls_lo), 8016 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 8017 8018 if (cls_lo & F_REPLICATE) { 8019 struct fw_ldst_cmd ldst_cmd; 8020 8021 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8022 ldst_cmd.op_to_addrspace = 8023 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8024 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8025 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8026 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8027 ldst_cmd.u.mps.rplc.fid_idx = 8028 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8029 V_FW_LDST_CMD_IDX(i)); 8030 8031 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8032 "t4mps"); 8033 if (rc) 8034 break; 8035 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8036 sizeof(ldst_cmd), &ldst_cmd); 8037 end_synchronized_op(sc, 0); 8038 8039 if (rc != 0) { 8040 sbuf_printf(sb, "%36d", rc); 8041 rc = 0; 8042 } else { 8043 sbuf_printf(sb, " %08x %08x %08x %08x", 8044 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8045 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8046 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8047 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8048 } 8049 } else 8050 sbuf_printf(sb, "%36s", ""); 8051 8052 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 8053 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 8054 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 8055 } 8056 8057 if (rc) 8058 (void) sbuf_finish(sb); 8059 else 8060 rc = sbuf_finish(sb); 8061 sbuf_delete(sb); 8062 8063 return (rc); 8064} 8065 8066static int 8067sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 8068{ 8069 struct adapter *sc = arg1; 8070 struct sbuf *sb; 8071 int rc, i; 8072 8073 MPASS(chip_id(sc) > CHELSIO_T5); 8074 8075 rc = sysctl_wire_old_buffer(req, 0); 8076 if (rc != 0) 8077 return (rc); 8078 8079 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8080 if (sb == NULL) 8081 return (ENOMEM); 8082 8083 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 8084 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 8085 " Replication" 8086 " P0 P1 P2 P3 ML\n"); 8087 8088 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 8089 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 8090 uint16_t ivlan; 8091 uint64_t tcamx, tcamy, val, mask; 8092 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 8093 uint8_t addr[ETHER_ADDR_LEN]; 8094 8095 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 8096 if (i < 256) 8097 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 8098 else 8099 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 8100 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8101 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8102 tcamy = G_DMACH(val) << 32; 8103 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8104 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8105 lookup_type = G_DATALKPTYPE(data2); 8106 port_num = G_DATAPORTNUM(data2); 8107 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8108 /* Inner header VNI */ 8109 vniy = ((data2 & F_DATAVIDH2) << 23) | 8110 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8111 dip_hit = data2 & F_DATADIPHIT; 8112 vlan_vld = 0; 8113 } else { 8114 vniy = 0; 8115 dip_hit = 0; 8116 vlan_vld = data2 & F_DATAVIDH2; 8117 ivlan = G_VIDL(val); 8118 } 8119 8120 ctl |= V_CTLXYBITSEL(1); 8121 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 8122 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 8123 tcamx = G_DMACH(val) << 32; 8124 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 8125 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 8126 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8127 /* Inner header VNI mask */ 8128 vnix = ((data2 & F_DATAVIDH2) << 23) | 8129 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 8130 } else 8131 vnix = 0; 8132 8133 if (tcamx & tcamy) 8134 continue; 8135 tcamxy2valmask(tcamx, tcamy, addr, &mask); 8136 8137 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 8138 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 8139 8140 if (lookup_type && lookup_type != M_DATALKPTYPE) { 8141 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8142 "%012jx %06x %06x - - %3c" 8143 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 8144 addr[1], addr[2], addr[3], addr[4], addr[5], 8145 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 8146 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8147 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8148 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8149 } else { 8150 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 8151 "%012jx - - ", i, addr[0], addr[1], 8152 addr[2], addr[3], addr[4], addr[5], 8153 (uintmax_t)mask); 8154 8155 if (vlan_vld) 8156 sbuf_printf(sb, "%4u Y ", ivlan); 8157 else 8158 sbuf_printf(sb, " - N "); 8159 8160 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 8161 lookup_type ? 'I' : 'O', port_num, 8162 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 8163 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 8164 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 8165 } 8166 8167 8168 if (cls_lo & F_T6_REPLICATE) { 8169 struct fw_ldst_cmd ldst_cmd; 8170 8171 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 8172 ldst_cmd.op_to_addrspace = 8173 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 8174 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8175 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 8176 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 8177 ldst_cmd.u.mps.rplc.fid_idx = 8178 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 8179 V_FW_LDST_CMD_IDX(i)); 8180 8181 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 8182 "t6mps"); 8183 if (rc) 8184 break; 8185 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 8186 sizeof(ldst_cmd), &ldst_cmd); 8187 end_synchronized_op(sc, 0); 8188 8189 if (rc != 0) { 8190 sbuf_printf(sb, "%72d", rc); 8191 rc = 0; 8192 } else { 8193 sbuf_printf(sb, " %08x %08x %08x %08x" 8194 " %08x %08x %08x %08x", 8195 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 8196 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 8197 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 8198 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 8199 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 8200 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 8201 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 8202 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 8203 } 8204 } else 8205 sbuf_printf(sb, "%72s", ""); 8206 8207 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 8208 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 8209 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 8210 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 8211 } 8212 8213 if (rc) 8214 (void) sbuf_finish(sb); 8215 else 8216 rc = sbuf_finish(sb); 8217 sbuf_delete(sb); 8218 8219 return (rc); 8220} 8221 8222static int 8223sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 8224{ 8225 struct adapter *sc = arg1; 8226 struct sbuf *sb; 8227 int rc; 8228 uint16_t mtus[NMTUS]; 8229 8230 rc = sysctl_wire_old_buffer(req, 0); 8231 if (rc != 0) 8232 return (rc); 8233 8234 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8235 if (sb == NULL) 8236 return (ENOMEM); 8237 8238 t4_read_mtu_tbl(sc, mtus, NULL); 8239 8240 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 8241 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 8242 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 8243 mtus[14], mtus[15]); 8244 8245 rc = sbuf_finish(sb); 8246 sbuf_delete(sb); 8247 8248 return (rc); 8249} 8250 8251static int 8252sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 8253{ 8254 struct adapter *sc = arg1; 8255 struct sbuf *sb; 8256 int rc, i; 8257 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 8258 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 8259 static const char *tx_stats[MAX_PM_NSTATS] = { 8260 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 8261 "Tx FIFO wait", NULL, "Tx latency" 8262 }; 8263 static const char *rx_stats[MAX_PM_NSTATS] = { 8264 "Read:", "Write bypass:", "Write mem:", "Flush:", 8265 "Rx FIFO wait", NULL, "Rx latency" 8266 }; 8267 8268 rc = sysctl_wire_old_buffer(req, 0); 8269 if (rc != 0) 8270 return (rc); 8271 8272 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8273 if (sb == NULL) 8274 return (ENOMEM); 8275 8276 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 8277 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 8278 8279 sbuf_printf(sb, " Tx pcmds Tx bytes"); 8280 for (i = 0; i < 4; i++) { 8281 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8282 tx_cyc[i]); 8283 } 8284 8285 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 8286 for (i = 0; i < 4; i++) { 8287 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8288 rx_cyc[i]); 8289 } 8290 8291 if (chip_id(sc) > CHELSIO_T5) { 8292 sbuf_printf(sb, 8293 "\n Total wait Total occupancy"); 8294 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8295 tx_cyc[i]); 8296 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8297 rx_cyc[i]); 8298 8299 i += 2; 8300 MPASS(i < nitems(tx_stats)); 8301 8302 sbuf_printf(sb, 8303 "\n Reads Total wait"); 8304 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 8305 tx_cyc[i]); 8306 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 8307 rx_cyc[i]); 8308 } 8309 8310 rc = sbuf_finish(sb); 8311 sbuf_delete(sb); 8312 8313 return (rc); 8314} 8315 8316static int 8317sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 8318{ 8319 struct adapter *sc = arg1; 8320 struct sbuf *sb; 8321 int rc; 8322 struct tp_rdma_stats stats; 8323 8324 rc = sysctl_wire_old_buffer(req, 0); 8325 if (rc != 0) 8326 return (rc); 8327 8328 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8329 if (sb == NULL) 8330 return (ENOMEM); 8331 8332 mtx_lock(&sc->reg_lock); 8333 t4_tp_get_rdma_stats(sc, &stats, 0); 8334 mtx_unlock(&sc->reg_lock); 8335 8336 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 8337 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 8338 8339 rc = sbuf_finish(sb); 8340 sbuf_delete(sb); 8341 8342 return (rc); 8343} 8344 8345static int 8346sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 8347{ 8348 struct adapter *sc = arg1; 8349 struct sbuf *sb; 8350 int rc; 8351 struct tp_tcp_stats v4, v6; 8352 8353 rc = sysctl_wire_old_buffer(req, 0); 8354 if (rc != 0) 8355 return (rc); 8356 8357 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8358 if (sb == NULL) 8359 return (ENOMEM); 8360 8361 mtx_lock(&sc->reg_lock); 8362 t4_tp_get_tcp_stats(sc, &v4, &v6, 0); 8363 mtx_unlock(&sc->reg_lock); 8364 8365 sbuf_printf(sb, 8366 " IP IPv6\n"); 8367 sbuf_printf(sb, "OutRsts: %20u %20u\n", 8368 v4.tcp_out_rsts, v6.tcp_out_rsts); 8369 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 8370 v4.tcp_in_segs, v6.tcp_in_segs); 8371 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 8372 v4.tcp_out_segs, v6.tcp_out_segs); 8373 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 8374 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 8375 8376 rc = sbuf_finish(sb); 8377 sbuf_delete(sb); 8378 8379 return (rc); 8380} 8381 8382static int 8383sysctl_tids(SYSCTL_HANDLER_ARGS) 8384{ 8385 struct adapter *sc = arg1; 8386 struct sbuf *sb; 8387 int rc; 8388 struct tid_info *t = &sc->tids; 8389 8390 rc = sysctl_wire_old_buffer(req, 0); 8391 if (rc != 0) 8392 return (rc); 8393 8394 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8395 if (sb == NULL) 8396 return (ENOMEM); 8397 8398 if (t->natids) { 8399 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 8400 t->atids_in_use); 8401 } 8402 8403 if (t->nhpftids) { 8404 sbuf_printf(sb, "HPFTID range: %u-%u, in use: %u\n", 8405 t->hpftid_base, t->hpftid_end, t->hpftids_in_use); 8406 } 8407 8408 if (t->ntids) { 8409 sbuf_printf(sb, "TID range: "); 8410 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 8411 uint32_t b, hb; 8412 8413 if (chip_id(sc) <= CHELSIO_T5) { 8414 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 8415 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 8416 } else { 8417 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 8418 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 8419 } 8420 8421 if (b) 8422 sbuf_printf(sb, "%u-%u, ", t->tid_base, b - 1); 8423 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 8424 } else 8425 sbuf_printf(sb, "%u-%u", t->tid_base, t->ntids - 1); 8426 sbuf_printf(sb, ", in use: %u\n", 8427 atomic_load_acq_int(&t->tids_in_use)); 8428 } 8429 8430 if (t->nstids) { 8431 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 8432 t->stid_base + t->nstids - 1, t->stids_in_use); 8433 } 8434 8435 if (t->nftids) { 8436 sbuf_printf(sb, "FTID range: %u-%u, in use: %u\n", t->ftid_base, 8437 t->ftid_end, t->ftids_in_use); 8438 } 8439 8440 if (t->netids) { 8441 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base, 8442 t->etid_base + t->netids - 1); 8443 } 8444 8445 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 8446 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 8447 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 8448 8449 rc = sbuf_finish(sb); 8450 sbuf_delete(sb); 8451 8452 return (rc); 8453} 8454 8455static int 8456sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 8457{ 8458 struct adapter *sc = arg1; 8459 struct sbuf *sb; 8460 int rc; 8461 struct tp_err_stats stats; 8462 8463 rc = sysctl_wire_old_buffer(req, 0); 8464 if (rc != 0) 8465 return (rc); 8466 8467 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8468 if (sb == NULL) 8469 return (ENOMEM); 8470 8471 mtx_lock(&sc->reg_lock); 8472 t4_tp_get_err_stats(sc, &stats, 0); 8473 mtx_unlock(&sc->reg_lock); 8474 8475 if (sc->chip_params->nchan > 2) { 8476 sbuf_printf(sb, " channel 0 channel 1" 8477 " channel 2 channel 3\n"); 8478 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 8479 stats.mac_in_errs[0], stats.mac_in_errs[1], 8480 stats.mac_in_errs[2], stats.mac_in_errs[3]); 8481 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 8482 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 8483 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 8484 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 8485 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 8486 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 8487 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 8488 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 8489 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 8490 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 8491 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 8492 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 8493 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 8494 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 8495 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 8496 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 8497 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 8498 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 8499 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 8500 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 8501 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 8502 } else { 8503 sbuf_printf(sb, " channel 0 channel 1\n"); 8504 sbuf_printf(sb, "macInErrs: %10u %10u\n", 8505 stats.mac_in_errs[0], stats.mac_in_errs[1]); 8506 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 8507 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 8508 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 8509 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 8510 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 8511 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 8512 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 8513 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 8514 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 8515 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 8516 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 8517 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 8518 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 8519 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 8520 } 8521 8522 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 8523 stats.ofld_no_neigh, stats.ofld_cong_defer); 8524 8525 rc = sbuf_finish(sb); 8526 sbuf_delete(sb); 8527 8528 return (rc); 8529} 8530 8531static int 8532sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 8533{ 8534 struct adapter *sc = arg1; 8535 struct tp_params *tpp = &sc->params.tp; 8536 u_int mask; 8537 int rc; 8538 8539 mask = tpp->la_mask >> 16; 8540 rc = sysctl_handle_int(oidp, &mask, 0, req); 8541 if (rc != 0 || req->newptr == NULL) 8542 return (rc); 8543 if (mask > 0xffff) 8544 return (EINVAL); 8545 tpp->la_mask = mask << 16; 8546 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 8547 8548 return (0); 8549} 8550 8551struct field_desc { 8552 const char *name; 8553 u_int start; 8554 u_int width; 8555}; 8556 8557static void 8558field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 8559{ 8560 char buf[32]; 8561 int line_size = 0; 8562 8563 while (f->name) { 8564 uint64_t mask = (1ULL << f->width) - 1; 8565 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 8566 ((uintmax_t)v >> f->start) & mask); 8567 8568 if (line_size + len >= 79) { 8569 line_size = 8; 8570 sbuf_printf(sb, "\n "); 8571 } 8572 sbuf_printf(sb, "%s ", buf); 8573 line_size += len + 1; 8574 f++; 8575 } 8576 sbuf_printf(sb, "\n"); 8577} 8578 8579static const struct field_desc tp_la0[] = { 8580 { "RcfOpCodeOut", 60, 4 }, 8581 { "State", 56, 4 }, 8582 { "WcfState", 52, 4 }, 8583 { "RcfOpcSrcOut", 50, 2 }, 8584 { "CRxError", 49, 1 }, 8585 { "ERxError", 48, 1 }, 8586 { "SanityFailed", 47, 1 }, 8587 { "SpuriousMsg", 46, 1 }, 8588 { "FlushInputMsg", 45, 1 }, 8589 { "FlushInputCpl", 44, 1 }, 8590 { "RssUpBit", 43, 1 }, 8591 { "RssFilterHit", 42, 1 }, 8592 { "Tid", 32, 10 }, 8593 { "InitTcb", 31, 1 }, 8594 { "LineNumber", 24, 7 }, 8595 { "Emsg", 23, 1 }, 8596 { "EdataOut", 22, 1 }, 8597 { "Cmsg", 21, 1 }, 8598 { "CdataOut", 20, 1 }, 8599 { "EreadPdu", 19, 1 }, 8600 { "CreadPdu", 18, 1 }, 8601 { "TunnelPkt", 17, 1 }, 8602 { "RcfPeerFin", 16, 1 }, 8603 { "RcfReasonOut", 12, 4 }, 8604 { "TxCchannel", 10, 2 }, 8605 { "RcfTxChannel", 8, 2 }, 8606 { "RxEchannel", 6, 2 }, 8607 { "RcfRxChannel", 5, 1 }, 8608 { "RcfDataOutSrdy", 4, 1 }, 8609 { "RxDvld", 3, 1 }, 8610 { "RxOoDvld", 2, 1 }, 8611 { "RxCongestion", 1, 1 }, 8612 { "TxCongestion", 0, 1 }, 8613 { NULL } 8614}; 8615 8616static const struct field_desc tp_la1[] = { 8617 { "CplCmdIn", 56, 8 }, 8618 { "CplCmdOut", 48, 8 }, 8619 { "ESynOut", 47, 1 }, 8620 { "EAckOut", 46, 1 }, 8621 { "EFinOut", 45, 1 }, 8622 { "ERstOut", 44, 1 }, 8623 { "SynIn", 43, 1 }, 8624 { "AckIn", 42, 1 }, 8625 { "FinIn", 41, 1 }, 8626 { "RstIn", 40, 1 }, 8627 { "DataIn", 39, 1 }, 8628 { "DataInVld", 38, 1 }, 8629 { "PadIn", 37, 1 }, 8630 { "RxBufEmpty", 36, 1 }, 8631 { "RxDdp", 35, 1 }, 8632 { "RxFbCongestion", 34, 1 }, 8633 { "TxFbCongestion", 33, 1 }, 8634 { "TxPktSumSrdy", 32, 1 }, 8635 { "RcfUlpType", 28, 4 }, 8636 { "Eread", 27, 1 }, 8637 { "Ebypass", 26, 1 }, 8638 { "Esave", 25, 1 }, 8639 { "Static0", 24, 1 }, 8640 { "Cread", 23, 1 }, 8641 { "Cbypass", 22, 1 }, 8642 { "Csave", 21, 1 }, 8643 { "CPktOut", 20, 1 }, 8644 { "RxPagePoolFull", 18, 2 }, 8645 { "RxLpbkPkt", 17, 1 }, 8646 { "TxLpbkPkt", 16, 1 }, 8647 { "RxVfValid", 15, 1 }, 8648 { "SynLearned", 14, 1 }, 8649 { "SetDelEntry", 13, 1 }, 8650 { "SetInvEntry", 12, 1 }, 8651 { "CpcmdDvld", 11, 1 }, 8652 { "CpcmdSave", 10, 1 }, 8653 { "RxPstructsFull", 8, 2 }, 8654 { "EpcmdDvld", 7, 1 }, 8655 { "EpcmdFlush", 6, 1 }, 8656 { "EpcmdTrimPrefix", 5, 1 }, 8657 { "EpcmdTrimPostfix", 4, 1 }, 8658 { "ERssIp4Pkt", 3, 1 }, 8659 { "ERssIp6Pkt", 2, 1 }, 8660 { "ERssTcpUdpPkt", 1, 1 }, 8661 { "ERssFceFipPkt", 0, 1 }, 8662 { NULL } 8663}; 8664 8665static const struct field_desc tp_la2[] = { 8666 { "CplCmdIn", 56, 8 }, 8667 { "MpsVfVld", 55, 1 }, 8668 { "MpsPf", 52, 3 }, 8669 { "MpsVf", 44, 8 }, 8670 { "SynIn", 43, 1 }, 8671 { "AckIn", 42, 1 }, 8672 { "FinIn", 41, 1 }, 8673 { "RstIn", 40, 1 }, 8674 { "DataIn", 39, 1 }, 8675 { "DataInVld", 38, 1 }, 8676 { "PadIn", 37, 1 }, 8677 { "RxBufEmpty", 36, 1 }, 8678 { "RxDdp", 35, 1 }, 8679 { "RxFbCongestion", 34, 1 }, 8680 { "TxFbCongestion", 33, 1 }, 8681 { "TxPktSumSrdy", 32, 1 }, 8682 { "RcfUlpType", 28, 4 }, 8683 { "Eread", 27, 1 }, 8684 { "Ebypass", 26, 1 }, 8685 { "Esave", 25, 1 }, 8686 { "Static0", 24, 1 }, 8687 { "Cread", 23, 1 }, 8688 { "Cbypass", 22, 1 }, 8689 { "Csave", 21, 1 }, 8690 { "CPktOut", 20, 1 }, 8691 { "RxPagePoolFull", 18, 2 }, 8692 { "RxLpbkPkt", 17, 1 }, 8693 { "TxLpbkPkt", 16, 1 }, 8694 { "RxVfValid", 15, 1 }, 8695 { "SynLearned", 14, 1 }, 8696 { "SetDelEntry", 13, 1 }, 8697 { "SetInvEntry", 12, 1 }, 8698 { "CpcmdDvld", 11, 1 }, 8699 { "CpcmdSave", 10, 1 }, 8700 { "RxPstructsFull", 8, 2 }, 8701 { "EpcmdDvld", 7, 1 }, 8702 { "EpcmdFlush", 6, 1 }, 8703 { "EpcmdTrimPrefix", 5, 1 }, 8704 { "EpcmdTrimPostfix", 4, 1 }, 8705 { "ERssIp4Pkt", 3, 1 }, 8706 { "ERssIp6Pkt", 2, 1 }, 8707 { "ERssTcpUdpPkt", 1, 1 }, 8708 { "ERssFceFipPkt", 0, 1 }, 8709 { NULL } 8710}; 8711 8712static void 8713tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 8714{ 8715 8716 field_desc_show(sb, *p, tp_la0); 8717} 8718 8719static void 8720tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 8721{ 8722 8723 if (idx) 8724 sbuf_printf(sb, "\n"); 8725 field_desc_show(sb, p[0], tp_la0); 8726 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 8727 field_desc_show(sb, p[1], tp_la0); 8728} 8729 8730static void 8731tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 8732{ 8733 8734 if (idx) 8735 sbuf_printf(sb, "\n"); 8736 field_desc_show(sb, p[0], tp_la0); 8737 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 8738 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 8739} 8740 8741static int 8742sysctl_tp_la(SYSCTL_HANDLER_ARGS) 8743{ 8744 struct adapter *sc = arg1; 8745 struct sbuf *sb; 8746 uint64_t *buf, *p; 8747 int rc; 8748 u_int i, inc; 8749 void (*show_func)(struct sbuf *, uint64_t *, int); 8750 8751 rc = sysctl_wire_old_buffer(req, 0); 8752 if (rc != 0) 8753 return (rc); 8754 8755 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8756 if (sb == NULL) 8757 return (ENOMEM); 8758 8759 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 8760 8761 t4_tp_read_la(sc, buf, NULL); 8762 p = buf; 8763 8764 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 8765 case 2: 8766 inc = 2; 8767 show_func = tp_la_show2; 8768 break; 8769 case 3: 8770 inc = 2; 8771 show_func = tp_la_show3; 8772 break; 8773 default: 8774 inc = 1; 8775 show_func = tp_la_show; 8776 } 8777 8778 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 8779 (*show_func)(sb, p, i); 8780 8781 rc = sbuf_finish(sb); 8782 sbuf_delete(sb); 8783 free(buf, M_CXGBE); 8784 return (rc); 8785} 8786 8787static int 8788sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 8789{ 8790 struct adapter *sc = arg1; 8791 struct sbuf *sb; 8792 int rc; 8793 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 8794 8795 rc = sysctl_wire_old_buffer(req, 0); 8796 if (rc != 0) 8797 return (rc); 8798 8799 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 8800 if (sb == NULL) 8801 return (ENOMEM); 8802 8803 t4_get_chan_txrate(sc, nrate, orate); 8804 8805 if (sc->chip_params->nchan > 2) { 8806 sbuf_printf(sb, " channel 0 channel 1" 8807 " channel 2 channel 3\n"); 8808 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 8809 nrate[0], nrate[1], nrate[2], nrate[3]); 8810 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 8811 orate[0], orate[1], orate[2], orate[3]); 8812 } else { 8813 sbuf_printf(sb, " channel 0 channel 1\n"); 8814 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 8815 nrate[0], nrate[1]); 8816 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 8817 orate[0], orate[1]); 8818 } 8819 8820 rc = sbuf_finish(sb); 8821 sbuf_delete(sb); 8822 8823 return (rc); 8824} 8825 8826static int 8827sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 8828{ 8829 struct adapter *sc = arg1; 8830 struct sbuf *sb; 8831 uint32_t *buf, *p; 8832 int rc, i; 8833 8834 rc = sysctl_wire_old_buffer(req, 0); 8835 if (rc != 0) 8836 return (rc); 8837 8838 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8839 if (sb == NULL) 8840 return (ENOMEM); 8841 8842 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 8843 M_ZERO | M_WAITOK); 8844 8845 t4_ulprx_read_la(sc, buf); 8846 p = buf; 8847 8848 sbuf_printf(sb, " Pcmd Type Message" 8849 " Data"); 8850 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 8851 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 8852 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 8853 } 8854 8855 rc = sbuf_finish(sb); 8856 sbuf_delete(sb); 8857 free(buf, M_CXGBE); 8858 return (rc); 8859} 8860 8861static int 8862sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 8863{ 8864 struct adapter *sc = arg1; 8865 struct sbuf *sb; 8866 int rc, v; 8867 8868 MPASS(chip_id(sc) >= CHELSIO_T5); 8869 8870 rc = sysctl_wire_old_buffer(req, 0); 8871 if (rc != 0) 8872 return (rc); 8873 8874 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8875 if (sb == NULL) 8876 return (ENOMEM); 8877 8878 v = t4_read_reg(sc, A_SGE_STAT_CFG); 8879 if (G_STATSOURCE_T5(v) == 7) { 8880 int mode; 8881 8882 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 8883 if (mode == 0) { 8884 sbuf_printf(sb, "total %d, incomplete %d", 8885 t4_read_reg(sc, A_SGE_STAT_TOTAL), 8886 t4_read_reg(sc, A_SGE_STAT_MATCH)); 8887 } else if (mode == 1) { 8888 sbuf_printf(sb, "total %d, data overflow %d", 8889 t4_read_reg(sc, A_SGE_STAT_TOTAL), 8890 t4_read_reg(sc, A_SGE_STAT_MATCH)); 8891 } else { 8892 sbuf_printf(sb, "unknown mode %d", mode); 8893 } 8894 } 8895 rc = sbuf_finish(sb); 8896 sbuf_delete(sb); 8897 8898 return (rc); 8899} 8900 8901static int 8902sysctl_cpus(SYSCTL_HANDLER_ARGS) 8903{ 8904 struct adapter *sc = arg1; 8905 enum cpu_sets op = arg2; 8906 cpuset_t cpuset; 8907 struct sbuf *sb; 8908 int i, rc; 8909 8910 MPASS(op == LOCAL_CPUS || op == INTR_CPUS); 8911 8912 CPU_ZERO(&cpuset); 8913 rc = bus_get_cpus(sc->dev, op, sizeof(cpuset), &cpuset); 8914 if (rc != 0) 8915 return (rc); 8916 8917 rc = sysctl_wire_old_buffer(req, 0); 8918 if (rc != 0) 8919 return (rc); 8920 8921 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 8922 if (sb == NULL) 8923 return (ENOMEM); 8924 8925 CPU_FOREACH(i) 8926 sbuf_printf(sb, "%d ", i); 8927 rc = sbuf_finish(sb); 8928 sbuf_delete(sb); 8929 8930 return (rc); 8931 8932} 8933 8934#ifdef TCP_OFFLOAD 8935static int 8936sysctl_tls_rx_ports(SYSCTL_HANDLER_ARGS) 8937{ 8938 struct adapter *sc = arg1; 8939 int *old_ports, *new_ports; 8940 int i, new_count, rc; 8941 8942 if (req->newptr == NULL && req->oldptr == NULL) 8943 return (SYSCTL_OUT(req, NULL, imax(sc->tt.num_tls_rx_ports, 1) * 8944 sizeof(sc->tt.tls_rx_ports[0]))); 8945 8946 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4tlsrx"); 8947 if (rc) 8948 return (rc); 8949 8950 if (sc->tt.num_tls_rx_ports == 0) { 8951 i = -1; 8952 rc = SYSCTL_OUT(req, &i, sizeof(i)); 8953 } else 8954 rc = SYSCTL_OUT(req, sc->tt.tls_rx_ports, 8955 sc->tt.num_tls_rx_ports * sizeof(sc->tt.tls_rx_ports[0])); 8956 if (rc == 0 && req->newptr != NULL) { 8957 new_count = req->newlen / sizeof(new_ports[0]); 8958 new_ports = malloc(new_count * sizeof(new_ports[0]), M_CXGBE, 8959 M_WAITOK); 8960 rc = SYSCTL_IN(req, new_ports, new_count * 8961 sizeof(new_ports[0])); 8962 if (rc) 8963 goto err; 8964 8965 /* Allow setting to a single '-1' to clear the list. */ 8966 if (new_count == 1 && new_ports[0] == -1) { 8967 ADAPTER_LOCK(sc); 8968 old_ports = sc->tt.tls_rx_ports; 8969 sc->tt.tls_rx_ports = NULL; 8970 sc->tt.num_tls_rx_ports = 0; 8971 ADAPTER_UNLOCK(sc); 8972 free(old_ports, M_CXGBE); 8973 } else { 8974 for (i = 0; i < new_count; i++) { 8975 if (new_ports[i] < 1 || 8976 new_ports[i] > IPPORT_MAX) { 8977 rc = EINVAL; 8978 goto err; 8979 } 8980 } 8981 8982 ADAPTER_LOCK(sc); 8983 old_ports = sc->tt.tls_rx_ports; 8984 sc->tt.tls_rx_ports = new_ports; 8985 sc->tt.num_tls_rx_ports = new_count; 8986 ADAPTER_UNLOCK(sc); 8987 free(old_ports, M_CXGBE); 8988 new_ports = NULL; 8989 } 8990 err: 8991 free(new_ports, M_CXGBE); 8992 } 8993 end_synchronized_op(sc, 0); 8994 return (rc); 8995} 8996 8997static void 8998unit_conv(char *buf, size_t len, u_int val, u_int factor) 8999{ 9000 u_int rem = val % factor; 9001 9002 if (rem == 0) 9003 snprintf(buf, len, "%u", val / factor); 9004 else { 9005 while (rem % 10 == 0) 9006 rem /= 10; 9007 snprintf(buf, len, "%u.%u", val / factor, rem); 9008 } 9009} 9010 9011static int 9012sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 9013{ 9014 struct adapter *sc = arg1; 9015 char buf[16]; 9016 u_int res, re; 9017 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9018 9019 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9020 switch (arg2) { 9021 case 0: 9022 /* timer_tick */ 9023 re = G_TIMERRESOLUTION(res); 9024 break; 9025 case 1: 9026 /* TCP timestamp tick */ 9027 re = G_TIMESTAMPRESOLUTION(res); 9028 break; 9029 case 2: 9030 /* DACK tick */ 9031 re = G_DELAYEDACKRESOLUTION(res); 9032 break; 9033 default: 9034 return (EDOOFUS); 9035 } 9036 9037 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 9038 9039 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 9040} 9041 9042static int 9043sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 9044{ 9045 struct adapter *sc = arg1; 9046 u_int res, dack_re, v; 9047 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9048 9049 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 9050 dack_re = G_DELAYEDACKRESOLUTION(res); 9051 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 9052 9053 return (sysctl_handle_int(oidp, &v, 0, req)); 9054} 9055 9056static int 9057sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 9058{ 9059 struct adapter *sc = arg1; 9060 int reg = arg2; 9061 u_int tre; 9062 u_long tp_tick_us, v; 9063 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 9064 9065 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 9066 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 9067 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL || 9068 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER); 9069 9070 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 9071 tp_tick_us = (cclk_ps << tre) / 1000000; 9072 9073 if (reg == A_TP_INIT_SRTT) 9074 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 9075 else 9076 v = tp_tick_us * t4_read_reg(sc, reg); 9077 9078 return (sysctl_handle_long(oidp, &v, 0, req)); 9079} 9080 9081/* 9082 * All fields in TP_SHIFT_CNT are 4b and the starting location of the field is 9083 * passed to this function. 9084 */ 9085static int 9086sysctl_tp_shift_cnt(SYSCTL_HANDLER_ARGS) 9087{ 9088 struct adapter *sc = arg1; 9089 int idx = arg2; 9090 u_int v; 9091 9092 MPASS(idx >= 0 && idx <= 24); 9093 9094 v = (t4_read_reg(sc, A_TP_SHIFT_CNT) >> idx) & 0xf; 9095 9096 return (sysctl_handle_int(oidp, &v, 0, req)); 9097} 9098 9099static int 9100sysctl_tp_backoff(SYSCTL_HANDLER_ARGS) 9101{ 9102 struct adapter *sc = arg1; 9103 int idx = arg2; 9104 u_int shift, v, r; 9105 9106 MPASS(idx >= 0 && idx < 16); 9107 9108 r = A_TP_TCP_BACKOFF_REG0 + (idx & ~3); 9109 shift = (idx & 3) << 3; 9110 v = (t4_read_reg(sc, r) >> shift) & M_TIMERBACKOFFINDEX0; 9111 9112 return (sysctl_handle_int(oidp, &v, 0, req)); 9113} 9114 9115static int 9116sysctl_holdoff_tmr_idx_ofld(SYSCTL_HANDLER_ARGS) 9117{ 9118 struct vi_info *vi = arg1; 9119 struct adapter *sc = vi->pi->adapter; 9120 int idx, rc, i; 9121 struct sge_ofld_rxq *ofld_rxq; 9122 uint8_t v; 9123 9124 idx = vi->ofld_tmr_idx; 9125 9126 rc = sysctl_handle_int(oidp, &idx, 0, req); 9127 if (rc != 0 || req->newptr == NULL) 9128 return (rc); 9129 9130 if (idx < 0 || idx >= SGE_NTIMERS) 9131 return (EINVAL); 9132 9133 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 9134 "t4otmr"); 9135 if (rc) 9136 return (rc); 9137 9138 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->ofld_pktc_idx != -1); 9139 for_each_ofld_rxq(vi, i, ofld_rxq) { 9140#ifdef atomic_store_rel_8 9141 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 9142#else 9143 ofld_rxq->iq.intr_params = v; 9144#endif 9145 } 9146 vi->ofld_tmr_idx = idx; 9147 9148 end_synchronized_op(sc, LOCK_HELD); 9149 return (0); 9150} 9151 9152static int 9153sysctl_holdoff_pktc_idx_ofld(SYSCTL_HANDLER_ARGS) 9154{ 9155 struct vi_info *vi = arg1; 9156 struct adapter *sc = vi->pi->adapter; 9157 int idx, rc; 9158 9159 idx = vi->ofld_pktc_idx; 9160 9161 rc = sysctl_handle_int(oidp, &idx, 0, req); 9162 if (rc != 0 || req->newptr == NULL) 9163 return (rc); 9164 9165 if (idx < -1 || idx >= SGE_NCOUNTERS) 9166 return (EINVAL); 9167 9168 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 9169 "t4opktc"); 9170 if (rc) 9171 return (rc); 9172 9173 if (vi->flags & VI_INIT_DONE) 9174 rc = EBUSY; /* cannot be changed once the queues are created */ 9175 else 9176 vi->ofld_pktc_idx = idx; 9177 9178 end_synchronized_op(sc, LOCK_HELD); 9179 return (rc); 9180} 9181#endif 9182 9183static int 9184get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 9185{ 9186 int rc; 9187 9188 if (cntxt->cid > M_CTXTQID) 9189 return (EINVAL); 9190 9191 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 9192 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 9193 return (EINVAL); 9194 9195 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 9196 if (rc) 9197 return (rc); 9198 9199 if (sc->flags & FW_OK) { 9200 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 9201 &cntxt->data[0]); 9202 if (rc == 0) 9203 goto done; 9204 } 9205 9206 /* 9207 * Read via firmware failed or wasn't even attempted. Read directly via 9208 * the backdoor. 9209 */ 9210 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 9211done: 9212 end_synchronized_op(sc, 0); 9213 return (rc); 9214} 9215 9216static int 9217load_fw(struct adapter *sc, struct t4_data *fw) 9218{ 9219 int rc; 9220 uint8_t *fw_data; 9221 9222 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 9223 if (rc) 9224 return (rc); 9225 9226 /* 9227 * The firmware, with the sole exception of the memory parity error 9228 * handler, runs from memory and not flash. It is almost always safe to 9229 * install a new firmware on a running system. Just set bit 1 in 9230 * hw.cxgbe.dflags or dev.<nexus>.<n>.dflags first. 9231 */ 9232 if (sc->flags & FULL_INIT_DONE && 9233 (sc->debug_flags & DF_LOAD_FW_ANYTIME) == 0) { 9234 rc = EBUSY; 9235 goto done; 9236 } 9237 9238 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 9239 if (fw_data == NULL) { 9240 rc = ENOMEM; 9241 goto done; 9242 } 9243 9244 rc = copyin(fw->data, fw_data, fw->len); 9245 if (rc == 0) 9246 rc = -t4_load_fw(sc, fw_data, fw->len); 9247 9248 free(fw_data, M_CXGBE); 9249done: 9250 end_synchronized_op(sc, 0); 9251 return (rc); 9252} 9253 9254static int 9255load_cfg(struct adapter *sc, struct t4_data *cfg) 9256{ 9257 int rc; 9258 uint8_t *cfg_data = NULL; 9259 9260 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9261 if (rc) 9262 return (rc); 9263 9264 if (cfg->len == 0) { 9265 /* clear */ 9266 rc = -t4_load_cfg(sc, NULL, 0); 9267 goto done; 9268 } 9269 9270 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 9271 if (cfg_data == NULL) { 9272 rc = ENOMEM; 9273 goto done; 9274 } 9275 9276 rc = copyin(cfg->data, cfg_data, cfg->len); 9277 if (rc == 0) 9278 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 9279 9280 free(cfg_data, M_CXGBE); 9281done: 9282 end_synchronized_op(sc, 0); 9283 return (rc); 9284} 9285 9286static int 9287load_boot(struct adapter *sc, struct t4_bootrom *br) 9288{ 9289 int rc; 9290 uint8_t *br_data = NULL; 9291 u_int offset; 9292 9293 if (br->len > 1024 * 1024) 9294 return (EFBIG); 9295 9296 if (br->pf_offset == 0) { 9297 /* pfidx */ 9298 if (br->pfidx_addr > 7) 9299 return (EINVAL); 9300 offset = G_OFFSET(t4_read_reg(sc, PF_REG(br->pfidx_addr, 9301 A_PCIE_PF_EXPROM_OFST))); 9302 } else if (br->pf_offset == 1) { 9303 /* offset */ 9304 offset = G_OFFSET(br->pfidx_addr); 9305 } else { 9306 return (EINVAL); 9307 } 9308 9309 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldbr"); 9310 if (rc) 9311 return (rc); 9312 9313 if (br->len == 0) { 9314 /* clear */ 9315 rc = -t4_load_boot(sc, NULL, offset, 0); 9316 goto done; 9317 } 9318 9319 br_data = malloc(br->len, M_CXGBE, M_WAITOK); 9320 if (br_data == NULL) { 9321 rc = ENOMEM; 9322 goto done; 9323 } 9324 9325 rc = copyin(br->data, br_data, br->len); 9326 if (rc == 0) 9327 rc = -t4_load_boot(sc, br_data, offset, br->len); 9328 9329 free(br_data, M_CXGBE); 9330done: 9331 end_synchronized_op(sc, 0); 9332 return (rc); 9333} 9334 9335static int 9336load_bootcfg(struct adapter *sc, struct t4_data *bc) 9337{ 9338 int rc; 9339 uint8_t *bc_data = NULL; 9340 9341 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 9342 if (rc) 9343 return (rc); 9344 9345 if (bc->len == 0) { 9346 /* clear */ 9347 rc = -t4_load_bootcfg(sc, NULL, 0); 9348 goto done; 9349 } 9350 9351 bc_data = malloc(bc->len, M_CXGBE, M_WAITOK); 9352 if (bc_data == NULL) { 9353 rc = ENOMEM; 9354 goto done; 9355 } 9356 9357 rc = copyin(bc->data, bc_data, bc->len); 9358 if (rc == 0) 9359 rc = -t4_load_bootcfg(sc, bc_data, bc->len); 9360 9361 free(bc_data, M_CXGBE); 9362done: 9363 end_synchronized_op(sc, 0); 9364 return (rc); 9365} 9366 9367static int 9368cudbg_dump(struct adapter *sc, struct t4_cudbg_dump *dump) 9369{ 9370 int rc; 9371 struct cudbg_init *cudbg; 9372 void *handle, *buf; 9373 9374 /* buf is large, don't block if no memory is available */ 9375 buf = malloc(dump->len, M_CXGBE, M_NOWAIT | M_ZERO); 9376 if (buf == NULL) 9377 return (ENOMEM); 9378 9379 handle = cudbg_alloc_handle(); 9380 if (handle == NULL) { 9381 rc = ENOMEM; 9382 goto done; 9383 } 9384 9385 cudbg = cudbg_get_init(handle); 9386 cudbg->adap = sc; 9387 cudbg->print = (cudbg_print_cb)printf; 9388 9389#ifndef notyet 9390 device_printf(sc->dev, "%s: wr_flash %u, len %u, data %p.\n", 9391 __func__, dump->wr_flash, dump->len, dump->data); 9392#endif 9393 9394 if (dump->wr_flash) 9395 cudbg->use_flash = 1; 9396 MPASS(sizeof(cudbg->dbg_bitmap) == sizeof(dump->bitmap)); 9397 memcpy(cudbg->dbg_bitmap, dump->bitmap, sizeof(cudbg->dbg_bitmap)); 9398 9399 rc = cudbg_collect(handle, buf, &dump->len); 9400 if (rc != 0) 9401 goto done; 9402 9403 rc = copyout(buf, dump->data, dump->len); 9404done: 9405 cudbg_free_handle(handle); 9406 free(buf, M_CXGBE); 9407 return (rc); 9408} 9409 9410static void 9411free_offload_policy(struct t4_offload_policy *op) 9412{ 9413 struct offload_rule *r; 9414 int i; 9415 9416 if (op == NULL) 9417 return; 9418 9419 r = &op->rule[0]; 9420 for (i = 0; i < op->nrules; i++, r++) { 9421 free(r->bpf_prog.bf_insns, M_CXGBE); 9422 } 9423 free(op->rule, M_CXGBE); 9424 free(op, M_CXGBE); 9425} 9426 9427static int 9428set_offload_policy(struct adapter *sc, struct t4_offload_policy *uop) 9429{ 9430 int i, rc, len; 9431 struct t4_offload_policy *op, *old; 9432 struct bpf_program *bf; 9433 const struct offload_settings *s; 9434 struct offload_rule *r; 9435 void *u; 9436 9437 if (!is_offload(sc)) 9438 return (ENODEV); 9439 9440 if (uop->nrules == 0) { 9441 /* Delete installed policies. */ 9442 op = NULL; 9443 goto set_policy; 9444 } if (uop->nrules > 256) { /* arbitrary */ 9445 return (E2BIG); 9446 } 9447 9448 /* Copy userspace offload policy to kernel */ 9449 op = malloc(sizeof(*op), M_CXGBE, M_ZERO | M_WAITOK); 9450 op->nrules = uop->nrules; 9451 len = op->nrules * sizeof(struct offload_rule); 9452 op->rule = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9453 rc = copyin(uop->rule, op->rule, len); 9454 if (rc) { 9455 free(op->rule, M_CXGBE); 9456 free(op, M_CXGBE); 9457 return (rc); 9458 } 9459 9460 r = &op->rule[0]; 9461 for (i = 0; i < op->nrules; i++, r++) { 9462 9463 /* Validate open_type */ 9464 if (r->open_type != OPEN_TYPE_LISTEN && 9465 r->open_type != OPEN_TYPE_ACTIVE && 9466 r->open_type != OPEN_TYPE_PASSIVE && 9467 r->open_type != OPEN_TYPE_DONTCARE) { 9468error: 9469 /* 9470 * Rules 0 to i have malloc'd filters that need to be 9471 * freed. Rules i+1 to nrules have userspace pointers 9472 * and should be left alone. 9473 */ 9474 op->nrules = i; 9475 free_offload_policy(op); 9476 return (rc); 9477 } 9478 9479 /* Validate settings */ 9480 s = &r->settings; 9481 if ((s->offload != 0 && s->offload != 1) || 9482 s->cong_algo < -1 || s->cong_algo > CONG_ALG_HIGHSPEED || 9483 s->sched_class < -1 || 9484 s->sched_class >= sc->chip_params->nsched_cls) { 9485 rc = EINVAL; 9486 goto error; 9487 } 9488 9489 bf = &r->bpf_prog; 9490 u = bf->bf_insns; /* userspace ptr */ 9491 bf->bf_insns = NULL; 9492 if (bf->bf_len == 0) { 9493 /* legal, matches everything */ 9494 continue; 9495 } 9496 len = bf->bf_len * sizeof(*bf->bf_insns); 9497 bf->bf_insns = malloc(len, M_CXGBE, M_ZERO | M_WAITOK); 9498 rc = copyin(u, bf->bf_insns, len); 9499 if (rc != 0) 9500 goto error; 9501 9502 if (!bpf_validate(bf->bf_insns, bf->bf_len)) { 9503 rc = EINVAL; 9504 goto error; 9505 } 9506 } 9507set_policy: 9508 rw_wlock(&sc->policy_lock); 9509 old = sc->policy; 9510 sc->policy = op; 9511 rw_wunlock(&sc->policy_lock); 9512 free_offload_policy(old); 9513 9514 return (0); 9515} 9516 9517#define MAX_READ_BUF_SIZE (128 * 1024) 9518static int 9519read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 9520{ 9521 uint32_t addr, remaining, n; 9522 uint32_t *buf; 9523 int rc; 9524 uint8_t *dst; 9525 9526 rc = validate_mem_range(sc, mr->addr, mr->len); 9527 if (rc != 0) 9528 return (rc); 9529 9530 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 9531 addr = mr->addr; 9532 remaining = mr->len; 9533 dst = (void *)mr->data; 9534 9535 while (remaining) { 9536 n = min(remaining, MAX_READ_BUF_SIZE); 9537 read_via_memwin(sc, 2, addr, buf, n); 9538 9539 rc = copyout(buf, dst, n); 9540 if (rc != 0) 9541 break; 9542 9543 dst += n; 9544 remaining -= n; 9545 addr += n; 9546 } 9547 9548 free(buf, M_CXGBE); 9549 return (rc); 9550} 9551#undef MAX_READ_BUF_SIZE 9552 9553static int 9554read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 9555{ 9556 int rc; 9557 9558 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 9559 return (EINVAL); 9560 9561 if (i2cd->len > sizeof(i2cd->data)) 9562 return (EFBIG); 9563 9564 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 9565 if (rc) 9566 return (rc); 9567 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 9568 i2cd->offset, i2cd->len, &i2cd->data[0]); 9569 end_synchronized_op(sc, 0); 9570 9571 return (rc); 9572} 9573 9574int 9575t4_os_find_pci_capability(struct adapter *sc, int cap) 9576{ 9577 int i; 9578 9579 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 9580} 9581 9582int 9583t4_os_pci_save_state(struct adapter *sc) 9584{ 9585 device_t dev; 9586 struct pci_devinfo *dinfo; 9587 9588 dev = sc->dev; 9589 dinfo = device_get_ivars(dev); 9590 9591 pci_cfg_save(dev, dinfo, 0); 9592 return (0); 9593} 9594 9595int 9596t4_os_pci_restore_state(struct adapter *sc) 9597{ 9598 device_t dev; 9599 struct pci_devinfo *dinfo; 9600 9601 dev = sc->dev; 9602 dinfo = device_get_ivars(dev); 9603 9604 pci_cfg_restore(dev, dinfo); 9605 return (0); 9606} 9607 9608void 9609t4_os_portmod_changed(struct port_info *pi) 9610{ 9611 struct adapter *sc = pi->adapter; 9612 struct vi_info *vi; 9613 struct ifnet *ifp; 9614 static const char *mod_str[] = { 9615 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 9616 }; 9617 9618 KASSERT((pi->flags & FIXED_IFMEDIA) == 0, 9619 ("%s: port_type %u", __func__, pi->port_type)); 9620 9621 vi = &pi->vi[0]; 9622 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) { 9623 PORT_LOCK(pi); 9624 build_medialist(pi); 9625 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 9626 fixup_link_config(pi); 9627 apply_link_config(pi); 9628 } 9629 PORT_UNLOCK(pi); 9630 end_synchronized_op(sc, LOCK_HELD); 9631 } 9632 9633 ifp = vi->ifp; 9634 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 9635 if_printf(ifp, "transceiver unplugged.\n"); 9636 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 9637 if_printf(ifp, "unknown transceiver inserted.\n"); 9638 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 9639 if_printf(ifp, "unsupported transceiver inserted.\n"); 9640 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 9641 if_printf(ifp, "%dGbps %s transceiver inserted.\n", 9642 port_top_speed(pi), mod_str[pi->mod_type]); 9643 } else { 9644 if_printf(ifp, "transceiver (type %d) inserted.\n", 9645 pi->mod_type); 9646 } 9647} 9648 9649void 9650t4_os_link_changed(struct port_info *pi) 9651{ 9652 struct vi_info *vi; 9653 struct ifnet *ifp; 9654 struct link_config *lc; 9655 int v; 9656 9657 PORT_LOCK_ASSERT_OWNED(pi); 9658 9659 for_each_vi(pi, v, vi) { 9660 ifp = vi->ifp; 9661 if (ifp == NULL) 9662 continue; 9663 9664 lc = &pi->link_cfg; 9665 if (lc->link_ok) { 9666 ifp->if_baudrate = IF_Mbps(lc->speed); 9667 if_link_state_change(ifp, LINK_STATE_UP); 9668 } else { 9669 if_link_state_change(ifp, LINK_STATE_DOWN); 9670 } 9671 } 9672} 9673 9674void 9675t4_iterate(void (*func)(struct adapter *, void *), void *arg) 9676{ 9677 struct adapter *sc; 9678 9679 sx_slock(&t4_list_lock); 9680 SLIST_FOREACH(sc, &t4_list, link) { 9681 /* 9682 * func should not make any assumptions about what state sc is 9683 * in - the only guarantee is that sc->sc_lock is a valid lock. 9684 */ 9685 func(sc, arg); 9686 } 9687 sx_sunlock(&t4_list_lock); 9688} 9689 9690static int 9691t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 9692 struct thread *td) 9693{ 9694 int rc; 9695 struct adapter *sc = dev->si_drv1; 9696 9697 rc = priv_check(td, PRIV_DRIVER); 9698 if (rc != 0) 9699 return (rc); 9700 9701 switch (cmd) { 9702 case CHELSIO_T4_GETREG: { 9703 struct t4_reg *edata = (struct t4_reg *)data; 9704 9705 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9706 return (EFAULT); 9707 9708 if (edata->size == 4) 9709 edata->val = t4_read_reg(sc, edata->addr); 9710 else if (edata->size == 8) 9711 edata->val = t4_read_reg64(sc, edata->addr); 9712 else 9713 return (EINVAL); 9714 9715 break; 9716 } 9717 case CHELSIO_T4_SETREG: { 9718 struct t4_reg *edata = (struct t4_reg *)data; 9719 9720 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9721 return (EFAULT); 9722 9723 if (edata->size == 4) { 9724 if (edata->val & 0xffffffff00000000) 9725 return (EINVAL); 9726 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 9727 } else if (edata->size == 8) 9728 t4_write_reg64(sc, edata->addr, edata->val); 9729 else 9730 return (EINVAL); 9731 break; 9732 } 9733 case CHELSIO_T4_REGDUMP: { 9734 struct t4_regdump *regs = (struct t4_regdump *)data; 9735 int reglen = t4_get_regs_len(sc); 9736 uint8_t *buf; 9737 9738 if (regs->len < reglen) { 9739 regs->len = reglen; /* hint to the caller */ 9740 return (ENOBUFS); 9741 } 9742 9743 regs->len = reglen; 9744 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 9745 get_regs(sc, regs, buf); 9746 rc = copyout(buf, regs->data, reglen); 9747 free(buf, M_CXGBE); 9748 break; 9749 } 9750 case CHELSIO_T4_GET_FILTER_MODE: 9751 rc = get_filter_mode(sc, (uint32_t *)data); 9752 break; 9753 case CHELSIO_T4_SET_FILTER_MODE: 9754 rc = set_filter_mode(sc, *(uint32_t *)data); 9755 break; 9756 case CHELSIO_T4_GET_FILTER: 9757 rc = get_filter(sc, (struct t4_filter *)data); 9758 break; 9759 case CHELSIO_T4_SET_FILTER: 9760 rc = set_filter(sc, (struct t4_filter *)data); 9761 break; 9762 case CHELSIO_T4_DEL_FILTER: 9763 rc = del_filter(sc, (struct t4_filter *)data); 9764 break; 9765 case CHELSIO_T4_GET_SGE_CONTEXT: 9766 rc = get_sge_context(sc, (struct t4_sge_context *)data); 9767 break; 9768 case CHELSIO_T4_LOAD_FW: 9769 rc = load_fw(sc, (struct t4_data *)data); 9770 break; 9771 case CHELSIO_T4_GET_MEM: 9772 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 9773 break; 9774 case CHELSIO_T4_GET_I2C: 9775 rc = read_i2c(sc, (struct t4_i2c_data *)data); 9776 break; 9777 case CHELSIO_T4_CLEAR_STATS: { 9778 int i, v, bg_map; 9779 u_int port_id = *(uint32_t *)data; 9780 struct port_info *pi; 9781 struct vi_info *vi; 9782 9783 if (port_id >= sc->params.nports) 9784 return (EINVAL); 9785 pi = sc->port[port_id]; 9786 if (pi == NULL) 9787 return (EIO); 9788 9789 /* MAC stats */ 9790 t4_clr_port_stats(sc, pi->tx_chan); 9791 pi->tx_parse_error = 0; 9792 pi->tnl_cong_drops = 0; 9793 mtx_lock(&sc->reg_lock); 9794 for_each_vi(pi, v, vi) { 9795 if (vi->flags & VI_INIT_DONE) 9796 t4_clr_vi_stats(sc, vi->viid); 9797 } 9798 bg_map = pi->mps_bg_map; 9799 v = 0; /* reuse */ 9800 while (bg_map) { 9801 i = ffs(bg_map) - 1; 9802 t4_write_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 9803 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 9804 bg_map &= ~(1 << i); 9805 } 9806 mtx_unlock(&sc->reg_lock); 9807 9808 /* 9809 * Since this command accepts a port, clear stats for 9810 * all VIs on this port. 9811 */ 9812 for_each_vi(pi, v, vi) { 9813 if (vi->flags & VI_INIT_DONE) { 9814 struct sge_rxq *rxq; 9815 struct sge_txq *txq; 9816 struct sge_wrq *wrq; 9817 9818 for_each_rxq(vi, i, rxq) { 9819#if defined(INET) || defined(INET6) 9820 rxq->lro.lro_queued = 0; 9821 rxq->lro.lro_flushed = 0; 9822#endif 9823 rxq->rxcsum = 0; 9824 rxq->vlan_extraction = 0; 9825 } 9826 9827 for_each_txq(vi, i, txq) { 9828 txq->txcsum = 0; 9829 txq->tso_wrs = 0; 9830 txq->vlan_insertion = 0; 9831 txq->imm_wrs = 0; 9832 txq->sgl_wrs = 0; 9833 txq->txpkt_wrs = 0; 9834 txq->txpkts0_wrs = 0; 9835 txq->txpkts1_wrs = 0; 9836 txq->txpkts0_pkts = 0; 9837 txq->txpkts1_pkts = 0; 9838 mp_ring_reset_stats(txq->r); 9839 } 9840 9841#ifdef TCP_OFFLOAD 9842 /* nothing to clear for each ofld_rxq */ 9843 9844 for_each_ofld_txq(vi, i, wrq) { 9845 wrq->tx_wrs_direct = 0; 9846 wrq->tx_wrs_copied = 0; 9847 } 9848#endif 9849 9850 if (IS_MAIN_VI(vi)) { 9851 wrq = &sc->sge.ctrlq[pi->port_id]; 9852 wrq->tx_wrs_direct = 0; 9853 wrq->tx_wrs_copied = 0; 9854 } 9855 } 9856 } 9857 break; 9858 } 9859 case CHELSIO_T4_SCHED_CLASS: 9860 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 9861 break; 9862 case CHELSIO_T4_SCHED_QUEUE: 9863 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 9864 break; 9865 case CHELSIO_T4_GET_TRACER: 9866 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 9867 break; 9868 case CHELSIO_T4_SET_TRACER: 9869 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 9870 break; 9871 case CHELSIO_T4_LOAD_CFG: 9872 rc = load_cfg(sc, (struct t4_data *)data); 9873 break; 9874 case CHELSIO_T4_LOAD_BOOT: 9875 rc = load_boot(sc, (struct t4_bootrom *)data); 9876 break; 9877 case CHELSIO_T4_LOAD_BOOTCFG: 9878 rc = load_bootcfg(sc, (struct t4_data *)data); 9879 break; 9880 case CHELSIO_T4_CUDBG_DUMP: 9881 rc = cudbg_dump(sc, (struct t4_cudbg_dump *)data); 9882 break; 9883 case CHELSIO_T4_SET_OFLD_POLICY: 9884 rc = set_offload_policy(sc, (struct t4_offload_policy *)data); 9885 break; 9886 default: 9887 rc = ENOTTY; 9888 } 9889 9890 return (rc); 9891} 9892 9893void 9894t4_db_full(struct adapter *sc) 9895{ 9896 9897 CXGBE_UNIMPLEMENTED(__func__); 9898} 9899 9900void 9901t4_db_dropped(struct adapter *sc) 9902{ 9903 9904 CXGBE_UNIMPLEMENTED(__func__); 9905} 9906 9907#ifdef TCP_OFFLOAD 9908void 9909t4_iscsi_init(struct adapter *sc, u_int tag_mask, const u_int *pgsz_order) 9910{ 9911 9912 t4_write_reg(sc, A_ULP_RX_ISCSI_TAGMASK, tag_mask); 9913 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, V_HPZ0(pgsz_order[0]) | 9914 V_HPZ1(pgsz_order[1]) | V_HPZ2(pgsz_order[2]) | 9915 V_HPZ3(pgsz_order[3])); 9916} 9917 9918static int 9919toe_capability(struct vi_info *vi, int enable) 9920{ 9921 int rc; 9922 struct port_info *pi = vi->pi; 9923 struct adapter *sc = pi->adapter; 9924 9925 ASSERT_SYNCHRONIZED_OP(sc); 9926 9927 if (!is_offload(sc)) 9928 return (ENODEV); 9929 9930 if (enable) { 9931 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 9932 /* TOE is already enabled. */ 9933 return (0); 9934 } 9935 9936 /* 9937 * We need the port's queues around so that we're able to send 9938 * and receive CPLs to/from the TOE even if the ifnet for this 9939 * port has never been UP'd administratively. 9940 */ 9941 if (!(vi->flags & VI_INIT_DONE)) { 9942 rc = vi_full_init(vi); 9943 if (rc) 9944 return (rc); 9945 } 9946 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 9947 rc = vi_full_init(&pi->vi[0]); 9948 if (rc) 9949 return (rc); 9950 } 9951 9952 if (isset(&sc->offload_map, pi->port_id)) { 9953 /* TOE is enabled on another VI of this port. */ 9954 pi->uld_vis++; 9955 return (0); 9956 } 9957 9958 if (!uld_active(sc, ULD_TOM)) { 9959 rc = t4_activate_uld(sc, ULD_TOM); 9960 if (rc == EAGAIN) { 9961 log(LOG_WARNING, 9962 "You must kldload t4_tom.ko before trying " 9963 "to enable TOE on a cxgbe interface.\n"); 9964 } 9965 if (rc != 0) 9966 return (rc); 9967 KASSERT(sc->tom_softc != NULL, 9968 ("%s: TOM activated but softc NULL", __func__)); 9969 KASSERT(uld_active(sc, ULD_TOM), 9970 ("%s: TOM activated but flag not set", __func__)); 9971 } 9972 9973 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 9974 if (!uld_active(sc, ULD_IWARP)) 9975 (void) t4_activate_uld(sc, ULD_IWARP); 9976 if (!uld_active(sc, ULD_ISCSI)) 9977 (void) t4_activate_uld(sc, ULD_ISCSI); 9978 9979 pi->uld_vis++; 9980 setbit(&sc->offload_map, pi->port_id); 9981 } else { 9982 pi->uld_vis--; 9983 9984 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 9985 return (0); 9986 9987 KASSERT(uld_active(sc, ULD_TOM), 9988 ("%s: TOM never initialized?", __func__)); 9989 clrbit(&sc->offload_map, pi->port_id); 9990 } 9991 9992 return (0); 9993} 9994 9995/* 9996 * Add an upper layer driver to the global list. 9997 */ 9998int 9999t4_register_uld(struct uld_info *ui) 10000{ 10001 int rc = 0; 10002 struct uld_info *u; 10003 10004 sx_xlock(&t4_uld_list_lock); 10005 SLIST_FOREACH(u, &t4_uld_list, link) { 10006 if (u->uld_id == ui->uld_id) { 10007 rc = EEXIST; 10008 goto done; 10009 } 10010 } 10011 10012 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 10013 ui->refcount = 0; 10014done: 10015 sx_xunlock(&t4_uld_list_lock); 10016 return (rc); 10017} 10018 10019int 10020t4_unregister_uld(struct uld_info *ui) 10021{ 10022 int rc = EINVAL; 10023 struct uld_info *u; 10024 10025 sx_xlock(&t4_uld_list_lock); 10026 10027 SLIST_FOREACH(u, &t4_uld_list, link) { 10028 if (u == ui) { 10029 if (ui->refcount > 0) { 10030 rc = EBUSY; 10031 goto done; 10032 } 10033 10034 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 10035 rc = 0; 10036 goto done; 10037 } 10038 } 10039done: 10040 sx_xunlock(&t4_uld_list_lock); 10041 return (rc); 10042} 10043 10044int 10045t4_activate_uld(struct adapter *sc, int id) 10046{ 10047 int rc; 10048 struct uld_info *ui; 10049 10050 ASSERT_SYNCHRONIZED_OP(sc); 10051 10052 if (id < 0 || id > ULD_MAX) 10053 return (EINVAL); 10054 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 10055 10056 sx_slock(&t4_uld_list_lock); 10057 10058 SLIST_FOREACH(ui, &t4_uld_list, link) { 10059 if (ui->uld_id == id) { 10060 if (!(sc->flags & FULL_INIT_DONE)) { 10061 rc = adapter_full_init(sc); 10062 if (rc != 0) 10063 break; 10064 } 10065 10066 rc = ui->activate(sc); 10067 if (rc == 0) { 10068 setbit(&sc->active_ulds, id); 10069 ui->refcount++; 10070 } 10071 break; 10072 } 10073 } 10074 10075 sx_sunlock(&t4_uld_list_lock); 10076 10077 return (rc); 10078} 10079 10080int 10081t4_deactivate_uld(struct adapter *sc, int id) 10082{ 10083 int rc; 10084 struct uld_info *ui; 10085 10086 ASSERT_SYNCHRONIZED_OP(sc); 10087 10088 if (id < 0 || id > ULD_MAX) 10089 return (EINVAL); 10090 rc = ENXIO; 10091 10092 sx_slock(&t4_uld_list_lock); 10093 10094 SLIST_FOREACH(ui, &t4_uld_list, link) { 10095 if (ui->uld_id == id) { 10096 rc = ui->deactivate(sc); 10097 if (rc == 0) { 10098 clrbit(&sc->active_ulds, id); 10099 ui->refcount--; 10100 } 10101 break; 10102 } 10103 } 10104 10105 sx_sunlock(&t4_uld_list_lock); 10106 10107 return (rc); 10108} 10109 10110int 10111uld_active(struct adapter *sc, int uld_id) 10112{ 10113 10114 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 10115 10116 return (isset(&sc->active_ulds, uld_id)); 10117} 10118#endif 10119 10120/* 10121 * t = ptr to tunable. 10122 * nc = number of CPUs. 10123 * c = compiled in default for that tunable. 10124 */ 10125static void 10126calculate_nqueues(int *t, int nc, const int c) 10127{ 10128 int nq; 10129 10130 if (*t > 0) 10131 return; 10132 nq = *t < 0 ? -*t : c; 10133 *t = min(nc, nq); 10134} 10135 10136/* 10137 * Come up with reasonable defaults for some of the tunables, provided they're 10138 * not set by the user (in which case we'll use the values as is). 10139 */ 10140static void 10141tweak_tunables(void) 10142{ 10143 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 10144 10145 if (t4_ntxq < 1) { 10146#ifdef RSS 10147 t4_ntxq = rss_getnumbuckets(); 10148#else 10149 calculate_nqueues(&t4_ntxq, nc, NTXQ); 10150#endif 10151 } 10152 10153 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI); 10154 10155 if (t4_nrxq < 1) { 10156#ifdef RSS 10157 t4_nrxq = rss_getnumbuckets(); 10158#else 10159 calculate_nqueues(&t4_nrxq, nc, NRXQ); 10160#endif 10161 } 10162 10163 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI); 10164 10165#ifdef TCP_OFFLOAD 10166 calculate_nqueues(&t4_nofldtxq, nc, NOFLDTXQ); 10167 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI); 10168 calculate_nqueues(&t4_nofldrxq, nc, NOFLDRXQ); 10169 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI); 10170 10171 if (t4_toecaps_allowed == -1) 10172 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 10173 10174 if (t4_rdmacaps_allowed == -1) { 10175 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 10176 FW_CAPS_CONFIG_RDMA_RDMAC; 10177 } 10178 10179 if (t4_iscsicaps_allowed == -1) { 10180 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 10181 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 10182 FW_CAPS_CONFIG_ISCSI_T10DIF; 10183 } 10184 10185 if (t4_tmr_idx_ofld < 0 || t4_tmr_idx_ofld >= SGE_NTIMERS) 10186 t4_tmr_idx_ofld = TMR_IDX_OFLD; 10187 10188 if (t4_pktc_idx_ofld < -1 || t4_pktc_idx_ofld >= SGE_NCOUNTERS) 10189 t4_pktc_idx_ofld = PKTC_IDX_OFLD; 10190#else 10191 if (t4_toecaps_allowed == -1) 10192 t4_toecaps_allowed = 0; 10193 10194 if (t4_rdmacaps_allowed == -1) 10195 t4_rdmacaps_allowed = 0; 10196 10197 if (t4_iscsicaps_allowed == -1) 10198 t4_iscsicaps_allowed = 0; 10199#endif 10200 10201#ifdef DEV_NETMAP 10202 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI); 10203 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI); 10204#endif 10205 10206 if (t4_tmr_idx < 0 || t4_tmr_idx >= SGE_NTIMERS) 10207 t4_tmr_idx = TMR_IDX; 10208 10209 if (t4_pktc_idx < -1 || t4_pktc_idx >= SGE_NCOUNTERS) 10210 t4_pktc_idx = PKTC_IDX; 10211 10212 if (t4_qsize_txq < 128) 10213 t4_qsize_txq = 128; 10214 10215 if (t4_qsize_rxq < 128) 10216 t4_qsize_rxq = 128; 10217 while (t4_qsize_rxq & 7) 10218 t4_qsize_rxq++; 10219 10220 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 10221 10222 /* 10223 * Number of VIs to create per-port. The first VI is the "main" regular 10224 * VI for the port. The rest are additional virtual interfaces on the 10225 * same physical port. Note that the main VI does not have native 10226 * netmap support but the extra VIs do. 10227 * 10228 * Limit the number of VIs per port to the number of available 10229 * MAC addresses per port. 10230 */ 10231 if (t4_num_vis < 1) 10232 t4_num_vis = 1; 10233 if (t4_num_vis > nitems(vi_mac_funcs)) { 10234 t4_num_vis = nitems(vi_mac_funcs); 10235 printf("cxgbe: number of VIs limited to %d\n", t4_num_vis); 10236 } 10237 10238 if (pcie_relaxed_ordering < 0 || pcie_relaxed_ordering > 2) { 10239 pcie_relaxed_ordering = 1; 10240#if defined(__i386__) || defined(__amd64__) 10241 if (cpu_vendor_id == CPU_VENDOR_INTEL) 10242 pcie_relaxed_ordering = 0; 10243#endif 10244 } 10245} 10246 10247#ifdef DDB 10248static void 10249t4_dump_tcb(struct adapter *sc, int tid) 10250{ 10251 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 10252 10253 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 10254 save = t4_read_reg(sc, reg); 10255 base = sc->memwin[2].mw_base; 10256 10257 /* Dump TCB for the tid */ 10258 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 10259 tcb_addr += tid * TCB_SIZE; 10260 10261 if (is_t4(sc)) { 10262 pf = 0; 10263 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 10264 } else { 10265 pf = V_PFNUM(sc->pf); 10266 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 10267 } 10268 t4_write_reg(sc, reg, win_pos | pf); 10269 t4_read_reg(sc, reg); 10270 10271 off = tcb_addr - win_pos; 10272 for (i = 0; i < 4; i++) { 10273 uint32_t buf[8]; 10274 for (j = 0; j < 8; j++, off += 4) 10275 buf[j] = htonl(t4_read_reg(sc, base + off)); 10276 10277 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 10278 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 10279 buf[7]); 10280 } 10281 10282 t4_write_reg(sc, reg, save); 10283 t4_read_reg(sc, reg); 10284} 10285 10286static void 10287t4_dump_devlog(struct adapter *sc) 10288{ 10289 struct devlog_params *dparams = &sc->params.devlog; 10290 struct fw_devlog_e e; 10291 int i, first, j, m, nentries, rc; 10292 uint64_t ftstamp = UINT64_MAX; 10293 10294 if (dparams->start == 0) { 10295 db_printf("devlog params not valid\n"); 10296 return; 10297 } 10298 10299 nentries = dparams->size / sizeof(struct fw_devlog_e); 10300 m = fwmtype_to_hwmtype(dparams->memtype); 10301 10302 /* Find the first entry. */ 10303 first = -1; 10304 for (i = 0; i < nentries && !db_pager_quit; i++) { 10305 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10306 sizeof(e), (void *)&e); 10307 if (rc != 0) 10308 break; 10309 10310 if (e.timestamp == 0) 10311 break; 10312 10313 e.timestamp = be64toh(e.timestamp); 10314 if (e.timestamp < ftstamp) { 10315 ftstamp = e.timestamp; 10316 first = i; 10317 } 10318 } 10319 10320 if (first == -1) 10321 return; 10322 10323 i = first; 10324 do { 10325 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 10326 sizeof(e), (void *)&e); 10327 if (rc != 0) 10328 return; 10329 10330 if (e.timestamp == 0) 10331 return; 10332 10333 e.timestamp = be64toh(e.timestamp); 10334 e.seqno = be32toh(e.seqno); 10335 for (j = 0; j < 8; j++) 10336 e.params[j] = be32toh(e.params[j]); 10337 10338 db_printf("%10d %15ju %8s %8s ", 10339 e.seqno, e.timestamp, 10340 (e.level < nitems(devlog_level_strings) ? 10341 devlog_level_strings[e.level] : "UNKNOWN"), 10342 (e.facility < nitems(devlog_facility_strings) ? 10343 devlog_facility_strings[e.facility] : "UNKNOWN")); 10344 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 10345 e.params[3], e.params[4], e.params[5], e.params[6], 10346 e.params[7]); 10347 10348 if (++i == nentries) 10349 i = 0; 10350 } while (i != first && !db_pager_quit); 10351} 10352 10353static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 10354_DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 10355 10356DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 10357{ 10358 device_t dev; 10359 int t; 10360 bool valid; 10361 10362 valid = false; 10363 t = db_read_token(); 10364 if (t == tIDENT) { 10365 dev = device_lookup_by_name(db_tok_string); 10366 valid = true; 10367 } 10368 db_skip_to_eol(); 10369 if (!valid) { 10370 db_printf("usage: show t4 devlog <nexus>\n"); 10371 return; 10372 } 10373 10374 if (dev == NULL) { 10375 db_printf("device not found\n"); 10376 return; 10377 } 10378 10379 t4_dump_devlog(device_get_softc(dev)); 10380} 10381 10382DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 10383{ 10384 device_t dev; 10385 int radix, tid, t; 10386 bool valid; 10387 10388 valid = false; 10389 radix = db_radix; 10390 db_radix = 10; 10391 t = db_read_token(); 10392 if (t == tIDENT) { 10393 dev = device_lookup_by_name(db_tok_string); 10394 t = db_read_token(); 10395 if (t == tNUMBER) { 10396 tid = db_tok_number; 10397 valid = true; 10398 } 10399 } 10400 db_radix = radix; 10401 db_skip_to_eol(); 10402 if (!valid) { 10403 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 10404 return; 10405 } 10406 10407 if (dev == NULL) { 10408 db_printf("device not found\n"); 10409 return; 10410 } 10411 if (tid < 0) { 10412 db_printf("invalid tid\n"); 10413 return; 10414 } 10415 10416 t4_dump_tcb(device_get_softc(dev), tid); 10417} 10418#endif 10419 10420/* 10421 * Borrowed from cesa_prep_aes_key(). 10422 * 10423 * NB: The crypto engine wants the words in the decryption key in reverse 10424 * order. 10425 */ 10426void 10427t4_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits) 10428{ 10429 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 10430 uint32_t *dkey; 10431 int i; 10432 10433 rijndaelKeySetupEnc(ek, enc_key, kbits); 10434 dkey = dec_key; 10435 dkey += (kbits / 8) / 4; 10436 10437 switch (kbits) { 10438 case 128: 10439 for (i = 0; i < 4; i++) 10440 *--dkey = htobe32(ek[4 * 10 + i]); 10441 break; 10442 case 192: 10443 for (i = 0; i < 2; i++) 10444 *--dkey = htobe32(ek[4 * 11 + 2 + i]); 10445 for (i = 0; i < 4; i++) 10446 *--dkey = htobe32(ek[4 * 12 + i]); 10447 break; 10448 case 256: 10449 for (i = 0; i < 4; i++) 10450 *--dkey = htobe32(ek[4 * 13 + i]); 10451 for (i = 0; i < 4; i++) 10452 *--dkey = htobe32(ek[4 * 14 + i]); 10453 break; 10454 } 10455 MPASS(dkey == dec_key); 10456} 10457 10458static struct sx mlu; /* mod load unload */ 10459SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 10460 10461static int 10462mod_event(module_t mod, int cmd, void *arg) 10463{ 10464 int rc = 0; 10465 static int loaded = 0; 10466 10467 switch (cmd) { 10468 case MOD_LOAD: 10469 sx_xlock(&mlu); 10470 if (loaded++ == 0) { 10471 t4_sge_modload(); 10472 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10473 t4_filter_rpl, CPL_COOKIE_FILTER); 10474 t4_register_shared_cpl_handler(CPL_L2T_WRITE_RPL, 10475 do_l2t_write_rpl, CPL_COOKIE_FILTER); 10476 t4_register_shared_cpl_handler(CPL_ACT_OPEN_RPL, 10477 t4_hashfilter_ao_rpl, CPL_COOKIE_HASHFILTER); 10478 t4_register_shared_cpl_handler(CPL_SET_TCB_RPL, 10479 t4_hashfilter_tcb_rpl, CPL_COOKIE_HASHFILTER); 10480 t4_register_shared_cpl_handler(CPL_ABORT_RPL_RSS, 10481 t4_del_hashfilter_rpl, CPL_COOKIE_HASHFILTER); 10482 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 10483 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 10484 t4_register_cpl_handler(CPL_SMT_WRITE_RPL, 10485 do_smt_write_rpl); 10486 sx_init(&t4_list_lock, "T4/T5 adapters"); 10487 SLIST_INIT(&t4_list); 10488#ifdef TCP_OFFLOAD 10489 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 10490 SLIST_INIT(&t4_uld_list); 10491#endif 10492 t4_tracer_modload(); 10493 tweak_tunables(); 10494 } 10495 sx_xunlock(&mlu); 10496 break; 10497 10498 case MOD_UNLOAD: 10499 sx_xlock(&mlu); 10500 if (--loaded == 0) { 10501 int tries; 10502 10503 sx_slock(&t4_list_lock); 10504 if (!SLIST_EMPTY(&t4_list)) { 10505 rc = EBUSY; 10506 sx_sunlock(&t4_list_lock); 10507 goto done_unload; 10508 } 10509#ifdef TCP_OFFLOAD 10510 sx_slock(&t4_uld_list_lock); 10511 if (!SLIST_EMPTY(&t4_uld_list)) { 10512 rc = EBUSY; 10513 sx_sunlock(&t4_uld_list_lock); 10514 sx_sunlock(&t4_list_lock); 10515 goto done_unload; 10516 } 10517#endif 10518 tries = 0; 10519 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 10520 uprintf("%ju clusters with custom free routine " 10521 "still is use.\n", t4_sge_extfree_refs()); 10522 pause("t4unload", 2 * hz); 10523 } 10524#ifdef TCP_OFFLOAD 10525 sx_sunlock(&t4_uld_list_lock); 10526#endif 10527 sx_sunlock(&t4_list_lock); 10528 10529 if (t4_sge_extfree_refs() == 0) { 10530 t4_tracer_modunload(); 10531#ifdef TCP_OFFLOAD 10532 sx_destroy(&t4_uld_list_lock); 10533#endif 10534 sx_destroy(&t4_list_lock); 10535 t4_sge_modunload(); 10536 loaded = 0; 10537 } else { 10538 rc = EBUSY; 10539 loaded++; /* undo earlier decrement */ 10540 } 10541 } 10542done_unload: 10543 sx_xunlock(&mlu); 10544 break; 10545 } 10546 10547 return (rc); 10548} 10549 10550static devclass_t t4_devclass, t5_devclass, t6_devclass; 10551static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 10552static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 10553 10554DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 10555MODULE_VERSION(t4nex, 1); 10556MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 10557#ifdef DEV_NETMAP 10558MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 10559#endif /* DEV_NETMAP */ 10560 10561DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 10562MODULE_VERSION(t5nex, 1); 10563MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 10564#ifdef DEV_NETMAP 10565MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 10566#endif /* DEV_NETMAP */ 10567 10568DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 10569MODULE_VERSION(t6nex, 1); 10570MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 10571#ifdef DEV_NETMAP 10572MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 10573#endif /* DEV_NETMAP */ 10574 10575DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 10576MODULE_VERSION(cxgbe, 1); 10577 10578DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 10579MODULE_VERSION(cxl, 1); 10580 10581DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 10582MODULE_VERSION(cc, 1); 10583 10584DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 10585MODULE_VERSION(vcxgbe, 1); 10586 10587DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 10588MODULE_VERSION(vcxl, 1); 10589 10590DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 10591MODULE_VERSION(vcc, 1); 10592