t4_main.c revision 312187
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/11/sys/dev/cxgbe/t4_main.c 312187 2017-01-14 15:52:56Z np $"); 30 31#include "opt_ddb.h" 32#include "opt_inet.h" 33#include "opt_inet6.h" 34#include "opt_rss.h" 35 36#include <sys/param.h> 37#include <sys/conf.h> 38#include <sys/priv.h> 39#include <sys/kernel.h> 40#include <sys/bus.h> 41#include <sys/module.h> 42#include <sys/malloc.h> 43#include <sys/queue.h> 44#include <sys/taskqueue.h> 45#include <sys/pciio.h> 46#include <dev/pci/pcireg.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pci_private.h> 49#include <sys/firmware.h> 50#include <sys/sbuf.h> 51#include <sys/smp.h> 52#include <sys/socket.h> 53#include <sys/sockio.h> 54#include <sys/sysctl.h> 55#include <net/ethernet.h> 56#include <net/if.h> 57#include <net/if_types.h> 58#include <net/if_dl.h> 59#include <net/if_vlan_var.h> 60#ifdef RSS 61#include <net/rss_config.h> 62#endif 63#if defined(__i386__) || defined(__amd64__) 64#include <vm/vm.h> 65#include <vm/pmap.h> 66#endif 67#ifdef DDB 68#include <ddb/ddb.h> 69#include <ddb/db_lex.h> 70#endif 71 72#include "common/common.h" 73#include "common/t4_msg.h" 74#include "common/t4_regs.h" 75#include "common/t4_regs_values.h" 76#include "t4_ioctl.h" 77#include "t4_l2t.h" 78#include "t4_mp_ring.h" 79#include "t4_if.h" 80 81/* T4 bus driver interface */ 82static int t4_probe(device_t); 83static int t4_attach(device_t); 84static int t4_detach(device_t); 85static int t4_ready(device_t); 86static int t4_read_port_device(device_t, int, device_t *); 87static device_method_t t4_methods[] = { 88 DEVMETHOD(device_probe, t4_probe), 89 DEVMETHOD(device_attach, t4_attach), 90 DEVMETHOD(device_detach, t4_detach), 91 92 DEVMETHOD(t4_is_main_ready, t4_ready), 93 DEVMETHOD(t4_read_port_device, t4_read_port_device), 94 95 DEVMETHOD_END 96}; 97static driver_t t4_driver = { 98 "t4nex", 99 t4_methods, 100 sizeof(struct adapter) 101}; 102 103 104/* T4 port (cxgbe) interface */ 105static int cxgbe_probe(device_t); 106static int cxgbe_attach(device_t); 107static int cxgbe_detach(device_t); 108device_method_t cxgbe_methods[] = { 109 DEVMETHOD(device_probe, cxgbe_probe), 110 DEVMETHOD(device_attach, cxgbe_attach), 111 DEVMETHOD(device_detach, cxgbe_detach), 112 { 0, 0 } 113}; 114static driver_t cxgbe_driver = { 115 "cxgbe", 116 cxgbe_methods, 117 sizeof(struct port_info) 118}; 119 120/* T4 VI (vcxgbe) interface */ 121static int vcxgbe_probe(device_t); 122static int vcxgbe_attach(device_t); 123static int vcxgbe_detach(device_t); 124static device_method_t vcxgbe_methods[] = { 125 DEVMETHOD(device_probe, vcxgbe_probe), 126 DEVMETHOD(device_attach, vcxgbe_attach), 127 DEVMETHOD(device_detach, vcxgbe_detach), 128 { 0, 0 } 129}; 130static driver_t vcxgbe_driver = { 131 "vcxgbe", 132 vcxgbe_methods, 133 sizeof(struct vi_info) 134}; 135 136static d_ioctl_t t4_ioctl; 137 138static struct cdevsw t4_cdevsw = { 139 .d_version = D_VERSION, 140 .d_ioctl = t4_ioctl, 141 .d_name = "t4nex", 142}; 143 144/* T5 bus driver interface */ 145static int t5_probe(device_t); 146static device_method_t t5_methods[] = { 147 DEVMETHOD(device_probe, t5_probe), 148 DEVMETHOD(device_attach, t4_attach), 149 DEVMETHOD(device_detach, t4_detach), 150 151 DEVMETHOD(t4_is_main_ready, t4_ready), 152 DEVMETHOD(t4_read_port_device, t4_read_port_device), 153 154 DEVMETHOD_END 155}; 156static driver_t t5_driver = { 157 "t5nex", 158 t5_methods, 159 sizeof(struct adapter) 160}; 161 162 163/* T5 port (cxl) interface */ 164static driver_t cxl_driver = { 165 "cxl", 166 cxgbe_methods, 167 sizeof(struct port_info) 168}; 169 170/* T5 VI (vcxl) interface */ 171static driver_t vcxl_driver = { 172 "vcxl", 173 vcxgbe_methods, 174 sizeof(struct vi_info) 175}; 176 177/* T6 bus driver interface */ 178static int t6_probe(device_t); 179static device_method_t t6_methods[] = { 180 DEVMETHOD(device_probe, t6_probe), 181 DEVMETHOD(device_attach, t4_attach), 182 DEVMETHOD(device_detach, t4_detach), 183 184 DEVMETHOD(t4_is_main_ready, t4_ready), 185 DEVMETHOD(t4_read_port_device, t4_read_port_device), 186 187 DEVMETHOD_END 188}; 189static driver_t t6_driver = { 190 "t6nex", 191 t6_methods, 192 sizeof(struct adapter) 193}; 194 195 196/* T6 port (cc) interface */ 197static driver_t cc_driver = { 198 "cc", 199 cxgbe_methods, 200 sizeof(struct port_info) 201}; 202 203/* T6 VI (vcc) interface */ 204static driver_t vcc_driver = { 205 "vcc", 206 vcxgbe_methods, 207 sizeof(struct vi_info) 208}; 209 210/* ifnet + media interface */ 211static void cxgbe_init(void *); 212static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t); 213static int cxgbe_transmit(struct ifnet *, struct mbuf *); 214static void cxgbe_qflush(struct ifnet *); 215static int cxgbe_media_change(struct ifnet *); 216static void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 217 218MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services"); 219 220/* 221 * Correct lock order when you need to acquire multiple locks is t4_list_lock, 222 * then ADAPTER_LOCK, then t4_uld_list_lock. 223 */ 224static struct sx t4_list_lock; 225SLIST_HEAD(, adapter) t4_list; 226#ifdef TCP_OFFLOAD 227static struct sx t4_uld_list_lock; 228SLIST_HEAD(, uld_info) t4_uld_list; 229#endif 230 231/* 232 * Tunables. See tweak_tunables() too. 233 * 234 * Each tunable is set to a default value here if it's known at compile-time. 235 * Otherwise it is set to -1 as an indication to tweak_tunables() that it should 236 * provide a reasonable default when the driver is loaded. 237 * 238 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to 239 * T5 are under hw.cxl. 240 */ 241 242/* 243 * Number of queues for tx and rx, 10G and 1G, NIC and offload. 244 */ 245#define NTXQ_10G 16 246int t4_ntxq10g = -1; 247TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g); 248 249#define NRXQ_10G 8 250int t4_nrxq10g = -1; 251TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g); 252 253#define NTXQ_1G 4 254int t4_ntxq1g = -1; 255TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g); 256 257#define NRXQ_1G 2 258int t4_nrxq1g = -1; 259TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g); 260 261#define NTXQ_VI 1 262static int t4_ntxq_vi = -1; 263TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi); 264 265#define NRXQ_VI 1 266static int t4_nrxq_vi = -1; 267TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi); 268 269static int t4_rsrv_noflowq = 0; 270TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq); 271 272#ifdef TCP_OFFLOAD 273#define NOFLDTXQ_10G 8 274static int t4_nofldtxq10g = -1; 275TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g); 276 277#define NOFLDRXQ_10G 2 278static int t4_nofldrxq10g = -1; 279TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g); 280 281#define NOFLDTXQ_1G 2 282static int t4_nofldtxq1g = -1; 283TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g); 284 285#define NOFLDRXQ_1G 1 286static int t4_nofldrxq1g = -1; 287TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g); 288 289#define NOFLDTXQ_VI 1 290static int t4_nofldtxq_vi = -1; 291TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi); 292 293#define NOFLDRXQ_VI 1 294static int t4_nofldrxq_vi = -1; 295TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi); 296#endif 297 298#ifdef DEV_NETMAP 299#define NNMTXQ_VI 2 300static int t4_nnmtxq_vi = -1; 301TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi); 302 303#define NNMRXQ_VI 2 304static int t4_nnmrxq_vi = -1; 305TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi); 306#endif 307 308/* 309 * Holdoff parameters for 10G and 1G ports. 310 */ 311#define TMR_IDX_10G 1 312int t4_tmr_idx_10g = TMR_IDX_10G; 313TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g); 314 315#define PKTC_IDX_10G (-1) 316int t4_pktc_idx_10g = PKTC_IDX_10G; 317TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g); 318 319#define TMR_IDX_1G 1 320int t4_tmr_idx_1g = TMR_IDX_1G; 321TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g); 322 323#define PKTC_IDX_1G (-1) 324int t4_pktc_idx_1g = PKTC_IDX_1G; 325TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g); 326 327/* 328 * Size (# of entries) of each tx and rx queue. 329 */ 330unsigned int t4_qsize_txq = TX_EQ_QSIZE; 331TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq); 332 333unsigned int t4_qsize_rxq = RX_IQ_QSIZE; 334TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq); 335 336/* 337 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively). 338 */ 339int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX; 340TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types); 341 342/* 343 * Configuration file. 344 */ 345#define DEFAULT_CF "default" 346#define FLASH_CF "flash" 347#define UWIRE_CF "uwire" 348#define FPGA_CF "fpga" 349static char t4_cfg_file[32] = DEFAULT_CF; 350TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file)); 351 352/* 353 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively). 354 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them. 355 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water 356 * mark or when signalled to do so, 0 to never emit PAUSE. 357 */ 358static int t4_pause_settings = PAUSE_TX | PAUSE_RX; 359TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings); 360 361/* 362 * Forward Error Correction settings (bit 0, 1, 2 = FEC_RS, FEC_BASER_RS, 363 * FEC_RESERVED respectively). 364 * -1 to run with the firmware default. 365 * 0 to disable FEC. 366 */ 367static int t4_fec = -1; 368TUNABLE_INT("hw.cxgbe.fec", &t4_fec); 369 370/* 371 * Link autonegotiation. 372 * -1 to run with the firmware default. 373 * 0 to disable. 374 * 1 to enable. 375 */ 376static int t4_autoneg = -1; 377TUNABLE_INT("hw.cxgbe.autoneg", &t4_autoneg); 378 379/* 380 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed, 381 * encouraged respectively). 382 */ 383static unsigned int t4_fw_install = 1; 384TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install); 385 386/* 387 * ASIC features that will be used. Disable the ones you don't want so that the 388 * chip resources aren't wasted on features that will not be used. 389 */ 390static int t4_nbmcaps_allowed = 0; 391TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed); 392 393static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */ 394TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed); 395 396static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS | 397 FW_CAPS_CONFIG_SWITCH_EGRESS; 398TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed); 399 400static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC; 401TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed); 402 403static int t4_toecaps_allowed = -1; 404TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed); 405 406static int t4_rdmacaps_allowed = -1; 407TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed); 408 409static int t4_cryptocaps_allowed = 0; 410TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed); 411 412static int t4_iscsicaps_allowed = -1; 413TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed); 414 415static int t4_fcoecaps_allowed = 0; 416TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed); 417 418static int t5_write_combine = 0; 419TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine); 420 421static int t4_num_vis = 1; 422TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis); 423 424/* Functions used by extra VIs to obtain unique MAC addresses for each VI. */ 425static int vi_mac_funcs[] = { 426 FW_VI_FUNC_OFLD, 427 FW_VI_FUNC_IWARP, 428 FW_VI_FUNC_OPENISCSI, 429 FW_VI_FUNC_OPENFCOE, 430 FW_VI_FUNC_FOISCSI, 431 FW_VI_FUNC_FOFCOE, 432}; 433 434struct intrs_and_queues { 435 uint16_t intr_type; /* INTx, MSI, or MSI-X */ 436 uint16_t nirq; /* Total # of vectors */ 437 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */ 438 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */ 439 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */ 440 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */ 441 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */ 442 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */ 443 uint16_t rsrv_noflowq; /* Flag whether to reserve queue 0 */ 444 uint16_t nofldtxq10g; /* # of TOE txq's for each 10G port */ 445 uint16_t nofldrxq10g; /* # of TOE rxq's for each 10G port */ 446 uint16_t nofldtxq1g; /* # of TOE txq's for each 1G port */ 447 uint16_t nofldrxq1g; /* # of TOE rxq's for each 1G port */ 448 449 /* The vcxgbe/vcxl interfaces use these and not the ones above. */ 450 uint16_t ntxq_vi; /* # of NIC txq's */ 451 uint16_t nrxq_vi; /* # of NIC rxq's */ 452 uint16_t nofldtxq_vi; /* # of TOE txq's */ 453 uint16_t nofldrxq_vi; /* # of TOE rxq's */ 454 uint16_t nnmtxq_vi; /* # of netmap txq's */ 455 uint16_t nnmrxq_vi; /* # of netmap rxq's */ 456}; 457 458struct filter_entry { 459 uint32_t valid:1; /* filter allocated and valid */ 460 uint32_t locked:1; /* filter is administratively locked */ 461 uint32_t pending:1; /* filter action is pending firmware reply */ 462 uint32_t smtidx:8; /* Source MAC Table index for smac */ 463 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 464 465 struct t4_filter_specification fs; 466}; 467 468static void setup_memwin(struct adapter *); 469static void position_memwin(struct adapter *, int, uint32_t); 470static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 471static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *, 472 int); 473static inline int write_via_memwin(struct adapter *, int, uint32_t, 474 const uint32_t *, int); 475static int validate_mem_range(struct adapter *, uint32_t, int); 476static int fwmtype_to_hwmtype(int); 477static int validate_mt_off_len(struct adapter *, int, uint32_t, int, 478 uint32_t *); 479static int fixup_devlog_params(struct adapter *); 480static int cfg_itype_and_nqueues(struct adapter *, int, int, int, 481 struct intrs_and_queues *); 482static int prep_firmware(struct adapter *); 483static int partition_resources(struct adapter *, const struct firmware *, 484 const char *); 485static int get_params__pre_init(struct adapter *); 486static int get_params__post_init(struct adapter *); 487static int set_params__post_init(struct adapter *); 488static void t4_set_desc(struct adapter *); 489static void build_medialist(struct port_info *, struct ifmedia *); 490static int cxgbe_init_synchronized(struct vi_info *); 491static int cxgbe_uninit_synchronized(struct vi_info *); 492static void quiesce_txq(struct adapter *, struct sge_txq *); 493static void quiesce_wrq(struct adapter *, struct sge_wrq *); 494static void quiesce_iq(struct adapter *, struct sge_iq *); 495static void quiesce_fl(struct adapter *, struct sge_fl *); 496static int t4_alloc_irq(struct adapter *, struct irq *, int rid, 497 driver_intr_t *, void *, char *); 498static int t4_free_irq(struct adapter *, struct irq *); 499static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *); 500static void vi_refresh_stats(struct adapter *, struct vi_info *); 501static void cxgbe_refresh_stats(struct adapter *, struct port_info *); 502static void cxgbe_tick(void *); 503static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t); 504static void cxgbe_sysctls(struct port_info *); 505static int sysctl_int_array(SYSCTL_HANDLER_ARGS); 506static int sysctl_bitfield(SYSCTL_HANDLER_ARGS); 507static int sysctl_btphy(SYSCTL_HANDLER_ARGS); 508static int sysctl_noflowq(SYSCTL_HANDLER_ARGS); 509static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS); 510static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS); 511static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS); 512static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS); 513static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS); 514static int sysctl_fec(SYSCTL_HANDLER_ARGS); 515static int sysctl_autoneg(SYSCTL_HANDLER_ARGS); 516static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS); 517static int sysctl_temperature(SYSCTL_HANDLER_ARGS); 518#ifdef SBUF_DRAIN 519static int sysctl_cctrl(SYSCTL_HANDLER_ARGS); 520static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS); 521static int sysctl_cim_la(SYSCTL_HANDLER_ARGS); 522static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS); 523static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS); 524static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS); 525static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS); 526static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS); 527static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS); 528static int sysctl_devlog(SYSCTL_HANDLER_ARGS); 529static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS); 530static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS); 531static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS); 532static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS); 533static int sysctl_meminfo(SYSCTL_HANDLER_ARGS); 534static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS); 535static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS); 536static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS); 537static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS); 538static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS); 539static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS); 540static int sysctl_tids(SYSCTL_HANDLER_ARGS); 541static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS); 542static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS); 543static int sysctl_tp_la(SYSCTL_HANDLER_ARGS); 544static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS); 545static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS); 546static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS); 547static int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 548#endif 549#ifdef TCP_OFFLOAD 550static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS); 551static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS); 552static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS); 553#endif 554static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t); 555static uint32_t mode_to_fconf(uint32_t); 556static uint32_t mode_to_iconf(uint32_t); 557static int check_fspec_against_fconf_iconf(struct adapter *, 558 struct t4_filter_specification *); 559static int get_filter_mode(struct adapter *, uint32_t *); 560static int set_filter_mode(struct adapter *, uint32_t); 561static inline uint64_t get_filter_hits(struct adapter *, uint32_t); 562static int get_filter(struct adapter *, struct t4_filter *); 563static int set_filter(struct adapter *, struct t4_filter *); 564static int del_filter(struct adapter *, struct t4_filter *); 565static void clear_filter(struct filter_entry *); 566static int set_filter_wr(struct adapter *, int); 567static int del_filter_wr(struct adapter *, int); 568static int set_tcb_rpl(struct sge_iq *, const struct rss_header *, 569 struct mbuf *); 570static int get_sge_context(struct adapter *, struct t4_sge_context *); 571static int load_fw(struct adapter *, struct t4_data *); 572static int load_cfg(struct adapter *, struct t4_data *); 573static int read_card_mem(struct adapter *, int, struct t4_mem_range *); 574static int read_i2c(struct adapter *, struct t4_i2c_data *); 575#ifdef TCP_OFFLOAD 576static int toe_capability(struct vi_info *, int); 577#endif 578static int mod_event(module_t, int, void *); 579static int notify_siblings(device_t, int); 580 581struct { 582 uint16_t device; 583 char *desc; 584} t4_pciids[] = { 585 {0xa000, "Chelsio Terminator 4 FPGA"}, 586 {0x4400, "Chelsio T440-dbg"}, 587 {0x4401, "Chelsio T420-CR"}, 588 {0x4402, "Chelsio T422-CR"}, 589 {0x4403, "Chelsio T440-CR"}, 590 {0x4404, "Chelsio T420-BCH"}, 591 {0x4405, "Chelsio T440-BCH"}, 592 {0x4406, "Chelsio T440-CH"}, 593 {0x4407, "Chelsio T420-SO"}, 594 {0x4408, "Chelsio T420-CX"}, 595 {0x4409, "Chelsio T420-BT"}, 596 {0x440a, "Chelsio T404-BT"}, 597 {0x440e, "Chelsio T440-LP-CR"}, 598}, t5_pciids[] = { 599 {0xb000, "Chelsio Terminator 5 FPGA"}, 600 {0x5400, "Chelsio T580-dbg"}, 601 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */ 602 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */ 603 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */ 604 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */ 605 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */ 606 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */ 607 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */ 608 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */ 609 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */ 610 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */ 611 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */ 612 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */ 613 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */ 614#ifdef notyet 615 {0x5404, "Chelsio T520-BCH"}, 616 {0x5405, "Chelsio T540-BCH"}, 617 {0x5406, "Chelsio T540-CH"}, 618 {0x5408, "Chelsio T520-CX"}, 619 {0x540b, "Chelsio B520-SR"}, 620 {0x540c, "Chelsio B504-BT"}, 621 {0x540f, "Chelsio Amsterdam"}, 622 {0x5413, "Chelsio T580-CHR"}, 623#endif 624}, t6_pciids[] = { 625 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */ 626 {0x6400, "Chelsio T6225-DBG"}, /* 2 x 10/25G, debug */ 627 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */ 628 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */ 629 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */ 630 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */ 631 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */ 632 {0x6410, "Chelsio T62100-DBG"}, /* 2 x 40/50/100G, debug */ 633}; 634 635#ifdef TCP_OFFLOAD 636/* 637 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be 638 * exactly the same for both rxq and ofld_rxq. 639 */ 640CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq)); 641CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl)); 642#endif 643CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE); 644 645static int 646t4_probe(device_t dev) 647{ 648 int i; 649 uint16_t v = pci_get_vendor(dev); 650 uint16_t d = pci_get_device(dev); 651 uint8_t f = pci_get_function(dev); 652 653 if (v != PCI_VENDOR_ID_CHELSIO) 654 return (ENXIO); 655 656 /* Attach only to PF0 of the FPGA */ 657 if (d == 0xa000 && f != 0) 658 return (ENXIO); 659 660 for (i = 0; i < nitems(t4_pciids); i++) { 661 if (d == t4_pciids[i].device) { 662 device_set_desc(dev, t4_pciids[i].desc); 663 return (BUS_PROBE_DEFAULT); 664 } 665 } 666 667 return (ENXIO); 668} 669 670static int 671t5_probe(device_t dev) 672{ 673 int i; 674 uint16_t v = pci_get_vendor(dev); 675 uint16_t d = pci_get_device(dev); 676 uint8_t f = pci_get_function(dev); 677 678 if (v != PCI_VENDOR_ID_CHELSIO) 679 return (ENXIO); 680 681 /* Attach only to PF0 of the FPGA */ 682 if (d == 0xb000 && f != 0) 683 return (ENXIO); 684 685 for (i = 0; i < nitems(t5_pciids); i++) { 686 if (d == t5_pciids[i].device) { 687 device_set_desc(dev, t5_pciids[i].desc); 688 return (BUS_PROBE_DEFAULT); 689 } 690 } 691 692 return (ENXIO); 693} 694 695static int 696t6_probe(device_t dev) 697{ 698 int i; 699 uint16_t v = pci_get_vendor(dev); 700 uint16_t d = pci_get_device(dev); 701 702 if (v != PCI_VENDOR_ID_CHELSIO) 703 return (ENXIO); 704 705 for (i = 0; i < nitems(t6_pciids); i++) { 706 if (d == t6_pciids[i].device) { 707 device_set_desc(dev, t6_pciids[i].desc); 708 return (BUS_PROBE_DEFAULT); 709 } 710 } 711 712 return (ENXIO); 713} 714 715static void 716t5_attribute_workaround(device_t dev) 717{ 718 device_t root_port; 719 uint32_t v; 720 721 /* 722 * The T5 chips do not properly echo the No Snoop and Relaxed 723 * Ordering attributes when replying to a TLP from a Root 724 * Port. As a workaround, find the parent Root Port and 725 * disable No Snoop and Relaxed Ordering. Note that this 726 * affects all devices under this root port. 727 */ 728 root_port = pci_find_pcie_root_port(dev); 729 if (root_port == NULL) { 730 device_printf(dev, "Unable to find parent root port\n"); 731 return; 732 } 733 734 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL, 735 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2); 736 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) != 737 0) 738 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n", 739 device_get_nameunit(root_port)); 740} 741 742static const struct devnames devnames[] = { 743 { 744 .nexus_name = "t4nex", 745 .ifnet_name = "cxgbe", 746 .vi_ifnet_name = "vcxgbe", 747 .pf03_drv_name = "t4iov", 748 .vf_nexus_name = "t4vf", 749 .vf_ifnet_name = "cxgbev" 750 }, { 751 .nexus_name = "t5nex", 752 .ifnet_name = "cxl", 753 .vi_ifnet_name = "vcxl", 754 .pf03_drv_name = "t5iov", 755 .vf_nexus_name = "t5vf", 756 .vf_ifnet_name = "cxlv" 757 }, { 758 .nexus_name = "t6nex", 759 .ifnet_name = "cc", 760 .vi_ifnet_name = "vcc", 761 .pf03_drv_name = "t6iov", 762 .vf_nexus_name = "t6vf", 763 .vf_ifnet_name = "ccv" 764 } 765}; 766 767void 768t4_init_devnames(struct adapter *sc) 769{ 770 int id; 771 772 id = chip_id(sc); 773 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames)) 774 sc->names = &devnames[id - CHELSIO_T4]; 775 else { 776 device_printf(sc->dev, "chip id %d is not supported.\n", id); 777 sc->names = NULL; 778 } 779} 780 781static int 782t4_attach(device_t dev) 783{ 784 struct adapter *sc; 785 int rc = 0, i, j, n10g, n1g, rqidx, tqidx; 786 struct make_dev_args mda; 787 struct intrs_and_queues iaq; 788 struct sge *s; 789 uint8_t *buf; 790#ifdef TCP_OFFLOAD 791 int ofld_rqidx, ofld_tqidx; 792#endif 793#ifdef DEV_NETMAP 794 int nm_rqidx, nm_tqidx; 795#endif 796 int num_vis; 797 798 sc = device_get_softc(dev); 799 sc->dev = dev; 800 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags); 801 802 if ((pci_get_device(dev) & 0xff00) == 0x5400) 803 t5_attribute_workaround(dev); 804 pci_enable_busmaster(dev); 805 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 806 uint32_t v; 807 808 pci_set_max_read_req(dev, 4096); 809 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 810 v |= PCIEM_CTL_RELAXED_ORD_ENABLE; 811 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); 812 813 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5); 814 } 815 816 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS); 817 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL); 818 sc->traceq = -1; 819 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF); 820 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer", 821 device_get_nameunit(dev)); 822 823 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 824 device_get_nameunit(dev)); 825 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 826 t4_add_adapter(sc); 827 828 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 829 TAILQ_INIT(&sc->sfl); 830 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 831 832 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 833 834 rc = t4_map_bars_0_and_4(sc); 835 if (rc != 0) 836 goto done; /* error message displayed already */ 837 838 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 839 840 /* Prepare the adapter for operation. */ 841 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK); 842 rc = -t4_prep_adapter(sc, buf); 843 free(buf, M_CXGBE); 844 if (rc != 0) { 845 device_printf(dev, "failed to prepare adapter: %d.\n", rc); 846 goto done; 847 } 848 849 /* 850 * This is the real PF# to which we're attaching. Works from within PCI 851 * passthrough environments too, where pci_get_function() could return a 852 * different PF# depending on the passthrough configuration. We need to 853 * use the real PF# in all our communication with the firmware. 854 */ 855 j = t4_read_reg(sc, A_PL_WHOAMI); 856 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j); 857 sc->mbox = sc->pf; 858 859 t4_init_devnames(sc); 860 if (sc->names == NULL) { 861 rc = ENOTSUP; 862 goto done; /* error message displayed already */ 863 } 864 865 /* 866 * Do this really early, with the memory windows set up even before the 867 * character device. The userland tool's register i/o and mem read 868 * will work even in "recovery mode". 869 */ 870 setup_memwin(sc); 871 if (t4_init_devlog_params(sc, 0) == 0) 872 fixup_devlog_params(sc); 873 make_dev_args_init(&mda); 874 mda.mda_devsw = &t4_cdevsw; 875 mda.mda_uid = UID_ROOT; 876 mda.mda_gid = GID_WHEEL; 877 mda.mda_mode = 0600; 878 mda.mda_si_drv1 = sc; 879 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 880 if (rc != 0) 881 device_printf(dev, "failed to create nexus char device: %d.\n", 882 rc); 883 884 /* Go no further if recovery mode has been requested. */ 885 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) { 886 device_printf(dev, "recovery mode.\n"); 887 goto done; 888 } 889 890#if defined(__i386__) 891 if ((cpu_feature & CPUID_CX8) == 0) { 892 device_printf(dev, "64 bit atomics not available.\n"); 893 rc = ENOTSUP; 894 goto done; 895 } 896#endif 897 898 /* Prepare the firmware for operation */ 899 rc = prep_firmware(sc); 900 if (rc != 0) 901 goto done; /* error message displayed already */ 902 903 rc = get_params__post_init(sc); 904 if (rc != 0) 905 goto done; /* error message displayed already */ 906 907 rc = set_params__post_init(sc); 908 if (rc != 0) 909 goto done; /* error message displayed already */ 910 911 rc = t4_map_bar_2(sc); 912 if (rc != 0) 913 goto done; /* error message displayed already */ 914 915 rc = t4_create_dma_tag(sc); 916 if (rc != 0) 917 goto done; /* error message displayed already */ 918 919 /* 920 * Number of VIs to create per-port. The first VI is the "main" regular 921 * VI for the port. The rest are additional virtual interfaces on the 922 * same physical port. Note that the main VI does not have native 923 * netmap support but the extra VIs do. 924 * 925 * Limit the number of VIs per port to the number of available 926 * MAC addresses per port. 927 */ 928 if (t4_num_vis >= 1) 929 num_vis = t4_num_vis; 930 else 931 num_vis = 1; 932 if (num_vis > nitems(vi_mac_funcs)) { 933 num_vis = nitems(vi_mac_funcs); 934 device_printf(dev, "Number of VIs limited to %d\n", num_vis); 935 } 936 937 /* 938 * First pass over all the ports - allocate VIs and initialize some 939 * basic parameters like mac address, port type, etc. We also figure 940 * out whether a port is 10G or 1G and use that information when 941 * calculating how many interrupts to attempt to allocate. 942 */ 943 n10g = n1g = 0; 944 for_each_port(sc, i) { 945 struct port_info *pi; 946 struct link_config *lc; 947 948 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 949 sc->port[i] = pi; 950 951 /* These must be set before t4_port_init */ 952 pi->adapter = sc; 953 pi->port_id = i; 954 /* 955 * XXX: vi[0] is special so we can't delay this allocation until 956 * pi->nvi's final value is known. 957 */ 958 pi->vi = malloc(sizeof(struct vi_info) * num_vis, M_CXGBE, 959 M_ZERO | M_WAITOK); 960 961 /* 962 * Allocate the "main" VI and initialize parameters 963 * like mac addr. 964 */ 965 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 966 if (rc != 0) { 967 device_printf(dev, "unable to initialize port %d: %d\n", 968 i, rc); 969 free(pi->vi, M_CXGBE); 970 free(pi, M_CXGBE); 971 sc->port[i] = NULL; 972 goto done; 973 } 974 975 lc = &pi->link_cfg; 976 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX); 977 lc->requested_fc |= t4_pause_settings; 978 if (t4_fec != -1) { 979 lc->requested_fec = t4_fec & 980 G_FW_PORT_CAP_FEC(lc->supported); 981 } 982 if (lc->supported & FW_PORT_CAP_ANEG && t4_autoneg != -1) { 983 lc->autoneg = t4_autoneg ? AUTONEG_ENABLE : 984 AUTONEG_DISABLE; 985 } 986 987 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 988 if (rc != 0) { 989 device_printf(dev, "port %d l1cfg failed: %d\n", i, rc); 990 free(pi->vi, M_CXGBE); 991 free(pi, M_CXGBE); 992 sc->port[i] = NULL; 993 goto done; 994 } 995 996 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 997 device_get_nameunit(dev), i); 998 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 999 sc->chan_map[pi->tx_chan] = i; 1000 1001 pi->tc = malloc(sizeof(struct tx_sched_class) * 1002 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK); 1003 1004 if (port_top_speed(pi) >= 10) { 1005 n10g++; 1006 } else { 1007 n1g++; 1008 } 1009 1010 pi->dev = device_add_child(dev, sc->names->ifnet_name, -1); 1011 if (pi->dev == NULL) { 1012 device_printf(dev, 1013 "failed to add device for port %d.\n", i); 1014 rc = ENXIO; 1015 goto done; 1016 } 1017 pi->vi[0].dev = pi->dev; 1018 device_set_softc(pi->dev, pi); 1019 } 1020 1021 /* 1022 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 1023 */ 1024 rc = cfg_itype_and_nqueues(sc, n10g, n1g, num_vis, &iaq); 1025 if (rc != 0) 1026 goto done; /* error message displayed already */ 1027 if (iaq.nrxq_vi + iaq.nofldrxq_vi + iaq.nnmrxq_vi == 0) 1028 num_vis = 1; 1029 1030 sc->intr_type = iaq.intr_type; 1031 sc->intr_count = iaq.nirq; 1032 1033 s = &sc->sge; 1034 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g; 1035 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g; 1036 if (num_vis > 1) { 1037 s->nrxq += (n10g + n1g) * (num_vis - 1) * iaq.nrxq_vi; 1038 s->ntxq += (n10g + n1g) * (num_vis - 1) * iaq.ntxq_vi; 1039 } 1040 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 1041 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */ 1042 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 1043#ifdef TCP_OFFLOAD 1044 if (is_offload(sc)) { 1045 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g; 1046 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g; 1047 if (num_vis > 1) { 1048 s->nofldrxq += (n10g + n1g) * (num_vis - 1) * 1049 iaq.nofldrxq_vi; 1050 s->nofldtxq += (n10g + n1g) * (num_vis - 1) * 1051 iaq.nofldtxq_vi; 1052 } 1053 s->neq += s->nofldtxq + s->nofldrxq; 1054 s->niq += s->nofldrxq; 1055 1056 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq), 1057 M_CXGBE, M_ZERO | M_WAITOK); 1058 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq), 1059 M_CXGBE, M_ZERO | M_WAITOK); 1060 } 1061#endif 1062#ifdef DEV_NETMAP 1063 if (num_vis > 1) { 1064 s->nnmrxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmrxq_vi; 1065 s->nnmtxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmtxq_vi; 1066 } 1067 s->neq += s->nnmtxq + s->nnmrxq; 1068 s->niq += s->nnmrxq; 1069 1070 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq), 1071 M_CXGBE, M_ZERO | M_WAITOK); 1072 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq), 1073 M_CXGBE, M_ZERO | M_WAITOK); 1074#endif 1075 1076 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE, 1077 M_ZERO | M_WAITOK); 1078 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 1079 M_ZERO | M_WAITOK); 1080 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 1081 M_ZERO | M_WAITOK); 1082 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 1083 M_ZERO | M_WAITOK); 1084 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 1085 M_ZERO | M_WAITOK); 1086 1087 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 1088 M_ZERO | M_WAITOK); 1089 1090 t4_init_l2t(sc, M_WAITOK); 1091 1092 /* 1093 * Second pass over the ports. This time we know the number of rx and 1094 * tx queues that each port should get. 1095 */ 1096 rqidx = tqidx = 0; 1097#ifdef TCP_OFFLOAD 1098 ofld_rqidx = ofld_tqidx = 0; 1099#endif 1100#ifdef DEV_NETMAP 1101 nm_rqidx = nm_tqidx = 0; 1102#endif 1103 for_each_port(sc, i) { 1104 struct port_info *pi = sc->port[i]; 1105 struct vi_info *vi; 1106 1107 if (pi == NULL) 1108 continue; 1109 1110 pi->nvi = num_vis; 1111 for_each_vi(pi, j, vi) { 1112 vi->pi = pi; 1113 vi->qsize_rxq = t4_qsize_rxq; 1114 vi->qsize_txq = t4_qsize_txq; 1115 1116 vi->first_rxq = rqidx; 1117 vi->first_txq = tqidx; 1118 if (port_top_speed(pi) >= 10) { 1119 vi->tmr_idx = t4_tmr_idx_10g; 1120 vi->pktc_idx = t4_pktc_idx_10g; 1121 vi->flags |= iaq.intr_flags_10g & INTR_RXQ; 1122 vi->nrxq = j == 0 ? iaq.nrxq10g : iaq.nrxq_vi; 1123 vi->ntxq = j == 0 ? iaq.ntxq10g : iaq.ntxq_vi; 1124 } else { 1125 vi->tmr_idx = t4_tmr_idx_1g; 1126 vi->pktc_idx = t4_pktc_idx_1g; 1127 vi->flags |= iaq.intr_flags_1g & INTR_RXQ; 1128 vi->nrxq = j == 0 ? iaq.nrxq1g : iaq.nrxq_vi; 1129 vi->ntxq = j == 0 ? iaq.ntxq1g : iaq.ntxq_vi; 1130 } 1131 rqidx += vi->nrxq; 1132 tqidx += vi->ntxq; 1133 1134 if (j == 0 && vi->ntxq > 1) 1135 vi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0; 1136 else 1137 vi->rsrv_noflowq = 0; 1138 1139#ifdef TCP_OFFLOAD 1140 vi->first_ofld_rxq = ofld_rqidx; 1141 vi->first_ofld_txq = ofld_tqidx; 1142 if (port_top_speed(pi) >= 10) { 1143 vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ; 1144 vi->nofldrxq = j == 0 ? iaq.nofldrxq10g : 1145 iaq.nofldrxq_vi; 1146 vi->nofldtxq = j == 0 ? iaq.nofldtxq10g : 1147 iaq.nofldtxq_vi; 1148 } else { 1149 vi->flags |= iaq.intr_flags_1g & INTR_OFLD_RXQ; 1150 vi->nofldrxq = j == 0 ? iaq.nofldrxq1g : 1151 iaq.nofldrxq_vi; 1152 vi->nofldtxq = j == 0 ? iaq.nofldtxq1g : 1153 iaq.nofldtxq_vi; 1154 } 1155 ofld_rqidx += vi->nofldrxq; 1156 ofld_tqidx += vi->nofldtxq; 1157#endif 1158#ifdef DEV_NETMAP 1159 if (j > 0) { 1160 vi->first_nm_rxq = nm_rqidx; 1161 vi->first_nm_txq = nm_tqidx; 1162 vi->nnmrxq = iaq.nnmrxq_vi; 1163 vi->nnmtxq = iaq.nnmtxq_vi; 1164 nm_rqidx += vi->nnmrxq; 1165 nm_tqidx += vi->nnmtxq; 1166 } 1167#endif 1168 } 1169 } 1170 1171 rc = t4_setup_intr_handlers(sc); 1172 if (rc != 0) { 1173 device_printf(dev, 1174 "failed to setup interrupt handlers: %d\n", rc); 1175 goto done; 1176 } 1177 1178 rc = bus_generic_attach(dev); 1179 if (rc != 0) { 1180 device_printf(dev, 1181 "failed to attach all child ports: %d\n", rc); 1182 goto done; 1183 } 1184 1185 device_printf(dev, 1186 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n", 1187 sc->params.pci.speed, sc->params.pci.width, sc->params.nports, 1188 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" : 1189 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"), 1190 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq); 1191 1192 t4_set_desc(sc); 1193 1194 notify_siblings(dev, 0); 1195 1196done: 1197 if (rc != 0 && sc->cdev) { 1198 /* cdev was created and so cxgbetool works; recover that way. */ 1199 device_printf(dev, 1200 "error during attach, adapter is now in recovery mode.\n"); 1201 rc = 0; 1202 } 1203 1204 if (rc != 0) 1205 t4_detach_common(dev); 1206 else 1207 t4_sysctls(sc); 1208 1209 return (rc); 1210} 1211 1212static int 1213t4_ready(device_t dev) 1214{ 1215 struct adapter *sc; 1216 1217 sc = device_get_softc(dev); 1218 if (sc->flags & FW_OK) 1219 return (0); 1220 return (ENXIO); 1221} 1222 1223static int 1224t4_read_port_device(device_t dev, int port, device_t *child) 1225{ 1226 struct adapter *sc; 1227 struct port_info *pi; 1228 1229 sc = device_get_softc(dev); 1230 if (port < 0 || port >= MAX_NPORTS) 1231 return (EINVAL); 1232 pi = sc->port[port]; 1233 if (pi == NULL || pi->dev == NULL) 1234 return (ENXIO); 1235 *child = pi->dev; 1236 return (0); 1237} 1238 1239static int 1240notify_siblings(device_t dev, int detaching) 1241{ 1242 device_t sibling; 1243 int error, i; 1244 1245 error = 0; 1246 for (i = 0; i < PCI_FUNCMAX; i++) { 1247 if (i == pci_get_function(dev)) 1248 continue; 1249 sibling = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1250 pci_get_slot(dev), i); 1251 if (sibling == NULL || !device_is_attached(sibling)) 1252 continue; 1253 if (detaching) 1254 error = T4_DETACH_CHILD(sibling); 1255 else 1256 (void)T4_ATTACH_CHILD(sibling); 1257 if (error) 1258 break; 1259 } 1260 return (error); 1261} 1262 1263/* 1264 * Idempotent 1265 */ 1266static int 1267t4_detach(device_t dev) 1268{ 1269 struct adapter *sc; 1270 int rc; 1271 1272 sc = device_get_softc(dev); 1273 1274 rc = notify_siblings(dev, 1); 1275 if (rc) { 1276 device_printf(dev, 1277 "failed to detach sibling devices: %d\n", rc); 1278 return (rc); 1279 } 1280 1281 return (t4_detach_common(dev)); 1282} 1283 1284int 1285t4_detach_common(device_t dev) 1286{ 1287 struct adapter *sc; 1288 struct port_info *pi; 1289 int i, rc; 1290 1291 sc = device_get_softc(dev); 1292 1293 if (sc->flags & FULL_INIT_DONE) { 1294 if (!(sc->flags & IS_VF)) 1295 t4_intr_disable(sc); 1296 } 1297 1298 if (sc->cdev) { 1299 destroy_dev(sc->cdev); 1300 sc->cdev = NULL; 1301 } 1302 1303 if (device_is_attached(dev)) { 1304 rc = bus_generic_detach(dev); 1305 if (rc) { 1306 device_printf(dev, 1307 "failed to detach child devices: %d\n", rc); 1308 return (rc); 1309 } 1310 } 1311 1312 for (i = 0; i < sc->intr_count; i++) 1313 t4_free_irq(sc, &sc->irq[i]); 1314 1315 for (i = 0; i < MAX_NPORTS; i++) { 1316 pi = sc->port[i]; 1317 if (pi) { 1318 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid); 1319 if (pi->dev) 1320 device_delete_child(dev, pi->dev); 1321 1322 mtx_destroy(&pi->pi_lock); 1323 free(pi->vi, M_CXGBE); 1324 free(pi->tc, M_CXGBE); 1325 free(pi, M_CXGBE); 1326 } 1327 } 1328 1329 if (sc->flags & FULL_INIT_DONE) 1330 adapter_full_uninit(sc); 1331 1332 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK) 1333 t4_fw_bye(sc, sc->mbox); 1334 1335 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX) 1336 pci_release_msi(dev); 1337 1338 if (sc->regs_res) 1339 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, 1340 sc->regs_res); 1341 1342 if (sc->udbs_res) 1343 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid, 1344 sc->udbs_res); 1345 1346 if (sc->msix_res) 1347 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid, 1348 sc->msix_res); 1349 1350 if (sc->l2t) 1351 t4_free_l2t(sc->l2t); 1352 1353#ifdef TCP_OFFLOAD 1354 free(sc->sge.ofld_rxq, M_CXGBE); 1355 free(sc->sge.ofld_txq, M_CXGBE); 1356#endif 1357#ifdef DEV_NETMAP 1358 free(sc->sge.nm_rxq, M_CXGBE); 1359 free(sc->sge.nm_txq, M_CXGBE); 1360#endif 1361 free(sc->irq, M_CXGBE); 1362 free(sc->sge.rxq, M_CXGBE); 1363 free(sc->sge.txq, M_CXGBE); 1364 free(sc->sge.ctrlq, M_CXGBE); 1365 free(sc->sge.iqmap, M_CXGBE); 1366 free(sc->sge.eqmap, M_CXGBE); 1367 free(sc->tids.ftid_tab, M_CXGBE); 1368 t4_destroy_dma_tag(sc); 1369 if (mtx_initialized(&sc->sc_lock)) { 1370 sx_xlock(&t4_list_lock); 1371 SLIST_REMOVE(&t4_list, sc, adapter, link); 1372 sx_xunlock(&t4_list_lock); 1373 mtx_destroy(&sc->sc_lock); 1374 } 1375 1376 callout_drain(&sc->sfl_callout); 1377 if (mtx_initialized(&sc->tids.ftid_lock)) 1378 mtx_destroy(&sc->tids.ftid_lock); 1379 if (mtx_initialized(&sc->sfl_lock)) 1380 mtx_destroy(&sc->sfl_lock); 1381 if (mtx_initialized(&sc->ifp_lock)) 1382 mtx_destroy(&sc->ifp_lock); 1383 if (mtx_initialized(&sc->reg_lock)) 1384 mtx_destroy(&sc->reg_lock); 1385 1386 for (i = 0; i < NUM_MEMWIN; i++) { 1387 struct memwin *mw = &sc->memwin[i]; 1388 1389 if (rw_initialized(&mw->mw_lock)) 1390 rw_destroy(&mw->mw_lock); 1391 } 1392 1393 bzero(sc, sizeof(*sc)); 1394 1395 return (0); 1396} 1397 1398static int 1399cxgbe_probe(device_t dev) 1400{ 1401 char buf[128]; 1402 struct port_info *pi = device_get_softc(dev); 1403 1404 snprintf(buf, sizeof(buf), "port %d", pi->port_id); 1405 device_set_desc_copy(dev, buf); 1406 1407 return (BUS_PROBE_DEFAULT); 1408} 1409 1410#define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \ 1411 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \ 1412 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS) 1413#define T4_CAP_ENABLE (T4_CAP) 1414 1415static int 1416cxgbe_vi_attach(device_t dev, struct vi_info *vi) 1417{ 1418 struct ifnet *ifp; 1419 struct sbuf *sb; 1420 1421 vi->xact_addr_filt = -1; 1422 callout_init(&vi->tick, 1); 1423 1424 /* Allocate an ifnet and set it up */ 1425 ifp = if_alloc(IFT_ETHER); 1426 if (ifp == NULL) { 1427 device_printf(dev, "Cannot allocate ifnet\n"); 1428 return (ENOMEM); 1429 } 1430 vi->ifp = ifp; 1431 ifp->if_softc = vi; 1432 1433 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1434 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1435 1436 ifp->if_init = cxgbe_init; 1437 ifp->if_ioctl = cxgbe_ioctl; 1438 ifp->if_transmit = cxgbe_transmit; 1439 ifp->if_qflush = cxgbe_qflush; 1440 ifp->if_get_counter = cxgbe_get_counter; 1441 1442 ifp->if_capabilities = T4_CAP; 1443#ifdef TCP_OFFLOAD 1444 if (vi->nofldrxq != 0) 1445 ifp->if_capabilities |= IFCAP_TOE; 1446#endif 1447 ifp->if_capenable = T4_CAP_ENABLE; 1448 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO | 1449 CSUM_UDP_IPV6 | CSUM_TCP_IPV6; 1450 1451 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 1452 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS; 1453 ifp->if_hw_tsomaxsegsize = 65536; 1454 1455 /* Initialize ifmedia for this VI */ 1456 ifmedia_init(&vi->media, IFM_IMASK, cxgbe_media_change, 1457 cxgbe_media_status); 1458 build_medialist(vi->pi, &vi->media); 1459 1460 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp, 1461 EVENTHANDLER_PRI_ANY); 1462 1463 ether_ifattach(ifp, vi->hw_addr); 1464#ifdef DEV_NETMAP 1465 if (vi->nnmrxq != 0) 1466 cxgbe_nm_attach(vi); 1467#endif 1468 sb = sbuf_new_auto(); 1469 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq); 1470#ifdef TCP_OFFLOAD 1471 if (ifp->if_capabilities & IFCAP_TOE) 1472 sbuf_printf(sb, "; %d txq, %d rxq (TOE)", 1473 vi->nofldtxq, vi->nofldrxq); 1474#endif 1475#ifdef DEV_NETMAP 1476 if (ifp->if_capabilities & IFCAP_NETMAP) 1477 sbuf_printf(sb, "; %d txq, %d rxq (netmap)", 1478 vi->nnmtxq, vi->nnmrxq); 1479#endif 1480 sbuf_finish(sb); 1481 device_printf(dev, "%s\n", sbuf_data(sb)); 1482 sbuf_delete(sb); 1483 1484 vi_sysctls(vi); 1485 1486 return (0); 1487} 1488 1489static int 1490cxgbe_attach(device_t dev) 1491{ 1492 struct port_info *pi = device_get_softc(dev); 1493 struct adapter *sc = pi->adapter; 1494 struct vi_info *vi; 1495 int i, rc; 1496 1497 callout_init_mtx(&pi->tick, &pi->pi_lock, 0); 1498 1499 rc = cxgbe_vi_attach(dev, &pi->vi[0]); 1500 if (rc) 1501 return (rc); 1502 1503 for_each_vi(pi, i, vi) { 1504 if (i == 0) 1505 continue; 1506 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1); 1507 if (vi->dev == NULL) { 1508 device_printf(dev, "failed to add VI %d\n", i); 1509 continue; 1510 } 1511 device_set_softc(vi->dev, vi); 1512 } 1513 1514 cxgbe_sysctls(pi); 1515 1516 bus_generic_attach(dev); 1517 1518 return (0); 1519} 1520 1521static void 1522cxgbe_vi_detach(struct vi_info *vi) 1523{ 1524 struct ifnet *ifp = vi->ifp; 1525 1526 ether_ifdetach(ifp); 1527 1528 if (vi->vlan_c) 1529 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c); 1530 1531 /* Let detach proceed even if these fail. */ 1532#ifdef DEV_NETMAP 1533 if (ifp->if_capabilities & IFCAP_NETMAP) 1534 cxgbe_nm_detach(vi); 1535#endif 1536 cxgbe_uninit_synchronized(vi); 1537 callout_drain(&vi->tick); 1538 vi_full_uninit(vi); 1539 1540 ifmedia_removeall(&vi->media); 1541 if_free(vi->ifp); 1542 vi->ifp = NULL; 1543} 1544 1545static int 1546cxgbe_detach(device_t dev) 1547{ 1548 struct port_info *pi = device_get_softc(dev); 1549 struct adapter *sc = pi->adapter; 1550 int rc; 1551 1552 /* Detach the extra VIs first. */ 1553 rc = bus_generic_detach(dev); 1554 if (rc) 1555 return (rc); 1556 device_delete_children(dev); 1557 1558 doom_vi(sc, &pi->vi[0]); 1559 1560 if (pi->flags & HAS_TRACEQ) { 1561 sc->traceq = -1; /* cloner should not create ifnet */ 1562 t4_tracer_port_detach(sc); 1563 } 1564 1565 cxgbe_vi_detach(&pi->vi[0]); 1566 callout_drain(&pi->tick); 1567 1568 end_synchronized_op(sc, 0); 1569 1570 return (0); 1571} 1572 1573static void 1574cxgbe_init(void *arg) 1575{ 1576 struct vi_info *vi = arg; 1577 struct adapter *sc = vi->pi->adapter; 1578 1579 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0) 1580 return; 1581 cxgbe_init_synchronized(vi); 1582 end_synchronized_op(sc, 0); 1583} 1584 1585static int 1586cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data) 1587{ 1588 int rc = 0, mtu, flags, can_sleep; 1589 struct vi_info *vi = ifp->if_softc; 1590 struct adapter *sc = vi->pi->adapter; 1591 struct ifreq *ifr = (struct ifreq *)data; 1592 uint32_t mask; 1593 1594 switch (cmd) { 1595 case SIOCSIFMTU: 1596 mtu = ifr->ifr_mtu; 1597 if (mtu < ETHERMIN || mtu > MAX_MTU) 1598 return (EINVAL); 1599 1600 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu"); 1601 if (rc) 1602 return (rc); 1603 ifp->if_mtu = mtu; 1604 if (vi->flags & VI_INIT_DONE) { 1605 t4_update_fl_bufsize(ifp); 1606 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1607 rc = update_mac_settings(ifp, XGMAC_MTU); 1608 } 1609 end_synchronized_op(sc, 0); 1610 break; 1611 1612 case SIOCSIFFLAGS: 1613 can_sleep = 0; 1614redo_sifflags: 1615 rc = begin_synchronized_op(sc, vi, 1616 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg"); 1617 if (rc) 1618 return (rc); 1619 1620 if (ifp->if_flags & IFF_UP) { 1621 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1622 flags = vi->if_flags; 1623 if ((ifp->if_flags ^ flags) & 1624 (IFF_PROMISC | IFF_ALLMULTI)) { 1625 if (can_sleep == 1) { 1626 end_synchronized_op(sc, 0); 1627 can_sleep = 0; 1628 goto redo_sifflags; 1629 } 1630 rc = update_mac_settings(ifp, 1631 XGMAC_PROMISC | XGMAC_ALLMULTI); 1632 } 1633 } else { 1634 if (can_sleep == 0) { 1635 end_synchronized_op(sc, LOCK_HELD); 1636 can_sleep = 1; 1637 goto redo_sifflags; 1638 } 1639 rc = cxgbe_init_synchronized(vi); 1640 } 1641 vi->if_flags = ifp->if_flags; 1642 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1643 if (can_sleep == 0) { 1644 end_synchronized_op(sc, LOCK_HELD); 1645 can_sleep = 1; 1646 goto redo_sifflags; 1647 } 1648 rc = cxgbe_uninit_synchronized(vi); 1649 } 1650 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD); 1651 break; 1652 1653 case SIOCADDMULTI: 1654 case SIOCDELMULTI: /* these two are called with a mutex held :-( */ 1655 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi"); 1656 if (rc) 1657 return (rc); 1658 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1659 rc = update_mac_settings(ifp, XGMAC_MCADDRS); 1660 end_synchronized_op(sc, LOCK_HELD); 1661 break; 1662 1663 case SIOCSIFCAP: 1664 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap"); 1665 if (rc) 1666 return (rc); 1667 1668 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1669 if (mask & IFCAP_TXCSUM) { 1670 ifp->if_capenable ^= IFCAP_TXCSUM; 1671 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP); 1672 1673 if (IFCAP_TSO4 & ifp->if_capenable && 1674 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1675 ifp->if_capenable &= ~IFCAP_TSO4; 1676 if_printf(ifp, 1677 "tso4 disabled due to -txcsum.\n"); 1678 } 1679 } 1680 if (mask & IFCAP_TXCSUM_IPV6) { 1681 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1682 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6); 1683 1684 if (IFCAP_TSO6 & ifp->if_capenable && 1685 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1686 ifp->if_capenable &= ~IFCAP_TSO6; 1687 if_printf(ifp, 1688 "tso6 disabled due to -txcsum6.\n"); 1689 } 1690 } 1691 if (mask & IFCAP_RXCSUM) 1692 ifp->if_capenable ^= IFCAP_RXCSUM; 1693 if (mask & IFCAP_RXCSUM_IPV6) 1694 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1695 1696 /* 1697 * Note that we leave CSUM_TSO alone (it is always set). The 1698 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before 1699 * sending a TSO request our way, so it's sufficient to toggle 1700 * IFCAP_TSOx only. 1701 */ 1702 if (mask & IFCAP_TSO4) { 1703 if (!(IFCAP_TSO4 & ifp->if_capenable) && 1704 !(IFCAP_TXCSUM & ifp->if_capenable)) { 1705 if_printf(ifp, "enable txcsum first.\n"); 1706 rc = EAGAIN; 1707 goto fail; 1708 } 1709 ifp->if_capenable ^= IFCAP_TSO4; 1710 } 1711 if (mask & IFCAP_TSO6) { 1712 if (!(IFCAP_TSO6 & ifp->if_capenable) && 1713 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) { 1714 if_printf(ifp, "enable txcsum6 first.\n"); 1715 rc = EAGAIN; 1716 goto fail; 1717 } 1718 ifp->if_capenable ^= IFCAP_TSO6; 1719 } 1720 if (mask & IFCAP_LRO) { 1721#if defined(INET) || defined(INET6) 1722 int i; 1723 struct sge_rxq *rxq; 1724 1725 ifp->if_capenable ^= IFCAP_LRO; 1726 for_each_rxq(vi, i, rxq) { 1727 if (ifp->if_capenable & IFCAP_LRO) 1728 rxq->iq.flags |= IQ_LRO_ENABLED; 1729 else 1730 rxq->iq.flags &= ~IQ_LRO_ENABLED; 1731 } 1732#endif 1733 } 1734#ifdef TCP_OFFLOAD 1735 if (mask & IFCAP_TOE) { 1736 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE; 1737 1738 rc = toe_capability(vi, enable); 1739 if (rc != 0) 1740 goto fail; 1741 1742 ifp->if_capenable ^= mask; 1743 } 1744#endif 1745 if (mask & IFCAP_VLAN_HWTAGGING) { 1746 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1747 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1748 rc = update_mac_settings(ifp, XGMAC_VLANEX); 1749 } 1750 if (mask & IFCAP_VLAN_MTU) { 1751 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1752 1753 /* Need to find out how to disable auto-mtu-inflation */ 1754 } 1755 if (mask & IFCAP_VLAN_HWTSO) 1756 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1757 if (mask & IFCAP_VLAN_HWCSUM) 1758 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1759 1760#ifdef VLAN_CAPABILITIES 1761 VLAN_CAPABILITIES(ifp); 1762#endif 1763fail: 1764 end_synchronized_op(sc, 0); 1765 break; 1766 1767 case SIOCSIFMEDIA: 1768 case SIOCGIFMEDIA: 1769 case SIOCGIFXMEDIA: 1770 ifmedia_ioctl(ifp, ifr, &vi->media, cmd); 1771 break; 1772 1773 case SIOCGI2C: { 1774 struct ifi2creq i2c; 1775 1776 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c)); 1777 if (rc != 0) 1778 break; 1779 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) { 1780 rc = EPERM; 1781 break; 1782 } 1783 if (i2c.len > sizeof(i2c.data)) { 1784 rc = EINVAL; 1785 break; 1786 } 1787 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c"); 1788 if (rc) 1789 return (rc); 1790 rc = -t4_i2c_rd(sc, sc->mbox, vi->pi->port_id, i2c.dev_addr, 1791 i2c.offset, i2c.len, &i2c.data[0]); 1792 end_synchronized_op(sc, 0); 1793 if (rc == 0) 1794 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c)); 1795 break; 1796 } 1797 1798 default: 1799 rc = ether_ioctl(ifp, cmd, data); 1800 } 1801 1802 return (rc); 1803} 1804 1805static int 1806cxgbe_transmit(struct ifnet *ifp, struct mbuf *m) 1807{ 1808 struct vi_info *vi = ifp->if_softc; 1809 struct port_info *pi = vi->pi; 1810 struct adapter *sc = pi->adapter; 1811 struct sge_txq *txq; 1812 void *items[1]; 1813 int rc; 1814 1815 M_ASSERTPKTHDR(m); 1816 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */ 1817 1818 if (__predict_false(pi->link_cfg.link_ok == 0)) { 1819 m_freem(m); 1820 return (ENETDOWN); 1821 } 1822 1823 rc = parse_pkt(sc, &m); 1824 if (__predict_false(rc != 0)) { 1825 MPASS(m == NULL); /* was freed already */ 1826 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */ 1827 return (rc); 1828 } 1829 1830 /* Select a txq. */ 1831 txq = &sc->sge.txq[vi->first_txq]; 1832 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 1833 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) + 1834 vi->rsrv_noflowq); 1835 1836 items[0] = m; 1837 rc = mp_ring_enqueue(txq->r, items, 1, 4096); 1838 if (__predict_false(rc != 0)) 1839 m_freem(m); 1840 1841 return (rc); 1842} 1843 1844static void 1845cxgbe_qflush(struct ifnet *ifp) 1846{ 1847 struct vi_info *vi = ifp->if_softc; 1848 struct sge_txq *txq; 1849 int i; 1850 1851 /* queues do not exist if !VI_INIT_DONE. */ 1852 if (vi->flags & VI_INIT_DONE) { 1853 for_each_txq(vi, i, txq) { 1854 TXQ_LOCK(txq); 1855 txq->eq.flags &= ~EQ_ENABLED; 1856 TXQ_UNLOCK(txq); 1857 while (!mp_ring_is_idle(txq->r)) { 1858 mp_ring_check_drainage(txq->r, 0); 1859 pause("qflush", 1); 1860 } 1861 } 1862 } 1863 if_qflush(ifp); 1864} 1865 1866static uint64_t 1867vi_get_counter(struct ifnet *ifp, ift_counter c) 1868{ 1869 struct vi_info *vi = ifp->if_softc; 1870 struct fw_vi_stats_vf *s = &vi->stats; 1871 1872 vi_refresh_stats(vi->pi->adapter, vi); 1873 1874 switch (c) { 1875 case IFCOUNTER_IPACKETS: 1876 return (s->rx_bcast_frames + s->rx_mcast_frames + 1877 s->rx_ucast_frames); 1878 case IFCOUNTER_IERRORS: 1879 return (s->rx_err_frames); 1880 case IFCOUNTER_OPACKETS: 1881 return (s->tx_bcast_frames + s->tx_mcast_frames + 1882 s->tx_ucast_frames + s->tx_offload_frames); 1883 case IFCOUNTER_OERRORS: 1884 return (s->tx_drop_frames); 1885 case IFCOUNTER_IBYTES: 1886 return (s->rx_bcast_bytes + s->rx_mcast_bytes + 1887 s->rx_ucast_bytes); 1888 case IFCOUNTER_OBYTES: 1889 return (s->tx_bcast_bytes + s->tx_mcast_bytes + 1890 s->tx_ucast_bytes + s->tx_offload_bytes); 1891 case IFCOUNTER_IMCASTS: 1892 return (s->rx_mcast_frames); 1893 case IFCOUNTER_OMCASTS: 1894 return (s->tx_mcast_frames); 1895 case IFCOUNTER_OQDROPS: { 1896 uint64_t drops; 1897 1898 drops = 0; 1899 if (vi->flags & VI_INIT_DONE) { 1900 int i; 1901 struct sge_txq *txq; 1902 1903 for_each_txq(vi, i, txq) 1904 drops += counter_u64_fetch(txq->r->drops); 1905 } 1906 1907 return (drops); 1908 1909 } 1910 1911 default: 1912 return (if_get_counter_default(ifp, c)); 1913 } 1914} 1915 1916uint64_t 1917cxgbe_get_counter(struct ifnet *ifp, ift_counter c) 1918{ 1919 struct vi_info *vi = ifp->if_softc; 1920 struct port_info *pi = vi->pi; 1921 struct adapter *sc = pi->adapter; 1922 struct port_stats *s = &pi->stats; 1923 1924 if (pi->nvi > 1 || sc->flags & IS_VF) 1925 return (vi_get_counter(ifp, c)); 1926 1927 cxgbe_refresh_stats(sc, pi); 1928 1929 switch (c) { 1930 case IFCOUNTER_IPACKETS: 1931 return (s->rx_frames); 1932 1933 case IFCOUNTER_IERRORS: 1934 return (s->rx_jabber + s->rx_runt + s->rx_too_long + 1935 s->rx_fcs_err + s->rx_len_err); 1936 1937 case IFCOUNTER_OPACKETS: 1938 return (s->tx_frames); 1939 1940 case IFCOUNTER_OERRORS: 1941 return (s->tx_error_frames); 1942 1943 case IFCOUNTER_IBYTES: 1944 return (s->rx_octets); 1945 1946 case IFCOUNTER_OBYTES: 1947 return (s->tx_octets); 1948 1949 case IFCOUNTER_IMCASTS: 1950 return (s->rx_mcast_frames); 1951 1952 case IFCOUNTER_OMCASTS: 1953 return (s->tx_mcast_frames); 1954 1955 case IFCOUNTER_IQDROPS: 1956 return (s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 + 1957 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 + 1958 s->rx_trunc3 + pi->tnl_cong_drops); 1959 1960 case IFCOUNTER_OQDROPS: { 1961 uint64_t drops; 1962 1963 drops = s->tx_drop; 1964 if (vi->flags & VI_INIT_DONE) { 1965 int i; 1966 struct sge_txq *txq; 1967 1968 for_each_txq(vi, i, txq) 1969 drops += counter_u64_fetch(txq->r->drops); 1970 } 1971 1972 return (drops); 1973 1974 } 1975 1976 default: 1977 return (if_get_counter_default(ifp, c)); 1978 } 1979} 1980 1981static int 1982cxgbe_media_change(struct ifnet *ifp) 1983{ 1984 struct vi_info *vi = ifp->if_softc; 1985 1986 device_printf(vi->dev, "%s unimplemented.\n", __func__); 1987 1988 return (EOPNOTSUPP); 1989} 1990 1991static void 1992cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1993{ 1994 struct vi_info *vi = ifp->if_softc; 1995 struct port_info *pi = vi->pi; 1996 struct ifmedia_entry *cur; 1997 int speed = pi->link_cfg.speed; 1998 1999 cur = vi->media.ifm_cur; 2000 2001 ifmr->ifm_status = IFM_AVALID; 2002 if (!pi->link_cfg.link_ok) 2003 return; 2004 2005 ifmr->ifm_status |= IFM_ACTIVE; 2006 2007 /* active and current will differ iff current media is autoselect. */ 2008 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO) 2009 return; 2010 2011 ifmr->ifm_active = IFM_ETHER | IFM_FDX; 2012 if (speed == 10000) 2013 ifmr->ifm_active |= IFM_10G_T; 2014 else if (speed == 1000) 2015 ifmr->ifm_active |= IFM_1000_T; 2016 else if (speed == 100) 2017 ifmr->ifm_active |= IFM_100_TX; 2018 else if (speed == 10) 2019 ifmr->ifm_active |= IFM_10_T; 2020 else 2021 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__, 2022 speed)); 2023} 2024 2025static int 2026vcxgbe_probe(device_t dev) 2027{ 2028 char buf[128]; 2029 struct vi_info *vi = device_get_softc(dev); 2030 2031 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id, 2032 vi - vi->pi->vi); 2033 device_set_desc_copy(dev, buf); 2034 2035 return (BUS_PROBE_DEFAULT); 2036} 2037 2038static int 2039vcxgbe_attach(device_t dev) 2040{ 2041 struct vi_info *vi; 2042 struct port_info *pi; 2043 struct adapter *sc; 2044 int func, index, rc; 2045 u32 param, val; 2046 2047 vi = device_get_softc(dev); 2048 pi = vi->pi; 2049 sc = pi->adapter; 2050 2051 index = vi - pi->vi; 2052 KASSERT(index < nitems(vi_mac_funcs), 2053 ("%s: VI %s doesn't have a MAC func", __func__, 2054 device_get_nameunit(dev))); 2055 func = vi_mac_funcs[index]; 2056 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, 2057 vi->hw_addr, &vi->rss_size, func, 0); 2058 if (rc < 0) { 2059 device_printf(dev, "Failed to allocate virtual interface " 2060 "for port %d: %d\n", pi->port_id, -rc); 2061 return (-rc); 2062 } 2063 vi->viid = rc; 2064 if (chip_id(sc) <= CHELSIO_T5) 2065 vi->smt_idx = (rc & 0x7f) << 1; 2066 else 2067 vi->smt_idx = (rc & 0x7f); 2068 2069 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 2070 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 2071 V_FW_PARAMS_PARAM_YZ(vi->viid); 2072 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 2073 if (rc) 2074 vi->rss_base = 0xffff; 2075 else { 2076 /* MPASS((val >> 16) == rss_size); */ 2077 vi->rss_base = val & 0xffff; 2078 } 2079 2080 rc = cxgbe_vi_attach(dev, vi); 2081 if (rc) { 2082 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2083 return (rc); 2084 } 2085 return (0); 2086} 2087 2088static int 2089vcxgbe_detach(device_t dev) 2090{ 2091 struct vi_info *vi; 2092 struct adapter *sc; 2093 2094 vi = device_get_softc(dev); 2095 sc = vi->pi->adapter; 2096 2097 doom_vi(sc, vi); 2098 2099 cxgbe_vi_detach(vi); 2100 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid); 2101 2102 end_synchronized_op(sc, 0); 2103 2104 return (0); 2105} 2106 2107void 2108t4_fatal_err(struct adapter *sc) 2109{ 2110 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0); 2111 t4_intr_disable(sc); 2112 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n", 2113 device_get_nameunit(sc->dev)); 2114} 2115 2116void 2117t4_add_adapter(struct adapter *sc) 2118{ 2119 sx_xlock(&t4_list_lock); 2120 SLIST_INSERT_HEAD(&t4_list, sc, link); 2121 sx_xunlock(&t4_list_lock); 2122} 2123 2124int 2125t4_map_bars_0_and_4(struct adapter *sc) 2126{ 2127 sc->regs_rid = PCIR_BAR(0); 2128 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2129 &sc->regs_rid, RF_ACTIVE); 2130 if (sc->regs_res == NULL) { 2131 device_printf(sc->dev, "cannot map registers.\n"); 2132 return (ENXIO); 2133 } 2134 sc->bt = rman_get_bustag(sc->regs_res); 2135 sc->bh = rman_get_bushandle(sc->regs_res); 2136 sc->mmio_len = rman_get_size(sc->regs_res); 2137 setbit(&sc->doorbells, DOORBELL_KDB); 2138 2139 sc->msix_rid = PCIR_BAR(4); 2140 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2141 &sc->msix_rid, RF_ACTIVE); 2142 if (sc->msix_res == NULL) { 2143 device_printf(sc->dev, "cannot map MSI-X BAR.\n"); 2144 return (ENXIO); 2145 } 2146 2147 return (0); 2148} 2149 2150int 2151t4_map_bar_2(struct adapter *sc) 2152{ 2153 2154 /* 2155 * T4: only iWARP driver uses the userspace doorbells. There is no need 2156 * to map it if RDMA is disabled. 2157 */ 2158 if (is_t4(sc) && sc->rdmacaps == 0) 2159 return (0); 2160 2161 sc->udbs_rid = PCIR_BAR(2); 2162 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 2163 &sc->udbs_rid, RF_ACTIVE); 2164 if (sc->udbs_res == NULL) { 2165 device_printf(sc->dev, "cannot map doorbell BAR.\n"); 2166 return (ENXIO); 2167 } 2168 sc->udbs_base = rman_get_virtual(sc->udbs_res); 2169 2170 if (chip_id(sc) >= CHELSIO_T5) { 2171 setbit(&sc->doorbells, DOORBELL_UDB); 2172#if defined(__i386__) || defined(__amd64__) 2173 if (t5_write_combine) { 2174 int rc, mode; 2175 2176 /* 2177 * Enable write combining on BAR2. This is the 2178 * userspace doorbell BAR and is split into 128B 2179 * (UDBS_SEG_SIZE) doorbell regions, each associated 2180 * with an egress queue. The first 64B has the doorbell 2181 * and the second 64B can be used to submit a tx work 2182 * request with an implicit doorbell. 2183 */ 2184 2185 rc = pmap_change_attr((vm_offset_t)sc->udbs_base, 2186 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING); 2187 if (rc == 0) { 2188 clrbit(&sc->doorbells, DOORBELL_UDB); 2189 setbit(&sc->doorbells, DOORBELL_WCWR); 2190 setbit(&sc->doorbells, DOORBELL_UDBWC); 2191 } else { 2192 device_printf(sc->dev, 2193 "couldn't enable write combining: %d\n", 2194 rc); 2195 } 2196 2197 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0); 2198 t4_write_reg(sc, A_SGE_STAT_CFG, 2199 V_STATSOURCE_T5(7) | mode); 2200 } 2201#endif 2202 } 2203 2204 return (0); 2205} 2206 2207struct memwin_init { 2208 uint32_t base; 2209 uint32_t aperture; 2210}; 2211 2212static const struct memwin_init t4_memwin[NUM_MEMWIN] = { 2213 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2214 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2215 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } 2216}; 2217 2218static const struct memwin_init t5_memwin[NUM_MEMWIN] = { 2219 { MEMWIN0_BASE, MEMWIN0_APERTURE }, 2220 { MEMWIN1_BASE, MEMWIN1_APERTURE }, 2221 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, 2222}; 2223 2224static void 2225setup_memwin(struct adapter *sc) 2226{ 2227 const struct memwin_init *mw_init; 2228 struct memwin *mw; 2229 int i; 2230 uint32_t bar0; 2231 2232 if (is_t4(sc)) { 2233 /* 2234 * Read low 32b of bar0 indirectly via the hardware backdoor 2235 * mechanism. Works from within PCI passthrough environments 2236 * too, where rman_get_start() can return a different value. We 2237 * need to program the T4 memory window decoders with the actual 2238 * addresses that will be coming across the PCIe link. 2239 */ 2240 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0)); 2241 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE; 2242 2243 mw_init = &t4_memwin[0]; 2244 } else { 2245 /* T5+ use the relative offset inside the PCIe BAR */ 2246 bar0 = 0; 2247 2248 mw_init = &t5_memwin[0]; 2249 } 2250 2251 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) { 2252 rw_init(&mw->mw_lock, "memory window access"); 2253 mw->mw_base = mw_init->base; 2254 mw->mw_aperture = mw_init->aperture; 2255 mw->mw_curpos = 0; 2256 t4_write_reg(sc, 2257 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i), 2258 (mw->mw_base + bar0) | V_BIR(0) | 2259 V_WINDOW(ilog2(mw->mw_aperture) - 10)); 2260 rw_wlock(&mw->mw_lock); 2261 position_memwin(sc, i, 0); 2262 rw_wunlock(&mw->mw_lock); 2263 } 2264 2265 /* flush */ 2266 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); 2267} 2268 2269/* 2270 * Positions the memory window at the given address in the card's address space. 2271 * There are some alignment requirements and the actual position may be at an 2272 * address prior to the requested address. mw->mw_curpos always has the actual 2273 * position of the window. 2274 */ 2275static void 2276position_memwin(struct adapter *sc, int idx, uint32_t addr) 2277{ 2278 struct memwin *mw; 2279 uint32_t pf; 2280 uint32_t reg; 2281 2282 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2283 mw = &sc->memwin[idx]; 2284 rw_assert(&mw->mw_lock, RA_WLOCKED); 2285 2286 if (is_t4(sc)) { 2287 pf = 0; 2288 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */ 2289 } else { 2290 pf = V_PFNUM(sc->pf); 2291 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */ 2292 } 2293 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx); 2294 t4_write_reg(sc, reg, mw->mw_curpos | pf); 2295 t4_read_reg(sc, reg); /* flush */ 2296} 2297 2298static int 2299rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2300 int len, int rw) 2301{ 2302 struct memwin *mw; 2303 uint32_t mw_end, v; 2304 2305 MPASS(idx >= 0 && idx < NUM_MEMWIN); 2306 2307 /* Memory can only be accessed in naturally aligned 4 byte units */ 2308 if (addr & 3 || len & 3 || len <= 0) 2309 return (EINVAL); 2310 2311 mw = &sc->memwin[idx]; 2312 while (len > 0) { 2313 rw_rlock(&mw->mw_lock); 2314 mw_end = mw->mw_curpos + mw->mw_aperture; 2315 if (addr >= mw_end || addr < mw->mw_curpos) { 2316 /* Will need to reposition the window */ 2317 if (!rw_try_upgrade(&mw->mw_lock)) { 2318 rw_runlock(&mw->mw_lock); 2319 rw_wlock(&mw->mw_lock); 2320 } 2321 rw_assert(&mw->mw_lock, RA_WLOCKED); 2322 position_memwin(sc, idx, addr); 2323 rw_downgrade(&mw->mw_lock); 2324 mw_end = mw->mw_curpos + mw->mw_aperture; 2325 } 2326 rw_assert(&mw->mw_lock, RA_RLOCKED); 2327 while (addr < mw_end && len > 0) { 2328 if (rw == 0) { 2329 v = t4_read_reg(sc, mw->mw_base + addr - 2330 mw->mw_curpos); 2331 *val++ = le32toh(v); 2332 } else { 2333 v = *val++; 2334 t4_write_reg(sc, mw->mw_base + addr - 2335 mw->mw_curpos, htole32(v)); 2336 } 2337 addr += 4; 2338 len -= 4; 2339 } 2340 rw_runlock(&mw->mw_lock); 2341 } 2342 2343 return (0); 2344} 2345 2346static inline int 2347read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 2348 int len) 2349{ 2350 2351 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 2352} 2353 2354static inline int 2355write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 2356 const uint32_t *val, int len) 2357{ 2358 2359 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 2360} 2361 2362static int 2363t4_range_cmp(const void *a, const void *b) 2364{ 2365 return ((const struct t4_range *)a)->start - 2366 ((const struct t4_range *)b)->start; 2367} 2368 2369/* 2370 * Verify that the memory range specified by the addr/len pair is valid within 2371 * the card's address space. 2372 */ 2373static int 2374validate_mem_range(struct adapter *sc, uint32_t addr, int len) 2375{ 2376 struct t4_range mem_ranges[4], *r, *next; 2377 uint32_t em, addr_len; 2378 int i, n, remaining; 2379 2380 /* Memory can only be accessed in naturally aligned 4 byte units */ 2381 if (addr & 3 || len & 3 || len <= 0) 2382 return (EINVAL); 2383 2384 /* Enabled memories */ 2385 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2386 2387 r = &mem_ranges[0]; 2388 n = 0; 2389 bzero(r, sizeof(mem_ranges)); 2390 if (em & F_EDRAM0_ENABLE) { 2391 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2392 r->size = G_EDRAM0_SIZE(addr_len) << 20; 2393 if (r->size > 0) { 2394 r->start = G_EDRAM0_BASE(addr_len) << 20; 2395 if (addr >= r->start && 2396 addr + len <= r->start + r->size) 2397 return (0); 2398 r++; 2399 n++; 2400 } 2401 } 2402 if (em & F_EDRAM1_ENABLE) { 2403 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2404 r->size = G_EDRAM1_SIZE(addr_len) << 20; 2405 if (r->size > 0) { 2406 r->start = G_EDRAM1_BASE(addr_len) << 20; 2407 if (addr >= r->start && 2408 addr + len <= r->start + r->size) 2409 return (0); 2410 r++; 2411 n++; 2412 } 2413 } 2414 if (em & F_EXT_MEM_ENABLE) { 2415 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2416 r->size = G_EXT_MEM_SIZE(addr_len) << 20; 2417 if (r->size > 0) { 2418 r->start = G_EXT_MEM_BASE(addr_len) << 20; 2419 if (addr >= r->start && 2420 addr + len <= r->start + r->size) 2421 return (0); 2422 r++; 2423 n++; 2424 } 2425 } 2426 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) { 2427 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2428 r->size = G_EXT_MEM1_SIZE(addr_len) << 20; 2429 if (r->size > 0) { 2430 r->start = G_EXT_MEM1_BASE(addr_len) << 20; 2431 if (addr >= r->start && 2432 addr + len <= r->start + r->size) 2433 return (0); 2434 r++; 2435 n++; 2436 } 2437 } 2438 MPASS(n <= nitems(mem_ranges)); 2439 2440 if (n > 1) { 2441 /* Sort and merge the ranges. */ 2442 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp); 2443 2444 /* Start from index 0 and examine the next n - 1 entries. */ 2445 r = &mem_ranges[0]; 2446 for (remaining = n - 1; remaining > 0; remaining--, r++) { 2447 2448 MPASS(r->size > 0); /* r is a valid entry. */ 2449 next = r + 1; 2450 MPASS(next->size > 0); /* and so is the next one. */ 2451 2452 while (r->start + r->size >= next->start) { 2453 /* Merge the next one into the current entry. */ 2454 r->size = max(r->start + r->size, 2455 next->start + next->size) - r->start; 2456 n--; /* One fewer entry in total. */ 2457 if (--remaining == 0) 2458 goto done; /* short circuit */ 2459 next++; 2460 } 2461 if (next != r + 1) { 2462 /* 2463 * Some entries were merged into r and next 2464 * points to the first valid entry that couldn't 2465 * be merged. 2466 */ 2467 MPASS(next->size > 0); /* must be valid */ 2468 memcpy(r + 1, next, remaining * sizeof(*r)); 2469#ifdef INVARIANTS 2470 /* 2471 * This so that the foo->size assertion in the 2472 * next iteration of the loop do the right 2473 * thing for entries that were pulled up and are 2474 * no longer valid. 2475 */ 2476 MPASS(n < nitems(mem_ranges)); 2477 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) * 2478 sizeof(struct t4_range)); 2479#endif 2480 } 2481 } 2482done: 2483 /* Done merging the ranges. */ 2484 MPASS(n > 0); 2485 r = &mem_ranges[0]; 2486 for (i = 0; i < n; i++, r++) { 2487 if (addr >= r->start && 2488 addr + len <= r->start + r->size) 2489 return (0); 2490 } 2491 } 2492 2493 return (EFAULT); 2494} 2495 2496static int 2497fwmtype_to_hwmtype(int mtype) 2498{ 2499 2500 switch (mtype) { 2501 case FW_MEMTYPE_EDC0: 2502 return (MEM_EDC0); 2503 case FW_MEMTYPE_EDC1: 2504 return (MEM_EDC1); 2505 case FW_MEMTYPE_EXTMEM: 2506 return (MEM_MC0); 2507 case FW_MEMTYPE_EXTMEM1: 2508 return (MEM_MC1); 2509 default: 2510 panic("%s: cannot translate fw mtype %d.", __func__, mtype); 2511 } 2512} 2513 2514/* 2515 * Verify that the memory range specified by the memtype/offset/len pair is 2516 * valid and lies entirely within the memtype specified. The global address of 2517 * the start of the range is returned in addr. 2518 */ 2519static int 2520validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len, 2521 uint32_t *addr) 2522{ 2523 uint32_t em, addr_len, maddr; 2524 2525 /* Memory can only be accessed in naturally aligned 4 byte units */ 2526 if (off & 3 || len & 3 || len == 0) 2527 return (EINVAL); 2528 2529 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 2530 switch (fwmtype_to_hwmtype(mtype)) { 2531 case MEM_EDC0: 2532 if (!(em & F_EDRAM0_ENABLE)) 2533 return (EINVAL); 2534 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); 2535 maddr = G_EDRAM0_BASE(addr_len) << 20; 2536 break; 2537 case MEM_EDC1: 2538 if (!(em & F_EDRAM1_ENABLE)) 2539 return (EINVAL); 2540 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); 2541 maddr = G_EDRAM1_BASE(addr_len) << 20; 2542 break; 2543 case MEM_MC: 2544 if (!(em & F_EXT_MEM_ENABLE)) 2545 return (EINVAL); 2546 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 2547 maddr = G_EXT_MEM_BASE(addr_len) << 20; 2548 break; 2549 case MEM_MC1: 2550 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE)) 2551 return (EINVAL); 2552 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 2553 maddr = G_EXT_MEM1_BASE(addr_len) << 20; 2554 break; 2555 default: 2556 return (EINVAL); 2557 } 2558 2559 *addr = maddr + off; /* global address */ 2560 return (validate_mem_range(sc, *addr, len)); 2561} 2562 2563static int 2564fixup_devlog_params(struct adapter *sc) 2565{ 2566 struct devlog_params *dparams = &sc->params.devlog; 2567 int rc; 2568 2569 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start, 2570 dparams->size, &dparams->addr); 2571 2572 return (rc); 2573} 2574 2575static int 2576cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, int num_vis, 2577 struct intrs_and_queues *iaq) 2578{ 2579 int rc, itype, navail, nrxq10g, nrxq1g, n; 2580 int nofldrxq10g = 0, nofldrxq1g = 0; 2581 2582 bzero(iaq, sizeof(*iaq)); 2583 2584 iaq->ntxq10g = t4_ntxq10g; 2585 iaq->ntxq1g = t4_ntxq1g; 2586 iaq->ntxq_vi = t4_ntxq_vi; 2587 iaq->nrxq10g = nrxq10g = t4_nrxq10g; 2588 iaq->nrxq1g = nrxq1g = t4_nrxq1g; 2589 iaq->nrxq_vi = t4_nrxq_vi; 2590 iaq->rsrv_noflowq = t4_rsrv_noflowq; 2591#ifdef TCP_OFFLOAD 2592 if (is_offload(sc)) { 2593 iaq->nofldtxq10g = t4_nofldtxq10g; 2594 iaq->nofldtxq1g = t4_nofldtxq1g; 2595 iaq->nofldtxq_vi = t4_nofldtxq_vi; 2596 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g; 2597 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g; 2598 iaq->nofldrxq_vi = t4_nofldrxq_vi; 2599 } 2600#endif 2601#ifdef DEV_NETMAP 2602 iaq->nnmtxq_vi = t4_nnmtxq_vi; 2603 iaq->nnmrxq_vi = t4_nnmrxq_vi; 2604#endif 2605 2606 for (itype = INTR_MSIX; itype; itype >>= 1) { 2607 2608 if ((itype & t4_intr_types) == 0) 2609 continue; /* not allowed */ 2610 2611 if (itype == INTR_MSIX) 2612 navail = pci_msix_count(sc->dev); 2613 else if (itype == INTR_MSI) 2614 navail = pci_msi_count(sc->dev); 2615 else 2616 navail = 1; 2617restart: 2618 if (navail == 0) 2619 continue; 2620 2621 iaq->intr_type = itype; 2622 iaq->intr_flags_10g = 0; 2623 iaq->intr_flags_1g = 0; 2624 2625 /* 2626 * Best option: an interrupt vector for errors, one for the 2627 * firmware event queue, and one for every rxq (NIC and TOE) of 2628 * every VI. The VIs that support netmap use the same 2629 * interrupts for the NIC rx queues and the netmap rx queues 2630 * because only one set of queues is active at a time. 2631 */ 2632 iaq->nirq = T4_EXTRA_INTR; 2633 iaq->nirq += n10g * (nrxq10g + nofldrxq10g); 2634 iaq->nirq += n1g * (nrxq1g + nofldrxq1g); 2635 iaq->nirq += (n10g + n1g) * (num_vis - 1) * 2636 max(iaq->nrxq_vi, iaq->nnmrxq_vi); /* See comment above. */ 2637 iaq->nirq += (n10g + n1g) * (num_vis - 1) * iaq->nofldrxq_vi; 2638 if (iaq->nirq <= navail && 2639 (itype != INTR_MSI || powerof2(iaq->nirq))) { 2640 iaq->intr_flags_10g = INTR_ALL; 2641 iaq->intr_flags_1g = INTR_ALL; 2642 goto allocate; 2643 } 2644 2645 /* Disable the VIs (and netmap) if there aren't enough intrs */ 2646 if (num_vis > 1) { 2647 device_printf(sc->dev, "virtual interfaces disabled " 2648 "because num_vis=%u with current settings " 2649 "(nrxq10g=%u, nrxq1g=%u, nofldrxq10g=%u, " 2650 "nofldrxq1g=%u, nrxq_vi=%u nofldrxq_vi=%u, " 2651 "nnmrxq_vi=%u) would need %u interrupts but " 2652 "only %u are available.\n", num_vis, nrxq10g, 2653 nrxq1g, nofldrxq10g, nofldrxq1g, iaq->nrxq_vi, 2654 iaq->nofldrxq_vi, iaq->nnmrxq_vi, iaq->nirq, 2655 navail); 2656 num_vis = 1; 2657 iaq->ntxq_vi = iaq->nrxq_vi = 0; 2658 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0; 2659 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0; 2660 goto restart; 2661 } 2662 2663 /* 2664 * Second best option: a vector for errors, one for the firmware 2665 * event queue, and vectors for either all the NIC rx queues or 2666 * all the TOE rx queues. The queues that don't get vectors 2667 * will forward their interrupts to those that do. 2668 */ 2669 iaq->nirq = T4_EXTRA_INTR; 2670 if (nrxq10g >= nofldrxq10g) { 2671 iaq->intr_flags_10g = INTR_RXQ; 2672 iaq->nirq += n10g * nrxq10g; 2673 } else { 2674 iaq->intr_flags_10g = INTR_OFLD_RXQ; 2675 iaq->nirq += n10g * nofldrxq10g; 2676 } 2677 if (nrxq1g >= nofldrxq1g) { 2678 iaq->intr_flags_1g = INTR_RXQ; 2679 iaq->nirq += n1g * nrxq1g; 2680 } else { 2681 iaq->intr_flags_1g = INTR_OFLD_RXQ; 2682 iaq->nirq += n1g * nofldrxq1g; 2683 } 2684 if (iaq->nirq <= navail && 2685 (itype != INTR_MSI || powerof2(iaq->nirq))) 2686 goto allocate; 2687 2688 /* 2689 * Next best option: an interrupt vector for errors, one for the 2690 * firmware event queue, and at least one per main-VI. At this 2691 * point we know we'll have to downsize nrxq and/or nofldrxq to 2692 * fit what's available to us. 2693 */ 2694 iaq->nirq = T4_EXTRA_INTR; 2695 iaq->nirq += n10g + n1g; 2696 if (iaq->nirq <= navail) { 2697 int leftover = navail - iaq->nirq; 2698 2699 if (n10g > 0) { 2700 int target = max(nrxq10g, nofldrxq10g); 2701 2702 iaq->intr_flags_10g = nrxq10g >= nofldrxq10g ? 2703 INTR_RXQ : INTR_OFLD_RXQ; 2704 2705 n = 1; 2706 while (n < target && leftover >= n10g) { 2707 leftover -= n10g; 2708 iaq->nirq += n10g; 2709 n++; 2710 } 2711 iaq->nrxq10g = min(n, nrxq10g); 2712#ifdef TCP_OFFLOAD 2713 iaq->nofldrxq10g = min(n, nofldrxq10g); 2714#endif 2715 } 2716 2717 if (n1g > 0) { 2718 int target = max(nrxq1g, nofldrxq1g); 2719 2720 iaq->intr_flags_1g = nrxq1g >= nofldrxq1g ? 2721 INTR_RXQ : INTR_OFLD_RXQ; 2722 2723 n = 1; 2724 while (n < target && leftover >= n1g) { 2725 leftover -= n1g; 2726 iaq->nirq += n1g; 2727 n++; 2728 } 2729 iaq->nrxq1g = min(n, nrxq1g); 2730#ifdef TCP_OFFLOAD 2731 iaq->nofldrxq1g = min(n, nofldrxq1g); 2732#endif 2733 } 2734 2735 if (itype != INTR_MSI || powerof2(iaq->nirq)) 2736 goto allocate; 2737 } 2738 2739 /* 2740 * Least desirable option: one interrupt vector for everything. 2741 */ 2742 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1; 2743 iaq->intr_flags_10g = iaq->intr_flags_1g = 0; 2744#ifdef TCP_OFFLOAD 2745 if (is_offload(sc)) 2746 iaq->nofldrxq10g = iaq->nofldrxq1g = 1; 2747#endif 2748allocate: 2749 navail = iaq->nirq; 2750 rc = 0; 2751 if (itype == INTR_MSIX) 2752 rc = pci_alloc_msix(sc->dev, &navail); 2753 else if (itype == INTR_MSI) 2754 rc = pci_alloc_msi(sc->dev, &navail); 2755 2756 if (rc == 0) { 2757 if (navail == iaq->nirq) 2758 return (0); 2759 2760 /* 2761 * Didn't get the number requested. Use whatever number 2762 * the kernel is willing to allocate (it's in navail). 2763 */ 2764 device_printf(sc->dev, "fewer vectors than requested, " 2765 "type=%d, req=%d, rcvd=%d; will downshift req.\n", 2766 itype, iaq->nirq, navail); 2767 pci_release_msi(sc->dev); 2768 goto restart; 2769 } 2770 2771 device_printf(sc->dev, 2772 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 2773 itype, rc, iaq->nirq, navail); 2774 } 2775 2776 device_printf(sc->dev, 2777 "failed to find a usable interrupt type. " 2778 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 2779 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 2780 2781 return (ENXIO); 2782} 2783 2784#define FW_VERSION(chip) ( \ 2785 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \ 2786 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \ 2787 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \ 2788 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD)) 2789#define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf) 2790 2791struct fw_info { 2792 uint8_t chip; 2793 char *kld_name; 2794 char *fw_mod_name; 2795 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */ 2796} fw_info[] = { 2797 { 2798 .chip = CHELSIO_T4, 2799 .kld_name = "t4fw_cfg", 2800 .fw_mod_name = "t4fw", 2801 .fw_hdr = { 2802 .chip = FW_HDR_CHIP_T4, 2803 .fw_ver = htobe32_const(FW_VERSION(T4)), 2804 .intfver_nic = FW_INTFVER(T4, NIC), 2805 .intfver_vnic = FW_INTFVER(T4, VNIC), 2806 .intfver_ofld = FW_INTFVER(T4, OFLD), 2807 .intfver_ri = FW_INTFVER(T4, RI), 2808 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU), 2809 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 2810 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU), 2811 .intfver_fcoe = FW_INTFVER(T4, FCOE), 2812 }, 2813 }, { 2814 .chip = CHELSIO_T5, 2815 .kld_name = "t5fw_cfg", 2816 .fw_mod_name = "t5fw", 2817 .fw_hdr = { 2818 .chip = FW_HDR_CHIP_T5, 2819 .fw_ver = htobe32_const(FW_VERSION(T5)), 2820 .intfver_nic = FW_INTFVER(T5, NIC), 2821 .intfver_vnic = FW_INTFVER(T5, VNIC), 2822 .intfver_ofld = FW_INTFVER(T5, OFLD), 2823 .intfver_ri = FW_INTFVER(T5, RI), 2824 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU), 2825 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 2826 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU), 2827 .intfver_fcoe = FW_INTFVER(T5, FCOE), 2828 }, 2829 }, { 2830 .chip = CHELSIO_T6, 2831 .kld_name = "t6fw_cfg", 2832 .fw_mod_name = "t6fw", 2833 .fw_hdr = { 2834 .chip = FW_HDR_CHIP_T6, 2835 .fw_ver = htobe32_const(FW_VERSION(T6)), 2836 .intfver_nic = FW_INTFVER(T6, NIC), 2837 .intfver_vnic = FW_INTFVER(T6, VNIC), 2838 .intfver_ofld = FW_INTFVER(T6, OFLD), 2839 .intfver_ri = FW_INTFVER(T6, RI), 2840 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 2841 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 2842 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 2843 .intfver_fcoe = FW_INTFVER(T6, FCOE), 2844 }, 2845 } 2846}; 2847 2848static struct fw_info * 2849find_fw_info(int chip) 2850{ 2851 int i; 2852 2853 for (i = 0; i < nitems(fw_info); i++) { 2854 if (fw_info[i].chip == chip) 2855 return (&fw_info[i]); 2856 } 2857 return (NULL); 2858} 2859 2860/* 2861 * Is the given firmware API compatible with the one the driver was compiled 2862 * with? 2863 */ 2864static int 2865fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2) 2866{ 2867 2868 /* short circuit if it's the exact same firmware version */ 2869 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) 2870 return (1); 2871 2872 /* 2873 * XXX: Is this too conservative? Perhaps I should limit this to the 2874 * features that are supported in the driver. 2875 */ 2876#define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x) 2877 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) && 2878 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) && 2879 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe)) 2880 return (1); 2881#undef SAME_INTF 2882 2883 return (0); 2884} 2885 2886/* 2887 * The firmware in the KLD is usable, but should it be installed? This routine 2888 * explains itself in detail if it indicates the KLD firmware should be 2889 * installed. 2890 */ 2891static int 2892should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c) 2893{ 2894 const char *reason; 2895 2896 if (!card_fw_usable) { 2897 reason = "incompatible or unusable"; 2898 goto install; 2899 } 2900 2901 if (k > c) { 2902 reason = "older than the version bundled with this driver"; 2903 goto install; 2904 } 2905 2906 if (t4_fw_install == 2 && k != c) { 2907 reason = "different than the version bundled with this driver"; 2908 goto install; 2909 } 2910 2911 return (0); 2912 2913install: 2914 if (t4_fw_install == 0) { 2915 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 2916 "but the driver is prohibited from installing a different " 2917 "firmware on the card.\n", 2918 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 2919 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason); 2920 2921 return (0); 2922 } 2923 2924 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, " 2925 "installing firmware %u.%u.%u.%u on card.\n", 2926 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 2927 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason, 2928 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 2929 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 2930 2931 return (1); 2932} 2933/* 2934 * Establish contact with the firmware and determine if we are the master driver 2935 * or not, and whether we are responsible for chip initialization. 2936 */ 2937static int 2938prep_firmware(struct adapter *sc) 2939{ 2940 const struct firmware *fw = NULL, *default_cfg; 2941 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1; 2942 enum dev_state state; 2943 struct fw_info *fw_info; 2944 struct fw_hdr *card_fw; /* fw on the card */ 2945 const struct fw_hdr *kld_fw; /* fw in the KLD */ 2946 const struct fw_hdr *drv_fw; /* fw header the driver was compiled 2947 against */ 2948 2949 /* Contact firmware. */ 2950 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state); 2951 if (rc < 0 || state == DEV_STATE_ERR) { 2952 rc = -rc; 2953 device_printf(sc->dev, 2954 "failed to connect to the firmware: %d, %d.\n", rc, state); 2955 return (rc); 2956 } 2957 pf = rc; 2958 if (pf == sc->mbox) 2959 sc->flags |= MASTER_PF; 2960 else if (state == DEV_STATE_UNINIT) { 2961 /* 2962 * We didn't get to be the master so we definitely won't be 2963 * configuring the chip. It's a bug if someone else hasn't 2964 * configured it already. 2965 */ 2966 device_printf(sc->dev, "couldn't be master(%d), " 2967 "device not already initialized either(%d).\n", rc, state); 2968 return (EDOOFUS); 2969 } 2970 2971 /* This is the firmware whose headers the driver was compiled against */ 2972 fw_info = find_fw_info(chip_id(sc)); 2973 if (fw_info == NULL) { 2974 device_printf(sc->dev, 2975 "unable to look up firmware information for chip %d.\n", 2976 chip_id(sc)); 2977 return (EINVAL); 2978 } 2979 drv_fw = &fw_info->fw_hdr; 2980 2981 /* 2982 * The firmware KLD contains many modules. The KLD name is also the 2983 * name of the module that contains the default config file. 2984 */ 2985 default_cfg = firmware_get(fw_info->kld_name); 2986 2987 /* Read the header of the firmware on the card */ 2988 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK); 2989 rc = -t4_read_flash(sc, FLASH_FW_START, 2990 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1); 2991 if (rc == 0) 2992 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw); 2993 else { 2994 device_printf(sc->dev, 2995 "Unable to read card's firmware header: %d\n", rc); 2996 card_fw_usable = 0; 2997 } 2998 2999 /* This is the firmware in the KLD */ 3000 fw = firmware_get(fw_info->fw_mod_name); 3001 if (fw != NULL) { 3002 kld_fw = (const void *)fw->data; 3003 kld_fw_usable = fw_compatible(drv_fw, kld_fw); 3004 } else { 3005 kld_fw = NULL; 3006 kld_fw_usable = 0; 3007 } 3008 3009 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver && 3010 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) { 3011 /* 3012 * Common case: the firmware on the card is an exact match and 3013 * the KLD is an exact match too, or the KLD is 3014 * absent/incompatible. Note that t4_fw_install = 2 is ignored 3015 * here -- use cxgbetool loadfw if you want to reinstall the 3016 * same firmware as the one on the card. 3017 */ 3018 } else if (kld_fw_usable && state == DEV_STATE_UNINIT && 3019 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver), 3020 be32toh(card_fw->fw_ver))) { 3021 3022 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0); 3023 if (rc != 0) { 3024 device_printf(sc->dev, 3025 "failed to install firmware: %d\n", rc); 3026 goto done; 3027 } 3028 3029 /* Installed successfully, update the cached header too. */ 3030 memcpy(card_fw, kld_fw, sizeof(*card_fw)); 3031 card_fw_usable = 1; 3032 need_fw_reset = 0; /* already reset as part of load_fw */ 3033 } 3034 3035 if (!card_fw_usable) { 3036 uint32_t d, c, k; 3037 3038 d = ntohl(drv_fw->fw_ver); 3039 c = ntohl(card_fw->fw_ver); 3040 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0; 3041 3042 device_printf(sc->dev, "Cannot find a usable firmware: " 3043 "fw_install %d, chip state %d, " 3044 "driver compiled with %d.%d.%d.%d, " 3045 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n", 3046 t4_fw_install, state, 3047 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d), 3048 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d), 3049 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c), 3050 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), 3051 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k), 3052 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k)); 3053 rc = EINVAL; 3054 goto done; 3055 } 3056 3057 /* Reset device */ 3058 if (need_fw_reset && 3059 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) { 3060 device_printf(sc->dev, "firmware reset failed: %d.\n", rc); 3061 if (rc != ETIMEDOUT && rc != EIO) 3062 t4_fw_bye(sc, sc->mbox); 3063 goto done; 3064 } 3065 sc->flags |= FW_OK; 3066 3067 rc = get_params__pre_init(sc); 3068 if (rc != 0) 3069 goto done; /* error message displayed already */ 3070 3071 /* Partition adapter resources as specified in the config file. */ 3072 if (state == DEV_STATE_UNINIT) { 3073 3074 KASSERT(sc->flags & MASTER_PF, 3075 ("%s: trying to change chip settings when not master.", 3076 __func__)); 3077 3078 rc = partition_resources(sc, default_cfg, fw_info->kld_name); 3079 if (rc != 0) 3080 goto done; /* error message displayed already */ 3081 3082 t4_tweak_chip_settings(sc); 3083 3084 /* get basic stuff going */ 3085 rc = -t4_fw_initialize(sc, sc->mbox); 3086 if (rc != 0) { 3087 device_printf(sc->dev, "fw init failed: %d.\n", rc); 3088 goto done; 3089 } 3090 } else { 3091 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf); 3092 sc->cfcsum = 0; 3093 } 3094 3095done: 3096 free(card_fw, M_CXGBE); 3097 if (fw != NULL) 3098 firmware_put(fw, FIRMWARE_UNLOAD); 3099 if (default_cfg != NULL) 3100 firmware_put(default_cfg, FIRMWARE_UNLOAD); 3101 3102 return (rc); 3103} 3104 3105#define FW_PARAM_DEV(param) \ 3106 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 3107 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 3108#define FW_PARAM_PFVF(param) \ 3109 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 3110 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 3111 3112/* 3113 * Partition chip resources for use between various PFs, VFs, etc. 3114 */ 3115static int 3116partition_resources(struct adapter *sc, const struct firmware *default_cfg, 3117 const char *name_prefix) 3118{ 3119 const struct firmware *cfg = NULL; 3120 int rc = 0; 3121 struct fw_caps_config_cmd caps; 3122 uint32_t mtype, moff, finicsum, cfcsum; 3123 3124 /* 3125 * Figure out what configuration file to use. Pick the default config 3126 * file for the card if the user hasn't specified one explicitly. 3127 */ 3128 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file); 3129 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) { 3130 /* Card specific overrides go here. */ 3131 if (pci_get_device(sc->dev) == 0x440a) 3132 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF); 3133 if (is_fpga(sc)) 3134 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF); 3135 } 3136 3137 /* 3138 * We need to load another module if the profile is anything except 3139 * "default" or "flash". 3140 */ 3141 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 && 3142 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3143 char s[32]; 3144 3145 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file); 3146 cfg = firmware_get(s); 3147 if (cfg == NULL) { 3148 if (default_cfg != NULL) { 3149 device_printf(sc->dev, 3150 "unable to load module \"%s\" for " 3151 "configuration profile \"%s\", will use " 3152 "the default config file instead.\n", 3153 s, sc->cfg_file); 3154 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3155 "%s", DEFAULT_CF); 3156 } else { 3157 device_printf(sc->dev, 3158 "unable to load module \"%s\" for " 3159 "configuration profile \"%s\", will use " 3160 "the config file on the card's flash " 3161 "instead.\n", s, sc->cfg_file); 3162 snprintf(sc->cfg_file, sizeof(sc->cfg_file), 3163 "%s", FLASH_CF); 3164 } 3165 } 3166 } 3167 3168 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 && 3169 default_cfg == NULL) { 3170 device_printf(sc->dev, 3171 "default config file not available, will use the config " 3172 "file on the card's flash instead.\n"); 3173 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF); 3174 } 3175 3176 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) { 3177 u_int cflen; 3178 const uint32_t *cfdata; 3179 uint32_t param, val, addr; 3180 3181 KASSERT(cfg != NULL || default_cfg != NULL, 3182 ("%s: no config to upload", __func__)); 3183 3184 /* 3185 * Ask the firmware where it wants us to upload the config file. 3186 */ 3187 param = FW_PARAM_DEV(CF); 3188 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3189 if (rc != 0) { 3190 /* No support for config file? Shouldn't happen. */ 3191 device_printf(sc->dev, 3192 "failed to query config file location: %d.\n", rc); 3193 goto done; 3194 } 3195 mtype = G_FW_PARAMS_PARAM_Y(val); 3196 moff = G_FW_PARAMS_PARAM_Z(val) << 16; 3197 3198 /* 3199 * XXX: sheer laziness. We deliberately added 4 bytes of 3200 * useless stuffing/comments at the end of the config file so 3201 * it's ok to simply throw away the last remaining bytes when 3202 * the config file is not an exact multiple of 4. This also 3203 * helps with the validate_mt_off_len check. 3204 */ 3205 if (cfg != NULL) { 3206 cflen = cfg->datasize & ~3; 3207 cfdata = cfg->data; 3208 } else { 3209 cflen = default_cfg->datasize & ~3; 3210 cfdata = default_cfg->data; 3211 } 3212 3213 if (cflen > FLASH_CFG_MAX_SIZE) { 3214 device_printf(sc->dev, 3215 "config file too long (%d, max allowed is %d). " 3216 "Will try to use the config on the card, if any.\n", 3217 cflen, FLASH_CFG_MAX_SIZE); 3218 goto use_config_on_flash; 3219 } 3220 3221 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr); 3222 if (rc != 0) { 3223 device_printf(sc->dev, 3224 "%s: addr (%d/0x%x) or len %d is not valid: %d. " 3225 "Will try to use the config on the card, if any.\n", 3226 __func__, mtype, moff, cflen, rc); 3227 goto use_config_on_flash; 3228 } 3229 write_via_memwin(sc, 2, addr, cfdata, cflen); 3230 } else { 3231use_config_on_flash: 3232 mtype = FW_MEMTYPE_FLASH; 3233 moff = t4_flash_cfg_addr(sc); 3234 } 3235 3236 bzero(&caps, sizeof(caps)); 3237 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3238 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3239 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID | 3240 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 3241 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps)); 3242 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3243 if (rc != 0) { 3244 device_printf(sc->dev, 3245 "failed to pre-process config file: %d " 3246 "(mtype %d, moff 0x%x).\n", rc, mtype, moff); 3247 goto done; 3248 } 3249 3250 finicsum = be32toh(caps.finicsum); 3251 cfcsum = be32toh(caps.cfcsum); 3252 if (finicsum != cfcsum) { 3253 device_printf(sc->dev, 3254 "WARNING: config file checksum mismatch: %08x %08x\n", 3255 finicsum, cfcsum); 3256 } 3257 sc->cfcsum = cfcsum; 3258 3259#define LIMIT_CAPS(x) do { \ 3260 caps.x &= htobe16(t4_##x##_allowed); \ 3261} while (0) 3262 3263 /* 3264 * Let the firmware know what features will (not) be used so it can tune 3265 * things accordingly. 3266 */ 3267 LIMIT_CAPS(nbmcaps); 3268 LIMIT_CAPS(linkcaps); 3269 LIMIT_CAPS(switchcaps); 3270 LIMIT_CAPS(niccaps); 3271 LIMIT_CAPS(toecaps); 3272 LIMIT_CAPS(rdmacaps); 3273 LIMIT_CAPS(cryptocaps); 3274 LIMIT_CAPS(iscsicaps); 3275 LIMIT_CAPS(fcoecaps); 3276#undef LIMIT_CAPS 3277 3278 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3279 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 3280 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3281 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL); 3282 if (rc != 0) { 3283 device_printf(sc->dev, 3284 "failed to process config file: %d.\n", rc); 3285 } 3286done: 3287 if (cfg != NULL) 3288 firmware_put(cfg, FIRMWARE_UNLOAD); 3289 return (rc); 3290} 3291 3292/* 3293 * Retrieve parameters that are needed (or nice to have) very early. 3294 */ 3295static int 3296get_params__pre_init(struct adapter *sc) 3297{ 3298 int rc; 3299 uint32_t param[2], val[2]; 3300 3301 t4_get_version_info(sc); 3302 3303 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 3304 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 3305 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 3306 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 3307 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 3308 3309 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u", 3310 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers), 3311 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers), 3312 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers), 3313 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers)); 3314 3315 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 3316 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 3317 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 3318 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 3319 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 3320 3321 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u", 3322 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers), 3323 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers), 3324 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers), 3325 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers)); 3326 3327 param[0] = FW_PARAM_DEV(PORTVEC); 3328 param[1] = FW_PARAM_DEV(CCLK); 3329 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3330 if (rc != 0) { 3331 device_printf(sc->dev, 3332 "failed to query parameters (pre_init): %d.\n", rc); 3333 return (rc); 3334 } 3335 3336 sc->params.portvec = val[0]; 3337 sc->params.nports = bitcount32(val[0]); 3338 sc->params.vpd.cclk = val[1]; 3339 3340 /* Read device log parameters. */ 3341 rc = -t4_init_devlog_params(sc, 1); 3342 if (rc == 0) 3343 fixup_devlog_params(sc); 3344 else { 3345 device_printf(sc->dev, 3346 "failed to get devlog parameters: %d.\n", rc); 3347 rc = 0; /* devlog isn't critical for device operation */ 3348 } 3349 3350 return (rc); 3351} 3352 3353/* 3354 * Retrieve various parameters that are of interest to the driver. The device 3355 * has been initialized by the firmware at this point. 3356 */ 3357static int 3358get_params__post_init(struct adapter *sc) 3359{ 3360 int rc; 3361 uint32_t param[7], val[7]; 3362 struct fw_caps_config_cmd caps; 3363 3364 param[0] = FW_PARAM_PFVF(IQFLINT_START); 3365 param[1] = FW_PARAM_PFVF(EQ_START); 3366 param[2] = FW_PARAM_PFVF(FILTER_START); 3367 param[3] = FW_PARAM_PFVF(FILTER_END); 3368 param[4] = FW_PARAM_PFVF(L2T_START); 3369 param[5] = FW_PARAM_PFVF(L2T_END); 3370 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3371 if (rc != 0) { 3372 device_printf(sc->dev, 3373 "failed to query parameters (post_init): %d.\n", rc); 3374 return (rc); 3375 } 3376 3377 sc->sge.iq_start = val[0]; 3378 sc->sge.eq_start = val[1]; 3379 sc->tids.ftid_base = val[2]; 3380 sc->tids.nftids = val[3] - val[2] + 1; 3381 sc->params.ftid_min = val[2]; 3382 sc->params.ftid_max = val[3]; 3383 sc->vres.l2t.start = val[4]; 3384 sc->vres.l2t.size = val[5] - val[4] + 1; 3385 KASSERT(sc->vres.l2t.size <= L2T_SIZE, 3386 ("%s: L2 table size (%u) larger than expected (%u)", 3387 __func__, sc->vres.l2t.size, L2T_SIZE)); 3388 3389 /* get capabilites */ 3390 bzero(&caps, sizeof(caps)); 3391 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 3392 F_FW_CMD_REQUEST | F_FW_CMD_READ); 3393 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps)); 3394 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps); 3395 if (rc != 0) { 3396 device_printf(sc->dev, 3397 "failed to get card capabilities: %d.\n", rc); 3398 return (rc); 3399 } 3400 3401#define READ_CAPS(x) do { \ 3402 sc->x = htobe16(caps.x); \ 3403} while (0) 3404 READ_CAPS(nbmcaps); 3405 READ_CAPS(linkcaps); 3406 READ_CAPS(switchcaps); 3407 READ_CAPS(niccaps); 3408 READ_CAPS(toecaps); 3409 READ_CAPS(rdmacaps); 3410 READ_CAPS(cryptocaps); 3411 READ_CAPS(iscsicaps); 3412 READ_CAPS(fcoecaps); 3413 3414 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) { 3415 param[0] = FW_PARAM_PFVF(ETHOFLD_START); 3416 param[1] = FW_PARAM_PFVF(ETHOFLD_END); 3417 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3418 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val); 3419 if (rc != 0) { 3420 device_printf(sc->dev, 3421 "failed to query NIC parameters: %d.\n", rc); 3422 return (rc); 3423 } 3424 sc->tids.etid_base = val[0]; 3425 sc->params.etid_min = val[0]; 3426 sc->tids.netids = val[1] - val[0] + 1; 3427 sc->params.netids = sc->tids.netids; 3428 sc->params.eo_wr_cred = val[2]; 3429 sc->params.ethoffload = 1; 3430 } 3431 3432 if (sc->toecaps) { 3433 /* query offload-related parameters */ 3434 param[0] = FW_PARAM_DEV(NTID); 3435 param[1] = FW_PARAM_PFVF(SERVER_START); 3436 param[2] = FW_PARAM_PFVF(SERVER_END); 3437 param[3] = FW_PARAM_PFVF(TDDP_START); 3438 param[4] = FW_PARAM_PFVF(TDDP_END); 3439 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3440 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3441 if (rc != 0) { 3442 device_printf(sc->dev, 3443 "failed to query TOE parameters: %d.\n", rc); 3444 return (rc); 3445 } 3446 sc->tids.ntids = val[0]; 3447 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS); 3448 sc->tids.stid_base = val[1]; 3449 sc->tids.nstids = val[2] - val[1] + 1; 3450 sc->vres.ddp.start = val[3]; 3451 sc->vres.ddp.size = val[4] - val[3] + 1; 3452 sc->params.ofldq_wr_cred = val[5]; 3453 sc->params.offload = 1; 3454 } 3455 if (sc->rdmacaps) { 3456 param[0] = FW_PARAM_PFVF(STAG_START); 3457 param[1] = FW_PARAM_PFVF(STAG_END); 3458 param[2] = FW_PARAM_PFVF(RQ_START); 3459 param[3] = FW_PARAM_PFVF(RQ_END); 3460 param[4] = FW_PARAM_PFVF(PBL_START); 3461 param[5] = FW_PARAM_PFVF(PBL_END); 3462 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3463 if (rc != 0) { 3464 device_printf(sc->dev, 3465 "failed to query RDMA parameters(1): %d.\n", rc); 3466 return (rc); 3467 } 3468 sc->vres.stag.start = val[0]; 3469 sc->vres.stag.size = val[1] - val[0] + 1; 3470 sc->vres.rq.start = val[2]; 3471 sc->vres.rq.size = val[3] - val[2] + 1; 3472 sc->vres.pbl.start = val[4]; 3473 sc->vres.pbl.size = val[5] - val[4] + 1; 3474 3475 param[0] = FW_PARAM_PFVF(SQRQ_START); 3476 param[1] = FW_PARAM_PFVF(SQRQ_END); 3477 param[2] = FW_PARAM_PFVF(CQ_START); 3478 param[3] = FW_PARAM_PFVF(CQ_END); 3479 param[4] = FW_PARAM_PFVF(OCQ_START); 3480 param[5] = FW_PARAM_PFVF(OCQ_END); 3481 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); 3482 if (rc != 0) { 3483 device_printf(sc->dev, 3484 "failed to query RDMA parameters(2): %d.\n", rc); 3485 return (rc); 3486 } 3487 sc->vres.qp.start = val[0]; 3488 sc->vres.qp.size = val[1] - val[0] + 1; 3489 sc->vres.cq.start = val[2]; 3490 sc->vres.cq.size = val[3] - val[2] + 1; 3491 sc->vres.ocq.start = val[4]; 3492 sc->vres.ocq.size = val[5] - val[4] + 1; 3493 } 3494 if (sc->iscsicaps) { 3495 param[0] = FW_PARAM_PFVF(ISCSI_START); 3496 param[1] = FW_PARAM_PFVF(ISCSI_END); 3497 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); 3498 if (rc != 0) { 3499 device_printf(sc->dev, 3500 "failed to query iSCSI parameters: %d.\n", rc); 3501 return (rc); 3502 } 3503 sc->vres.iscsi.start = val[0]; 3504 sc->vres.iscsi.size = val[1] - val[0] + 1; 3505 } 3506 3507 t4_init_sge_params(sc); 3508 3509 /* 3510 * We've got the params we wanted to query via the firmware. Now grab 3511 * some others directly from the chip. 3512 */ 3513 rc = t4_read_chip_settings(sc); 3514 3515 return (rc); 3516} 3517 3518static int 3519set_params__post_init(struct adapter *sc) 3520{ 3521 uint32_t param, val; 3522 3523 /* ask for encapsulated CPLs */ 3524 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 3525 val = 1; 3526 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 3527 3528 return (0); 3529} 3530 3531#undef FW_PARAM_PFVF 3532#undef FW_PARAM_DEV 3533 3534static void 3535t4_set_desc(struct adapter *sc) 3536{ 3537 char buf[128]; 3538 struct adapter_params *p = &sc->params; 3539 3540 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id); 3541 3542 device_set_desc_copy(sc->dev, buf); 3543} 3544 3545static void 3546build_medialist(struct port_info *pi, struct ifmedia *media) 3547{ 3548 int m; 3549 3550 PORT_LOCK(pi); 3551 3552 ifmedia_removeall(media); 3553 3554 m = IFM_ETHER | IFM_FDX; 3555 3556 switch(pi->port_type) { 3557 case FW_PORT_TYPE_BT_XFI: 3558 case FW_PORT_TYPE_BT_XAUI: 3559 ifmedia_add(media, m | IFM_10G_T, 0, NULL); 3560 /* fall through */ 3561 3562 case FW_PORT_TYPE_BT_SGMII: 3563 ifmedia_add(media, m | IFM_1000_T, 0, NULL); 3564 ifmedia_add(media, m | IFM_100_TX, 0, NULL); 3565 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL); 3566 ifmedia_set(media, IFM_ETHER | IFM_AUTO); 3567 break; 3568 3569 case FW_PORT_TYPE_CX4: 3570 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL); 3571 ifmedia_set(media, m | IFM_10G_CX4); 3572 break; 3573 3574 case FW_PORT_TYPE_QSFP_10G: 3575 case FW_PORT_TYPE_SFP: 3576 case FW_PORT_TYPE_FIBER_XFI: 3577 case FW_PORT_TYPE_FIBER_XAUI: 3578 switch (pi->mod_type) { 3579 3580 case FW_PORT_MOD_TYPE_LR: 3581 ifmedia_add(media, m | IFM_10G_LR, 0, NULL); 3582 ifmedia_set(media, m | IFM_10G_LR); 3583 break; 3584 3585 case FW_PORT_MOD_TYPE_SR: 3586 ifmedia_add(media, m | IFM_10G_SR, 0, NULL); 3587 ifmedia_set(media, m | IFM_10G_SR); 3588 break; 3589 3590 case FW_PORT_MOD_TYPE_LRM: 3591 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL); 3592 ifmedia_set(media, m | IFM_10G_LRM); 3593 break; 3594 3595 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3596 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3597 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL); 3598 ifmedia_set(media, m | IFM_10G_TWINAX); 3599 break; 3600 3601 case FW_PORT_MOD_TYPE_NONE: 3602 m &= ~IFM_FDX; 3603 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3604 ifmedia_set(media, m | IFM_NONE); 3605 break; 3606 3607 case FW_PORT_MOD_TYPE_NA: 3608 case FW_PORT_MOD_TYPE_ER: 3609 default: 3610 device_printf(pi->dev, 3611 "unknown port_type (%d), mod_type (%d)\n", 3612 pi->port_type, pi->mod_type); 3613 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3614 ifmedia_set(media, m | IFM_UNKNOWN); 3615 break; 3616 } 3617 break; 3618 3619 case FW_PORT_TYPE_CR_QSFP: 3620 case FW_PORT_TYPE_SFP28: 3621 case FW_PORT_TYPE_KR_SFP28: 3622 switch (pi->mod_type) { 3623 3624 case FW_PORT_MOD_TYPE_SR: 3625 ifmedia_add(media, m | IFM_25G_SR, 0, NULL); 3626 ifmedia_set(media, m | IFM_25G_SR); 3627 break; 3628 3629 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3630 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3631 ifmedia_add(media, m | IFM_25G_CR, 0, NULL); 3632 ifmedia_set(media, m | IFM_25G_CR); 3633 break; 3634 3635 case FW_PORT_MOD_TYPE_NONE: 3636 m &= ~IFM_FDX; 3637 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3638 ifmedia_set(media, m | IFM_NONE); 3639 break; 3640 3641 default: 3642 device_printf(pi->dev, 3643 "unknown port_type (%d), mod_type (%d)\n", 3644 pi->port_type, pi->mod_type); 3645 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3646 ifmedia_set(media, m | IFM_UNKNOWN); 3647 break; 3648 } 3649 break; 3650 3651 case FW_PORT_TYPE_QSFP: 3652 switch (pi->mod_type) { 3653 3654 case FW_PORT_MOD_TYPE_LR: 3655 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL); 3656 ifmedia_set(media, m | IFM_40G_LR4); 3657 break; 3658 3659 case FW_PORT_MOD_TYPE_SR: 3660 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL); 3661 ifmedia_set(media, m | IFM_40G_SR4); 3662 break; 3663 3664 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3665 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3666 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL); 3667 ifmedia_set(media, m | IFM_40G_CR4); 3668 break; 3669 3670 case FW_PORT_MOD_TYPE_NONE: 3671 m &= ~IFM_FDX; 3672 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3673 ifmedia_set(media, m | IFM_NONE); 3674 break; 3675 3676 default: 3677 device_printf(pi->dev, 3678 "unknown port_type (%d), mod_type (%d)\n", 3679 pi->port_type, pi->mod_type); 3680 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3681 ifmedia_set(media, m | IFM_UNKNOWN); 3682 break; 3683 } 3684 break; 3685 3686 case FW_PORT_TYPE_KR4_100G: 3687 case FW_PORT_TYPE_CR4_QSFP: 3688 switch (pi->mod_type) { 3689 3690 case FW_PORT_MOD_TYPE_LR: 3691 ifmedia_add(media, m | IFM_100G_LR4, 0, NULL); 3692 ifmedia_set(media, m | IFM_100G_LR4); 3693 break; 3694 3695 case FW_PORT_MOD_TYPE_SR: 3696 ifmedia_add(media, m | IFM_100G_SR4, 0, NULL); 3697 ifmedia_set(media, m | IFM_100G_SR4); 3698 break; 3699 3700 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE: 3701 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE: 3702 ifmedia_add(media, m | IFM_100G_CR4, 0, NULL); 3703 ifmedia_set(media, m | IFM_100G_CR4); 3704 break; 3705 3706 case FW_PORT_MOD_TYPE_NONE: 3707 m &= ~IFM_FDX; 3708 ifmedia_add(media, m | IFM_NONE, 0, NULL); 3709 ifmedia_set(media, m | IFM_NONE); 3710 break; 3711 3712 default: 3713 device_printf(pi->dev, 3714 "unknown port_type (%d), mod_type (%d)\n", 3715 pi->port_type, pi->mod_type); 3716 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3717 ifmedia_set(media, m | IFM_UNKNOWN); 3718 break; 3719 } 3720 break; 3721 3722 default: 3723 device_printf(pi->dev, 3724 "unknown port_type (%d), mod_type (%d)\n", pi->port_type, 3725 pi->mod_type); 3726 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL); 3727 ifmedia_set(media, m | IFM_UNKNOWN); 3728 break; 3729 } 3730 3731 PORT_UNLOCK(pi); 3732} 3733 3734#define FW_MAC_EXACT_CHUNK 7 3735 3736/* 3737 * Program the port's XGMAC based on parameters in ifnet. The caller also 3738 * indicates which parameters should be programmed (the rest are left alone). 3739 */ 3740int 3741update_mac_settings(struct ifnet *ifp, int flags) 3742{ 3743 int rc = 0; 3744 struct vi_info *vi = ifp->if_softc; 3745 struct port_info *pi = vi->pi; 3746 struct adapter *sc = pi->adapter; 3747 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1; 3748 3749 ASSERT_SYNCHRONIZED_OP(sc); 3750 KASSERT(flags, ("%s: not told what to update.", __func__)); 3751 3752 if (flags & XGMAC_MTU) 3753 mtu = ifp->if_mtu; 3754 3755 if (flags & XGMAC_PROMISC) 3756 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0; 3757 3758 if (flags & XGMAC_ALLMULTI) 3759 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0; 3760 3761 if (flags & XGMAC_VLANEX) 3762 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0; 3763 3764 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) { 3765 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc, 3766 allmulti, 1, vlanex, false); 3767 if (rc) { 3768 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags, 3769 rc); 3770 return (rc); 3771 } 3772 } 3773 3774 if (flags & XGMAC_UCADDR) { 3775 uint8_t ucaddr[ETHER_ADDR_LEN]; 3776 3777 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr)); 3778 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt, 3779 ucaddr, true, true); 3780 if (rc < 0) { 3781 rc = -rc; 3782 if_printf(ifp, "change_mac failed: %d\n", rc); 3783 return (rc); 3784 } else { 3785 vi->xact_addr_filt = rc; 3786 rc = 0; 3787 } 3788 } 3789 3790 if (flags & XGMAC_MCADDRS) { 3791 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK]; 3792 int del = 1; 3793 uint64_t hash = 0; 3794 struct ifmultiaddr *ifma; 3795 int i = 0, j; 3796 3797 if_maddr_rlock(ifp); 3798 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 3799 if (ifma->ifma_addr->sa_family != AF_LINK) 3800 continue; 3801 mcaddr[i] = 3802 LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 3803 MPASS(ETHER_IS_MULTICAST(mcaddr[i])); 3804 i++; 3805 3806 if (i == FW_MAC_EXACT_CHUNK) { 3807 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, 3808 del, i, mcaddr, NULL, &hash, 0); 3809 if (rc < 0) { 3810 rc = -rc; 3811 for (j = 0; j < i; j++) { 3812 if_printf(ifp, 3813 "failed to add mc address" 3814 " %02x:%02x:%02x:" 3815 "%02x:%02x:%02x rc=%d\n", 3816 mcaddr[j][0], mcaddr[j][1], 3817 mcaddr[j][2], mcaddr[j][3], 3818 mcaddr[j][4], mcaddr[j][5], 3819 rc); 3820 } 3821 goto mcfail; 3822 } 3823 del = 0; 3824 i = 0; 3825 } 3826 } 3827 if (i > 0) { 3828 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i, 3829 mcaddr, NULL, &hash, 0); 3830 if (rc < 0) { 3831 rc = -rc; 3832 for (j = 0; j < i; j++) { 3833 if_printf(ifp, 3834 "failed to add mc address" 3835 " %02x:%02x:%02x:" 3836 "%02x:%02x:%02x rc=%d\n", 3837 mcaddr[j][0], mcaddr[j][1], 3838 mcaddr[j][2], mcaddr[j][3], 3839 mcaddr[j][4], mcaddr[j][5], 3840 rc); 3841 } 3842 goto mcfail; 3843 } 3844 } 3845 3846 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0); 3847 if (rc != 0) 3848 if_printf(ifp, "failed to set mc address hash: %d", rc); 3849mcfail: 3850 if_maddr_runlock(ifp); 3851 } 3852 3853 return (rc); 3854} 3855 3856/* 3857 * {begin|end}_synchronized_op must be called from the same thread. 3858 */ 3859int 3860begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags, 3861 char *wmesg) 3862{ 3863 int rc, pri; 3864 3865#ifdef WITNESS 3866 /* the caller thinks it's ok to sleep, but is it really? */ 3867 if (flags & SLEEP_OK) 3868 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL, 3869 "begin_synchronized_op"); 3870#endif 3871 3872 if (INTR_OK) 3873 pri = PCATCH; 3874 else 3875 pri = 0; 3876 3877 ADAPTER_LOCK(sc); 3878 for (;;) { 3879 3880 if (vi && IS_DOOMED(vi)) { 3881 rc = ENXIO; 3882 goto done; 3883 } 3884 3885 if (!IS_BUSY(sc)) { 3886 rc = 0; 3887 break; 3888 } 3889 3890 if (!(flags & SLEEP_OK)) { 3891 rc = EBUSY; 3892 goto done; 3893 } 3894 3895 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) { 3896 rc = EINTR; 3897 goto done; 3898 } 3899 } 3900 3901 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__)); 3902 SET_BUSY(sc); 3903#ifdef INVARIANTS 3904 sc->last_op = wmesg; 3905 sc->last_op_thr = curthread; 3906 sc->last_op_flags = flags; 3907#endif 3908 3909done: 3910 if (!(flags & HOLD_LOCK) || rc) 3911 ADAPTER_UNLOCK(sc); 3912 3913 return (rc); 3914} 3915 3916/* 3917 * Tell if_ioctl and if_init that the VI is going away. This is 3918 * special variant of begin_synchronized_op and must be paired with a 3919 * call to end_synchronized_op. 3920 */ 3921void 3922doom_vi(struct adapter *sc, struct vi_info *vi) 3923{ 3924 3925 ADAPTER_LOCK(sc); 3926 SET_DOOMED(vi); 3927 wakeup(&sc->flags); 3928 while (IS_BUSY(sc)) 3929 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0); 3930 SET_BUSY(sc); 3931#ifdef INVARIANTS 3932 sc->last_op = "t4detach"; 3933 sc->last_op_thr = curthread; 3934 sc->last_op_flags = 0; 3935#endif 3936 ADAPTER_UNLOCK(sc); 3937} 3938 3939/* 3940 * {begin|end}_synchronized_op must be called from the same thread. 3941 */ 3942void 3943end_synchronized_op(struct adapter *sc, int flags) 3944{ 3945 3946 if (flags & LOCK_HELD) 3947 ADAPTER_LOCK_ASSERT_OWNED(sc); 3948 else 3949 ADAPTER_LOCK(sc); 3950 3951 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__)); 3952 CLR_BUSY(sc); 3953 wakeup(&sc->flags); 3954 ADAPTER_UNLOCK(sc); 3955} 3956 3957static int 3958cxgbe_init_synchronized(struct vi_info *vi) 3959{ 3960 struct port_info *pi = vi->pi; 3961 struct adapter *sc = pi->adapter; 3962 struct ifnet *ifp = vi->ifp; 3963 int rc = 0, i; 3964 struct sge_txq *txq; 3965 3966 ASSERT_SYNCHRONIZED_OP(sc); 3967 3968 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3969 return (0); /* already running */ 3970 3971 if (!(sc->flags & FULL_INIT_DONE) && 3972 ((rc = adapter_full_init(sc)) != 0)) 3973 return (rc); /* error message displayed already */ 3974 3975 if (!(vi->flags & VI_INIT_DONE) && 3976 ((rc = vi_full_init(vi)) != 0)) 3977 return (rc); /* error message displayed already */ 3978 3979 rc = update_mac_settings(ifp, XGMAC_ALL); 3980 if (rc) 3981 goto done; /* error message displayed already */ 3982 3983 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true); 3984 if (rc != 0) { 3985 if_printf(ifp, "enable_vi failed: %d\n", rc); 3986 goto done; 3987 } 3988 3989 /* 3990 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized 3991 * if this changes. 3992 */ 3993 3994 for_each_txq(vi, i, txq) { 3995 TXQ_LOCK(txq); 3996 txq->eq.flags |= EQ_ENABLED; 3997 TXQ_UNLOCK(txq); 3998 } 3999 4000 /* 4001 * The first iq of the first port to come up is used for tracing. 4002 */ 4003 if (sc->traceq < 0 && IS_MAIN_VI(vi)) { 4004 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id; 4005 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL : 4006 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) | 4007 V_QUEUENUMBER(sc->traceq)); 4008 pi->flags |= HAS_TRACEQ; 4009 } 4010 4011 /* all ok */ 4012 PORT_LOCK(pi); 4013 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4014 pi->up_vis++; 4015 4016 if (pi->nvi > 1 || sc->flags & IS_VF) 4017 callout_reset(&vi->tick, hz, vi_tick, vi); 4018 else 4019 callout_reset(&pi->tick, hz, cxgbe_tick, pi); 4020 PORT_UNLOCK(pi); 4021done: 4022 if (rc != 0) 4023 cxgbe_uninit_synchronized(vi); 4024 4025 return (rc); 4026} 4027 4028/* 4029 * Idempotent. 4030 */ 4031static int 4032cxgbe_uninit_synchronized(struct vi_info *vi) 4033{ 4034 struct port_info *pi = vi->pi; 4035 struct adapter *sc = pi->adapter; 4036 struct ifnet *ifp = vi->ifp; 4037 int rc, i; 4038 struct sge_txq *txq; 4039 4040 ASSERT_SYNCHRONIZED_OP(sc); 4041 4042 if (!(vi->flags & VI_INIT_DONE)) { 4043 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING), 4044 ("uninited VI is running")); 4045 return (0); 4046 } 4047 4048 /* 4049 * Disable the VI so that all its data in either direction is discarded 4050 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz 4051 * tick) intact as the TP can deliver negative advice or data that it's 4052 * holding in its RAM (for an offloaded connection) even after the VI is 4053 * disabled. 4054 */ 4055 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false); 4056 if (rc) { 4057 if_printf(ifp, "disable_vi failed: %d\n", rc); 4058 return (rc); 4059 } 4060 4061 for_each_txq(vi, i, txq) { 4062 TXQ_LOCK(txq); 4063 txq->eq.flags &= ~EQ_ENABLED; 4064 TXQ_UNLOCK(txq); 4065 } 4066 4067 PORT_LOCK(pi); 4068 if (pi->nvi > 1 || sc->flags & IS_VF) 4069 callout_stop(&vi->tick); 4070 else 4071 callout_stop(&pi->tick); 4072 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4073 PORT_UNLOCK(pi); 4074 return (0); 4075 } 4076 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4077 pi->up_vis--; 4078 if (pi->up_vis > 0) { 4079 PORT_UNLOCK(pi); 4080 return (0); 4081 } 4082 PORT_UNLOCK(pi); 4083 4084 pi->link_cfg.link_ok = 0; 4085 pi->link_cfg.speed = 0; 4086 pi->link_cfg.link_down_rc = 255; 4087 t4_os_link_changed(sc, pi->port_id, 0); 4088 4089 return (0); 4090} 4091 4092/* 4093 * It is ok for this function to fail midway and return right away. t4_detach 4094 * will walk the entire sc->irq list and clean up whatever is valid. 4095 */ 4096int 4097t4_setup_intr_handlers(struct adapter *sc) 4098{ 4099 int rc, rid, p, q, v; 4100 char s[8]; 4101 struct irq *irq; 4102 struct port_info *pi; 4103 struct vi_info *vi; 4104 struct sge *sge = &sc->sge; 4105 struct sge_rxq *rxq; 4106#ifdef TCP_OFFLOAD 4107 struct sge_ofld_rxq *ofld_rxq; 4108#endif 4109#ifdef DEV_NETMAP 4110 struct sge_nm_rxq *nm_rxq; 4111#endif 4112#ifdef RSS 4113 int nbuckets = rss_getnumbuckets(); 4114#endif 4115 4116 /* 4117 * Setup interrupts. 4118 */ 4119 irq = &sc->irq[0]; 4120 rid = sc->intr_type == INTR_INTX ? 0 : 1; 4121 if (sc->intr_count == 1) 4122 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all")); 4123 4124 /* Multiple interrupts. */ 4125 if (sc->flags & IS_VF) 4126 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports, 4127 ("%s: too few intr.", __func__)); 4128 else 4129 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports, 4130 ("%s: too few intr.", __func__)); 4131 4132 /* The first one is always error intr on PFs */ 4133 if (!(sc->flags & IS_VF)) { 4134 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err"); 4135 if (rc != 0) 4136 return (rc); 4137 irq++; 4138 rid++; 4139 } 4140 4141 /* The second one is always the firmware event queue (first on VFs) */ 4142 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt"); 4143 if (rc != 0) 4144 return (rc); 4145 irq++; 4146 rid++; 4147 4148 for_each_port(sc, p) { 4149 pi = sc->port[p]; 4150 for_each_vi(pi, v, vi) { 4151 vi->first_intr = rid - 1; 4152 4153 if (vi->nnmrxq > 0) { 4154 int n = max(vi->nrxq, vi->nnmrxq); 4155 4156 MPASS(vi->flags & INTR_RXQ); 4157 4158 rxq = &sge->rxq[vi->first_rxq]; 4159#ifdef DEV_NETMAP 4160 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq]; 4161#endif 4162 for (q = 0; q < n; q++) { 4163 snprintf(s, sizeof(s), "%x%c%x", p, 4164 'a' + v, q); 4165 if (q < vi->nrxq) 4166 irq->rxq = rxq++; 4167#ifdef DEV_NETMAP 4168 if (q < vi->nnmrxq) 4169 irq->nm_rxq = nm_rxq++; 4170#endif 4171 rc = t4_alloc_irq(sc, irq, rid, 4172 t4_vi_intr, irq, s); 4173 if (rc != 0) 4174 return (rc); 4175 irq++; 4176 rid++; 4177 vi->nintr++; 4178 } 4179 } else if (vi->flags & INTR_RXQ) { 4180 for_each_rxq(vi, q, rxq) { 4181 snprintf(s, sizeof(s), "%x%c%x", p, 4182 'a' + v, q); 4183 rc = t4_alloc_irq(sc, irq, rid, 4184 t4_intr, rxq, s); 4185 if (rc != 0) 4186 return (rc); 4187#ifdef RSS 4188 bus_bind_intr(sc->dev, irq->res, 4189 rss_getcpu(q % nbuckets)); 4190#endif 4191 irq++; 4192 rid++; 4193 vi->nintr++; 4194 } 4195 } 4196#ifdef TCP_OFFLOAD 4197 if (vi->flags & INTR_OFLD_RXQ) { 4198 for_each_ofld_rxq(vi, q, ofld_rxq) { 4199 snprintf(s, sizeof(s), "%x%c%x", p, 4200 'A' + v, q); 4201 rc = t4_alloc_irq(sc, irq, rid, 4202 t4_intr, ofld_rxq, s); 4203 if (rc != 0) 4204 return (rc); 4205 irq++; 4206 rid++; 4207 vi->nintr++; 4208 } 4209 } 4210#endif 4211 } 4212 } 4213 MPASS(irq == &sc->irq[sc->intr_count]); 4214 4215 return (0); 4216} 4217 4218int 4219adapter_full_init(struct adapter *sc) 4220{ 4221 int rc, i; 4222 4223 ASSERT_SYNCHRONIZED_OP(sc); 4224 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4225 KASSERT((sc->flags & FULL_INIT_DONE) == 0, 4226 ("%s: FULL_INIT_DONE already", __func__)); 4227 4228 /* 4229 * queues that belong to the adapter (not any particular port). 4230 */ 4231 rc = t4_setup_adapter_queues(sc); 4232 if (rc != 0) 4233 goto done; 4234 4235 for (i = 0; i < nitems(sc->tq); i++) { 4236 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT, 4237 taskqueue_thread_enqueue, &sc->tq[i]); 4238 if (sc->tq[i] == NULL) { 4239 device_printf(sc->dev, 4240 "failed to allocate task queue %d\n", i); 4241 rc = ENOMEM; 4242 goto done; 4243 } 4244 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d", 4245 device_get_nameunit(sc->dev), i); 4246 } 4247 4248 if (!(sc->flags & IS_VF)) 4249 t4_intr_enable(sc); 4250 sc->flags |= FULL_INIT_DONE; 4251done: 4252 if (rc != 0) 4253 adapter_full_uninit(sc); 4254 4255 return (rc); 4256} 4257 4258int 4259adapter_full_uninit(struct adapter *sc) 4260{ 4261 int i; 4262 4263 ADAPTER_LOCK_ASSERT_NOTOWNED(sc); 4264 4265 t4_teardown_adapter_queues(sc); 4266 4267 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) { 4268 taskqueue_free(sc->tq[i]); 4269 sc->tq[i] = NULL; 4270 } 4271 4272 sc->flags &= ~FULL_INIT_DONE; 4273 4274 return (0); 4275} 4276 4277#ifdef RSS 4278#define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \ 4279 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \ 4280 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \ 4281 RSS_HASHTYPE_RSS_UDP_IPV6) 4282 4283/* Translates kernel hash types to hardware. */ 4284static int 4285hashconfig_to_hashen(int hashconfig) 4286{ 4287 int hashen = 0; 4288 4289 if (hashconfig & RSS_HASHTYPE_RSS_IPV4) 4290 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN; 4291 if (hashconfig & RSS_HASHTYPE_RSS_IPV6) 4292 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN; 4293 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) { 4294 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4295 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4296 } 4297 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) { 4298 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN | 4299 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4300 } 4301 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4) 4302 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN; 4303 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6) 4304 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN; 4305 4306 return (hashen); 4307} 4308 4309/* Translates hardware hash types to kernel. */ 4310static int 4311hashen_to_hashconfig(int hashen) 4312{ 4313 int hashconfig = 0; 4314 4315 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) { 4316 /* 4317 * If UDP hashing was enabled it must have been enabled for 4318 * either IPv4 or IPv6 (inclusive or). Enabling UDP without 4319 * enabling any 4-tuple hash is nonsense configuration. 4320 */ 4321 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4322 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)); 4323 4324 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4325 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4; 4326 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4327 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6; 4328 } 4329 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 4330 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4; 4331 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 4332 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6; 4333 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 4334 hashconfig |= RSS_HASHTYPE_RSS_IPV4; 4335 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 4336 hashconfig |= RSS_HASHTYPE_RSS_IPV6; 4337 4338 return (hashconfig); 4339} 4340#endif 4341 4342int 4343vi_full_init(struct vi_info *vi) 4344{ 4345 struct adapter *sc = vi->pi->adapter; 4346 struct ifnet *ifp = vi->ifp; 4347 uint16_t *rss; 4348 struct sge_rxq *rxq; 4349 int rc, i, j, hashen; 4350#ifdef RSS 4351 int nbuckets = rss_getnumbuckets(); 4352 int hashconfig = rss_gethashconfig(); 4353 int extra; 4354 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4355 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)]; 4356#endif 4357 4358 ASSERT_SYNCHRONIZED_OP(sc); 4359 KASSERT((vi->flags & VI_INIT_DONE) == 0, 4360 ("%s: VI_INIT_DONE already", __func__)); 4361 4362 sysctl_ctx_init(&vi->ctx); 4363 vi->flags |= VI_SYSCTL_CTX; 4364 4365 /* 4366 * Allocate tx/rx/fl queues for this VI. 4367 */ 4368 rc = t4_setup_vi_queues(vi); 4369 if (rc != 0) 4370 goto done; /* error message displayed already */ 4371 4372 /* 4373 * Setup RSS for this VI. Save a copy of the RSS table for later use. 4374 */ 4375 if (vi->nrxq > vi->rss_size) { 4376 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); " 4377 "some queues will never receive traffic.\n", vi->nrxq, 4378 vi->rss_size); 4379 } else if (vi->rss_size % vi->nrxq) { 4380 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); " 4381 "expect uneven traffic distribution.\n", vi->nrxq, 4382 vi->rss_size); 4383 } 4384#ifdef RSS 4385 MPASS(RSS_KEYSIZE == 40); 4386 if (vi->nrxq != nbuckets) { 4387 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);" 4388 "performance will be impacted.\n", vi->nrxq, nbuckets); 4389 } 4390 4391 rss_getkey((void *)&raw_rss_key[0]); 4392 for (i = 0; i < nitems(rss_key); i++) { 4393 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]); 4394 } 4395 t4_write_rss_key(sc, &rss_key[0], -1); 4396#endif 4397 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK); 4398 for (i = 0; i < vi->rss_size;) { 4399#ifdef RSS 4400 j = rss_get_indirection_to_bucket(i); 4401 j %= vi->nrxq; 4402 rxq = &sc->sge.rxq[vi->first_rxq + j]; 4403 rss[i++] = rxq->iq.abs_id; 4404#else 4405 for_each_rxq(vi, j, rxq) { 4406 rss[i++] = rxq->iq.abs_id; 4407 if (i == vi->rss_size) 4408 break; 4409 } 4410#endif 4411 } 4412 4413 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss, 4414 vi->rss_size); 4415 if (rc != 0) { 4416 if_printf(ifp, "rss_config failed: %d\n", rc); 4417 goto done; 4418 } 4419 4420#ifdef RSS 4421 hashen = hashconfig_to_hashen(hashconfig); 4422 4423 /* 4424 * We may have had to enable some hashes even though the global config 4425 * wants them disabled. This is a potential problem that must be 4426 * reported to the user. 4427 */ 4428 extra = hashen_to_hashconfig(hashen) ^ hashconfig; 4429 4430 /* 4431 * If we consider only the supported hash types, then the enabled hashes 4432 * are a superset of the requested hashes. In other words, there cannot 4433 * be any supported hash that was requested but not enabled, but there 4434 * can be hashes that were not requested but had to be enabled. 4435 */ 4436 extra &= SUPPORTED_RSS_HASHTYPES; 4437 MPASS((extra & hashconfig) == 0); 4438 4439 if (extra) { 4440 if_printf(ifp, 4441 "global RSS config (0x%x) cannot be accommodated.\n", 4442 hashconfig); 4443 } 4444 if (extra & RSS_HASHTYPE_RSS_IPV4) 4445 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n"); 4446 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4) 4447 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n"); 4448 if (extra & RSS_HASHTYPE_RSS_IPV6) 4449 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n"); 4450 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6) 4451 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n"); 4452 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4) 4453 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n"); 4454 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6) 4455 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n"); 4456#else 4457 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 4458 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 4459 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 4460 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN; 4461#endif 4462 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0); 4463 if (rc != 0) { 4464 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc); 4465 goto done; 4466 } 4467 4468 vi->rss = rss; 4469 vi->flags |= VI_INIT_DONE; 4470done: 4471 if (rc != 0) 4472 vi_full_uninit(vi); 4473 4474 return (rc); 4475} 4476 4477/* 4478 * Idempotent. 4479 */ 4480int 4481vi_full_uninit(struct vi_info *vi) 4482{ 4483 struct port_info *pi = vi->pi; 4484 struct adapter *sc = pi->adapter; 4485 int i; 4486 struct sge_rxq *rxq; 4487 struct sge_txq *txq; 4488#ifdef TCP_OFFLOAD 4489 struct sge_ofld_rxq *ofld_rxq; 4490 struct sge_wrq *ofld_txq; 4491#endif 4492 4493 if (vi->flags & VI_INIT_DONE) { 4494 4495 /* Need to quiesce queues. */ 4496 4497 /* XXX: Only for the first VI? */ 4498 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF)) 4499 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]); 4500 4501 for_each_txq(vi, i, txq) { 4502 quiesce_txq(sc, txq); 4503 } 4504 4505#ifdef TCP_OFFLOAD 4506 for_each_ofld_txq(vi, i, ofld_txq) { 4507 quiesce_wrq(sc, ofld_txq); 4508 } 4509#endif 4510 4511 for_each_rxq(vi, i, rxq) { 4512 quiesce_iq(sc, &rxq->iq); 4513 quiesce_fl(sc, &rxq->fl); 4514 } 4515 4516#ifdef TCP_OFFLOAD 4517 for_each_ofld_rxq(vi, i, ofld_rxq) { 4518 quiesce_iq(sc, &ofld_rxq->iq); 4519 quiesce_fl(sc, &ofld_rxq->fl); 4520 } 4521#endif 4522 free(vi->rss, M_CXGBE); 4523 free(vi->nm_rss, M_CXGBE); 4524 } 4525 4526 t4_teardown_vi_queues(vi); 4527 vi->flags &= ~VI_INIT_DONE; 4528 4529 return (0); 4530} 4531 4532static void 4533quiesce_txq(struct adapter *sc, struct sge_txq *txq) 4534{ 4535 struct sge_eq *eq = &txq->eq; 4536 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx]; 4537 4538 (void) sc; /* unused */ 4539 4540#ifdef INVARIANTS 4541 TXQ_LOCK(txq); 4542 MPASS((eq->flags & EQ_ENABLED) == 0); 4543 TXQ_UNLOCK(txq); 4544#endif 4545 4546 /* Wait for the mp_ring to empty. */ 4547 while (!mp_ring_is_idle(txq->r)) { 4548 mp_ring_check_drainage(txq->r, 0); 4549 pause("rquiesce", 1); 4550 } 4551 4552 /* Then wait for the hardware to finish. */ 4553 while (spg->cidx != htobe16(eq->pidx)) 4554 pause("equiesce", 1); 4555 4556 /* Finally, wait for the driver to reclaim all descriptors. */ 4557 while (eq->cidx != eq->pidx) 4558 pause("dquiesce", 1); 4559} 4560 4561static void 4562quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq) 4563{ 4564 4565 /* XXXTX */ 4566} 4567 4568static void 4569quiesce_iq(struct adapter *sc, struct sge_iq *iq) 4570{ 4571 (void) sc; /* unused */ 4572 4573 /* Synchronize with the interrupt handler */ 4574 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED)) 4575 pause("iqfree", 1); 4576} 4577 4578static void 4579quiesce_fl(struct adapter *sc, struct sge_fl *fl) 4580{ 4581 mtx_lock(&sc->sfl_lock); 4582 FL_LOCK(fl); 4583 fl->flags |= FL_DOOMED; 4584 FL_UNLOCK(fl); 4585 callout_stop(&sc->sfl_callout); 4586 mtx_unlock(&sc->sfl_lock); 4587 4588 KASSERT((fl->flags & FL_STARVING) == 0, 4589 ("%s: still starving", __func__)); 4590} 4591 4592static int 4593t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid, 4594 driver_intr_t *handler, void *arg, char *name) 4595{ 4596 int rc; 4597 4598 irq->rid = rid; 4599 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid, 4600 RF_SHAREABLE | RF_ACTIVE); 4601 if (irq->res == NULL) { 4602 device_printf(sc->dev, 4603 "failed to allocate IRQ for rid %d, name %s.\n", rid, name); 4604 return (ENOMEM); 4605 } 4606 4607 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET, 4608 NULL, handler, arg, &irq->tag); 4609 if (rc != 0) { 4610 device_printf(sc->dev, 4611 "failed to setup interrupt for rid %d, name %s: %d\n", 4612 rid, name, rc); 4613 } else if (name) 4614 bus_describe_intr(sc->dev, irq->res, irq->tag, "%s", name); 4615 4616 return (rc); 4617} 4618 4619static int 4620t4_free_irq(struct adapter *sc, struct irq *irq) 4621{ 4622 if (irq->tag) 4623 bus_teardown_intr(sc->dev, irq->res, irq->tag); 4624 if (irq->res) 4625 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res); 4626 4627 bzero(irq, sizeof(*irq)); 4628 4629 return (0); 4630} 4631 4632static void 4633get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 4634{ 4635 4636 regs->version = chip_id(sc) | chip_rev(sc) << 10; 4637 t4_get_regs(sc, buf, regs->len); 4638} 4639 4640#define A_PL_INDIR_CMD 0x1f8 4641 4642#define S_PL_AUTOINC 31 4643#define M_PL_AUTOINC 0x1U 4644#define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC) 4645#define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC) 4646 4647#define S_PL_VFID 20 4648#define M_PL_VFID 0xffU 4649#define V_PL_VFID(x) ((x) << S_PL_VFID) 4650#define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID) 4651 4652#define S_PL_ADDR 0 4653#define M_PL_ADDR 0xfffffU 4654#define V_PL_ADDR(x) ((x) << S_PL_ADDR) 4655#define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR) 4656 4657#define A_PL_INDIR_DATA 0x1fc 4658 4659static uint64_t 4660read_vf_stat(struct adapter *sc, unsigned int viid, int reg) 4661{ 4662 u32 stats[2]; 4663 4664 mtx_assert(&sc->reg_lock, MA_OWNED); 4665 if (sc->flags & IS_VF) { 4666 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg)); 4667 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4)); 4668 } else { 4669 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 4670 V_PL_VFID(G_FW_VIID_VIN(viid)) | 4671 V_PL_ADDR(VF_MPS_REG(reg))); 4672 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA); 4673 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA); 4674 } 4675 return (((uint64_t)stats[1]) << 32 | stats[0]); 4676} 4677 4678static void 4679t4_get_vi_stats(struct adapter *sc, unsigned int viid, 4680 struct fw_vi_stats_vf *stats) 4681{ 4682 4683#define GET_STAT(name) \ 4684 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L) 4685 4686 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES); 4687 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES); 4688 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES); 4689 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES); 4690 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES); 4691 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES); 4692 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES); 4693 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES); 4694 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES); 4695 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES); 4696 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES); 4697 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES); 4698 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES); 4699 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES); 4700 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES); 4701 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES); 4702 4703#undef GET_STAT 4704} 4705 4706static void 4707t4_clr_vi_stats(struct adapter *sc, unsigned int viid) 4708{ 4709 int reg; 4710 4711 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) | 4712 V_PL_VFID(G_FW_VIID_VIN(viid)) | 4713 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L))); 4714 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 4715 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 4716 t4_write_reg(sc, A_PL_INDIR_DATA, 0); 4717} 4718 4719static void 4720vi_refresh_stats(struct adapter *sc, struct vi_info *vi) 4721{ 4722 struct timeval tv; 4723 const struct timeval interval = {0, 250000}; /* 250ms */ 4724 4725 if (!(vi->flags & VI_INIT_DONE)) 4726 return; 4727 4728 getmicrotime(&tv); 4729 timevalsub(&tv, &interval); 4730 if (timevalcmp(&tv, &vi->last_refreshed, <)) 4731 return; 4732 4733 mtx_lock(&sc->reg_lock); 4734 t4_get_vi_stats(sc, vi->viid, &vi->stats); 4735 getmicrotime(&vi->last_refreshed); 4736 mtx_unlock(&sc->reg_lock); 4737} 4738 4739static void 4740cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi) 4741{ 4742 int i; 4743 u_int v, tnl_cong_drops; 4744 struct timeval tv; 4745 const struct timeval interval = {0, 250000}; /* 250ms */ 4746 4747 getmicrotime(&tv); 4748 timevalsub(&tv, &interval); 4749 if (timevalcmp(&tv, &pi->last_refreshed, <)) 4750 return; 4751 4752 tnl_cong_drops = 0; 4753 t4_get_port_stats(sc, pi->tx_chan, &pi->stats); 4754 for (i = 0; i < sc->chip_params->nchan; i++) { 4755 if (pi->rx_chan_map & (1 << i)) { 4756 mtx_lock(&sc->reg_lock); 4757 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v, 4758 1, A_TP_MIB_TNL_CNG_DROP_0 + i); 4759 mtx_unlock(&sc->reg_lock); 4760 tnl_cong_drops += v; 4761 } 4762 } 4763 pi->tnl_cong_drops = tnl_cong_drops; 4764 getmicrotime(&pi->last_refreshed); 4765} 4766 4767static void 4768cxgbe_tick(void *arg) 4769{ 4770 struct port_info *pi = arg; 4771 struct adapter *sc = pi->adapter; 4772 4773 PORT_LOCK_ASSERT_OWNED(pi); 4774 cxgbe_refresh_stats(sc, pi); 4775 4776 callout_schedule(&pi->tick, hz); 4777} 4778 4779void 4780vi_tick(void *arg) 4781{ 4782 struct vi_info *vi = arg; 4783 struct adapter *sc = vi->pi->adapter; 4784 4785 vi_refresh_stats(sc, vi); 4786 4787 callout_schedule(&vi->tick, hz); 4788} 4789 4790static void 4791cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid) 4792{ 4793 struct ifnet *vlan; 4794 4795 if (arg != ifp || ifp->if_type != IFT_ETHER) 4796 return; 4797 4798 vlan = VLAN_DEVAT(ifp, vid); 4799 VLAN_SETCOOKIE(vlan, ifp); 4800} 4801 4802/* 4803 * Should match fw_caps_config_<foo> enums in t4fw_interface.h 4804 */ 4805static char *caps_decoder[] = { 4806 "\20\001IPMI\002NCSI", /* 0: NBM */ 4807 "\20\001PPP\002QFC\003DCBX", /* 1: link */ 4808 "\20\001INGRESS\002EGRESS", /* 2: switch */ 4809 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */ 4810 "\006HASHFILTER\007ETHOFLD", 4811 "\20\001TOE", /* 4: TOE */ 4812 "\20\001RDDP\002RDMAC", /* 5: RDMA */ 4813 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */ 4814 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD" 4815 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD" 4816 "\007T10DIF" 4817 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD", 4818 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */ 4819 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */ 4820 "\004PO_INITIATOR\005PO_TARGET", 4821}; 4822 4823void 4824t4_sysctls(struct adapter *sc) 4825{ 4826 struct sysctl_ctx_list *ctx; 4827 struct sysctl_oid *oid; 4828 struct sysctl_oid_list *children, *c0; 4829 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"}; 4830 4831 ctx = device_get_sysctl_ctx(sc->dev); 4832 4833 /* 4834 * dev.t4nex.X. 4835 */ 4836 oid = device_get_sysctl_tree(sc->dev); 4837 c0 = children = SYSCTL_CHILDREN(oid); 4838 4839 sc->sc_do_rxcopy = 1; 4840 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW, 4841 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames"); 4842 4843 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL, 4844 sc->params.nports, "# of ports"); 4845 4846 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells", 4847 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells, 4848 sysctl_bitfield, "A", "available doorbells"); 4849 4850 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL, 4851 sc->params.vpd.cclk, "core clock frequency (in KHz)"); 4852 4853 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers", 4854 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val, 4855 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A", 4856 "interrupt holdoff timer values (us)"); 4857 4858 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts", 4859 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val, 4860 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A", 4861 "interrupt holdoff packet counter values"); 4862 4863 t4_sge_sysctls(sc, ctx, children); 4864 4865 sc->lro_timeout = 100; 4866 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW, 4867 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)"); 4868 4869 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW, 4870 &sc->debug_flags, 0, "flags to enable runtime debugging"); 4871 4872 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version", 4873 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version"); 4874 4875 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version", 4876 CTLFLAG_RD, sc->fw_version, 0, "firmware version"); 4877 4878 if (sc->flags & IS_VF) 4879 return; 4880 4881 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD, 4882 NULL, chip_rev(sc), "chip hardware revision"); 4883 4884 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn", 4885 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number"); 4886 4887 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn", 4888 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number"); 4889 4890 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec", 4891 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change"); 4892 4893 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na", 4894 CTLFLAG_RD, sc->params.vpd.na, 0, "network address"); 4895 4896 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD, 4897 sc->er_version, 0, "expansion ROM version"); 4898 4899 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD, 4900 sc->bs_version, 0, "bootstrap firmware version"); 4901 4902 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD, 4903 NULL, sc->params.scfg_vers, "serial config version"); 4904 4905 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD, 4906 NULL, sc->params.vpd_vers, "VPD version"); 4907 4908 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf", 4909 CTLFLAG_RD, sc->cfg_file, 0, "configuration file"); 4910 4911 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL, 4912 sc->cfcsum, "config file checksum"); 4913 4914#define SYSCTL_CAP(name, n, text) \ 4915 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \ 4916 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \ 4917 sysctl_bitfield, "A", "available " text " capabilities") 4918 4919 SYSCTL_CAP(nbmcaps, 0, "NBM"); 4920 SYSCTL_CAP(linkcaps, 1, "link"); 4921 SYSCTL_CAP(switchcaps, 2, "switch"); 4922 SYSCTL_CAP(niccaps, 3, "NIC"); 4923 SYSCTL_CAP(toecaps, 4, "TCP offload"); 4924 SYSCTL_CAP(rdmacaps, 5, "RDMA"); 4925 SYSCTL_CAP(iscsicaps, 6, "iSCSI"); 4926 SYSCTL_CAP(cryptocaps, 7, "crypto"); 4927 SYSCTL_CAP(fcoecaps, 8, "FCoE"); 4928#undef SYSCTL_CAP 4929 4930 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, 4931 NULL, sc->tids.nftids, "number of filters"); 4932 4933 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | 4934 CTLFLAG_RD, sc, 0, sysctl_temperature, "I", 4935 "chip temperature (in Celsius)"); 4936 4937#ifdef SBUF_DRAIN 4938 /* 4939 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload. 4940 */ 4941 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc", 4942 CTLFLAG_RD | CTLFLAG_SKIP, NULL, 4943 "logs and miscellaneous information"); 4944 children = SYSCTL_CHILDREN(oid); 4945 4946 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl", 4947 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4948 sysctl_cctrl, "A", "congestion control"); 4949 4950 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0", 4951 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4952 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)"); 4953 4954 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1", 4955 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, 4956 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)"); 4957 4958 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp", 4959 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, 4960 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)"); 4961 4962 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0", 4963 CTLTYPE_STRING | CTLFLAG_RD, sc, 3, 4964 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)"); 4965 4966 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1", 4967 CTLTYPE_STRING | CTLFLAG_RD, sc, 4, 4968 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)"); 4969 4970 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi", 4971 CTLTYPE_STRING | CTLFLAG_RD, sc, 5, 4972 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)"); 4973 4974 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la", 4975 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4976 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6, 4977 "A", "CIM logic analyzer"); 4978 4979 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la", 4980 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 4981 sysctl_cim_ma_la, "A", "CIM MA logic analyzer"); 4982 4983 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0", 4984 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ, 4985 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)"); 4986 4987 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1", 4988 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ, 4989 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)"); 4990 4991 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2", 4992 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ, 4993 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)"); 4994 4995 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3", 4996 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ, 4997 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)"); 4998 4999 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge", 5000 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ, 5001 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)"); 5002 5003 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi", 5004 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ, 5005 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)"); 5006 5007 if (chip_id(sc) > CHELSIO_T4) { 5008 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx", 5009 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ, 5010 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)"); 5011 5012 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx", 5013 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ, 5014 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)"); 5015 } 5016 5017 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la", 5018 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5019 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer"); 5020 5021 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg", 5022 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5023 sysctl_cim_qcfg, "A", "CIM queue configuration"); 5024 5025 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats", 5026 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5027 sysctl_cpl_stats, "A", "CPL statistics"); 5028 5029 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats", 5030 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5031 sysctl_ddp_stats, "A", "non-TCP DDP statistics"); 5032 5033 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog", 5034 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5035 sysctl_devlog, "A", "firmware's device log"); 5036 5037 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats", 5038 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5039 sysctl_fcoe_stats, "A", "FCoE statistics"); 5040 5041 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched", 5042 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5043 sysctl_hw_sched, "A", "hardware scheduler "); 5044 5045 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t", 5046 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5047 sysctl_l2t, "A", "hardware L2 table"); 5048 5049 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats", 5050 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5051 sysctl_lb_stats, "A", "loopback statistics"); 5052 5053 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo", 5054 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5055 sysctl_meminfo, "A", "memory regions"); 5056 5057 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam", 5058 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5059 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6, 5060 "A", "MPS TCAM entries"); 5061 5062 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus", 5063 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5064 sysctl_path_mtus, "A", "path MTUs"); 5065 5066 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats", 5067 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5068 sysctl_pm_stats, "A", "PM statistics"); 5069 5070 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats", 5071 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5072 sysctl_rdma_stats, "A", "RDMA statistics"); 5073 5074 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats", 5075 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5076 sysctl_tcp_stats, "A", "TCP statistics"); 5077 5078 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids", 5079 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5080 sysctl_tids, "A", "TID information"); 5081 5082 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats", 5083 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5084 sysctl_tp_err_stats, "A", "TP error statistics"); 5085 5086 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask", 5087 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I", 5088 "TP logic analyzer event capture mask"); 5089 5090 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la", 5091 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5092 sysctl_tp_la, "A", "TP logic analyzer"); 5093 5094 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate", 5095 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5096 sysctl_tx_rate, "A", "Tx rate"); 5097 5098 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la", 5099 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5100 sysctl_ulprx_la, "A", "ULPRX logic analyzer"); 5101 5102 if (chip_id(sc) >= CHELSIO_T5) { 5103 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats", 5104 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, 5105 sysctl_wcwr_stats, "A", "write combined work requests"); 5106 } 5107#endif 5108 5109#ifdef TCP_OFFLOAD 5110 if (is_offload(sc)) { 5111 /* 5112 * dev.t4nex.X.toe. 5113 */ 5114 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD, 5115 NULL, "TOE parameters"); 5116 children = SYSCTL_CHILDREN(oid); 5117 5118 sc->tt.sndbuf = 256 * 1024; 5119 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW, 5120 &sc->tt.sndbuf, 0, "max hardware send buffer size"); 5121 5122 sc->tt.ddp = 0; 5123 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW, 5124 &sc->tt.ddp, 0, "DDP allowed"); 5125 5126 sc->tt.rx_coalesce = 1; 5127 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce", 5128 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing"); 5129 5130 sc->tt.tx_align = 1; 5131 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align", 5132 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload"); 5133 5134 sc->tt.tx_zcopy = 0; 5135 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_zcopy", 5136 CTLFLAG_RW, &sc->tt.tx_zcopy, 0, 5137 "Enable zero-copy aio_write(2)"); 5138 5139 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick", 5140 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A", 5141 "TP timer tick (us)"); 5142 5143 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick", 5144 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A", 5145 "TCP timestamp tick (us)"); 5146 5147 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick", 5148 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A", 5149 "DACK tick (us)"); 5150 5151 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer", 5152 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer, 5153 "IU", "DACK timer (us)"); 5154 5155 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min", 5156 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN, 5157 sysctl_tp_timer, "LU", "Retransmit min (us)"); 5158 5159 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max", 5160 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX, 5161 sysctl_tp_timer, "LU", "Retransmit max (us)"); 5162 5163 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min", 5164 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN, 5165 sysctl_tp_timer, "LU", "Persist timer min (us)"); 5166 5167 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max", 5168 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX, 5169 sysctl_tp_timer, "LU", "Persist timer max (us)"); 5170 5171 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle", 5172 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE, 5173 sysctl_tp_timer, "LU", "Keepidle idle timer (us)"); 5174 5175 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_intvl", 5176 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL, 5177 sysctl_tp_timer, "LU", "Keepidle interval (us)"); 5178 5179 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt", 5180 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT, 5181 sysctl_tp_timer, "LU", "Initial SRTT (us)"); 5182 5183 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer", 5184 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER, 5185 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)"); 5186 } 5187#endif 5188} 5189 5190void 5191vi_sysctls(struct vi_info *vi) 5192{ 5193 struct sysctl_ctx_list *ctx; 5194 struct sysctl_oid *oid; 5195 struct sysctl_oid_list *children; 5196 5197 ctx = device_get_sysctl_ctx(vi->dev); 5198 5199 /* 5200 * dev.v?(cxgbe|cxl).X. 5201 */ 5202 oid = device_get_sysctl_tree(vi->dev); 5203 children = SYSCTL_CHILDREN(oid); 5204 5205 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL, 5206 vi->viid, "VI identifer"); 5207 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD, 5208 &vi->nrxq, 0, "# of rx queues"); 5209 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD, 5210 &vi->ntxq, 0, "# of tx queues"); 5211 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD, 5212 &vi->first_rxq, 0, "index of first rx queue"); 5213 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD, 5214 &vi->first_txq, 0, "index of first tx queue"); 5215 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL, 5216 vi->rss_size, "size of RSS indirection table"); 5217 5218 if (IS_MAIN_VI(vi)) { 5219 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", 5220 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU", 5221 "Reserve queue 0 for non-flowid packets"); 5222 } 5223 5224#ifdef TCP_OFFLOAD 5225 if (vi->nofldrxq != 0) { 5226 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD, 5227 &vi->nofldrxq, 0, 5228 "# of rx queues for offloaded TCP connections"); 5229 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD, 5230 &vi->nofldtxq, 0, 5231 "# of tx queues for offloaded TCP connections"); 5232 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq", 5233 CTLFLAG_RD, &vi->first_ofld_rxq, 0, 5234 "index of first TOE rx queue"); 5235 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq", 5236 CTLFLAG_RD, &vi->first_ofld_txq, 0, 5237 "index of first TOE tx queue"); 5238 } 5239#endif 5240#ifdef DEV_NETMAP 5241 if (vi->nnmrxq != 0) { 5242 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD, 5243 &vi->nnmrxq, 0, "# of netmap rx queues"); 5244 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD, 5245 &vi->nnmtxq, 0, "# of netmap tx queues"); 5246 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq", 5247 CTLFLAG_RD, &vi->first_nm_rxq, 0, 5248 "index of first netmap rx queue"); 5249 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq", 5250 CTLFLAG_RD, &vi->first_nm_txq, 0, 5251 "index of first netmap tx queue"); 5252 } 5253#endif 5254 5255 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx", 5256 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I", 5257 "holdoff timer index"); 5258 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx", 5259 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I", 5260 "holdoff packet counter index"); 5261 5262 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq", 5263 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I", 5264 "rx queue size"); 5265 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq", 5266 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I", 5267 "tx queue size"); 5268} 5269 5270static void 5271cxgbe_sysctls(struct port_info *pi) 5272{ 5273 struct sysctl_ctx_list *ctx; 5274 struct sysctl_oid *oid; 5275 struct sysctl_oid_list *children, *children2; 5276 struct adapter *sc = pi->adapter; 5277 int i; 5278 char name[16]; 5279 5280 ctx = device_get_sysctl_ctx(pi->dev); 5281 5282 /* 5283 * dev.cxgbe.X. 5284 */ 5285 oid = device_get_sysctl_tree(pi->dev); 5286 children = SYSCTL_CHILDREN(oid); 5287 5288 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING | 5289 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down"); 5290 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) { 5291 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", 5292 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I", 5293 "PHY temperature (in Celsius)"); 5294 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version", 5295 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I", 5296 "PHY firmware version"); 5297 } 5298 5299 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings", 5300 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A", 5301 "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)"); 5302 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec", 5303 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A", 5304 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)"); 5305 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg", 5306 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I", 5307 "autonegotiation (-1 = not supported)"); 5308 5309 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL, 5310 port_top_speed(pi), "max speed (in Gbps)"); 5311 5312 if (sc->flags & IS_VF) 5313 return; 5314 5315 /* 5316 * dev.(cxgbe|cxl).X.tc. 5317 */ 5318 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL, 5319 "Tx scheduler traffic classes"); 5320 for (i = 0; i < sc->chip_params->nsched_cls; i++) { 5321 struct tx_sched_class *tc = &pi->tc[i]; 5322 5323 snprintf(name, sizeof(name), "%d", i); 5324 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx, 5325 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL, 5326 "traffic class")); 5327 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD, 5328 &tc->flags, 0, "flags"); 5329 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount", 5330 CTLFLAG_RD, &tc->refcount, 0, "references to this class"); 5331#ifdef SBUF_DRAIN 5332 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params", 5333 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i, 5334 sysctl_tc_params, "A", "traffic class parameters"); 5335#endif 5336 } 5337 5338 /* 5339 * dev.cxgbe.X.stats. 5340 */ 5341 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 5342 NULL, "port statistics"); 5343 children = SYSCTL_CHILDREN(oid); 5344 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD, 5345 &pi->tx_parse_error, 0, 5346 "# of tx packets with invalid length or # of segments"); 5347 5348#define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \ 5349 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \ 5350 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \ 5351 sysctl_handle_t4_reg64, "QU", desc) 5352 5353 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames", 5354 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L)); 5355 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames", 5356 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L)); 5357 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames", 5358 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L)); 5359 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames", 5360 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L)); 5361 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames", 5362 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L)); 5363 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames", 5364 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L)); 5365 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64", 5366 "# of tx frames in this range", 5367 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L)); 5368 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127", 5369 "# of tx frames in this range", 5370 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L)); 5371 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255", 5372 "# of tx frames in this range", 5373 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L)); 5374 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511", 5375 "# of tx frames in this range", 5376 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L)); 5377 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023", 5378 "# of tx frames in this range", 5379 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L)); 5380 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518", 5381 "# of tx frames in this range", 5382 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L)); 5383 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max", 5384 "# of tx frames in this range", 5385 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L)); 5386 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames", 5387 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L)); 5388 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted", 5389 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L)); 5390 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted", 5391 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L)); 5392 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted", 5393 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L)); 5394 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted", 5395 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L)); 5396 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted", 5397 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L)); 5398 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted", 5399 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L)); 5400 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted", 5401 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L)); 5402 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted", 5403 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L)); 5404 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted", 5405 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L)); 5406 5407 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames", 5408 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L)); 5409 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames", 5410 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L)); 5411 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames", 5412 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L)); 5413 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames", 5414 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L)); 5415 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames", 5416 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L)); 5417 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU", 5418 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L)); 5419 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames", 5420 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L)); 5421 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err", 5422 "# of frames received with bad FCS", 5423 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L)); 5424 SYSCTL_ADD_T4_REG64(pi, "rx_len_err", 5425 "# of frames received with length error", 5426 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L)); 5427 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors", 5428 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L)); 5429 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received", 5430 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L)); 5431 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64", 5432 "# of rx frames in this range", 5433 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L)); 5434 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127", 5435 "# of rx frames in this range", 5436 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L)); 5437 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255", 5438 "# of rx frames in this range", 5439 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L)); 5440 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511", 5441 "# of rx frames in this range", 5442 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L)); 5443 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023", 5444 "# of rx frames in this range", 5445 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L)); 5446 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518", 5447 "# of rx frames in this range", 5448 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L)); 5449 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max", 5450 "# of rx frames in this range", 5451 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L)); 5452 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received", 5453 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L)); 5454 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received", 5455 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L)); 5456 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received", 5457 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L)); 5458 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received", 5459 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L)); 5460 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received", 5461 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L)); 5462 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received", 5463 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L)); 5464 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received", 5465 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L)); 5466 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received", 5467 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L)); 5468 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received", 5469 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L)); 5470 5471#undef SYSCTL_ADD_T4_REG64 5472 5473#define SYSCTL_ADD_T4_PORTSTAT(name, desc) \ 5474 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \ 5475 &pi->stats.name, desc) 5476 5477 /* We get these from port_stats and they may be stale by up to 1s */ 5478 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0, 5479 "# drops due to buffer-group 0 overflows"); 5480 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1, 5481 "# drops due to buffer-group 1 overflows"); 5482 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2, 5483 "# drops due to buffer-group 2 overflows"); 5484 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3, 5485 "# drops due to buffer-group 3 overflows"); 5486 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0, 5487 "# of buffer-group 0 truncated packets"); 5488 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1, 5489 "# of buffer-group 1 truncated packets"); 5490 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2, 5491 "# of buffer-group 2 truncated packets"); 5492 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3, 5493 "# of buffer-group 3 truncated packets"); 5494 5495#undef SYSCTL_ADD_T4_PORTSTAT 5496} 5497 5498static int 5499sysctl_int_array(SYSCTL_HANDLER_ARGS) 5500{ 5501 int rc, *i, space = 0; 5502 struct sbuf sb; 5503 5504 sbuf_new_for_sysctl(&sb, NULL, 64, req); 5505 for (i = arg1; arg2; arg2 -= sizeof(int), i++) { 5506 if (space) 5507 sbuf_printf(&sb, " "); 5508 sbuf_printf(&sb, "%d", *i); 5509 space = 1; 5510 } 5511 rc = sbuf_finish(&sb); 5512 sbuf_delete(&sb); 5513 return (rc); 5514} 5515 5516static int 5517sysctl_bitfield(SYSCTL_HANDLER_ARGS) 5518{ 5519 int rc; 5520 struct sbuf *sb; 5521 5522 rc = sysctl_wire_old_buffer(req, 0); 5523 if (rc != 0) 5524 return(rc); 5525 5526 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5527 if (sb == NULL) 5528 return (ENOMEM); 5529 5530 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1); 5531 rc = sbuf_finish(sb); 5532 sbuf_delete(sb); 5533 5534 return (rc); 5535} 5536 5537static int 5538sysctl_btphy(SYSCTL_HANDLER_ARGS) 5539{ 5540 struct port_info *pi = arg1; 5541 int op = arg2; 5542 struct adapter *sc = pi->adapter; 5543 u_int v; 5544 int rc; 5545 5546 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt"); 5547 if (rc) 5548 return (rc); 5549 /* XXX: magic numbers */ 5550 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820, 5551 &v); 5552 end_synchronized_op(sc, 0); 5553 if (rc) 5554 return (rc); 5555 if (op == 0) 5556 v /= 256; 5557 5558 rc = sysctl_handle_int(oidp, &v, 0, req); 5559 return (rc); 5560} 5561 5562static int 5563sysctl_noflowq(SYSCTL_HANDLER_ARGS) 5564{ 5565 struct vi_info *vi = arg1; 5566 int rc, val; 5567 5568 val = vi->rsrv_noflowq; 5569 rc = sysctl_handle_int(oidp, &val, 0, req); 5570 if (rc != 0 || req->newptr == NULL) 5571 return (rc); 5572 5573 if ((val >= 1) && (vi->ntxq > 1)) 5574 vi->rsrv_noflowq = 1; 5575 else 5576 vi->rsrv_noflowq = 0; 5577 5578 return (rc); 5579} 5580 5581static int 5582sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS) 5583{ 5584 struct vi_info *vi = arg1; 5585 struct adapter *sc = vi->pi->adapter; 5586 int idx, rc, i; 5587 struct sge_rxq *rxq; 5588#ifdef TCP_OFFLOAD 5589 struct sge_ofld_rxq *ofld_rxq; 5590#endif 5591 uint8_t v; 5592 5593 idx = vi->tmr_idx; 5594 5595 rc = sysctl_handle_int(oidp, &idx, 0, req); 5596 if (rc != 0 || req->newptr == NULL) 5597 return (rc); 5598 5599 if (idx < 0 || idx >= SGE_NTIMERS) 5600 return (EINVAL); 5601 5602 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5603 "t4tmr"); 5604 if (rc) 5605 return (rc); 5606 5607 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1); 5608 for_each_rxq(vi, i, rxq) { 5609#ifdef atomic_store_rel_8 5610 atomic_store_rel_8(&rxq->iq.intr_params, v); 5611#else 5612 rxq->iq.intr_params = v; 5613#endif 5614 } 5615#ifdef TCP_OFFLOAD 5616 for_each_ofld_rxq(vi, i, ofld_rxq) { 5617#ifdef atomic_store_rel_8 5618 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v); 5619#else 5620 ofld_rxq->iq.intr_params = v; 5621#endif 5622 } 5623#endif 5624 vi->tmr_idx = idx; 5625 5626 end_synchronized_op(sc, LOCK_HELD); 5627 return (0); 5628} 5629 5630static int 5631sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS) 5632{ 5633 struct vi_info *vi = arg1; 5634 struct adapter *sc = vi->pi->adapter; 5635 int idx, rc; 5636 5637 idx = vi->pktc_idx; 5638 5639 rc = sysctl_handle_int(oidp, &idx, 0, req); 5640 if (rc != 0 || req->newptr == NULL) 5641 return (rc); 5642 5643 if (idx < -1 || idx >= SGE_NCOUNTERS) 5644 return (EINVAL); 5645 5646 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5647 "t4pktc"); 5648 if (rc) 5649 return (rc); 5650 5651 if (vi->flags & VI_INIT_DONE) 5652 rc = EBUSY; /* cannot be changed once the queues are created */ 5653 else 5654 vi->pktc_idx = idx; 5655 5656 end_synchronized_op(sc, LOCK_HELD); 5657 return (rc); 5658} 5659 5660static int 5661sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS) 5662{ 5663 struct vi_info *vi = arg1; 5664 struct adapter *sc = vi->pi->adapter; 5665 int qsize, rc; 5666 5667 qsize = vi->qsize_rxq; 5668 5669 rc = sysctl_handle_int(oidp, &qsize, 0, req); 5670 if (rc != 0 || req->newptr == NULL) 5671 return (rc); 5672 5673 if (qsize < 128 || (qsize & 7)) 5674 return (EINVAL); 5675 5676 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5677 "t4rxqs"); 5678 if (rc) 5679 return (rc); 5680 5681 if (vi->flags & VI_INIT_DONE) 5682 rc = EBUSY; /* cannot be changed once the queues are created */ 5683 else 5684 vi->qsize_rxq = qsize; 5685 5686 end_synchronized_op(sc, LOCK_HELD); 5687 return (rc); 5688} 5689 5690static int 5691sysctl_qsize_txq(SYSCTL_HANDLER_ARGS) 5692{ 5693 struct vi_info *vi = arg1; 5694 struct adapter *sc = vi->pi->adapter; 5695 int qsize, rc; 5696 5697 qsize = vi->qsize_txq; 5698 5699 rc = sysctl_handle_int(oidp, &qsize, 0, req); 5700 if (rc != 0 || req->newptr == NULL) 5701 return (rc); 5702 5703 if (qsize < 128 || qsize > 65536) 5704 return (EINVAL); 5705 5706 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK, 5707 "t4txqs"); 5708 if (rc) 5709 return (rc); 5710 5711 if (vi->flags & VI_INIT_DONE) 5712 rc = EBUSY; /* cannot be changed once the queues are created */ 5713 else 5714 vi->qsize_txq = qsize; 5715 5716 end_synchronized_op(sc, LOCK_HELD); 5717 return (rc); 5718} 5719 5720static int 5721sysctl_pause_settings(SYSCTL_HANDLER_ARGS) 5722{ 5723 struct port_info *pi = arg1; 5724 struct adapter *sc = pi->adapter; 5725 struct link_config *lc = &pi->link_cfg; 5726 int rc; 5727 5728 if (req->newptr == NULL) { 5729 struct sbuf *sb; 5730 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX"; 5731 5732 rc = sysctl_wire_old_buffer(req, 0); 5733 if (rc != 0) 5734 return(rc); 5735 5736 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5737 if (sb == NULL) 5738 return (ENOMEM); 5739 5740 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits); 5741 rc = sbuf_finish(sb); 5742 sbuf_delete(sb); 5743 } else { 5744 char s[2]; 5745 int n; 5746 5747 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX)); 5748 s[1] = 0; 5749 5750 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 5751 if (rc != 0) 5752 return(rc); 5753 5754 if (s[1] != 0) 5755 return (EINVAL); 5756 if (s[0] < '0' || s[0] > '9') 5757 return (EINVAL); /* not a number */ 5758 n = s[0] - '0'; 5759 if (n & ~(PAUSE_TX | PAUSE_RX)) 5760 return (EINVAL); /* some other bit is set too */ 5761 5762 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 5763 "t4PAUSE"); 5764 if (rc) 5765 return (rc); 5766 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) { 5767 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX); 5768 lc->requested_fc |= n; 5769 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 5770 } 5771 end_synchronized_op(sc, 0); 5772 } 5773 5774 return (rc); 5775} 5776 5777static int 5778sysctl_fec(SYSCTL_HANDLER_ARGS) 5779{ 5780 struct port_info *pi = arg1; 5781 struct adapter *sc = pi->adapter; 5782 struct link_config *lc = &pi->link_cfg; 5783 int rc; 5784 5785 if (req->newptr == NULL) { 5786 struct sbuf *sb; 5787 static char *bits = "\20\1RS\2BASER_RS\3RESERVED"; 5788 5789 rc = sysctl_wire_old_buffer(req, 0); 5790 if (rc != 0) 5791 return(rc); 5792 5793 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req); 5794 if (sb == NULL) 5795 return (ENOMEM); 5796 5797 sbuf_printf(sb, "%b", lc->fec & M_FW_PORT_CAP_FEC, bits); 5798 rc = sbuf_finish(sb); 5799 sbuf_delete(sb); 5800 } else { 5801 char s[2]; 5802 int n; 5803 5804 s[0] = '0' + (lc->requested_fec & M_FW_PORT_CAP_FEC); 5805 s[1] = 0; 5806 5807 rc = sysctl_handle_string(oidp, s, sizeof(s), req); 5808 if (rc != 0) 5809 return(rc); 5810 5811 if (s[1] != 0) 5812 return (EINVAL); 5813 if (s[0] < '0' || s[0] > '9') 5814 return (EINVAL); /* not a number */ 5815 n = s[0] - '0'; 5816 if (n & ~M_FW_PORT_CAP_FEC) 5817 return (EINVAL); /* some other bit is set too */ 5818 5819 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 5820 "t4fec"); 5821 if (rc) 5822 return (rc); 5823 if ((lc->requested_fec & M_FW_PORT_CAP_FEC) != n) { 5824 lc->requested_fec = n & 5825 G_FW_PORT_CAP_FEC(lc->supported); 5826 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 5827 } 5828 end_synchronized_op(sc, 0); 5829 } 5830 5831 return (rc); 5832} 5833 5834static int 5835sysctl_autoneg(SYSCTL_HANDLER_ARGS) 5836{ 5837 struct port_info *pi = arg1; 5838 struct adapter *sc = pi->adapter; 5839 struct link_config *lc = &pi->link_cfg; 5840 int rc, val, old; 5841 5842 if (lc->supported & FW_PORT_CAP_ANEG) 5843 val = lc->autoneg == AUTONEG_ENABLE ? 1 : 0; 5844 else 5845 val = -1; 5846 rc = sysctl_handle_int(oidp, &val, 0, req); 5847 if (rc != 0 || req->newptr == NULL) 5848 return (rc); 5849 if ((lc->supported & FW_PORT_CAP_ANEG) == 0) 5850 return (ENOTSUP); 5851 5852 val = val ? AUTONEG_ENABLE : AUTONEG_DISABLE; 5853 if (lc->autoneg == val) 5854 return (0); /* no change */ 5855 5856 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, 5857 "t4aneg"); 5858 if (rc) 5859 return (rc); 5860 old = lc->autoneg; 5861 lc->autoneg = val; 5862 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc); 5863 if (rc != 0) 5864 lc->autoneg = old; 5865 return (rc); 5866} 5867 5868static int 5869sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS) 5870{ 5871 struct adapter *sc = arg1; 5872 int reg = arg2; 5873 uint64_t val; 5874 5875 val = t4_read_reg64(sc, reg); 5876 5877 return (sysctl_handle_64(oidp, &val, 0, req)); 5878} 5879 5880static int 5881sysctl_temperature(SYSCTL_HANDLER_ARGS) 5882{ 5883 struct adapter *sc = arg1; 5884 int rc, t; 5885 uint32_t param, val; 5886 5887 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp"); 5888 if (rc) 5889 return (rc); 5890 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 5891 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) | 5892 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP); 5893 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 5894 end_synchronized_op(sc, 0); 5895 if (rc) 5896 return (rc); 5897 5898 /* unknown is returned as 0 but we display -1 in that case */ 5899 t = val == 0 ? -1 : val; 5900 5901 rc = sysctl_handle_int(oidp, &t, 0, req); 5902 return (rc); 5903} 5904 5905#ifdef SBUF_DRAIN 5906static int 5907sysctl_cctrl(SYSCTL_HANDLER_ARGS) 5908{ 5909 struct adapter *sc = arg1; 5910 struct sbuf *sb; 5911 int rc, i; 5912 uint16_t incr[NMTUS][NCCTRL_WIN]; 5913 static const char *dec_fac[] = { 5914 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875", 5915 "0.9375" 5916 }; 5917 5918 rc = sysctl_wire_old_buffer(req, 0); 5919 if (rc != 0) 5920 return (rc); 5921 5922 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 5923 if (sb == NULL) 5924 return (ENOMEM); 5925 5926 t4_read_cong_tbl(sc, incr); 5927 5928 for (i = 0; i < NCCTRL_WIN; ++i) { 5929 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i, 5930 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i], 5931 incr[5][i], incr[6][i], incr[7][i]); 5932 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n", 5933 incr[8][i], incr[9][i], incr[10][i], incr[11][i], 5934 incr[12][i], incr[13][i], incr[14][i], incr[15][i], 5935 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]); 5936 } 5937 5938 rc = sbuf_finish(sb); 5939 sbuf_delete(sb); 5940 5941 return (rc); 5942} 5943 5944static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = { 5945 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */ 5946 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */ 5947 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */ 5948}; 5949 5950static int 5951sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS) 5952{ 5953 struct adapter *sc = arg1; 5954 struct sbuf *sb; 5955 int rc, i, n, qid = arg2; 5956 uint32_t *buf, *p; 5957 char *qtype; 5958 u_int cim_num_obq = sc->chip_params->cim_num_obq; 5959 5960 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq, 5961 ("%s: bad qid %d\n", __func__, qid)); 5962 5963 if (qid < CIM_NUM_IBQ) { 5964 /* inbound queue */ 5965 qtype = "IBQ"; 5966 n = 4 * CIM_IBQ_SIZE; 5967 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 5968 rc = t4_read_cim_ibq(sc, qid, buf, n); 5969 } else { 5970 /* outbound queue */ 5971 qtype = "OBQ"; 5972 qid -= CIM_NUM_IBQ; 5973 n = 4 * cim_num_obq * CIM_OBQ_SIZE; 5974 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK); 5975 rc = t4_read_cim_obq(sc, qid, buf, n); 5976 } 5977 5978 if (rc < 0) { 5979 rc = -rc; 5980 goto done; 5981 } 5982 n = rc * sizeof(uint32_t); /* rc has # of words actually read */ 5983 5984 rc = sysctl_wire_old_buffer(req, 0); 5985 if (rc != 0) 5986 goto done; 5987 5988 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 5989 if (sb == NULL) { 5990 rc = ENOMEM; 5991 goto done; 5992 } 5993 5994 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]); 5995 for (i = 0, p = buf; i < n; i += 16, p += 4) 5996 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1], 5997 p[2], p[3]); 5998 5999 rc = sbuf_finish(sb); 6000 sbuf_delete(sb); 6001done: 6002 free(buf, M_CXGBE); 6003 return (rc); 6004} 6005 6006static int 6007sysctl_cim_la(SYSCTL_HANDLER_ARGS) 6008{ 6009 struct adapter *sc = arg1; 6010 u_int cfg; 6011 struct sbuf *sb; 6012 uint32_t *buf, *p; 6013 int rc; 6014 6015 MPASS(chip_id(sc) <= CHELSIO_T5); 6016 6017 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 6018 if (rc != 0) 6019 return (rc); 6020 6021 rc = sysctl_wire_old_buffer(req, 0); 6022 if (rc != 0) 6023 return (rc); 6024 6025 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6026 if (sb == NULL) 6027 return (ENOMEM); 6028 6029 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 6030 M_ZERO | M_WAITOK); 6031 6032 rc = -t4_cim_read_la(sc, buf, NULL); 6033 if (rc != 0) 6034 goto done; 6035 6036 sbuf_printf(sb, "Status Data PC%s", 6037 cfg & F_UPDBGLACAPTPCONLY ? "" : 6038 " LS0Stat LS0Addr LS0Data"); 6039 6040 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) { 6041 if (cfg & F_UPDBGLACAPTPCONLY) { 6042 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff, 6043 p[6], p[7]); 6044 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x", 6045 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8, 6046 p[4] & 0xff, p[5] >> 8); 6047 sbuf_printf(sb, "\n %02x %x%07x %x%07x", 6048 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 6049 p[1] & 0xf, p[2] >> 4); 6050 } else { 6051 sbuf_printf(sb, 6052 "\n %02x %x%07x %x%07x %08x %08x " 6053 "%08x%08x%08x%08x", 6054 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4, 6055 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5], 6056 p[6], p[7]); 6057 } 6058 } 6059 6060 rc = sbuf_finish(sb); 6061 sbuf_delete(sb); 6062done: 6063 free(buf, M_CXGBE); 6064 return (rc); 6065} 6066 6067static int 6068sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS) 6069{ 6070 struct adapter *sc = arg1; 6071 u_int cfg; 6072 struct sbuf *sb; 6073 uint32_t *buf, *p; 6074 int rc; 6075 6076 MPASS(chip_id(sc) > CHELSIO_T5); 6077 6078 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg); 6079 if (rc != 0) 6080 return (rc); 6081 6082 rc = sysctl_wire_old_buffer(req, 0); 6083 if (rc != 0) 6084 return (rc); 6085 6086 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6087 if (sb == NULL) 6088 return (ENOMEM); 6089 6090 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE, 6091 M_ZERO | M_WAITOK); 6092 6093 rc = -t4_cim_read_la(sc, buf, NULL); 6094 if (rc != 0) 6095 goto done; 6096 6097 sbuf_printf(sb, "Status Inst Data PC%s", 6098 cfg & F_UPDBGLACAPTPCONLY ? "" : 6099 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data"); 6100 6101 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) { 6102 if (cfg & F_UPDBGLACAPTPCONLY) { 6103 sbuf_printf(sb, "\n %02x %08x %08x %08x", 6104 p[3] & 0xff, p[2], p[1], p[0]); 6105 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x", 6106 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8, 6107 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8); 6108 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x", 6109 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16, 6110 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff, 6111 p[6] >> 16); 6112 } else { 6113 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x " 6114 "%08x %08x %08x %08x %08x %08x", 6115 (p[9] >> 16) & 0xff, 6116 p[9] & 0xffff, p[8] >> 16, 6117 p[8] & 0xffff, p[7] >> 16, 6118 p[7] & 0xffff, p[6] >> 16, 6119 p[2], p[1], p[0], p[5], p[4], p[3]); 6120 } 6121 } 6122 6123 rc = sbuf_finish(sb); 6124 sbuf_delete(sb); 6125done: 6126 free(buf, M_CXGBE); 6127 return (rc); 6128} 6129 6130static int 6131sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS) 6132{ 6133 struct adapter *sc = arg1; 6134 u_int i; 6135 struct sbuf *sb; 6136 uint32_t *buf, *p; 6137 int rc; 6138 6139 rc = sysctl_wire_old_buffer(req, 0); 6140 if (rc != 0) 6141 return (rc); 6142 6143 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6144 if (sb == NULL) 6145 return (ENOMEM); 6146 6147 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE, 6148 M_ZERO | M_WAITOK); 6149 6150 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE); 6151 p = buf; 6152 6153 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6154 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2], 6155 p[1], p[0]); 6156 } 6157 6158 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD"); 6159 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) { 6160 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u", 6161 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7, 6162 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1, 6163 (p[1] >> 2) | ((p[2] & 3) << 30), 6164 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1, 6165 p[0] & 1); 6166 } 6167 6168 rc = sbuf_finish(sb); 6169 sbuf_delete(sb); 6170 free(buf, M_CXGBE); 6171 return (rc); 6172} 6173 6174static int 6175sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS) 6176{ 6177 struct adapter *sc = arg1; 6178 u_int i; 6179 struct sbuf *sb; 6180 uint32_t *buf, *p; 6181 int rc; 6182 6183 rc = sysctl_wire_old_buffer(req, 0); 6184 if (rc != 0) 6185 return (rc); 6186 6187 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6188 if (sb == NULL) 6189 return (ENOMEM); 6190 6191 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE, 6192 M_ZERO | M_WAITOK); 6193 6194 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL); 6195 p = buf; 6196 6197 sbuf_printf(sb, "Cntl ID DataBE Addr Data"); 6198 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6199 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x", 6200 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff, 6201 p[4], p[3], p[2], p[1], p[0]); 6202 } 6203 6204 sbuf_printf(sb, "\n\nCntl ID Data"); 6205 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) { 6206 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x", 6207 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]); 6208 } 6209 6210 rc = sbuf_finish(sb); 6211 sbuf_delete(sb); 6212 free(buf, M_CXGBE); 6213 return (rc); 6214} 6215 6216static int 6217sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS) 6218{ 6219 struct adapter *sc = arg1; 6220 struct sbuf *sb; 6221 int rc, i; 6222 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6223 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 6224 uint16_t thres[CIM_NUM_IBQ]; 6225 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr; 6226 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat; 6227 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq; 6228 6229 cim_num_obq = sc->chip_params->cim_num_obq; 6230 if (is_t4(sc)) { 6231 ibq_rdaddr = A_UP_IBQ_0_RDADDR; 6232 obq_rdaddr = A_UP_OBQ_0_REALADDR; 6233 } else { 6234 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; 6235 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; 6236 } 6237 nq = CIM_NUM_IBQ + cim_num_obq; 6238 6239 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat); 6240 if (rc == 0) 6241 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr); 6242 if (rc != 0) 6243 return (rc); 6244 6245 t4_read_cimq_cfg(sc, base, size, thres); 6246 6247 rc = sysctl_wire_old_buffer(req, 0); 6248 if (rc != 0) 6249 return (rc); 6250 6251 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req); 6252 if (sb == NULL) 6253 return (ENOMEM); 6254 6255 sbuf_printf(sb, 6256 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail"); 6257 6258 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) 6259 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u", 6260 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]), 6261 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6262 G_QUEREMFLITS(p[2]) * 16); 6263 for ( ; i < nq; i++, p += 4, wr += 2) 6264 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i], 6265 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff, 6266 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]), 6267 G_QUEREMFLITS(p[2]) * 16); 6268 6269 rc = sbuf_finish(sb); 6270 sbuf_delete(sb); 6271 6272 return (rc); 6273} 6274 6275static int 6276sysctl_cpl_stats(SYSCTL_HANDLER_ARGS) 6277{ 6278 struct adapter *sc = arg1; 6279 struct sbuf *sb; 6280 int rc; 6281 struct tp_cpl_stats stats; 6282 6283 rc = sysctl_wire_old_buffer(req, 0); 6284 if (rc != 0) 6285 return (rc); 6286 6287 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6288 if (sb == NULL) 6289 return (ENOMEM); 6290 6291 mtx_lock(&sc->reg_lock); 6292 t4_tp_get_cpl_stats(sc, &stats); 6293 mtx_unlock(&sc->reg_lock); 6294 6295 if (sc->chip_params->nchan > 2) { 6296 sbuf_printf(sb, " channel 0 channel 1" 6297 " channel 2 channel 3"); 6298 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u", 6299 stats.req[0], stats.req[1], stats.req[2], stats.req[3]); 6300 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u", 6301 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]); 6302 } else { 6303 sbuf_printf(sb, " channel 0 channel 1"); 6304 sbuf_printf(sb, "\nCPL requests: %10u %10u", 6305 stats.req[0], stats.req[1]); 6306 sbuf_printf(sb, "\nCPL responses: %10u %10u", 6307 stats.rsp[0], stats.rsp[1]); 6308 } 6309 6310 rc = sbuf_finish(sb); 6311 sbuf_delete(sb); 6312 6313 return (rc); 6314} 6315 6316static int 6317sysctl_ddp_stats(SYSCTL_HANDLER_ARGS) 6318{ 6319 struct adapter *sc = arg1; 6320 struct sbuf *sb; 6321 int rc; 6322 struct tp_usm_stats stats; 6323 6324 rc = sysctl_wire_old_buffer(req, 0); 6325 if (rc != 0) 6326 return(rc); 6327 6328 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6329 if (sb == NULL) 6330 return (ENOMEM); 6331 6332 t4_get_usm_stats(sc, &stats); 6333 6334 sbuf_printf(sb, "Frames: %u\n", stats.frames); 6335 sbuf_printf(sb, "Octets: %ju\n", stats.octets); 6336 sbuf_printf(sb, "Drops: %u", stats.drops); 6337 6338 rc = sbuf_finish(sb); 6339 sbuf_delete(sb); 6340 6341 return (rc); 6342} 6343 6344static const char * const devlog_level_strings[] = { 6345 [FW_DEVLOG_LEVEL_EMERG] = "EMERG", 6346 [FW_DEVLOG_LEVEL_CRIT] = "CRIT", 6347 [FW_DEVLOG_LEVEL_ERR] = "ERR", 6348 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE", 6349 [FW_DEVLOG_LEVEL_INFO] = "INFO", 6350 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG" 6351}; 6352 6353static const char * const devlog_facility_strings[] = { 6354 [FW_DEVLOG_FACILITY_CORE] = "CORE", 6355 [FW_DEVLOG_FACILITY_CF] = "CF", 6356 [FW_DEVLOG_FACILITY_SCHED] = "SCHED", 6357 [FW_DEVLOG_FACILITY_TIMER] = "TIMER", 6358 [FW_DEVLOG_FACILITY_RES] = "RES", 6359 [FW_DEVLOG_FACILITY_HW] = "HW", 6360 [FW_DEVLOG_FACILITY_FLR] = "FLR", 6361 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ", 6362 [FW_DEVLOG_FACILITY_PHY] = "PHY", 6363 [FW_DEVLOG_FACILITY_MAC] = "MAC", 6364 [FW_DEVLOG_FACILITY_PORT] = "PORT", 6365 [FW_DEVLOG_FACILITY_VI] = "VI", 6366 [FW_DEVLOG_FACILITY_FILTER] = "FILTER", 6367 [FW_DEVLOG_FACILITY_ACL] = "ACL", 6368 [FW_DEVLOG_FACILITY_TM] = "TM", 6369 [FW_DEVLOG_FACILITY_QFC] = "QFC", 6370 [FW_DEVLOG_FACILITY_DCB] = "DCB", 6371 [FW_DEVLOG_FACILITY_ETH] = "ETH", 6372 [FW_DEVLOG_FACILITY_OFLD] = "OFLD", 6373 [FW_DEVLOG_FACILITY_RI] = "RI", 6374 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI", 6375 [FW_DEVLOG_FACILITY_FCOE] = "FCOE", 6376 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI", 6377 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE", 6378 [FW_DEVLOG_FACILITY_CHNET] = "CHNET", 6379}; 6380 6381static int 6382sysctl_devlog(SYSCTL_HANDLER_ARGS) 6383{ 6384 struct adapter *sc = arg1; 6385 struct devlog_params *dparams = &sc->params.devlog; 6386 struct fw_devlog_e *buf, *e; 6387 int i, j, rc, nentries, first = 0; 6388 struct sbuf *sb; 6389 uint64_t ftstamp = UINT64_MAX; 6390 6391 if (dparams->addr == 0) 6392 return (ENXIO); 6393 6394 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT); 6395 if (buf == NULL) 6396 return (ENOMEM); 6397 6398 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size); 6399 if (rc != 0) 6400 goto done; 6401 6402 nentries = dparams->size / sizeof(struct fw_devlog_e); 6403 for (i = 0; i < nentries; i++) { 6404 e = &buf[i]; 6405 6406 if (e->timestamp == 0) 6407 break; /* end */ 6408 6409 e->timestamp = be64toh(e->timestamp); 6410 e->seqno = be32toh(e->seqno); 6411 for (j = 0; j < 8; j++) 6412 e->params[j] = be32toh(e->params[j]); 6413 6414 if (e->timestamp < ftstamp) { 6415 ftstamp = e->timestamp; 6416 first = i; 6417 } 6418 } 6419 6420 if (buf[first].timestamp == 0) 6421 goto done; /* nothing in the log */ 6422 6423 rc = sysctl_wire_old_buffer(req, 0); 6424 if (rc != 0) 6425 goto done; 6426 6427 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6428 if (sb == NULL) { 6429 rc = ENOMEM; 6430 goto done; 6431 } 6432 sbuf_printf(sb, "%10s %15s %8s %8s %s\n", 6433 "Seq#", "Tstamp", "Level", "Facility", "Message"); 6434 6435 i = first; 6436 do { 6437 e = &buf[i]; 6438 if (e->timestamp == 0) 6439 break; /* end */ 6440 6441 sbuf_printf(sb, "%10d %15ju %8s %8s ", 6442 e->seqno, e->timestamp, 6443 (e->level < nitems(devlog_level_strings) ? 6444 devlog_level_strings[e->level] : "UNKNOWN"), 6445 (e->facility < nitems(devlog_facility_strings) ? 6446 devlog_facility_strings[e->facility] : "UNKNOWN")); 6447 sbuf_printf(sb, e->fmt, e->params[0], e->params[1], 6448 e->params[2], e->params[3], e->params[4], 6449 e->params[5], e->params[6], e->params[7]); 6450 6451 if (++i == nentries) 6452 i = 0; 6453 } while (i != first); 6454 6455 rc = sbuf_finish(sb); 6456 sbuf_delete(sb); 6457done: 6458 free(buf, M_CXGBE); 6459 return (rc); 6460} 6461 6462static int 6463sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS) 6464{ 6465 struct adapter *sc = arg1; 6466 struct sbuf *sb; 6467 int rc; 6468 struct tp_fcoe_stats stats[MAX_NCHAN]; 6469 int i, nchan = sc->chip_params->nchan; 6470 6471 rc = sysctl_wire_old_buffer(req, 0); 6472 if (rc != 0) 6473 return (rc); 6474 6475 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6476 if (sb == NULL) 6477 return (ENOMEM); 6478 6479 for (i = 0; i < nchan; i++) 6480 t4_get_fcoe_stats(sc, i, &stats[i]); 6481 6482 if (nchan > 2) { 6483 sbuf_printf(sb, " channel 0 channel 1" 6484 " channel 2 channel 3"); 6485 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju", 6486 stats[0].octets_ddp, stats[1].octets_ddp, 6487 stats[2].octets_ddp, stats[3].octets_ddp); 6488 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u", 6489 stats[0].frames_ddp, stats[1].frames_ddp, 6490 stats[2].frames_ddp, stats[3].frames_ddp); 6491 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u", 6492 stats[0].frames_drop, stats[1].frames_drop, 6493 stats[2].frames_drop, stats[3].frames_drop); 6494 } else { 6495 sbuf_printf(sb, " channel 0 channel 1"); 6496 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju", 6497 stats[0].octets_ddp, stats[1].octets_ddp); 6498 sbuf_printf(sb, "\nframesDDP: %16u %16u", 6499 stats[0].frames_ddp, stats[1].frames_ddp); 6500 sbuf_printf(sb, "\nframesDrop: %16u %16u", 6501 stats[0].frames_drop, stats[1].frames_drop); 6502 } 6503 6504 rc = sbuf_finish(sb); 6505 sbuf_delete(sb); 6506 6507 return (rc); 6508} 6509 6510static int 6511sysctl_hw_sched(SYSCTL_HANDLER_ARGS) 6512{ 6513 struct adapter *sc = arg1; 6514 struct sbuf *sb; 6515 int rc, i; 6516 unsigned int map, kbps, ipg, mode; 6517 unsigned int pace_tab[NTX_SCHED]; 6518 6519 rc = sysctl_wire_old_buffer(req, 0); 6520 if (rc != 0) 6521 return (rc); 6522 6523 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 6524 if (sb == NULL) 6525 return (ENOMEM); 6526 6527 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP); 6528 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG)); 6529 t4_read_pace_tbl(sc, pace_tab); 6530 6531 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) " 6532 "Class IPG (0.1 ns) Flow IPG (us)"); 6533 6534 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) { 6535 t4_get_tx_sched(sc, i, &kbps, &ipg); 6536 sbuf_printf(sb, "\n %u %-5s %u ", i, 6537 (mode & (1 << i)) ? "flow" : "class", map & 3); 6538 if (kbps) 6539 sbuf_printf(sb, "%9u ", kbps); 6540 else 6541 sbuf_printf(sb, " disabled "); 6542 6543 if (ipg) 6544 sbuf_printf(sb, "%13u ", ipg); 6545 else 6546 sbuf_printf(sb, " disabled "); 6547 6548 if (pace_tab[i]) 6549 sbuf_printf(sb, "%10u", pace_tab[i]); 6550 else 6551 sbuf_printf(sb, " disabled"); 6552 } 6553 6554 rc = sbuf_finish(sb); 6555 sbuf_delete(sb); 6556 6557 return (rc); 6558} 6559 6560static int 6561sysctl_lb_stats(SYSCTL_HANDLER_ARGS) 6562{ 6563 struct adapter *sc = arg1; 6564 struct sbuf *sb; 6565 int rc, i, j; 6566 uint64_t *p0, *p1; 6567 struct lb_port_stats s[2]; 6568 static const char *stat_name[] = { 6569 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:", 6570 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:", 6571 "Frames128To255:", "Frames256To511:", "Frames512To1023:", 6572 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:", 6573 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:", 6574 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:", 6575 "BG2FramesTrunc:", "BG3FramesTrunc:" 6576 }; 6577 6578 rc = sysctl_wire_old_buffer(req, 0); 6579 if (rc != 0) 6580 return (rc); 6581 6582 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6583 if (sb == NULL) 6584 return (ENOMEM); 6585 6586 memset(s, 0, sizeof(s)); 6587 6588 for (i = 0; i < sc->chip_params->nchan; i += 2) { 6589 t4_get_lb_stats(sc, i, &s[0]); 6590 t4_get_lb_stats(sc, i + 1, &s[1]); 6591 6592 p0 = &s[0].octets; 6593 p1 = &s[1].octets; 6594 sbuf_printf(sb, "%s Loopback %u" 6595 " Loopback %u", i == 0 ? "" : "\n", i, i + 1); 6596 6597 for (j = 0; j < nitems(stat_name); j++) 6598 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j], 6599 *p0++, *p1++); 6600 } 6601 6602 rc = sbuf_finish(sb); 6603 sbuf_delete(sb); 6604 6605 return (rc); 6606} 6607 6608static int 6609sysctl_linkdnrc(SYSCTL_HANDLER_ARGS) 6610{ 6611 int rc = 0; 6612 struct port_info *pi = arg1; 6613 struct link_config *lc = &pi->link_cfg; 6614 struct sbuf *sb; 6615 6616 rc = sysctl_wire_old_buffer(req, 0); 6617 if (rc != 0) 6618 return(rc); 6619 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req); 6620 if (sb == NULL) 6621 return (ENOMEM); 6622 6623 if (lc->link_ok || lc->link_down_rc == 255) 6624 sbuf_printf(sb, "n/a"); 6625 else 6626 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc)); 6627 6628 rc = sbuf_finish(sb); 6629 sbuf_delete(sb); 6630 6631 return (rc); 6632} 6633 6634struct mem_desc { 6635 unsigned int base; 6636 unsigned int limit; 6637 unsigned int idx; 6638}; 6639 6640static int 6641mem_desc_cmp(const void *a, const void *b) 6642{ 6643 return ((const struct mem_desc *)a)->base - 6644 ((const struct mem_desc *)b)->base; 6645} 6646 6647static void 6648mem_region_show(struct sbuf *sb, const char *name, unsigned int from, 6649 unsigned int to) 6650{ 6651 unsigned int size; 6652 6653 if (from == to) 6654 return; 6655 6656 size = to - from + 1; 6657 if (size == 0) 6658 return; 6659 6660 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */ 6661 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size); 6662} 6663 6664static int 6665sysctl_meminfo(SYSCTL_HANDLER_ARGS) 6666{ 6667 struct adapter *sc = arg1; 6668 struct sbuf *sb; 6669 int rc, i, n; 6670 uint32_t lo, hi, used, alloc; 6671 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"}; 6672 static const char *region[] = { 6673 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 6674 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 6675 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 6676 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 6677 "RQUDP region:", "PBL region:", "TXPBL region:", 6678 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 6679 "On-chip queues:" 6680 }; 6681 struct mem_desc avail[4]; 6682 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */ 6683 struct mem_desc *md = mem; 6684 6685 rc = sysctl_wire_old_buffer(req, 0); 6686 if (rc != 0) 6687 return (rc); 6688 6689 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6690 if (sb == NULL) 6691 return (ENOMEM); 6692 6693 for (i = 0; i < nitems(mem); i++) { 6694 mem[i].limit = 0; 6695 mem[i].idx = i; 6696 } 6697 6698 /* Find and sort the populated memory ranges */ 6699 i = 0; 6700 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); 6701 if (lo & F_EDRAM0_ENABLE) { 6702 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); 6703 avail[i].base = G_EDRAM0_BASE(hi) << 20; 6704 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20); 6705 avail[i].idx = 0; 6706 i++; 6707 } 6708 if (lo & F_EDRAM1_ENABLE) { 6709 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); 6710 avail[i].base = G_EDRAM1_BASE(hi) << 20; 6711 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20); 6712 avail[i].idx = 1; 6713 i++; 6714 } 6715 if (lo & F_EXT_MEM_ENABLE) { 6716 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); 6717 avail[i].base = G_EXT_MEM_BASE(hi) << 20; 6718 avail[i].limit = avail[i].base + 6719 (G_EXT_MEM_SIZE(hi) << 20); 6720 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */ 6721 i++; 6722 } 6723 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) { 6724 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); 6725 avail[i].base = G_EXT_MEM1_BASE(hi) << 20; 6726 avail[i].limit = avail[i].base + 6727 (G_EXT_MEM1_SIZE(hi) << 20); 6728 avail[i].idx = 4; 6729 i++; 6730 } 6731 if (!i) /* no memory available */ 6732 return 0; 6733 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp); 6734 6735 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR); 6736 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR); 6737 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR); 6738 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 6739 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE); 6740 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE); 6741 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE); 6742 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE); 6743 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE); 6744 6745 /* the next few have explicit upper bounds */ 6746 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE); 6747 md->limit = md->base - 1 + 6748 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) * 6749 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE)); 6750 md++; 6751 6752 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE); 6753 md->limit = md->base - 1 + 6754 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) * 6755 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE)); 6756 md++; 6757 6758 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 6759 if (chip_id(sc) <= CHELSIO_T5) 6760 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE); 6761 else 6762 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR); 6763 md->limit = 0; 6764 } else { 6765 md->base = 0; 6766 md->idx = nitems(region); /* hide it */ 6767 } 6768 md++; 6769 6770#define ulp_region(reg) \ 6771 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\ 6772 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT) 6773 6774 ulp_region(RX_ISCSI); 6775 ulp_region(RX_TDDP); 6776 ulp_region(TX_TPT); 6777 ulp_region(RX_STAG); 6778 ulp_region(RX_RQ); 6779 ulp_region(RX_RQUDP); 6780 ulp_region(RX_PBL); 6781 ulp_region(TX_PBL); 6782#undef ulp_region 6783 6784 md->base = 0; 6785 md->idx = nitems(region); 6786 if (!is_t4(sc)) { 6787 uint32_t size = 0; 6788 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2); 6789 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE); 6790 6791 if (is_t5(sc)) { 6792 if (sge_ctrl & F_VFIFO_ENABLE) 6793 size = G_DBVFIFO_SIZE(fifo_size); 6794 } else 6795 size = G_T6_DBVFIFO_SIZE(fifo_size); 6796 6797 if (size) { 6798 md->base = G_BASEADDR(t4_read_reg(sc, 6799 A_SGE_DBVFIFO_BADDR)); 6800 md->limit = md->base + (size << 2) - 1; 6801 } 6802 } 6803 md++; 6804 6805 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE); 6806 md->limit = 0; 6807 md++; 6808 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE); 6809 md->limit = 0; 6810 md++; 6811 6812 md->base = sc->vres.ocq.start; 6813 if (sc->vres.ocq.size) 6814 md->limit = md->base + sc->vres.ocq.size - 1; 6815 else 6816 md->idx = nitems(region); /* hide it */ 6817 md++; 6818 6819 /* add any address-space holes, there can be up to 3 */ 6820 for (n = 0; n < i - 1; n++) 6821 if (avail[n].limit < avail[n + 1].base) 6822 (md++)->base = avail[n].limit; 6823 if (avail[n].limit) 6824 (md++)->base = avail[n].limit; 6825 6826 n = md - mem; 6827 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp); 6828 6829 for (lo = 0; lo < i; lo++) 6830 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base, 6831 avail[lo].limit - 1); 6832 6833 sbuf_printf(sb, "\n"); 6834 for (i = 0; i < n; i++) { 6835 if (mem[i].idx >= nitems(region)) 6836 continue; /* skip holes */ 6837 if (!mem[i].limit) 6838 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0; 6839 mem_region_show(sb, region[mem[i].idx], mem[i].base, 6840 mem[i].limit); 6841 } 6842 6843 sbuf_printf(sb, "\n"); 6844 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR); 6845 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1; 6846 mem_region_show(sb, "uP RAM:", lo, hi); 6847 6848 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR); 6849 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1; 6850 mem_region_show(sb, "uP Extmem2:", lo, hi); 6851 6852 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE); 6853 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n", 6854 G_PMRXMAXPAGE(lo), 6855 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10, 6856 (lo & F_PMRXNUMCHN) ? 2 : 1); 6857 6858 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE); 6859 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 6860 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n", 6861 G_PMTXMAXPAGE(lo), 6862 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10), 6863 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo)); 6864 sbuf_printf(sb, "%u p-structs\n", 6865 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT)); 6866 6867 for (i = 0; i < 4; i++) { 6868 if (chip_id(sc) > CHELSIO_T5) 6869 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4); 6870 else 6871 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4); 6872 if (is_t5(sc)) { 6873 used = G_T5_USED(lo); 6874 alloc = G_T5_ALLOC(lo); 6875 } else { 6876 used = G_USED(lo); 6877 alloc = G_ALLOC(lo); 6878 } 6879 /* For T6 these are MAC buffer groups */ 6880 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated", 6881 i, used, alloc); 6882 } 6883 for (i = 0; i < sc->chip_params->nchan; i++) { 6884 if (chip_id(sc) > CHELSIO_T5) 6885 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4); 6886 else 6887 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4); 6888 if (is_t5(sc)) { 6889 used = G_T5_USED(lo); 6890 alloc = G_T5_ALLOC(lo); 6891 } else { 6892 used = G_USED(lo); 6893 alloc = G_ALLOC(lo); 6894 } 6895 /* For T6 these are MAC buffer groups */ 6896 sbuf_printf(sb, 6897 "\nLoopback %d using %u pages out of %u allocated", 6898 i, used, alloc); 6899 } 6900 6901 rc = sbuf_finish(sb); 6902 sbuf_delete(sb); 6903 6904 return (rc); 6905} 6906 6907static inline void 6908tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask) 6909{ 6910 *mask = x | y; 6911 y = htobe64(y); 6912 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN); 6913} 6914 6915static int 6916sysctl_mps_tcam(SYSCTL_HANDLER_ARGS) 6917{ 6918 struct adapter *sc = arg1; 6919 struct sbuf *sb; 6920 int rc, i; 6921 6922 MPASS(chip_id(sc) <= CHELSIO_T5); 6923 6924 rc = sysctl_wire_old_buffer(req, 0); 6925 if (rc != 0) 6926 return (rc); 6927 6928 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 6929 if (sb == NULL) 6930 return (ENOMEM); 6931 6932 sbuf_printf(sb, 6933 "Idx Ethernet address Mask Vld Ports PF" 6934 " VF Replication P0 P1 P2 P3 ML"); 6935 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 6936 uint64_t tcamx, tcamy, mask; 6937 uint32_t cls_lo, cls_hi; 6938 uint8_t addr[ETHER_ADDR_LEN]; 6939 6940 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i)); 6941 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i)); 6942 if (tcamx & tcamy) 6943 continue; 6944 tcamxy2valmask(tcamx, tcamy, addr, &mask); 6945 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 6946 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 6947 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx" 6948 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2], 6949 addr[3], addr[4], addr[5], (uintmax_t)mask, 6950 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N', 6951 G_PORTMAP(cls_hi), G_PF(cls_lo), 6952 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1); 6953 6954 if (cls_lo & F_REPLICATE) { 6955 struct fw_ldst_cmd ldst_cmd; 6956 6957 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 6958 ldst_cmd.op_to_addrspace = 6959 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 6960 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6961 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 6962 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 6963 ldst_cmd.u.mps.rplc.fid_idx = 6964 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 6965 V_FW_LDST_CMD_IDX(i)); 6966 6967 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 6968 "t4mps"); 6969 if (rc) 6970 break; 6971 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 6972 sizeof(ldst_cmd), &ldst_cmd); 6973 end_synchronized_op(sc, 0); 6974 6975 if (rc != 0) { 6976 sbuf_printf(sb, "%36d", rc); 6977 rc = 0; 6978 } else { 6979 sbuf_printf(sb, " %08x %08x %08x %08x", 6980 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 6981 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 6982 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 6983 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 6984 } 6985 } else 6986 sbuf_printf(sb, "%36s", ""); 6987 6988 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo), 6989 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo), 6990 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf); 6991 } 6992 6993 if (rc) 6994 (void) sbuf_finish(sb); 6995 else 6996 rc = sbuf_finish(sb); 6997 sbuf_delete(sb); 6998 6999 return (rc); 7000} 7001 7002static int 7003sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS) 7004{ 7005 struct adapter *sc = arg1; 7006 struct sbuf *sb; 7007 int rc, i; 7008 7009 MPASS(chip_id(sc) > CHELSIO_T5); 7010 7011 rc = sysctl_wire_old_buffer(req, 0); 7012 if (rc != 0) 7013 return (rc); 7014 7015 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7016 if (sb == NULL) 7017 return (ENOMEM); 7018 7019 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask" 7020 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF" 7021 " Replication" 7022 " P0 P1 P2 P3 ML\n"); 7023 7024 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) { 7025 uint8_t dip_hit, vlan_vld, lookup_type, port_num; 7026 uint16_t ivlan; 7027 uint64_t tcamx, tcamy, val, mask; 7028 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy; 7029 uint8_t addr[ETHER_ADDR_LEN]; 7030 7031 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0); 7032 if (i < 256) 7033 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0); 7034 else 7035 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1); 7036 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 7037 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 7038 tcamy = G_DMACH(val) << 32; 7039 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 7040 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 7041 lookup_type = G_DATALKPTYPE(data2); 7042 port_num = G_DATAPORTNUM(data2); 7043 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7044 /* Inner header VNI */ 7045 vniy = ((data2 & F_DATAVIDH2) << 23) | 7046 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 7047 dip_hit = data2 & F_DATADIPHIT; 7048 vlan_vld = 0; 7049 } else { 7050 vniy = 0; 7051 dip_hit = 0; 7052 vlan_vld = data2 & F_DATAVIDH2; 7053 ivlan = G_VIDL(val); 7054 } 7055 7056 ctl |= V_CTLXYBITSEL(1); 7057 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl); 7058 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1); 7059 tcamx = G_DMACH(val) << 32; 7060 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1); 7061 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1); 7062 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7063 /* Inner header VNI mask */ 7064 vnix = ((data2 & F_DATAVIDH2) << 23) | 7065 (G_DATAVIDH1(data2) << 16) | G_VIDL(val); 7066 } else 7067 vnix = 0; 7068 7069 if (tcamx & tcamy) 7070 continue; 7071 tcamxy2valmask(tcamx, tcamy, addr, &mask); 7072 7073 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i)); 7074 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i)); 7075 7076 if (lookup_type && lookup_type != M_DATALKPTYPE) { 7077 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 7078 "%012jx %06x %06x - - %3c" 7079 " 'I' %4x %3c %#x%4u%4d", i, addr[0], 7080 addr[1], addr[2], addr[3], addr[4], addr[5], 7081 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N', 7082 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 7083 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 7084 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 7085 } else { 7086 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x " 7087 "%012jx - - ", i, addr[0], addr[1], 7088 addr[2], addr[3], addr[4], addr[5], 7089 (uintmax_t)mask); 7090 7091 if (vlan_vld) 7092 sbuf_printf(sb, "%4u Y ", ivlan); 7093 else 7094 sbuf_printf(sb, " - N "); 7095 7096 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d", 7097 lookup_type ? 'I' : 'O', port_num, 7098 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N', 7099 G_PORTMAP(cls_hi), G_T6_PF(cls_lo), 7100 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1); 7101 } 7102 7103 7104 if (cls_lo & F_T6_REPLICATE) { 7105 struct fw_ldst_cmd ldst_cmd; 7106 7107 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 7108 ldst_cmd.op_to_addrspace = 7109 htobe32(V_FW_CMD_OP(FW_LDST_CMD) | 7110 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7111 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS)); 7112 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd)); 7113 ldst_cmd.u.mps.rplc.fid_idx = 7114 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) | 7115 V_FW_LDST_CMD_IDX(i)); 7116 7117 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, 7118 "t6mps"); 7119 if (rc) 7120 break; 7121 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd, 7122 sizeof(ldst_cmd), &ldst_cmd); 7123 end_synchronized_op(sc, 0); 7124 7125 if (rc != 0) { 7126 sbuf_printf(sb, "%72d", rc); 7127 rc = 0; 7128 } else { 7129 sbuf_printf(sb, " %08x %08x %08x %08x" 7130 " %08x %08x %08x %08x", 7131 be32toh(ldst_cmd.u.mps.rplc.rplc255_224), 7132 be32toh(ldst_cmd.u.mps.rplc.rplc223_192), 7133 be32toh(ldst_cmd.u.mps.rplc.rplc191_160), 7134 be32toh(ldst_cmd.u.mps.rplc.rplc159_128), 7135 be32toh(ldst_cmd.u.mps.rplc.rplc127_96), 7136 be32toh(ldst_cmd.u.mps.rplc.rplc95_64), 7137 be32toh(ldst_cmd.u.mps.rplc.rplc63_32), 7138 be32toh(ldst_cmd.u.mps.rplc.rplc31_0)); 7139 } 7140 } else 7141 sbuf_printf(sb, "%72s", ""); 7142 7143 sbuf_printf(sb, "%4u%3u%3u%3u %#x", 7144 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo), 7145 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo), 7146 (cls_lo >> S_T6_MULTILISTEN0) & 0xf); 7147 } 7148 7149 if (rc) 7150 (void) sbuf_finish(sb); 7151 else 7152 rc = sbuf_finish(sb); 7153 sbuf_delete(sb); 7154 7155 return (rc); 7156} 7157 7158static int 7159sysctl_path_mtus(SYSCTL_HANDLER_ARGS) 7160{ 7161 struct adapter *sc = arg1; 7162 struct sbuf *sb; 7163 int rc; 7164 uint16_t mtus[NMTUS]; 7165 7166 rc = sysctl_wire_old_buffer(req, 0); 7167 if (rc != 0) 7168 return (rc); 7169 7170 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7171 if (sb == NULL) 7172 return (ENOMEM); 7173 7174 t4_read_mtu_tbl(sc, mtus, NULL); 7175 7176 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u", 7177 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6], 7178 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13], 7179 mtus[14], mtus[15]); 7180 7181 rc = sbuf_finish(sb); 7182 sbuf_delete(sb); 7183 7184 return (rc); 7185} 7186 7187static int 7188sysctl_pm_stats(SYSCTL_HANDLER_ARGS) 7189{ 7190 struct adapter *sc = arg1; 7191 struct sbuf *sb; 7192 int rc, i; 7193 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS]; 7194 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS]; 7195 static const char *tx_stats[MAX_PM_NSTATS] = { 7196 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:", 7197 "Tx FIFO wait", NULL, "Tx latency" 7198 }; 7199 static const char *rx_stats[MAX_PM_NSTATS] = { 7200 "Read:", "Write bypass:", "Write mem:", "Flush:", 7201 "Rx FIFO wait", NULL, "Rx latency" 7202 }; 7203 7204 rc = sysctl_wire_old_buffer(req, 0); 7205 if (rc != 0) 7206 return (rc); 7207 7208 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7209 if (sb == NULL) 7210 return (ENOMEM); 7211 7212 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc); 7213 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc); 7214 7215 sbuf_printf(sb, " Tx pcmds Tx bytes"); 7216 for (i = 0; i < 4; i++) { 7217 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7218 tx_cyc[i]); 7219 } 7220 7221 sbuf_printf(sb, "\n Rx pcmds Rx bytes"); 7222 for (i = 0; i < 4; i++) { 7223 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7224 rx_cyc[i]); 7225 } 7226 7227 if (chip_id(sc) > CHELSIO_T5) { 7228 sbuf_printf(sb, 7229 "\n Total wait Total occupancy"); 7230 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7231 tx_cyc[i]); 7232 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7233 rx_cyc[i]); 7234 7235 i += 2; 7236 MPASS(i < nitems(tx_stats)); 7237 7238 sbuf_printf(sb, 7239 "\n Reads Total wait"); 7240 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i], 7241 tx_cyc[i]); 7242 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i], 7243 rx_cyc[i]); 7244 } 7245 7246 rc = sbuf_finish(sb); 7247 sbuf_delete(sb); 7248 7249 return (rc); 7250} 7251 7252static int 7253sysctl_rdma_stats(SYSCTL_HANDLER_ARGS) 7254{ 7255 struct adapter *sc = arg1; 7256 struct sbuf *sb; 7257 int rc; 7258 struct tp_rdma_stats stats; 7259 7260 rc = sysctl_wire_old_buffer(req, 0); 7261 if (rc != 0) 7262 return (rc); 7263 7264 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7265 if (sb == NULL) 7266 return (ENOMEM); 7267 7268 mtx_lock(&sc->reg_lock); 7269 t4_tp_get_rdma_stats(sc, &stats); 7270 mtx_unlock(&sc->reg_lock); 7271 7272 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod); 7273 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt); 7274 7275 rc = sbuf_finish(sb); 7276 sbuf_delete(sb); 7277 7278 return (rc); 7279} 7280 7281static int 7282sysctl_tcp_stats(SYSCTL_HANDLER_ARGS) 7283{ 7284 struct adapter *sc = arg1; 7285 struct sbuf *sb; 7286 int rc; 7287 struct tp_tcp_stats v4, v6; 7288 7289 rc = sysctl_wire_old_buffer(req, 0); 7290 if (rc != 0) 7291 return (rc); 7292 7293 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7294 if (sb == NULL) 7295 return (ENOMEM); 7296 7297 mtx_lock(&sc->reg_lock); 7298 t4_tp_get_tcp_stats(sc, &v4, &v6); 7299 mtx_unlock(&sc->reg_lock); 7300 7301 sbuf_printf(sb, 7302 " IP IPv6\n"); 7303 sbuf_printf(sb, "OutRsts: %20u %20u\n", 7304 v4.tcp_out_rsts, v6.tcp_out_rsts); 7305 sbuf_printf(sb, "InSegs: %20ju %20ju\n", 7306 v4.tcp_in_segs, v6.tcp_in_segs); 7307 sbuf_printf(sb, "OutSegs: %20ju %20ju\n", 7308 v4.tcp_out_segs, v6.tcp_out_segs); 7309 sbuf_printf(sb, "RetransSegs: %20ju %20ju", 7310 v4.tcp_retrans_segs, v6.tcp_retrans_segs); 7311 7312 rc = sbuf_finish(sb); 7313 sbuf_delete(sb); 7314 7315 return (rc); 7316} 7317 7318static int 7319sysctl_tids(SYSCTL_HANDLER_ARGS) 7320{ 7321 struct adapter *sc = arg1; 7322 struct sbuf *sb; 7323 int rc; 7324 struct tid_info *t = &sc->tids; 7325 7326 rc = sysctl_wire_old_buffer(req, 0); 7327 if (rc != 0) 7328 return (rc); 7329 7330 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7331 if (sb == NULL) 7332 return (ENOMEM); 7333 7334 if (t->natids) { 7335 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1, 7336 t->atids_in_use); 7337 } 7338 7339 if (t->ntids) { 7340 sbuf_printf(sb, "TID range: "); 7341 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) { 7342 uint32_t b, hb; 7343 7344 if (chip_id(sc) <= CHELSIO_T5) { 7345 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4; 7346 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4; 7347 } else { 7348 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX); 7349 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE); 7350 } 7351 7352 if (b) 7353 sbuf_printf(sb, "0-%u, ", b - 1); 7354 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1); 7355 } else 7356 sbuf_printf(sb, "0-%u", t->ntids - 1); 7357 sbuf_printf(sb, ", in use: %u\n", 7358 atomic_load_acq_int(&t->tids_in_use)); 7359 } 7360 7361 if (t->nstids) { 7362 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base, 7363 t->stid_base + t->nstids - 1, t->stids_in_use); 7364 } 7365 7366 if (t->nftids) { 7367 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base, 7368 t->ftid_base + t->nftids - 1); 7369 } 7370 7371 if (t->netids) { 7372 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base, 7373 t->etid_base + t->netids - 1); 7374 } 7375 7376 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users", 7377 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4), 7378 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6)); 7379 7380 rc = sbuf_finish(sb); 7381 sbuf_delete(sb); 7382 7383 return (rc); 7384} 7385 7386static int 7387sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS) 7388{ 7389 struct adapter *sc = arg1; 7390 struct sbuf *sb; 7391 int rc; 7392 struct tp_err_stats stats; 7393 7394 rc = sysctl_wire_old_buffer(req, 0); 7395 if (rc != 0) 7396 return (rc); 7397 7398 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7399 if (sb == NULL) 7400 return (ENOMEM); 7401 7402 mtx_lock(&sc->reg_lock); 7403 t4_tp_get_err_stats(sc, &stats); 7404 mtx_unlock(&sc->reg_lock); 7405 7406 if (sc->chip_params->nchan > 2) { 7407 sbuf_printf(sb, " channel 0 channel 1" 7408 " channel 2 channel 3\n"); 7409 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n", 7410 stats.mac_in_errs[0], stats.mac_in_errs[1], 7411 stats.mac_in_errs[2], stats.mac_in_errs[3]); 7412 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n", 7413 stats.hdr_in_errs[0], stats.hdr_in_errs[1], 7414 stats.hdr_in_errs[2], stats.hdr_in_errs[3]); 7415 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n", 7416 stats.tcp_in_errs[0], stats.tcp_in_errs[1], 7417 stats.tcp_in_errs[2], stats.tcp_in_errs[3]); 7418 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n", 7419 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1], 7420 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]); 7421 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n", 7422 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1], 7423 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]); 7424 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n", 7425 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1], 7426 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]); 7427 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n", 7428 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1], 7429 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]); 7430 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n", 7431 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1], 7432 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]); 7433 } else { 7434 sbuf_printf(sb, " channel 0 channel 1\n"); 7435 sbuf_printf(sb, "macInErrs: %10u %10u\n", 7436 stats.mac_in_errs[0], stats.mac_in_errs[1]); 7437 sbuf_printf(sb, "hdrInErrs: %10u %10u\n", 7438 stats.hdr_in_errs[0], stats.hdr_in_errs[1]); 7439 sbuf_printf(sb, "tcpInErrs: %10u %10u\n", 7440 stats.tcp_in_errs[0], stats.tcp_in_errs[1]); 7441 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n", 7442 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]); 7443 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n", 7444 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]); 7445 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n", 7446 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]); 7447 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n", 7448 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]); 7449 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n", 7450 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]); 7451 } 7452 7453 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u", 7454 stats.ofld_no_neigh, stats.ofld_cong_defer); 7455 7456 rc = sbuf_finish(sb); 7457 sbuf_delete(sb); 7458 7459 return (rc); 7460} 7461 7462static int 7463sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS) 7464{ 7465 struct adapter *sc = arg1; 7466 struct tp_params *tpp = &sc->params.tp; 7467 u_int mask; 7468 int rc; 7469 7470 mask = tpp->la_mask >> 16; 7471 rc = sysctl_handle_int(oidp, &mask, 0, req); 7472 if (rc != 0 || req->newptr == NULL) 7473 return (rc); 7474 if (mask > 0xffff) 7475 return (EINVAL); 7476 tpp->la_mask = mask << 16; 7477 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask); 7478 7479 return (0); 7480} 7481 7482struct field_desc { 7483 const char *name; 7484 u_int start; 7485 u_int width; 7486}; 7487 7488static void 7489field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f) 7490{ 7491 char buf[32]; 7492 int line_size = 0; 7493 7494 while (f->name) { 7495 uint64_t mask = (1ULL << f->width) - 1; 7496 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name, 7497 ((uintmax_t)v >> f->start) & mask); 7498 7499 if (line_size + len >= 79) { 7500 line_size = 8; 7501 sbuf_printf(sb, "\n "); 7502 } 7503 sbuf_printf(sb, "%s ", buf); 7504 line_size += len + 1; 7505 f++; 7506 } 7507 sbuf_printf(sb, "\n"); 7508} 7509 7510static const struct field_desc tp_la0[] = { 7511 { "RcfOpCodeOut", 60, 4 }, 7512 { "State", 56, 4 }, 7513 { "WcfState", 52, 4 }, 7514 { "RcfOpcSrcOut", 50, 2 }, 7515 { "CRxError", 49, 1 }, 7516 { "ERxError", 48, 1 }, 7517 { "SanityFailed", 47, 1 }, 7518 { "SpuriousMsg", 46, 1 }, 7519 { "FlushInputMsg", 45, 1 }, 7520 { "FlushInputCpl", 44, 1 }, 7521 { "RssUpBit", 43, 1 }, 7522 { "RssFilterHit", 42, 1 }, 7523 { "Tid", 32, 10 }, 7524 { "InitTcb", 31, 1 }, 7525 { "LineNumber", 24, 7 }, 7526 { "Emsg", 23, 1 }, 7527 { "EdataOut", 22, 1 }, 7528 { "Cmsg", 21, 1 }, 7529 { "CdataOut", 20, 1 }, 7530 { "EreadPdu", 19, 1 }, 7531 { "CreadPdu", 18, 1 }, 7532 { "TunnelPkt", 17, 1 }, 7533 { "RcfPeerFin", 16, 1 }, 7534 { "RcfReasonOut", 12, 4 }, 7535 { "TxCchannel", 10, 2 }, 7536 { "RcfTxChannel", 8, 2 }, 7537 { "RxEchannel", 6, 2 }, 7538 { "RcfRxChannel", 5, 1 }, 7539 { "RcfDataOutSrdy", 4, 1 }, 7540 { "RxDvld", 3, 1 }, 7541 { "RxOoDvld", 2, 1 }, 7542 { "RxCongestion", 1, 1 }, 7543 { "TxCongestion", 0, 1 }, 7544 { NULL } 7545}; 7546 7547static const struct field_desc tp_la1[] = { 7548 { "CplCmdIn", 56, 8 }, 7549 { "CplCmdOut", 48, 8 }, 7550 { "ESynOut", 47, 1 }, 7551 { "EAckOut", 46, 1 }, 7552 { "EFinOut", 45, 1 }, 7553 { "ERstOut", 44, 1 }, 7554 { "SynIn", 43, 1 }, 7555 { "AckIn", 42, 1 }, 7556 { "FinIn", 41, 1 }, 7557 { "RstIn", 40, 1 }, 7558 { "DataIn", 39, 1 }, 7559 { "DataInVld", 38, 1 }, 7560 { "PadIn", 37, 1 }, 7561 { "RxBufEmpty", 36, 1 }, 7562 { "RxDdp", 35, 1 }, 7563 { "RxFbCongestion", 34, 1 }, 7564 { "TxFbCongestion", 33, 1 }, 7565 { "TxPktSumSrdy", 32, 1 }, 7566 { "RcfUlpType", 28, 4 }, 7567 { "Eread", 27, 1 }, 7568 { "Ebypass", 26, 1 }, 7569 { "Esave", 25, 1 }, 7570 { "Static0", 24, 1 }, 7571 { "Cread", 23, 1 }, 7572 { "Cbypass", 22, 1 }, 7573 { "Csave", 21, 1 }, 7574 { "CPktOut", 20, 1 }, 7575 { "RxPagePoolFull", 18, 2 }, 7576 { "RxLpbkPkt", 17, 1 }, 7577 { "TxLpbkPkt", 16, 1 }, 7578 { "RxVfValid", 15, 1 }, 7579 { "SynLearned", 14, 1 }, 7580 { "SetDelEntry", 13, 1 }, 7581 { "SetInvEntry", 12, 1 }, 7582 { "CpcmdDvld", 11, 1 }, 7583 { "CpcmdSave", 10, 1 }, 7584 { "RxPstructsFull", 8, 2 }, 7585 { "EpcmdDvld", 7, 1 }, 7586 { "EpcmdFlush", 6, 1 }, 7587 { "EpcmdTrimPrefix", 5, 1 }, 7588 { "EpcmdTrimPostfix", 4, 1 }, 7589 { "ERssIp4Pkt", 3, 1 }, 7590 { "ERssIp6Pkt", 2, 1 }, 7591 { "ERssTcpUdpPkt", 1, 1 }, 7592 { "ERssFceFipPkt", 0, 1 }, 7593 { NULL } 7594}; 7595 7596static const struct field_desc tp_la2[] = { 7597 { "CplCmdIn", 56, 8 }, 7598 { "MpsVfVld", 55, 1 }, 7599 { "MpsPf", 52, 3 }, 7600 { "MpsVf", 44, 8 }, 7601 { "SynIn", 43, 1 }, 7602 { "AckIn", 42, 1 }, 7603 { "FinIn", 41, 1 }, 7604 { "RstIn", 40, 1 }, 7605 { "DataIn", 39, 1 }, 7606 { "DataInVld", 38, 1 }, 7607 { "PadIn", 37, 1 }, 7608 { "RxBufEmpty", 36, 1 }, 7609 { "RxDdp", 35, 1 }, 7610 { "RxFbCongestion", 34, 1 }, 7611 { "TxFbCongestion", 33, 1 }, 7612 { "TxPktSumSrdy", 32, 1 }, 7613 { "RcfUlpType", 28, 4 }, 7614 { "Eread", 27, 1 }, 7615 { "Ebypass", 26, 1 }, 7616 { "Esave", 25, 1 }, 7617 { "Static0", 24, 1 }, 7618 { "Cread", 23, 1 }, 7619 { "Cbypass", 22, 1 }, 7620 { "Csave", 21, 1 }, 7621 { "CPktOut", 20, 1 }, 7622 { "RxPagePoolFull", 18, 2 }, 7623 { "RxLpbkPkt", 17, 1 }, 7624 { "TxLpbkPkt", 16, 1 }, 7625 { "RxVfValid", 15, 1 }, 7626 { "SynLearned", 14, 1 }, 7627 { "SetDelEntry", 13, 1 }, 7628 { "SetInvEntry", 12, 1 }, 7629 { "CpcmdDvld", 11, 1 }, 7630 { "CpcmdSave", 10, 1 }, 7631 { "RxPstructsFull", 8, 2 }, 7632 { "EpcmdDvld", 7, 1 }, 7633 { "EpcmdFlush", 6, 1 }, 7634 { "EpcmdTrimPrefix", 5, 1 }, 7635 { "EpcmdTrimPostfix", 4, 1 }, 7636 { "ERssIp4Pkt", 3, 1 }, 7637 { "ERssIp6Pkt", 2, 1 }, 7638 { "ERssTcpUdpPkt", 1, 1 }, 7639 { "ERssFceFipPkt", 0, 1 }, 7640 { NULL } 7641}; 7642 7643static void 7644tp_la_show(struct sbuf *sb, uint64_t *p, int idx) 7645{ 7646 7647 field_desc_show(sb, *p, tp_la0); 7648} 7649 7650static void 7651tp_la_show2(struct sbuf *sb, uint64_t *p, int idx) 7652{ 7653 7654 if (idx) 7655 sbuf_printf(sb, "\n"); 7656 field_desc_show(sb, p[0], tp_la0); 7657 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 7658 field_desc_show(sb, p[1], tp_la0); 7659} 7660 7661static void 7662tp_la_show3(struct sbuf *sb, uint64_t *p, int idx) 7663{ 7664 7665 if (idx) 7666 sbuf_printf(sb, "\n"); 7667 field_desc_show(sb, p[0], tp_la0); 7668 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL) 7669 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1); 7670} 7671 7672static int 7673sysctl_tp_la(SYSCTL_HANDLER_ARGS) 7674{ 7675 struct adapter *sc = arg1; 7676 struct sbuf *sb; 7677 uint64_t *buf, *p; 7678 int rc; 7679 u_int i, inc; 7680 void (*show_func)(struct sbuf *, uint64_t *, int); 7681 7682 rc = sysctl_wire_old_buffer(req, 0); 7683 if (rc != 0) 7684 return (rc); 7685 7686 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7687 if (sb == NULL) 7688 return (ENOMEM); 7689 7690 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK); 7691 7692 t4_tp_read_la(sc, buf, NULL); 7693 p = buf; 7694 7695 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) { 7696 case 2: 7697 inc = 2; 7698 show_func = tp_la_show2; 7699 break; 7700 case 3: 7701 inc = 2; 7702 show_func = tp_la_show3; 7703 break; 7704 default: 7705 inc = 1; 7706 show_func = tp_la_show; 7707 } 7708 7709 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc) 7710 (*show_func)(sb, p, i); 7711 7712 rc = sbuf_finish(sb); 7713 sbuf_delete(sb); 7714 free(buf, M_CXGBE); 7715 return (rc); 7716} 7717 7718static int 7719sysctl_tx_rate(SYSCTL_HANDLER_ARGS) 7720{ 7721 struct adapter *sc = arg1; 7722 struct sbuf *sb; 7723 int rc; 7724 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN]; 7725 7726 rc = sysctl_wire_old_buffer(req, 0); 7727 if (rc != 0) 7728 return (rc); 7729 7730 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req); 7731 if (sb == NULL) 7732 return (ENOMEM); 7733 7734 t4_get_chan_txrate(sc, nrate, orate); 7735 7736 if (sc->chip_params->nchan > 2) { 7737 sbuf_printf(sb, " channel 0 channel 1" 7738 " channel 2 channel 3\n"); 7739 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n", 7740 nrate[0], nrate[1], nrate[2], nrate[3]); 7741 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju", 7742 orate[0], orate[1], orate[2], orate[3]); 7743 } else { 7744 sbuf_printf(sb, " channel 0 channel 1\n"); 7745 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n", 7746 nrate[0], nrate[1]); 7747 sbuf_printf(sb, "Offload B/s: %10ju %10ju", 7748 orate[0], orate[1]); 7749 } 7750 7751 rc = sbuf_finish(sb); 7752 sbuf_delete(sb); 7753 7754 return (rc); 7755} 7756 7757static int 7758sysctl_ulprx_la(SYSCTL_HANDLER_ARGS) 7759{ 7760 struct adapter *sc = arg1; 7761 struct sbuf *sb; 7762 uint32_t *buf, *p; 7763 int rc, i; 7764 7765 rc = sysctl_wire_old_buffer(req, 0); 7766 if (rc != 0) 7767 return (rc); 7768 7769 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7770 if (sb == NULL) 7771 return (ENOMEM); 7772 7773 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE, 7774 M_ZERO | M_WAITOK); 7775 7776 t4_ulprx_read_la(sc, buf); 7777 p = buf; 7778 7779 sbuf_printf(sb, " Pcmd Type Message" 7780 " Data"); 7781 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) { 7782 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x", 7783 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]); 7784 } 7785 7786 rc = sbuf_finish(sb); 7787 sbuf_delete(sb); 7788 free(buf, M_CXGBE); 7789 return (rc); 7790} 7791 7792static int 7793sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS) 7794{ 7795 struct adapter *sc = arg1; 7796 struct sbuf *sb; 7797 int rc, v; 7798 7799 MPASS(chip_id(sc) >= CHELSIO_T5); 7800 7801 rc = sysctl_wire_old_buffer(req, 0); 7802 if (rc != 0) 7803 return (rc); 7804 7805 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7806 if (sb == NULL) 7807 return (ENOMEM); 7808 7809 v = t4_read_reg(sc, A_SGE_STAT_CFG); 7810 if (G_STATSOURCE_T5(v) == 7) { 7811 int mode; 7812 7813 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v); 7814 if (mode == 0) { 7815 sbuf_printf(sb, "total %d, incomplete %d", 7816 t4_read_reg(sc, A_SGE_STAT_TOTAL), 7817 t4_read_reg(sc, A_SGE_STAT_MATCH)); 7818 } else if (mode == 1) { 7819 sbuf_printf(sb, "total %d, data overflow %d", 7820 t4_read_reg(sc, A_SGE_STAT_TOTAL), 7821 t4_read_reg(sc, A_SGE_STAT_MATCH)); 7822 } else { 7823 sbuf_printf(sb, "unknown mode %d", mode); 7824 } 7825 } 7826 rc = sbuf_finish(sb); 7827 sbuf_delete(sb); 7828 7829 return (rc); 7830} 7831 7832static int 7833sysctl_tc_params(SYSCTL_HANDLER_ARGS) 7834{ 7835 struct adapter *sc = arg1; 7836 struct tx_sched_class *tc; 7837 struct t4_sched_class_params p; 7838 struct sbuf *sb; 7839 int i, rc, port_id, flags, mbps, gbps; 7840 7841 rc = sysctl_wire_old_buffer(req, 0); 7842 if (rc != 0) 7843 return (rc); 7844 7845 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req); 7846 if (sb == NULL) 7847 return (ENOMEM); 7848 7849 port_id = arg2 >> 16; 7850 MPASS(port_id < sc->params.nports); 7851 MPASS(sc->port[port_id] != NULL); 7852 i = arg2 & 0xffff; 7853 MPASS(i < sc->chip_params->nsched_cls); 7854 tc = &sc->port[port_id]->tc[i]; 7855 7856 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 7857 "t4tc_p"); 7858 if (rc) 7859 goto done; 7860 flags = tc->flags; 7861 p = tc->params; 7862 end_synchronized_op(sc, LOCK_HELD); 7863 7864 if ((flags & TX_SC_OK) == 0) { 7865 sbuf_printf(sb, "none"); 7866 goto done; 7867 } 7868 7869 if (p.level == SCHED_CLASS_LEVEL_CL_WRR) { 7870 sbuf_printf(sb, "cl-wrr weight %u", p.weight); 7871 goto done; 7872 } else if (p.level == SCHED_CLASS_LEVEL_CL_RL) 7873 sbuf_printf(sb, "cl-rl"); 7874 else if (p.level == SCHED_CLASS_LEVEL_CH_RL) 7875 sbuf_printf(sb, "ch-rl"); 7876 else { 7877 rc = ENXIO; 7878 goto done; 7879 } 7880 7881 if (p.ratemode == SCHED_CLASS_RATEMODE_REL) { 7882 /* XXX: top speed or actual link speed? */ 7883 gbps = port_top_speed(sc->port[port_id]); 7884 sbuf_printf(sb, " %u%% of %uGbps", p.maxrate, gbps); 7885 } 7886 else if (p.ratemode == SCHED_CLASS_RATEMODE_ABS) { 7887 switch (p.rateunit) { 7888 case SCHED_CLASS_RATEUNIT_BITS: 7889 mbps = p.maxrate / 1000; 7890 gbps = p.maxrate / 1000000; 7891 if (p.maxrate == gbps * 1000000) 7892 sbuf_printf(sb, " %uGbps", gbps); 7893 else if (p.maxrate == mbps * 1000) 7894 sbuf_printf(sb, " %uMbps", mbps); 7895 else 7896 sbuf_printf(sb, " %uKbps", p.maxrate); 7897 break; 7898 case SCHED_CLASS_RATEUNIT_PKTS: 7899 sbuf_printf(sb, " %upps", p.maxrate); 7900 break; 7901 default: 7902 rc = ENXIO; 7903 goto done; 7904 } 7905 } 7906 7907 switch (p.mode) { 7908 case SCHED_CLASS_MODE_CLASS: 7909 sbuf_printf(sb, " aggregate"); 7910 break; 7911 case SCHED_CLASS_MODE_FLOW: 7912 sbuf_printf(sb, " per-flow"); 7913 break; 7914 default: 7915 rc = ENXIO; 7916 goto done; 7917 } 7918 7919done: 7920 if (rc == 0) 7921 rc = sbuf_finish(sb); 7922 sbuf_delete(sb); 7923 7924 return (rc); 7925} 7926#endif 7927 7928#ifdef TCP_OFFLOAD 7929static void 7930unit_conv(char *buf, size_t len, u_int val, u_int factor) 7931{ 7932 u_int rem = val % factor; 7933 7934 if (rem == 0) 7935 snprintf(buf, len, "%u", val / factor); 7936 else { 7937 while (rem % 10 == 0) 7938 rem /= 10; 7939 snprintf(buf, len, "%u.%u", val / factor, rem); 7940 } 7941} 7942 7943static int 7944sysctl_tp_tick(SYSCTL_HANDLER_ARGS) 7945{ 7946 struct adapter *sc = arg1; 7947 char buf[16]; 7948 u_int res, re; 7949 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 7950 7951 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 7952 switch (arg2) { 7953 case 0: 7954 /* timer_tick */ 7955 re = G_TIMERRESOLUTION(res); 7956 break; 7957 case 1: 7958 /* TCP timestamp tick */ 7959 re = G_TIMESTAMPRESOLUTION(res); 7960 break; 7961 case 2: 7962 /* DACK tick */ 7963 re = G_DELAYEDACKRESOLUTION(res); 7964 break; 7965 default: 7966 return (EDOOFUS); 7967 } 7968 7969 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000); 7970 7971 return (sysctl_handle_string(oidp, buf, sizeof(buf), req)); 7972} 7973 7974static int 7975sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS) 7976{ 7977 struct adapter *sc = arg1; 7978 u_int res, dack_re, v; 7979 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 7980 7981 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION); 7982 dack_re = G_DELAYEDACKRESOLUTION(res); 7983 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER); 7984 7985 return (sysctl_handle_int(oidp, &v, 0, req)); 7986} 7987 7988static int 7989sysctl_tp_timer(SYSCTL_HANDLER_ARGS) 7990{ 7991 struct adapter *sc = arg1; 7992 int reg = arg2; 7993 u_int tre; 7994 u_long tp_tick_us, v; 7995 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk; 7996 7997 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX || 7998 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX || 7999 reg == A_TP_KEEP_IDLE || A_TP_KEEP_INTVL || reg == A_TP_INIT_SRTT || 8000 reg == A_TP_FINWAIT2_TIMER); 8001 8002 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION)); 8003 tp_tick_us = (cclk_ps << tre) / 1000000; 8004 8005 if (reg == A_TP_INIT_SRTT) 8006 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg)); 8007 else 8008 v = tp_tick_us * t4_read_reg(sc, reg); 8009 8010 return (sysctl_handle_long(oidp, &v, 0, req)); 8011} 8012#endif 8013 8014static uint32_t 8015fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf) 8016{ 8017 uint32_t mode; 8018 8019 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR | 8020 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT; 8021 8022 if (fconf & F_FRAGMENTATION) 8023 mode |= T4_FILTER_IP_FRAGMENT; 8024 8025 if (fconf & F_MPSHITTYPE) 8026 mode |= T4_FILTER_MPS_HIT_TYPE; 8027 8028 if (fconf & F_MACMATCH) 8029 mode |= T4_FILTER_MAC_IDX; 8030 8031 if (fconf & F_ETHERTYPE) 8032 mode |= T4_FILTER_ETH_TYPE; 8033 8034 if (fconf & F_PROTOCOL) 8035 mode |= T4_FILTER_IP_PROTO; 8036 8037 if (fconf & F_TOS) 8038 mode |= T4_FILTER_IP_TOS; 8039 8040 if (fconf & F_VLAN) 8041 mode |= T4_FILTER_VLAN; 8042 8043 if (fconf & F_VNIC_ID) { 8044 mode |= T4_FILTER_VNIC; 8045 if (iconf & F_VNIC) 8046 mode |= T4_FILTER_IC_VNIC; 8047 } 8048 8049 if (fconf & F_PORT) 8050 mode |= T4_FILTER_PORT; 8051 8052 if (fconf & F_FCOE) 8053 mode |= T4_FILTER_FCoE; 8054 8055 return (mode); 8056} 8057 8058static uint32_t 8059mode_to_fconf(uint32_t mode) 8060{ 8061 uint32_t fconf = 0; 8062 8063 if (mode & T4_FILTER_IP_FRAGMENT) 8064 fconf |= F_FRAGMENTATION; 8065 8066 if (mode & T4_FILTER_MPS_HIT_TYPE) 8067 fconf |= F_MPSHITTYPE; 8068 8069 if (mode & T4_FILTER_MAC_IDX) 8070 fconf |= F_MACMATCH; 8071 8072 if (mode & T4_FILTER_ETH_TYPE) 8073 fconf |= F_ETHERTYPE; 8074 8075 if (mode & T4_FILTER_IP_PROTO) 8076 fconf |= F_PROTOCOL; 8077 8078 if (mode & T4_FILTER_IP_TOS) 8079 fconf |= F_TOS; 8080 8081 if (mode & T4_FILTER_VLAN) 8082 fconf |= F_VLAN; 8083 8084 if (mode & T4_FILTER_VNIC) 8085 fconf |= F_VNIC_ID; 8086 8087 if (mode & T4_FILTER_PORT) 8088 fconf |= F_PORT; 8089 8090 if (mode & T4_FILTER_FCoE) 8091 fconf |= F_FCOE; 8092 8093 return (fconf); 8094} 8095 8096static uint32_t 8097mode_to_iconf(uint32_t mode) 8098{ 8099 8100 if (mode & T4_FILTER_IC_VNIC) 8101 return (F_VNIC); 8102 return (0); 8103} 8104 8105static int check_fspec_against_fconf_iconf(struct adapter *sc, 8106 struct t4_filter_specification *fs) 8107{ 8108 struct tp_params *tpp = &sc->params.tp; 8109 uint32_t fconf = 0; 8110 8111 if (fs->val.frag || fs->mask.frag) 8112 fconf |= F_FRAGMENTATION; 8113 8114 if (fs->val.matchtype || fs->mask.matchtype) 8115 fconf |= F_MPSHITTYPE; 8116 8117 if (fs->val.macidx || fs->mask.macidx) 8118 fconf |= F_MACMATCH; 8119 8120 if (fs->val.ethtype || fs->mask.ethtype) 8121 fconf |= F_ETHERTYPE; 8122 8123 if (fs->val.proto || fs->mask.proto) 8124 fconf |= F_PROTOCOL; 8125 8126 if (fs->val.tos || fs->mask.tos) 8127 fconf |= F_TOS; 8128 8129 if (fs->val.vlan_vld || fs->mask.vlan_vld) 8130 fconf |= F_VLAN; 8131 8132 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) { 8133 fconf |= F_VNIC_ID; 8134 if (tpp->ingress_config & F_VNIC) 8135 return (EINVAL); 8136 } 8137 8138 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) { 8139 fconf |= F_VNIC_ID; 8140 if ((tpp->ingress_config & F_VNIC) == 0) 8141 return (EINVAL); 8142 } 8143 8144 if (fs->val.iport || fs->mask.iport) 8145 fconf |= F_PORT; 8146 8147 if (fs->val.fcoe || fs->mask.fcoe) 8148 fconf |= F_FCOE; 8149 8150 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map) 8151 return (E2BIG); 8152 8153 return (0); 8154} 8155 8156static int 8157get_filter_mode(struct adapter *sc, uint32_t *mode) 8158{ 8159 struct tp_params *tpp = &sc->params.tp; 8160 8161 /* 8162 * We trust the cached values of the relevant TP registers. This means 8163 * things work reliably only if writes to those registers are always via 8164 * t4_set_filter_mode. 8165 */ 8166 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config); 8167 8168 return (0); 8169} 8170 8171static int 8172set_filter_mode(struct adapter *sc, uint32_t mode) 8173{ 8174 struct tp_params *tpp = &sc->params.tp; 8175 uint32_t fconf, iconf; 8176 int rc; 8177 8178 iconf = mode_to_iconf(mode); 8179 if ((iconf ^ tpp->ingress_config) & F_VNIC) { 8180 /* 8181 * For now we just complain if A_TP_INGRESS_CONFIG is not 8182 * already set to the correct value for the requested filter 8183 * mode. It's not clear if it's safe to write to this register 8184 * on the fly. (And we trust the cached value of the register). 8185 */ 8186 return (EBUSY); 8187 } 8188 8189 fconf = mode_to_fconf(mode); 8190 8191 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 8192 "t4setfm"); 8193 if (rc) 8194 return (rc); 8195 8196 if (sc->tids.ftids_in_use > 0) { 8197 rc = EBUSY; 8198 goto done; 8199 } 8200 8201#ifdef TCP_OFFLOAD 8202 if (uld_active(sc, ULD_TOM)) { 8203 rc = EBUSY; 8204 goto done; 8205 } 8206#endif 8207 8208 rc = -t4_set_filter_mode(sc, fconf); 8209done: 8210 end_synchronized_op(sc, LOCK_HELD); 8211 return (rc); 8212} 8213 8214static inline uint64_t 8215get_filter_hits(struct adapter *sc, uint32_t fid) 8216{ 8217 uint32_t tcb_addr; 8218 8219 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) + 8220 (fid + sc->tids.ftid_base) * TCB_SIZE; 8221 8222 if (is_t4(sc)) { 8223 uint64_t hits; 8224 8225 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8); 8226 return (be64toh(hits)); 8227 } else { 8228 uint32_t hits; 8229 8230 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4); 8231 return (be32toh(hits)); 8232 } 8233} 8234 8235static int 8236get_filter(struct adapter *sc, struct t4_filter *t) 8237{ 8238 int i, rc, nfilters = sc->tids.nftids; 8239 struct filter_entry *f; 8240 8241 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK, 8242 "t4getf"); 8243 if (rc) 8244 return (rc); 8245 8246 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL || 8247 t->idx >= nfilters) { 8248 t->idx = 0xffffffff; 8249 goto done; 8250 } 8251 8252 f = &sc->tids.ftid_tab[t->idx]; 8253 for (i = t->idx; i < nfilters; i++, f++) { 8254 if (f->valid) { 8255 t->idx = i; 8256 t->l2tidx = f->l2t ? f->l2t->idx : 0; 8257 t->smtidx = f->smtidx; 8258 if (f->fs.hitcnts) 8259 t->hits = get_filter_hits(sc, t->idx); 8260 else 8261 t->hits = UINT64_MAX; 8262 t->fs = f->fs; 8263 8264 goto done; 8265 } 8266 } 8267 8268 t->idx = 0xffffffff; 8269done: 8270 end_synchronized_op(sc, LOCK_HELD); 8271 return (0); 8272} 8273 8274static int 8275set_filter(struct adapter *sc, struct t4_filter *t) 8276{ 8277 unsigned int nfilters, nports; 8278 struct filter_entry *f; 8279 int i, rc; 8280 8281 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf"); 8282 if (rc) 8283 return (rc); 8284 8285 nfilters = sc->tids.nftids; 8286 nports = sc->params.nports; 8287 8288 if (nfilters == 0) { 8289 rc = ENOTSUP; 8290 goto done; 8291 } 8292 8293 if (t->idx >= nfilters) { 8294 rc = EINVAL; 8295 goto done; 8296 } 8297 8298 /* Validate against the global filter mode and ingress config */ 8299 rc = check_fspec_against_fconf_iconf(sc, &t->fs); 8300 if (rc != 0) 8301 goto done; 8302 8303 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) { 8304 rc = EINVAL; 8305 goto done; 8306 } 8307 8308 if (t->fs.val.iport >= nports) { 8309 rc = EINVAL; 8310 goto done; 8311 } 8312 8313 /* Can't specify an iq if not steering to it */ 8314 if (!t->fs.dirsteer && t->fs.iq) { 8315 rc = EINVAL; 8316 goto done; 8317 } 8318 8319 /* IPv6 filter idx must be 4 aligned */ 8320 if (t->fs.type == 1 && 8321 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) { 8322 rc = EINVAL; 8323 goto done; 8324 } 8325 8326 if (!(sc->flags & FULL_INIT_DONE) && 8327 ((rc = adapter_full_init(sc)) != 0)) 8328 goto done; 8329 8330 if (sc->tids.ftid_tab == NULL) { 8331 KASSERT(sc->tids.ftids_in_use == 0, 8332 ("%s: no memory allocated but filters_in_use > 0", 8333 __func__)); 8334 8335 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) * 8336 nfilters, M_CXGBE, M_NOWAIT | M_ZERO); 8337 if (sc->tids.ftid_tab == NULL) { 8338 rc = ENOMEM; 8339 goto done; 8340 } 8341 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF); 8342 } 8343 8344 for (i = 0; i < 4; i++) { 8345 f = &sc->tids.ftid_tab[t->idx + i]; 8346 8347 if (f->pending || f->valid) { 8348 rc = EBUSY; 8349 goto done; 8350 } 8351 if (f->locked) { 8352 rc = EPERM; 8353 goto done; 8354 } 8355 8356 if (t->fs.type == 0) 8357 break; 8358 } 8359 8360 f = &sc->tids.ftid_tab[t->idx]; 8361 f->fs = t->fs; 8362 8363 rc = set_filter_wr(sc, t->idx); 8364done: 8365 end_synchronized_op(sc, 0); 8366 8367 if (rc == 0) { 8368 mtx_lock(&sc->tids.ftid_lock); 8369 for (;;) { 8370 if (f->pending == 0) { 8371 rc = f->valid ? 0 : EIO; 8372 break; 8373 } 8374 8375 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock, 8376 PCATCH, "t4setfw", 0)) { 8377 rc = EINPROGRESS; 8378 break; 8379 } 8380 } 8381 mtx_unlock(&sc->tids.ftid_lock); 8382 } 8383 return (rc); 8384} 8385 8386static int 8387del_filter(struct adapter *sc, struct t4_filter *t) 8388{ 8389 unsigned int nfilters; 8390 struct filter_entry *f; 8391 int rc; 8392 8393 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf"); 8394 if (rc) 8395 return (rc); 8396 8397 nfilters = sc->tids.nftids; 8398 8399 if (nfilters == 0) { 8400 rc = ENOTSUP; 8401 goto done; 8402 } 8403 8404 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 || 8405 t->idx >= nfilters) { 8406 rc = EINVAL; 8407 goto done; 8408 } 8409 8410 if (!(sc->flags & FULL_INIT_DONE)) { 8411 rc = EAGAIN; 8412 goto done; 8413 } 8414 8415 f = &sc->tids.ftid_tab[t->idx]; 8416 8417 if (f->pending) { 8418 rc = EBUSY; 8419 goto done; 8420 } 8421 if (f->locked) { 8422 rc = EPERM; 8423 goto done; 8424 } 8425 8426 if (f->valid) { 8427 t->fs = f->fs; /* extra info for the caller */ 8428 rc = del_filter_wr(sc, t->idx); 8429 } 8430 8431done: 8432 end_synchronized_op(sc, 0); 8433 8434 if (rc == 0) { 8435 mtx_lock(&sc->tids.ftid_lock); 8436 for (;;) { 8437 if (f->pending == 0) { 8438 rc = f->valid ? EIO : 0; 8439 break; 8440 } 8441 8442 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock, 8443 PCATCH, "t4delfw", 0)) { 8444 rc = EINPROGRESS; 8445 break; 8446 } 8447 } 8448 mtx_unlock(&sc->tids.ftid_lock); 8449 } 8450 8451 return (rc); 8452} 8453 8454static void 8455clear_filter(struct filter_entry *f) 8456{ 8457 if (f->l2t) 8458 t4_l2t_release(f->l2t); 8459 8460 bzero(f, sizeof (*f)); 8461} 8462 8463static int 8464set_filter_wr(struct adapter *sc, int fidx) 8465{ 8466 struct filter_entry *f = &sc->tids.ftid_tab[fidx]; 8467 struct fw_filter_wr *fwr; 8468 unsigned int ftid, vnic_vld, vnic_vld_mask; 8469 struct wrq_cookie cookie; 8470 8471 ASSERT_SYNCHRONIZED_OP(sc); 8472 8473 if (f->fs.newdmac || f->fs.newvlan) { 8474 /* This filter needs an L2T entry; allocate one. */ 8475 f->l2t = t4_l2t_alloc_switching(sc->l2t); 8476 if (f->l2t == NULL) 8477 return (EAGAIN); 8478 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport, 8479 f->fs.dmac)) { 8480 t4_l2t_release(f->l2t); 8481 f->l2t = NULL; 8482 return (ENOMEM); 8483 } 8484 } 8485 8486 /* Already validated against fconf, iconf */ 8487 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0); 8488 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0); 8489 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld) 8490 vnic_vld = 1; 8491 else 8492 vnic_vld = 0; 8493 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld) 8494 vnic_vld_mask = 1; 8495 else 8496 vnic_vld_mask = 0; 8497 8498 ftid = sc->tids.ftid_base + fidx; 8499 8500 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie); 8501 if (fwr == NULL) 8502 return (ENOMEM); 8503 bzero(fwr, sizeof(*fwr)); 8504 8505 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR)); 8506 fwr->len16_pkd = htobe32(FW_LEN16(*fwr)); 8507 fwr->tid_to_iq = 8508 htobe32(V_FW_FILTER_WR_TID(ftid) | 8509 V_FW_FILTER_WR_RQTYPE(f->fs.type) | 8510 V_FW_FILTER_WR_NOREPLY(0) | 8511 V_FW_FILTER_WR_IQ(f->fs.iq)); 8512 fwr->del_filter_to_l2tix = 8513 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) | 8514 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) | 8515 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) | 8516 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) | 8517 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) | 8518 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) | 8519 V_FW_FILTER_WR_DMAC(f->fs.newdmac) | 8520 V_FW_FILTER_WR_SMAC(f->fs.newsmac) | 8521 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT || 8522 f->fs.newvlan == VLAN_REWRITE) | 8523 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE || 8524 f->fs.newvlan == VLAN_REWRITE) | 8525 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) | 8526 V_FW_FILTER_WR_TXCHAN(f->fs.eport) | 8527 V_FW_FILTER_WR_PRIO(f->fs.prio) | 8528 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0)); 8529 fwr->ethtype = htobe16(f->fs.val.ethtype); 8530 fwr->ethtypem = htobe16(f->fs.mask.ethtype); 8531 fwr->frag_to_ovlan_vldm = 8532 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) | 8533 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) | 8534 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) | 8535 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) | 8536 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) | 8537 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask)); 8538 fwr->smac_sel = 0; 8539 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) | 8540 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id)); 8541 fwr->maci_to_matchtypem = 8542 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) | 8543 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) | 8544 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) | 8545 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) | 8546 V_FW_FILTER_WR_PORT(f->fs.val.iport) | 8547 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) | 8548 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) | 8549 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype)); 8550 fwr->ptcl = f->fs.val.proto; 8551 fwr->ptclm = f->fs.mask.proto; 8552 fwr->ttyp = f->fs.val.tos; 8553 fwr->ttypm = f->fs.mask.tos; 8554 fwr->ivlan = htobe16(f->fs.val.vlan); 8555 fwr->ivlanm = htobe16(f->fs.mask.vlan); 8556 fwr->ovlan = htobe16(f->fs.val.vnic); 8557 fwr->ovlanm = htobe16(f->fs.mask.vnic); 8558 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip)); 8559 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm)); 8560 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip)); 8561 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm)); 8562 fwr->lp = htobe16(f->fs.val.dport); 8563 fwr->lpm = htobe16(f->fs.mask.dport); 8564 fwr->fp = htobe16(f->fs.val.sport); 8565 fwr->fpm = htobe16(f->fs.mask.sport); 8566 if (f->fs.newsmac) 8567 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma)); 8568 8569 f->pending = 1; 8570 sc->tids.ftids_in_use++; 8571 8572 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie); 8573 return (0); 8574} 8575 8576static int 8577del_filter_wr(struct adapter *sc, int fidx) 8578{ 8579 struct filter_entry *f = &sc->tids.ftid_tab[fidx]; 8580 struct fw_filter_wr *fwr; 8581 unsigned int ftid; 8582 struct wrq_cookie cookie; 8583 8584 ftid = sc->tids.ftid_base + fidx; 8585 8586 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie); 8587 if (fwr == NULL) 8588 return (ENOMEM); 8589 bzero(fwr, sizeof (*fwr)); 8590 8591 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id); 8592 8593 f->pending = 1; 8594 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie); 8595 return (0); 8596} 8597 8598int 8599t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 8600{ 8601 struct adapter *sc = iq->adapter; 8602 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1); 8603 unsigned int idx = GET_TID(rpl); 8604 unsigned int rc; 8605 struct filter_entry *f; 8606 8607 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__, 8608 rss->opcode)); 8609 MPASS(iq == &sc->sge.fwq); 8610 MPASS(is_ftid(sc, idx)); 8611 8612 idx -= sc->tids.ftid_base; 8613 f = &sc->tids.ftid_tab[idx]; 8614 rc = G_COOKIE(rpl->cookie); 8615 8616 mtx_lock(&sc->tids.ftid_lock); 8617 if (rc == FW_FILTER_WR_FLT_ADDED) { 8618 KASSERT(f->pending, ("%s: filter[%u] isn't pending.", 8619 __func__, idx)); 8620 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff; 8621 f->pending = 0; /* asynchronous setup completed */ 8622 f->valid = 1; 8623 } else { 8624 if (rc != FW_FILTER_WR_FLT_DELETED) { 8625 /* Add or delete failed, display an error */ 8626 log(LOG_ERR, 8627 "filter %u setup failed with error %u\n", 8628 idx, rc); 8629 } 8630 8631 clear_filter(f); 8632 sc->tids.ftids_in_use--; 8633 } 8634 wakeup(&sc->tids.ftid_tab); 8635 mtx_unlock(&sc->tids.ftid_lock); 8636 8637 return (0); 8638} 8639 8640static int 8641set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 8642{ 8643 8644 MPASS(iq->set_tcb_rpl != NULL); 8645 return (iq->set_tcb_rpl(iq, rss, m)); 8646} 8647 8648static int 8649l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 8650{ 8651 8652 MPASS(iq->l2t_write_rpl != NULL); 8653 return (iq->l2t_write_rpl(iq, rss, m)); 8654} 8655 8656static int 8657get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt) 8658{ 8659 int rc; 8660 8661 if (cntxt->cid > M_CTXTQID) 8662 return (EINVAL); 8663 8664 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS && 8665 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM) 8666 return (EINVAL); 8667 8668 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt"); 8669 if (rc) 8670 return (rc); 8671 8672 if (sc->flags & FW_OK) { 8673 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id, 8674 &cntxt->data[0]); 8675 if (rc == 0) 8676 goto done; 8677 } 8678 8679 /* 8680 * Read via firmware failed or wasn't even attempted. Read directly via 8681 * the backdoor. 8682 */ 8683 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]); 8684done: 8685 end_synchronized_op(sc, 0); 8686 return (rc); 8687} 8688 8689static int 8690load_fw(struct adapter *sc, struct t4_data *fw) 8691{ 8692 int rc; 8693 uint8_t *fw_data; 8694 8695 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw"); 8696 if (rc) 8697 return (rc); 8698 8699 if (sc->flags & FULL_INIT_DONE) { 8700 rc = EBUSY; 8701 goto done; 8702 } 8703 8704 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK); 8705 if (fw_data == NULL) { 8706 rc = ENOMEM; 8707 goto done; 8708 } 8709 8710 rc = copyin(fw->data, fw_data, fw->len); 8711 if (rc == 0) 8712 rc = -t4_load_fw(sc, fw_data, fw->len); 8713 8714 free(fw_data, M_CXGBE); 8715done: 8716 end_synchronized_op(sc, 0); 8717 return (rc); 8718} 8719 8720static int 8721load_cfg(struct adapter *sc, struct t4_data *cfg) 8722{ 8723 int rc; 8724 uint8_t *cfg_data = NULL; 8725 8726 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf"); 8727 if (rc) 8728 return (rc); 8729 8730 if (cfg->len == 0) { 8731 /* clear */ 8732 rc = -t4_load_cfg(sc, NULL, 0); 8733 goto done; 8734 } 8735 8736 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK); 8737 if (cfg_data == NULL) { 8738 rc = ENOMEM; 8739 goto done; 8740 } 8741 8742 rc = copyin(cfg->data, cfg_data, cfg->len); 8743 if (rc == 0) 8744 rc = -t4_load_cfg(sc, cfg_data, cfg->len); 8745 8746 free(cfg_data, M_CXGBE); 8747done: 8748 end_synchronized_op(sc, 0); 8749 return (rc); 8750} 8751 8752#define MAX_READ_BUF_SIZE (128 * 1024) 8753static int 8754read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr) 8755{ 8756 uint32_t addr, remaining, n; 8757 uint32_t *buf; 8758 int rc; 8759 uint8_t *dst; 8760 8761 rc = validate_mem_range(sc, mr->addr, mr->len); 8762 if (rc != 0) 8763 return (rc); 8764 8765 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK); 8766 addr = mr->addr; 8767 remaining = mr->len; 8768 dst = (void *)mr->data; 8769 8770 while (remaining) { 8771 n = min(remaining, MAX_READ_BUF_SIZE); 8772 read_via_memwin(sc, 2, addr, buf, n); 8773 8774 rc = copyout(buf, dst, n); 8775 if (rc != 0) 8776 break; 8777 8778 dst += n; 8779 remaining -= n; 8780 addr += n; 8781 } 8782 8783 free(buf, M_CXGBE); 8784 return (rc); 8785} 8786#undef MAX_READ_BUF_SIZE 8787 8788static int 8789read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd) 8790{ 8791 int rc; 8792 8793 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports) 8794 return (EINVAL); 8795 8796 if (i2cd->len > sizeof(i2cd->data)) 8797 return (EFBIG); 8798 8799 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd"); 8800 if (rc) 8801 return (rc); 8802 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr, 8803 i2cd->offset, i2cd->len, &i2cd->data[0]); 8804 end_synchronized_op(sc, 0); 8805 8806 return (rc); 8807} 8808 8809static int 8810in_range(int val, int lo, int hi) 8811{ 8812 8813 return (val < 0 || (val <= hi && val >= lo)); 8814} 8815 8816static int 8817set_sched_class_config(struct adapter *sc, int minmax) 8818{ 8819 int rc; 8820 8821 if (minmax < 0) 8822 return (EINVAL); 8823 8824 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4sscc"); 8825 if (rc) 8826 return (rc); 8827 rc = -t4_sched_config(sc, FW_SCHED_TYPE_PKTSCHED, minmax, 1); 8828 end_synchronized_op(sc, 0); 8829 8830 return (rc); 8831} 8832 8833static int 8834set_sched_class_params(struct adapter *sc, struct t4_sched_class_params *p, 8835 int sleep_ok) 8836{ 8837 int rc, top_speed, fw_level, fw_mode, fw_rateunit, fw_ratemode; 8838 struct port_info *pi; 8839 struct tx_sched_class *tc; 8840 8841 if (p->level == SCHED_CLASS_LEVEL_CL_RL) 8842 fw_level = FW_SCHED_PARAMS_LEVEL_CL_RL; 8843 else if (p->level == SCHED_CLASS_LEVEL_CL_WRR) 8844 fw_level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 8845 else if (p->level == SCHED_CLASS_LEVEL_CH_RL) 8846 fw_level = FW_SCHED_PARAMS_LEVEL_CH_RL; 8847 else 8848 return (EINVAL); 8849 8850 if (p->mode == SCHED_CLASS_MODE_CLASS) 8851 fw_mode = FW_SCHED_PARAMS_MODE_CLASS; 8852 else if (p->mode == SCHED_CLASS_MODE_FLOW) 8853 fw_mode = FW_SCHED_PARAMS_MODE_FLOW; 8854 else 8855 return (EINVAL); 8856 8857 if (p->rateunit == SCHED_CLASS_RATEUNIT_BITS) 8858 fw_rateunit = FW_SCHED_PARAMS_UNIT_BITRATE; 8859 else if (p->rateunit == SCHED_CLASS_RATEUNIT_PKTS) 8860 fw_rateunit = FW_SCHED_PARAMS_UNIT_PKTRATE; 8861 else 8862 return (EINVAL); 8863 8864 if (p->ratemode == SCHED_CLASS_RATEMODE_REL) 8865 fw_ratemode = FW_SCHED_PARAMS_RATE_REL; 8866 else if (p->ratemode == SCHED_CLASS_RATEMODE_ABS) 8867 fw_ratemode = FW_SCHED_PARAMS_RATE_ABS; 8868 else 8869 return (EINVAL); 8870 8871 /* Vet our parameters ... */ 8872 if (!in_range(p->channel, 0, sc->chip_params->nchan - 1)) 8873 return (ERANGE); 8874 8875 pi = sc->port[sc->chan_map[p->channel]]; 8876 if (pi == NULL) 8877 return (ENXIO); 8878 MPASS(pi->tx_chan == p->channel); 8879 top_speed = port_top_speed(pi) * 1000000; /* Gbps -> Kbps */ 8880 8881 if (!in_range(p->cl, 0, sc->chip_params->nsched_cls) || 8882 !in_range(p->minrate, 0, top_speed) || 8883 !in_range(p->maxrate, 0, top_speed) || 8884 !in_range(p->weight, 0, 100)) 8885 return (ERANGE); 8886 8887 /* 8888 * Translate any unset parameters into the firmware's 8889 * nomenclature and/or fail the call if the parameters 8890 * are required ... 8891 */ 8892 if (p->rateunit < 0 || p->ratemode < 0 || p->channel < 0 || p->cl < 0) 8893 return (EINVAL); 8894 8895 if (p->minrate < 0) 8896 p->minrate = 0; 8897 if (p->maxrate < 0) { 8898 if (p->level == SCHED_CLASS_LEVEL_CL_RL || 8899 p->level == SCHED_CLASS_LEVEL_CH_RL) 8900 return (EINVAL); 8901 else 8902 p->maxrate = 0; 8903 } 8904 if (p->weight < 0) { 8905 if (p->level == SCHED_CLASS_LEVEL_CL_WRR) 8906 return (EINVAL); 8907 else 8908 p->weight = 0; 8909 } 8910 if (p->pktsize < 0) { 8911 if (p->level == SCHED_CLASS_LEVEL_CL_RL || 8912 p->level == SCHED_CLASS_LEVEL_CH_RL) 8913 return (EINVAL); 8914 else 8915 p->pktsize = 0; 8916 } 8917 8918 rc = begin_synchronized_op(sc, NULL, 8919 sleep_ok ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4sscp"); 8920 if (rc) 8921 return (rc); 8922 tc = &pi->tc[p->cl]; 8923 tc->params = *p; 8924 rc = -t4_sched_params(sc, FW_SCHED_TYPE_PKTSCHED, fw_level, fw_mode, 8925 fw_rateunit, fw_ratemode, p->channel, p->cl, p->minrate, p->maxrate, 8926 p->weight, p->pktsize, sleep_ok); 8927 if (rc == 0) 8928 tc->flags |= TX_SC_OK; 8929 else { 8930 /* 8931 * Unknown state at this point, see tc->params for what was 8932 * attempted. 8933 */ 8934 tc->flags &= ~TX_SC_OK; 8935 } 8936 end_synchronized_op(sc, sleep_ok ? 0 : LOCK_HELD); 8937 8938 return (rc); 8939} 8940 8941int 8942t4_set_sched_class(struct adapter *sc, struct t4_sched_params *p) 8943{ 8944 8945 if (p->type != SCHED_CLASS_TYPE_PACKET) 8946 return (EINVAL); 8947 8948 if (p->subcmd == SCHED_CLASS_SUBCMD_CONFIG) 8949 return (set_sched_class_config(sc, p->u.config.minmax)); 8950 8951 if (p->subcmd == SCHED_CLASS_SUBCMD_PARAMS) 8952 return (set_sched_class_params(sc, &p->u.params, 1)); 8953 8954 return (EINVAL); 8955} 8956 8957int 8958t4_set_sched_queue(struct adapter *sc, struct t4_sched_queue *p) 8959{ 8960 struct port_info *pi = NULL; 8961 struct vi_info *vi; 8962 struct sge_txq *txq; 8963 uint32_t fw_mnem, fw_queue, fw_class; 8964 int i, rc; 8965 8966 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsq"); 8967 if (rc) 8968 return (rc); 8969 8970 if (p->port >= sc->params.nports) { 8971 rc = EINVAL; 8972 goto done; 8973 } 8974 8975 /* XXX: Only supported for the main VI. */ 8976 pi = sc->port[p->port]; 8977 vi = &pi->vi[0]; 8978 if (!(vi->flags & VI_INIT_DONE)) { 8979 /* tx queues not set up yet */ 8980 rc = EAGAIN; 8981 goto done; 8982 } 8983 8984 if (!in_range(p->queue, 0, vi->ntxq - 1) || 8985 !in_range(p->cl, 0, sc->chip_params->nsched_cls - 1)) { 8986 rc = EINVAL; 8987 goto done; 8988 } 8989 8990 /* 8991 * Create a template for the FW_PARAMS_CMD mnemonic and value (TX 8992 * Scheduling Class in this case). 8993 */ 8994 fw_mnem = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 8995 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH)); 8996 fw_class = p->cl < 0 ? 0xffffffff : p->cl; 8997 8998 /* 8999 * If op.queue is non-negative, then we're only changing the scheduling 9000 * on a single specified TX queue. 9001 */ 9002 if (p->queue >= 0) { 9003 txq = &sc->sge.txq[vi->first_txq + p->queue]; 9004 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id)); 9005 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, 9006 &fw_class); 9007 goto done; 9008 } 9009 9010 /* 9011 * Change the scheduling on all the TX queues for the 9012 * interface. 9013 */ 9014 for_each_txq(vi, i, txq) { 9015 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id)); 9016 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue, 9017 &fw_class); 9018 if (rc) 9019 goto done; 9020 } 9021 9022 rc = 0; 9023done: 9024 end_synchronized_op(sc, 0); 9025 return (rc); 9026} 9027 9028int 9029t4_os_find_pci_capability(struct adapter *sc, int cap) 9030{ 9031 int i; 9032 9033 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0); 9034} 9035 9036int 9037t4_os_pci_save_state(struct adapter *sc) 9038{ 9039 device_t dev; 9040 struct pci_devinfo *dinfo; 9041 9042 dev = sc->dev; 9043 dinfo = device_get_ivars(dev); 9044 9045 pci_cfg_save(dev, dinfo, 0); 9046 return (0); 9047} 9048 9049int 9050t4_os_pci_restore_state(struct adapter *sc) 9051{ 9052 device_t dev; 9053 struct pci_devinfo *dinfo; 9054 9055 dev = sc->dev; 9056 dinfo = device_get_ivars(dev); 9057 9058 pci_cfg_restore(dev, dinfo); 9059 return (0); 9060} 9061 9062void 9063t4_os_portmod_changed(const struct adapter *sc, int idx) 9064{ 9065 struct port_info *pi = sc->port[idx]; 9066 struct vi_info *vi; 9067 struct ifnet *ifp; 9068 int v; 9069 static const char *mod_str[] = { 9070 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM" 9071 }; 9072 9073 for_each_vi(pi, v, vi) { 9074 build_medialist(pi, &vi->media); 9075 } 9076 9077 ifp = pi->vi[0].ifp; 9078 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 9079 if_printf(ifp, "transceiver unplugged.\n"); 9080 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 9081 if_printf(ifp, "unknown transceiver inserted.\n"); 9082 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 9083 if_printf(ifp, "unsupported transceiver inserted.\n"); 9084 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) { 9085 if_printf(ifp, "%s transceiver inserted.\n", 9086 mod_str[pi->mod_type]); 9087 } else { 9088 if_printf(ifp, "transceiver (type %d) inserted.\n", 9089 pi->mod_type); 9090 } 9091} 9092 9093void 9094t4_os_link_changed(struct adapter *sc, int idx, int link_stat) 9095{ 9096 struct port_info *pi = sc->port[idx]; 9097 struct vi_info *vi; 9098 struct ifnet *ifp; 9099 int v; 9100 9101 for_each_vi(pi, v, vi) { 9102 ifp = vi->ifp; 9103 if (ifp == NULL) 9104 continue; 9105 9106 if (link_stat) { 9107 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed); 9108 if_link_state_change(ifp, LINK_STATE_UP); 9109 } else { 9110 if_link_state_change(ifp, LINK_STATE_DOWN); 9111 } 9112 } 9113} 9114 9115void 9116t4_iterate(void (*func)(struct adapter *, void *), void *arg) 9117{ 9118 struct adapter *sc; 9119 9120 sx_slock(&t4_list_lock); 9121 SLIST_FOREACH(sc, &t4_list, link) { 9122 /* 9123 * func should not make any assumptions about what state sc is 9124 * in - the only guarantee is that sc->sc_lock is a valid lock. 9125 */ 9126 func(sc, arg); 9127 } 9128 sx_sunlock(&t4_list_lock); 9129} 9130 9131static int 9132t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 9133 struct thread *td) 9134{ 9135 int rc; 9136 struct adapter *sc = dev->si_drv1; 9137 9138 rc = priv_check(td, PRIV_DRIVER); 9139 if (rc != 0) 9140 return (rc); 9141 9142 switch (cmd) { 9143 case CHELSIO_T4_GETREG: { 9144 struct t4_reg *edata = (struct t4_reg *)data; 9145 9146 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9147 return (EFAULT); 9148 9149 if (edata->size == 4) 9150 edata->val = t4_read_reg(sc, edata->addr); 9151 else if (edata->size == 8) 9152 edata->val = t4_read_reg64(sc, edata->addr); 9153 else 9154 return (EINVAL); 9155 9156 break; 9157 } 9158 case CHELSIO_T4_SETREG: { 9159 struct t4_reg *edata = (struct t4_reg *)data; 9160 9161 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 9162 return (EFAULT); 9163 9164 if (edata->size == 4) { 9165 if (edata->val & 0xffffffff00000000) 9166 return (EINVAL); 9167 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 9168 } else if (edata->size == 8) 9169 t4_write_reg64(sc, edata->addr, edata->val); 9170 else 9171 return (EINVAL); 9172 break; 9173 } 9174 case CHELSIO_T4_REGDUMP: { 9175 struct t4_regdump *regs = (struct t4_regdump *)data; 9176 int reglen = t4_get_regs_len(sc); 9177 uint8_t *buf; 9178 9179 if (regs->len < reglen) { 9180 regs->len = reglen; /* hint to the caller */ 9181 return (ENOBUFS); 9182 } 9183 9184 regs->len = reglen; 9185 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 9186 get_regs(sc, regs, buf); 9187 rc = copyout(buf, regs->data, reglen); 9188 free(buf, M_CXGBE); 9189 break; 9190 } 9191 case CHELSIO_T4_GET_FILTER_MODE: 9192 rc = get_filter_mode(sc, (uint32_t *)data); 9193 break; 9194 case CHELSIO_T4_SET_FILTER_MODE: 9195 rc = set_filter_mode(sc, *(uint32_t *)data); 9196 break; 9197 case CHELSIO_T4_GET_FILTER: 9198 rc = get_filter(sc, (struct t4_filter *)data); 9199 break; 9200 case CHELSIO_T4_SET_FILTER: 9201 rc = set_filter(sc, (struct t4_filter *)data); 9202 break; 9203 case CHELSIO_T4_DEL_FILTER: 9204 rc = del_filter(sc, (struct t4_filter *)data); 9205 break; 9206 case CHELSIO_T4_GET_SGE_CONTEXT: 9207 rc = get_sge_context(sc, (struct t4_sge_context *)data); 9208 break; 9209 case CHELSIO_T4_LOAD_FW: 9210 rc = load_fw(sc, (struct t4_data *)data); 9211 break; 9212 case CHELSIO_T4_GET_MEM: 9213 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data); 9214 break; 9215 case CHELSIO_T4_GET_I2C: 9216 rc = read_i2c(sc, (struct t4_i2c_data *)data); 9217 break; 9218 case CHELSIO_T4_CLEAR_STATS: { 9219 int i, v; 9220 u_int port_id = *(uint32_t *)data; 9221 struct port_info *pi; 9222 struct vi_info *vi; 9223 9224 if (port_id >= sc->params.nports) 9225 return (EINVAL); 9226 pi = sc->port[port_id]; 9227 if (pi == NULL) 9228 return (EIO); 9229 9230 /* MAC stats */ 9231 t4_clr_port_stats(sc, pi->tx_chan); 9232 pi->tx_parse_error = 0; 9233 mtx_lock(&sc->reg_lock); 9234 for_each_vi(pi, v, vi) { 9235 if (vi->flags & VI_INIT_DONE) 9236 t4_clr_vi_stats(sc, vi->viid); 9237 } 9238 mtx_unlock(&sc->reg_lock); 9239 9240 /* 9241 * Since this command accepts a port, clear stats for 9242 * all VIs on this port. 9243 */ 9244 for_each_vi(pi, v, vi) { 9245 if (vi->flags & VI_INIT_DONE) { 9246 struct sge_rxq *rxq; 9247 struct sge_txq *txq; 9248 struct sge_wrq *wrq; 9249 9250 for_each_rxq(vi, i, rxq) { 9251#if defined(INET) || defined(INET6) 9252 rxq->lro.lro_queued = 0; 9253 rxq->lro.lro_flushed = 0; 9254#endif 9255 rxq->rxcsum = 0; 9256 rxq->vlan_extraction = 0; 9257 } 9258 9259 for_each_txq(vi, i, txq) { 9260 txq->txcsum = 0; 9261 txq->tso_wrs = 0; 9262 txq->vlan_insertion = 0; 9263 txq->imm_wrs = 0; 9264 txq->sgl_wrs = 0; 9265 txq->txpkt_wrs = 0; 9266 txq->txpkts0_wrs = 0; 9267 txq->txpkts1_wrs = 0; 9268 txq->txpkts0_pkts = 0; 9269 txq->txpkts1_pkts = 0; 9270 mp_ring_reset_stats(txq->r); 9271 } 9272 9273#ifdef TCP_OFFLOAD 9274 /* nothing to clear for each ofld_rxq */ 9275 9276 for_each_ofld_txq(vi, i, wrq) { 9277 wrq->tx_wrs_direct = 0; 9278 wrq->tx_wrs_copied = 0; 9279 } 9280#endif 9281 9282 if (IS_MAIN_VI(vi)) { 9283 wrq = &sc->sge.ctrlq[pi->port_id]; 9284 wrq->tx_wrs_direct = 0; 9285 wrq->tx_wrs_copied = 0; 9286 } 9287 } 9288 } 9289 break; 9290 } 9291 case CHELSIO_T4_SCHED_CLASS: 9292 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 9293 break; 9294 case CHELSIO_T4_SCHED_QUEUE: 9295 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 9296 break; 9297 case CHELSIO_T4_GET_TRACER: 9298 rc = t4_get_tracer(sc, (struct t4_tracer *)data); 9299 break; 9300 case CHELSIO_T4_SET_TRACER: 9301 rc = t4_set_tracer(sc, (struct t4_tracer *)data); 9302 break; 9303 case CHELSIO_T4_LOAD_CFG: 9304 rc = load_cfg(sc, (struct t4_data *)data); 9305 break; 9306 default: 9307 rc = ENOTTY; 9308 } 9309 9310 return (rc); 9311} 9312 9313void 9314t4_db_full(struct adapter *sc) 9315{ 9316 9317 CXGBE_UNIMPLEMENTED(__func__); 9318} 9319 9320void 9321t4_db_dropped(struct adapter *sc) 9322{ 9323 9324 CXGBE_UNIMPLEMENTED(__func__); 9325} 9326 9327#ifdef TCP_OFFLOAD 9328void 9329t4_iscsi_init(struct adapter *sc, u_int tag_mask, const u_int *pgsz_order) 9330{ 9331 9332 t4_write_reg(sc, A_ULP_RX_ISCSI_TAGMASK, tag_mask); 9333 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, V_HPZ0(pgsz_order[0]) | 9334 V_HPZ1(pgsz_order[1]) | V_HPZ2(pgsz_order[2]) | 9335 V_HPZ3(pgsz_order[3])); 9336} 9337 9338static int 9339toe_capability(struct vi_info *vi, int enable) 9340{ 9341 int rc; 9342 struct port_info *pi = vi->pi; 9343 struct adapter *sc = pi->adapter; 9344 9345 ASSERT_SYNCHRONIZED_OP(sc); 9346 9347 if (!is_offload(sc)) 9348 return (ENODEV); 9349 9350 if (enable) { 9351 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) { 9352 /* TOE is already enabled. */ 9353 return (0); 9354 } 9355 9356 /* 9357 * We need the port's queues around so that we're able to send 9358 * and receive CPLs to/from the TOE even if the ifnet for this 9359 * port has never been UP'd administratively. 9360 */ 9361 if (!(vi->flags & VI_INIT_DONE)) { 9362 rc = vi_full_init(vi); 9363 if (rc) 9364 return (rc); 9365 } 9366 if (!(pi->vi[0].flags & VI_INIT_DONE)) { 9367 rc = vi_full_init(&pi->vi[0]); 9368 if (rc) 9369 return (rc); 9370 } 9371 9372 if (isset(&sc->offload_map, pi->port_id)) { 9373 /* TOE is enabled on another VI of this port. */ 9374 pi->uld_vis++; 9375 return (0); 9376 } 9377 9378 if (!uld_active(sc, ULD_TOM)) { 9379 rc = t4_activate_uld(sc, ULD_TOM); 9380 if (rc == EAGAIN) { 9381 log(LOG_WARNING, 9382 "You must kldload t4_tom.ko before trying " 9383 "to enable TOE on a cxgbe interface.\n"); 9384 } 9385 if (rc != 0) 9386 return (rc); 9387 KASSERT(sc->tom_softc != NULL, 9388 ("%s: TOM activated but softc NULL", __func__)); 9389 KASSERT(uld_active(sc, ULD_TOM), 9390 ("%s: TOM activated but flag not set", __func__)); 9391 } 9392 9393 /* Activate iWARP and iSCSI too, if the modules are loaded. */ 9394 if (!uld_active(sc, ULD_IWARP)) 9395 (void) t4_activate_uld(sc, ULD_IWARP); 9396 if (!uld_active(sc, ULD_ISCSI)) 9397 (void) t4_activate_uld(sc, ULD_ISCSI); 9398 9399 pi->uld_vis++; 9400 setbit(&sc->offload_map, pi->port_id); 9401 } else { 9402 pi->uld_vis--; 9403 9404 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0) 9405 return (0); 9406 9407 KASSERT(uld_active(sc, ULD_TOM), 9408 ("%s: TOM never initialized?", __func__)); 9409 clrbit(&sc->offload_map, pi->port_id); 9410 } 9411 9412 return (0); 9413} 9414 9415/* 9416 * Add an upper layer driver to the global list. 9417 */ 9418int 9419t4_register_uld(struct uld_info *ui) 9420{ 9421 int rc = 0; 9422 struct uld_info *u; 9423 9424 sx_xlock(&t4_uld_list_lock); 9425 SLIST_FOREACH(u, &t4_uld_list, link) { 9426 if (u->uld_id == ui->uld_id) { 9427 rc = EEXIST; 9428 goto done; 9429 } 9430 } 9431 9432 SLIST_INSERT_HEAD(&t4_uld_list, ui, link); 9433 ui->refcount = 0; 9434done: 9435 sx_xunlock(&t4_uld_list_lock); 9436 return (rc); 9437} 9438 9439int 9440t4_unregister_uld(struct uld_info *ui) 9441{ 9442 int rc = EINVAL; 9443 struct uld_info *u; 9444 9445 sx_xlock(&t4_uld_list_lock); 9446 9447 SLIST_FOREACH(u, &t4_uld_list, link) { 9448 if (u == ui) { 9449 if (ui->refcount > 0) { 9450 rc = EBUSY; 9451 goto done; 9452 } 9453 9454 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link); 9455 rc = 0; 9456 goto done; 9457 } 9458 } 9459done: 9460 sx_xunlock(&t4_uld_list_lock); 9461 return (rc); 9462} 9463 9464int 9465t4_activate_uld(struct adapter *sc, int id) 9466{ 9467 int rc; 9468 struct uld_info *ui; 9469 9470 ASSERT_SYNCHRONIZED_OP(sc); 9471 9472 if (id < 0 || id > ULD_MAX) 9473 return (EINVAL); 9474 rc = EAGAIN; /* kldoad the module with this ULD and try again. */ 9475 9476 sx_slock(&t4_uld_list_lock); 9477 9478 SLIST_FOREACH(ui, &t4_uld_list, link) { 9479 if (ui->uld_id == id) { 9480 if (!(sc->flags & FULL_INIT_DONE)) { 9481 rc = adapter_full_init(sc); 9482 if (rc != 0) 9483 break; 9484 } 9485 9486 rc = ui->activate(sc); 9487 if (rc == 0) { 9488 setbit(&sc->active_ulds, id); 9489 ui->refcount++; 9490 } 9491 break; 9492 } 9493 } 9494 9495 sx_sunlock(&t4_uld_list_lock); 9496 9497 return (rc); 9498} 9499 9500int 9501t4_deactivate_uld(struct adapter *sc, int id) 9502{ 9503 int rc; 9504 struct uld_info *ui; 9505 9506 ASSERT_SYNCHRONIZED_OP(sc); 9507 9508 if (id < 0 || id > ULD_MAX) 9509 return (EINVAL); 9510 rc = ENXIO; 9511 9512 sx_slock(&t4_uld_list_lock); 9513 9514 SLIST_FOREACH(ui, &t4_uld_list, link) { 9515 if (ui->uld_id == id) { 9516 rc = ui->deactivate(sc); 9517 if (rc == 0) { 9518 clrbit(&sc->active_ulds, id); 9519 ui->refcount--; 9520 } 9521 break; 9522 } 9523 } 9524 9525 sx_sunlock(&t4_uld_list_lock); 9526 9527 return (rc); 9528} 9529 9530int 9531uld_active(struct adapter *sc, int uld_id) 9532{ 9533 9534 MPASS(uld_id >= 0 && uld_id <= ULD_MAX); 9535 9536 return (isset(&sc->active_ulds, uld_id)); 9537} 9538#endif 9539 9540/* 9541 * Come up with reasonable defaults for some of the tunables, provided they're 9542 * not set by the user (in which case we'll use the values as is). 9543 */ 9544static void 9545tweak_tunables(void) 9546{ 9547 int nc = mp_ncpus; /* our snapshot of the number of CPUs */ 9548 9549 if (t4_ntxq10g < 1) { 9550#ifdef RSS 9551 t4_ntxq10g = rss_getnumbuckets(); 9552#else 9553 t4_ntxq10g = min(nc, NTXQ_10G); 9554#endif 9555 } 9556 9557 if (t4_ntxq1g < 1) { 9558#ifdef RSS 9559 /* XXX: way too many for 1GbE? */ 9560 t4_ntxq1g = rss_getnumbuckets(); 9561#else 9562 t4_ntxq1g = min(nc, NTXQ_1G); 9563#endif 9564 } 9565 9566 if (t4_ntxq_vi < 1) 9567 t4_ntxq_vi = min(nc, NTXQ_VI); 9568 9569 if (t4_nrxq10g < 1) { 9570#ifdef RSS 9571 t4_nrxq10g = rss_getnumbuckets(); 9572#else 9573 t4_nrxq10g = min(nc, NRXQ_10G); 9574#endif 9575 } 9576 9577 if (t4_nrxq1g < 1) { 9578#ifdef RSS 9579 /* XXX: way too many for 1GbE? */ 9580 t4_nrxq1g = rss_getnumbuckets(); 9581#else 9582 t4_nrxq1g = min(nc, NRXQ_1G); 9583#endif 9584 } 9585 9586 if (t4_nrxq_vi < 1) 9587 t4_nrxq_vi = min(nc, NRXQ_VI); 9588 9589#ifdef TCP_OFFLOAD 9590 if (t4_nofldtxq10g < 1) 9591 t4_nofldtxq10g = min(nc, NOFLDTXQ_10G); 9592 9593 if (t4_nofldtxq1g < 1) 9594 t4_nofldtxq1g = min(nc, NOFLDTXQ_1G); 9595 9596 if (t4_nofldtxq_vi < 1) 9597 t4_nofldtxq_vi = min(nc, NOFLDTXQ_VI); 9598 9599 if (t4_nofldrxq10g < 1) 9600 t4_nofldrxq10g = min(nc, NOFLDRXQ_10G); 9601 9602 if (t4_nofldrxq1g < 1) 9603 t4_nofldrxq1g = min(nc, NOFLDRXQ_1G); 9604 9605 if (t4_nofldrxq_vi < 1) 9606 t4_nofldrxq_vi = min(nc, NOFLDRXQ_VI); 9607 9608 if (t4_toecaps_allowed == -1) 9609 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE; 9610 9611 if (t4_rdmacaps_allowed == -1) { 9612 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP | 9613 FW_CAPS_CONFIG_RDMA_RDMAC; 9614 } 9615 9616 if (t4_iscsicaps_allowed == -1) { 9617 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU | 9618 FW_CAPS_CONFIG_ISCSI_TARGET_PDU | 9619 FW_CAPS_CONFIG_ISCSI_T10DIF; 9620 } 9621#else 9622 if (t4_toecaps_allowed == -1) 9623 t4_toecaps_allowed = 0; 9624 9625 if (t4_rdmacaps_allowed == -1) 9626 t4_rdmacaps_allowed = 0; 9627 9628 if (t4_iscsicaps_allowed == -1) 9629 t4_iscsicaps_allowed = 0; 9630#endif 9631 9632#ifdef DEV_NETMAP 9633 if (t4_nnmtxq_vi < 1) 9634 t4_nnmtxq_vi = min(nc, NNMTXQ_VI); 9635 9636 if (t4_nnmrxq_vi < 1) 9637 t4_nnmrxq_vi = min(nc, NNMRXQ_VI); 9638#endif 9639 9640 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS) 9641 t4_tmr_idx_10g = TMR_IDX_10G; 9642 9643 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS) 9644 t4_pktc_idx_10g = PKTC_IDX_10G; 9645 9646 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS) 9647 t4_tmr_idx_1g = TMR_IDX_1G; 9648 9649 if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS) 9650 t4_pktc_idx_1g = PKTC_IDX_1G; 9651 9652 if (t4_qsize_txq < 128) 9653 t4_qsize_txq = 128; 9654 9655 if (t4_qsize_rxq < 128) 9656 t4_qsize_rxq = 128; 9657 while (t4_qsize_rxq & 7) 9658 t4_qsize_rxq++; 9659 9660 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX; 9661} 9662 9663#ifdef DDB 9664static void 9665t4_dump_tcb(struct adapter *sc, int tid) 9666{ 9667 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos; 9668 9669 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2); 9670 save = t4_read_reg(sc, reg); 9671 base = sc->memwin[2].mw_base; 9672 9673 /* Dump TCB for the tid */ 9674 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE); 9675 tcb_addr += tid * TCB_SIZE; 9676 9677 if (is_t4(sc)) { 9678 pf = 0; 9679 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */ 9680 } else { 9681 pf = V_PFNUM(sc->pf); 9682 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */ 9683 } 9684 t4_write_reg(sc, reg, win_pos | pf); 9685 t4_read_reg(sc, reg); 9686 9687 off = tcb_addr - win_pos; 9688 for (i = 0; i < 4; i++) { 9689 uint32_t buf[8]; 9690 for (j = 0; j < 8; j++, off += 4) 9691 buf[j] = htonl(t4_read_reg(sc, base + off)); 9692 9693 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n", 9694 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], 9695 buf[7]); 9696 } 9697 9698 t4_write_reg(sc, reg, save); 9699 t4_read_reg(sc, reg); 9700} 9701 9702static void 9703t4_dump_devlog(struct adapter *sc) 9704{ 9705 struct devlog_params *dparams = &sc->params.devlog; 9706 struct fw_devlog_e e; 9707 int i, first, j, m, nentries, rc; 9708 uint64_t ftstamp = UINT64_MAX; 9709 9710 if (dparams->start == 0) { 9711 db_printf("devlog params not valid\n"); 9712 return; 9713 } 9714 9715 nentries = dparams->size / sizeof(struct fw_devlog_e); 9716 m = fwmtype_to_hwmtype(dparams->memtype); 9717 9718 /* Find the first entry. */ 9719 first = -1; 9720 for (i = 0; i < nentries && !db_pager_quit; i++) { 9721 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 9722 sizeof(e), (void *)&e); 9723 if (rc != 0) 9724 break; 9725 9726 if (e.timestamp == 0) 9727 break; 9728 9729 e.timestamp = be64toh(e.timestamp); 9730 if (e.timestamp < ftstamp) { 9731 ftstamp = e.timestamp; 9732 first = i; 9733 } 9734 } 9735 9736 if (first == -1) 9737 return; 9738 9739 i = first; 9740 do { 9741 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e), 9742 sizeof(e), (void *)&e); 9743 if (rc != 0) 9744 return; 9745 9746 if (e.timestamp == 0) 9747 return; 9748 9749 e.timestamp = be64toh(e.timestamp); 9750 e.seqno = be32toh(e.seqno); 9751 for (j = 0; j < 8; j++) 9752 e.params[j] = be32toh(e.params[j]); 9753 9754 db_printf("%10d %15ju %8s %8s ", 9755 e.seqno, e.timestamp, 9756 (e.level < nitems(devlog_level_strings) ? 9757 devlog_level_strings[e.level] : "UNKNOWN"), 9758 (e.facility < nitems(devlog_facility_strings) ? 9759 devlog_facility_strings[e.facility] : "UNKNOWN")); 9760 db_printf(e.fmt, e.params[0], e.params[1], e.params[2], 9761 e.params[3], e.params[4], e.params[5], e.params[6], 9762 e.params[7]); 9763 9764 if (++i == nentries) 9765 i = 0; 9766 } while (i != first && !db_pager_quit); 9767} 9768 9769static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table); 9770_DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table); 9771 9772DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL) 9773{ 9774 device_t dev; 9775 int t; 9776 bool valid; 9777 9778 valid = false; 9779 t = db_read_token(); 9780 if (t == tIDENT) { 9781 dev = device_lookup_by_name(db_tok_string); 9782 valid = true; 9783 } 9784 db_skip_to_eol(); 9785 if (!valid) { 9786 db_printf("usage: show t4 devlog <nexus>\n"); 9787 return; 9788 } 9789 9790 if (dev == NULL) { 9791 db_printf("device not found\n"); 9792 return; 9793 } 9794 9795 t4_dump_devlog(device_get_softc(dev)); 9796} 9797 9798DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL) 9799{ 9800 device_t dev; 9801 int radix, tid, t; 9802 bool valid; 9803 9804 valid = false; 9805 radix = db_radix; 9806 db_radix = 10; 9807 t = db_read_token(); 9808 if (t == tIDENT) { 9809 dev = device_lookup_by_name(db_tok_string); 9810 t = db_read_token(); 9811 if (t == tNUMBER) { 9812 tid = db_tok_number; 9813 valid = true; 9814 } 9815 } 9816 db_radix = radix; 9817 db_skip_to_eol(); 9818 if (!valid) { 9819 db_printf("usage: show t4 tcb <nexus> <tid>\n"); 9820 return; 9821 } 9822 9823 if (dev == NULL) { 9824 db_printf("device not found\n"); 9825 return; 9826 } 9827 if (tid < 0) { 9828 db_printf("invalid tid\n"); 9829 return; 9830 } 9831 9832 t4_dump_tcb(device_get_softc(dev), tid); 9833} 9834#endif 9835 9836static struct sx mlu; /* mod load unload */ 9837SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload"); 9838 9839static int 9840mod_event(module_t mod, int cmd, void *arg) 9841{ 9842 int rc = 0; 9843 static int loaded = 0; 9844 9845 switch (cmd) { 9846 case MOD_LOAD: 9847 sx_xlock(&mlu); 9848 if (loaded++ == 0) { 9849 t4_sge_modload(); 9850 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl); 9851 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl); 9852 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt); 9853 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt); 9854 sx_init(&t4_list_lock, "T4/T5 adapters"); 9855 SLIST_INIT(&t4_list); 9856#ifdef TCP_OFFLOAD 9857 sx_init(&t4_uld_list_lock, "T4/T5 ULDs"); 9858 SLIST_INIT(&t4_uld_list); 9859#endif 9860 t4_tracer_modload(); 9861 tweak_tunables(); 9862 } 9863 sx_xunlock(&mlu); 9864 break; 9865 9866 case MOD_UNLOAD: 9867 sx_xlock(&mlu); 9868 if (--loaded == 0) { 9869 int tries; 9870 9871 sx_slock(&t4_list_lock); 9872 if (!SLIST_EMPTY(&t4_list)) { 9873 rc = EBUSY; 9874 sx_sunlock(&t4_list_lock); 9875 goto done_unload; 9876 } 9877#ifdef TCP_OFFLOAD 9878 sx_slock(&t4_uld_list_lock); 9879 if (!SLIST_EMPTY(&t4_uld_list)) { 9880 rc = EBUSY; 9881 sx_sunlock(&t4_uld_list_lock); 9882 sx_sunlock(&t4_list_lock); 9883 goto done_unload; 9884 } 9885#endif 9886 tries = 0; 9887 while (tries++ < 5 && t4_sge_extfree_refs() != 0) { 9888 uprintf("%ju clusters with custom free routine " 9889 "still is use.\n", t4_sge_extfree_refs()); 9890 pause("t4unload", 2 * hz); 9891 } 9892#ifdef TCP_OFFLOAD 9893 sx_sunlock(&t4_uld_list_lock); 9894#endif 9895 sx_sunlock(&t4_list_lock); 9896 9897 if (t4_sge_extfree_refs() == 0) { 9898 t4_tracer_modunload(); 9899#ifdef TCP_OFFLOAD 9900 sx_destroy(&t4_uld_list_lock); 9901#endif 9902 sx_destroy(&t4_list_lock); 9903 t4_sge_modunload(); 9904 loaded = 0; 9905 } else { 9906 rc = EBUSY; 9907 loaded++; /* undo earlier decrement */ 9908 } 9909 } 9910done_unload: 9911 sx_xunlock(&mlu); 9912 break; 9913 } 9914 9915 return (rc); 9916} 9917 9918static devclass_t t4_devclass, t5_devclass, t6_devclass; 9919static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass; 9920static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass; 9921 9922DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0); 9923MODULE_VERSION(t4nex, 1); 9924MODULE_DEPEND(t4nex, firmware, 1, 1, 1); 9925#ifdef DEV_NETMAP 9926MODULE_DEPEND(t4nex, netmap, 1, 1, 1); 9927#endif /* DEV_NETMAP */ 9928 9929DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0); 9930MODULE_VERSION(t5nex, 1); 9931MODULE_DEPEND(t5nex, firmware, 1, 1, 1); 9932#ifdef DEV_NETMAP 9933MODULE_DEPEND(t5nex, netmap, 1, 1, 1); 9934#endif /* DEV_NETMAP */ 9935 9936DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0); 9937MODULE_VERSION(t6nex, 1); 9938MODULE_DEPEND(t6nex, firmware, 1, 1, 1); 9939#ifdef DEV_NETMAP 9940MODULE_DEPEND(t6nex, netmap, 1, 1, 1); 9941#endif /* DEV_NETMAP */ 9942 9943DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0); 9944MODULE_VERSION(cxgbe, 1); 9945 9946DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0); 9947MODULE_VERSION(cxl, 1); 9948 9949DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0); 9950MODULE_VERSION(cc, 1); 9951 9952DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0); 9953MODULE_VERSION(vcxgbe, 1); 9954 9955DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0); 9956MODULE_VERSION(vcxl, 1); 9957 9958DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0); 9959MODULE_VERSION(vcc, 1); 9960