t4_ioctl.h revision 302408
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/11/sys/dev/cxgbe/t4_ioctl.h 301520 2016-06-06 20:42:46Z np $ 28 * 29 */ 30 31#ifndef __T4_IOCTL_H__ 32#define __T4_IOCTL_H__ 33 34#include <sys/types.h> 35#include <net/ethernet.h> 36 37/* 38 * Ioctl commands specific to this driver. 39 */ 40enum { 41 T4_GETREG = 0x40, /* read register */ 42 T4_SETREG, /* write register */ 43 T4_REGDUMP, /* dump of all registers */ 44 T4_GET_FILTER_MODE, /* get global filter mode */ 45 T4_SET_FILTER_MODE, /* set global filter mode */ 46 T4_GET_FILTER, /* get information about a filter */ 47 T4_SET_FILTER, /* program a filter */ 48 T4_DEL_FILTER, /* delete a filter */ 49 T4_GET_SGE_CONTEXT, /* get SGE context for a queue */ 50 T4_LOAD_FW, /* flash firmware */ 51 T4_GET_MEM, /* read memory */ 52 T4_GET_I2C, /* read from i2c addressible device */ 53 T4_CLEAR_STATS, /* clear a port's MAC statistics */ 54 T4_SET_OFLD_POLICY, /* Set offload policy */ 55 T4_SET_SCHED_CLASS, /* set sched class */ 56 T4_SET_SCHED_QUEUE, /* set queue class */ 57 T4_GET_TRACER, /* get information about a tracer */ 58 T4_SET_TRACER, /* program a tracer */ 59}; 60 61struct t4_reg { 62 uint32_t addr; 63 uint32_t size; 64 uint64_t val; 65}; 66 67#define T4_REGDUMP_SIZE (160 * 1024) 68#define T5_REGDUMP_SIZE (332 * 1024) 69struct t4_regdump { 70 uint32_t version; 71 uint32_t len; /* bytes */ 72 uint32_t *data; 73}; 74 75struct t4_data { 76 uint32_t len; 77 uint8_t *data; 78}; 79 80struct t4_i2c_data { 81 uint8_t port_id; 82 uint8_t dev_addr; 83 uint8_t offset; 84 uint8_t len; 85 uint8_t data[8]; 86}; 87 88/* 89 * A hardware filter is some valid combination of these. 90 */ 91#define T4_FILTER_IPv4 0x1 /* IPv4 packet */ 92#define T4_FILTER_IPv6 0x2 /* IPv6 packet */ 93#define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ 94#define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ 95#define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ 96#define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ 97#define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ 98#define T4_FILTER_PORT 0x80 /* Physical ingress port */ 99#define T4_FILTER_VNIC 0x100 /* VNIC id or outer VLAN */ 100#define T4_FILTER_VLAN 0x200 /* VLAN ID */ 101#define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ 102#define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ 103#define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ 104#define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ 105#define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ 106#define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ 107 108#define T4_FILTER_IC_VNIC 0x80000000 /* TP Ingress Config's F_VNIC 109 bit. It indicates whether 110 T4_FILTER_VNIC bit means VNIC 111 id (PF/VF) or outer VLAN. 112 0 = oVLAN, 1 = VNIC */ 113 114/* Filter action */ 115enum { 116 FILTER_PASS = 0, /* default */ 117 FILTER_DROP, 118 FILTER_SWITCH 119}; 120 121/* 802.1q manipulation on FILTER_SWITCH */ 122enum { 123 VLAN_NOCHANGE = 0, /* default */ 124 VLAN_REMOVE, 125 VLAN_INSERT, 126 VLAN_REWRITE 127}; 128 129/* MPS match type */ 130enum { 131 UCAST_EXACT = 0, /* exact unicast match */ 132 UCAST_HASH = 1, /* inexact (hashed) unicast match */ 133 MCAST_EXACT = 2, /* exact multicast match */ 134 MCAST_HASH = 3, /* inexact (hashed) multicast match */ 135 PROMISC = 4, /* no match but port is promiscuous */ 136 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ 137 BCAST = 6, /* broadcast packet */ 138}; 139 140/* Rx steering */ 141enum { 142 DST_MODE_QUEUE, /* queue is directly specified by filter */ 143 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ 144 DST_MODE_RSS, /* queue selected by default RSS hash lookup */ 145 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified 146 RSS subtable */ 147}; 148 149struct t4_filter_tuple { 150 /* 151 * These are always available. 152 */ 153 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ 154 uint8_t dip[16]; /* destinatin IP address (IPv4 in [3:0]) */ 155 uint16_t sport; /* source port */ 156 uint16_t dport; /* destination port */ 157 158 /* 159 * A combination of these (up to 36 bits) is available. TP_VLAN_PRI_MAP 160 * is used to select the global mode and all filters are limited to the 161 * set of fields allowed by the global mode. 162 */ 163 uint16_t vnic; /* VNIC id (PF/VF) or outer VLAN tag */ 164 uint16_t vlan; /* VLAN tag */ 165 uint16_t ethtype; /* Ethernet type */ 166 uint8_t tos; /* TOS/Traffic Type */ 167 uint8_t proto; /* protocol type */ 168 uint32_t fcoe:1; /* FCoE packet */ 169 uint32_t iport:3; /* ingress port */ 170 uint32_t matchtype:3; /* MPS match type */ 171 uint32_t frag:1; /* fragmentation extension header */ 172 uint32_t macidx:9; /* exact match MAC index */ 173 uint32_t vlan_vld:1; /* VLAN valid */ 174 uint32_t ovlan_vld:1; /* outer VLAN tag valid, value in "vnic" */ 175 uint32_t pfvf_vld:1; /* VNIC id (PF/VF) valid, value in "vnic" */ 176}; 177 178struct t4_filter_specification { 179 uint32_t hitcnts:1; /* count filter hits in TCB */ 180 uint32_t prio:1; /* filter has priority over active/server */ 181 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 182 uint32_t action:2; /* drop, pass, switch */ 183 uint32_t rpttid:1; /* report TID in RSS hash field */ 184 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 185 uint32_t iq:10; /* ingress queue */ 186 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 187 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 188 /* 1 => TCB contains IQ ID */ 189 190 /* 191 * Switch proxy/rewrite fields. An ingress packet which matches a 192 * filter with "switch" set will be looped back out as an egress 193 * packet -- potentially with some Ethernet header rewriting. 194 */ 195 uint32_t eport:2; /* egress port to switch packet out */ 196 uint32_t newdmac:1; /* rewrite destination MAC address */ 197 uint32_t newsmac:1; /* rewrite source MAC address */ 198 uint32_t newvlan:2; /* rewrite VLAN Tag */ 199 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ 200 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ 201 uint16_t vlan; /* VLAN Tag to insert */ 202 203 /* 204 * Filter rule value/mask pairs. 205 */ 206 struct t4_filter_tuple val; 207 struct t4_filter_tuple mask; 208}; 209 210struct t4_filter { 211 uint32_t idx; 212 uint16_t l2tidx; 213 uint16_t smtidx; 214 uint64_t hits; 215 struct t4_filter_specification fs; 216}; 217 218/* Tx Scheduling Class parameters */ 219struct t4_sched_class_params { 220 int8_t level; /* scheduler hierarchy level */ 221 int8_t mode; /* per-class or per-flow */ 222 int8_t rateunit; /* bit or packet rate */ 223 int8_t ratemode; /* %port relative or kbps absolute */ 224 int8_t channel; /* scheduler channel [0..N] */ 225 int8_t cl; /* scheduler class [0..N] */ 226 int32_t minrate; /* minimum rate */ 227 int32_t maxrate; /* maximum rate */ 228 int16_t weight; /* percent weight */ 229 int16_t pktsize; /* average packet size */ 230}; 231 232/* 233 * Support for "sched-class" command to allow a TX Scheduling Class to be 234 * programmed with various parameters. 235 */ 236struct t4_sched_params { 237 int8_t subcmd; /* sub-command */ 238 int8_t type; /* packet or flow */ 239 union { 240 struct { /* sub-command SCHED_CLASS_CONFIG */ 241 int8_t minmax; /* minmax enable */ 242 } config; 243 struct t4_sched_class_params params; 244 uint8_t reserved[6 + 8 * 8]; 245 } u; 246}; 247 248enum { 249 SCHED_CLASS_SUBCMD_CONFIG, /* config sub-command */ 250 SCHED_CLASS_SUBCMD_PARAMS, /* params sub-command */ 251}; 252 253enum { 254 SCHED_CLASS_TYPE_PACKET, 255}; 256 257enum { 258 SCHED_CLASS_LEVEL_CL_RL, /* class rate limiter */ 259 SCHED_CLASS_LEVEL_CL_WRR, /* class weighted round robin */ 260 SCHED_CLASS_LEVEL_CH_RL, /* channel rate limiter */ 261}; 262 263enum { 264 SCHED_CLASS_MODE_CLASS, /* per-class scheduling */ 265 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */ 266}; 267 268enum { 269 SCHED_CLASS_RATEUNIT_BITS, /* bit rate scheduling */ 270 SCHED_CLASS_RATEUNIT_PKTS, /* packet rate scheduling */ 271}; 272 273enum { 274 SCHED_CLASS_RATEMODE_REL, /* percent of port bandwidth */ 275 SCHED_CLASS_RATEMODE_ABS, /* Kb/s */ 276}; 277 278/* 279 * Support for "sched_queue" command to allow one or more NIC TX Queues to be 280 * bound to a TX Scheduling Class. 281 */ 282struct t4_sched_queue { 283 uint8_t port; 284 int8_t queue; /* queue index; -1 => all queues */ 285 int8_t cl; /* class index; -1 => unbind */ 286}; 287 288#define T4_SGE_CONTEXT_SIZE 24 289enum { 290 SGE_CONTEXT_EGRESS, 291 SGE_CONTEXT_INGRESS, 292 SGE_CONTEXT_FLM, 293 SGE_CONTEXT_CNM 294}; 295 296struct t4_sge_context { 297 uint32_t mem_id; 298 uint32_t cid; 299 uint32_t data[T4_SGE_CONTEXT_SIZE / 4]; 300}; 301 302struct t4_mem_range { 303 uint32_t addr; 304 uint32_t len; 305 uint32_t *data; 306}; 307 308#define T4_TRACE_LEN 112 309struct t4_trace_params { 310 uint32_t data[T4_TRACE_LEN / 4]; 311 uint32_t mask[T4_TRACE_LEN / 4]; 312 uint16_t snap_len; 313 uint16_t min_len; 314 uint8_t skip_ofst; 315 uint8_t skip_len; 316 uint8_t invert; 317 uint8_t port; 318}; 319 320struct t4_tracer { 321 uint8_t idx; 322 uint8_t enabled; 323 uint8_t valid; 324 struct t4_trace_params tp; 325}; 326 327#define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) 328#define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) 329#define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) 330#define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) 331#define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) 332#define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) 333#define CHELSIO_T4_SET_FILTER _IOW('f', T4_SET_FILTER, struct t4_filter) 334#define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) 335#define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \ 336 struct t4_sge_context) 337#define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data) 338#define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range) 339#define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data) 340#define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t) 341#define CHELSIO_T4_SCHED_CLASS _IOW('f', T4_SET_SCHED_CLASS, \ 342 struct t4_sched_params) 343#define CHELSIO_T4_SCHED_QUEUE _IOW('f', T4_SET_SCHED_QUEUE, \ 344 struct t4_sched_queue) 345#define CHELSIO_T4_GET_TRACER _IOWR('f', T4_GET_TRACER, struct t4_tracer) 346#define CHELSIO_T4_SET_TRACER _IOW('f', T4_SET_TRACER, struct t4_tracer) 347#endif 348