t4_ioctl.h revision 221474
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/dev/cxgbe/t4_ioctl.h 221474 2011-05-05 02:04:56Z np $ 28 * 29 */ 30 31#ifndef __T4_IOCTL_H__ 32#define __T4_IOCTL_H__ 33 34#include <sys/types.h> 35#include <net/ethernet.h> 36 37/* 38 * Ioctl commands specific to this driver. 39 */ 40enum { 41 T4_GETREG = 0x40, /* read register */ 42 T4_SETREG, /* write register */ 43 T4_REGDUMP, /* dump of all registers */ 44 T4_GET_FILTER_MODE, /* get global filter mode */ 45 T4_SET_FILTER_MODE, /* set global filter mode */ 46 T4_GET_FILTER, /* get information about a filter */ 47 T4_SET_FILTER, /* program a filter */ 48 T4_DEL_FILTER, /* delete a filter */ 49}; 50 51struct t4_reg { 52 uint32_t addr; 53 uint32_t size; 54 uint64_t val; 55}; 56 57#define T4_REGDUMP_SIZE (160 * 1024) 58struct t4_regdump { 59 uint32_t version; 60 uint32_t len; /* bytes */ 61 uint32_t *data; 62}; 63 64/* 65 * A hardware filter is some valid combination of these. 66 */ 67#define T4_FILTER_IPv4 0x1 /* IPv4 packet */ 68#define T4_FILTER_IPv6 0x2 /* IPv6 packet */ 69#define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ 70#define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ 71#define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ 72#define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ 73#define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ 74#define T4_FILTER_PORT 0x80 /* Physical ingress port */ 75#define T4_FILTER_OVLAN 0x100 /* Outer VLAN ID */ 76#define T4_FILTER_IVLAN 0x200 /* Inner VLAN ID */ 77#define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ 78#define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ 79#define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ 80#define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ 81#define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ 82#define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ 83 84/* Filter action */ 85enum { 86 FILTER_PASS = 0, /* default */ 87 FILTER_DROP, 88 FILTER_SWITCH 89}; 90 91/* 802.1q manipulation on FILTER_SWITCH */ 92enum { 93 VLAN_NOCHANGE = 0, /* default */ 94 VLAN_REMOVE, 95 VLAN_INSERT, 96 VLAN_REWRITE 97}; 98 99/* MPS match type */ 100enum { 101 UCAST_EXACT = 0, /* exact unicast match */ 102 UCAST_HASH = 1, /* inexact (hashed) unicast match */ 103 MCAST_EXACT = 2, /* exact multicast match */ 104 MCAST_HASH = 3, /* inexact (hashed) multicast match */ 105 PROMISC = 4, /* no match but port is promiscuous */ 106 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ 107 BCAST = 6, /* broadcast packet */ 108}; 109 110/* Rx steering */ 111enum { 112 DST_MODE_QUEUE, /* queue is directly specified by filter */ 113 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ 114 DST_MODE_RSS, /* queue selected by default RSS hash lookup */ 115 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified 116 RSS subtable */ 117}; 118 119struct t4_filter_tuple { 120 /* 121 * These are always available. 122 */ 123 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ 124 uint8_t dip[16]; /* destinatin IP address (IPv4 in [3:0]) */ 125 uint16_t sport; /* source port */ 126 uint16_t dport; /* destination port */ 127 128 /* 129 * A combination of these (upto 36 bits) is available. TP_VLAN_PRI_MAP 130 * is used to select the global mode and all filters are limited to the 131 * set of fields allowed by the global mode. 132 */ 133 uint16_t ovlan; /* outer VLAN */ 134 uint16_t ivlan; /* inner VLAN */ 135 uint16_t ethtype; /* Ethernet type */ 136 uint8_t tos; /* TOS/Traffic Type */ 137 uint8_t proto; /* protocol type */ 138 uint32_t fcoe:1; /* FCoE packet */ 139 uint32_t iport:3; /* ingress port */ 140 uint32_t matchtype:3; /* MPS match type */ 141 uint32_t frag:1; /* fragmentation extension header */ 142 uint32_t macidx:9; /* exact match MAC index */ 143 uint32_t ivlan_vld:1; /* inner VLAN valid */ 144 uint32_t ovlan_vld:1; /* outer VLAN valid */ 145}; 146 147struct t4_filter_specification { 148 uint32_t hitcnts:1; /* count filter hits in TCB */ 149 uint32_t prio:1; /* filter has priority over active/server */ 150 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 151 uint32_t action:2; /* drop, pass, switch */ 152 uint32_t rpttid:1; /* report TID in RSS hash field */ 153 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 154 uint32_t iq:10; /* ingress queue */ 155 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 156 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 157 /* 1 => TCB contains IQ ID */ 158 159 /* 160 * Switch proxy/rewrite fields. An ingress packet which matches a 161 * filter with "switch" set will be looped back out as an egress 162 * packet -- potentially with some Ethernet header rewriting. 163 */ 164 uint32_t eport:2; /* egress port to switch packet out */ 165 uint32_t newdmac:1; /* rewrite destination MAC address */ 166 uint32_t newsmac:1; /* rewrite source MAC address */ 167 uint32_t newvlan:2; /* rewrite VLAN Tag */ 168 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ 169 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ 170 uint16_t vlan; /* VLAN Tag to insert */ 171 172 /* 173 * Filter rule value/mask pairs. 174 */ 175 struct t4_filter_tuple val; 176 struct t4_filter_tuple mask; 177}; 178 179struct t4_filter { 180 uint32_t idx; 181 uint64_t hits; 182 struct t4_filter_specification fs; 183}; 184 185#define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) 186#define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) 187#define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) 188#define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) 189#define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) 190#define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) 191#define CHELSIO_T4_SET_FILTER _IOW('f', T4_SET_FILTER, struct t4_filter) 192#define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) 193#endif 194