t4.h revision 314775 
1/*
2 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses.  You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 *     Redistribution and use in source and binary forms, with or
11 *     without modification, are permitted provided that the following
12 *     conditions are met:
13 *
14 *      - Redistributions of source code must retain the above
15 *        copyright notice, this list of conditions and the following
16 *        disclaimer.
17 *      - Redistributions in binary form must reproduce the above
18 *        copyright notice, this list of conditions and the following
19 *        disclaimer in the documentation and/or other materials
20 *        provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 *
31 * $FreeBSD: stable/11/sys/dev/cxgbe/iw_cxgbe/t4.h 314775 2017-03-06 15:14:59Z np $
32 */
33#ifndef __T4_H__
34#define __T4_H__
35
36/*
37 * Fixme: Adding missing defines
38 */
39#define SGE_PF_KDOORBELL 0x0
40#define  QID_MASK    0xffff8000U
41#define  QID_SHIFT   15
42#define  QID(x)      ((x) << QID_SHIFT)
43#define  DBPRIO      0x00004000U
44#define  PIDX_MASK   0x00003fffU
45#define  PIDX_SHIFT  0
46#define  PIDX(x)     ((x) << PIDX_SHIFT)
47
48#define SGE_PF_GTS 0x4
49#define  INGRESSQID_MASK   0xffff0000U
50#define  INGRESSQID_SHIFT  16
51#define  INGRESSQID(x)     ((x) << INGRESSQID_SHIFT)
52#define  TIMERREG_MASK     0x0000e000U
53#define  TIMERREG_SHIFT    13
54#define  TIMERREG(x)       ((x) << TIMERREG_SHIFT)
55#define  SEINTARM_MASK     0x00001000U
56#define  SEINTARM_SHIFT    12
57#define  SEINTARM(x)       ((x) << SEINTARM_SHIFT)
58#define  CIDXINC_MASK      0x00000fffU
59#define  CIDXINC_SHIFT     0
60#define  CIDXINC(x)        ((x) << CIDXINC_SHIFT)
61
62#define T4_MAX_NUM_QP (1<<16)
63#define T4_MAX_NUM_CQ (1<<15)
64#define T4_MAX_NUM_PD (1<<15)
65#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
66#define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES)
67#define T4_MAX_IQ_SIZE (65520 - 1)
68#define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES)
69#define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1)
70#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1)
71#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1)
72#define T4_MAX_MR_SIZE (~0ULL - 1)
73#define T4_PAGESIZE_MASK 0xffff000  /* 4KB-128MB */
74#define T4_STAG_UNSET 0xffffffff
75#define T4_FW_MAJ 0
76#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
77#define A_PCIE_MA_SYNC 0x30b4
78
79struct t4_status_page {
80	__be32 rsvd1;	/* flit 0 - hw owns */
81	__be16 rsvd2;
82	__be16 qid;
83	__be16 cidx;
84	__be16 pidx;
85	u8 qp_err;	/* flit 1 - sw owns */
86	u8 db_off;
87	u8 pad;
88	u16 host_wq_pidx;
89	u16 host_cidx;
90	u16 host_pidx;
91};
92
93#define T4_EQ_ENTRY_SIZE 64
94
95#define T4_SQ_NUM_SLOTS 5
96#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
97#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
98			sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
99#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
100			sizeof(struct fw_ri_immd)))
101#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
102			sizeof(struct fw_ri_rdma_write_wr) - \
103			sizeof(struct fw_ri_immd)))
104#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
105			sizeof(struct fw_ri_rdma_write_wr) - \
106			sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
107#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
108			sizeof(struct fw_ri_immd)) & ~31UL)
109#define T4_MAX_FR_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
110
111#define T4_RQ_NUM_SLOTS 2
112#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
113#define T4_MAX_RECV_SGE 4
114
115union t4_wr {
116	struct fw_ri_res_wr res;
117	struct fw_ri_wr ri;
118	struct fw_ri_rdma_write_wr write;
119	struct fw_ri_send_wr send;
120	struct fw_ri_rdma_read_wr read;
121	struct fw_ri_bind_mw_wr bind;
122	struct fw_ri_fr_nsmr_wr fr;
123	struct fw_ri_inv_lstag_wr inv;
124	struct t4_status_page status;
125	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
126};
127
128union t4_recv_wr {
129	struct fw_ri_recv_wr recv;
130	struct t4_status_page status;
131	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
132};
133
134static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
135			       enum fw_wr_opcodes opcode, u8 flags, u8 len16)
136{
137	wqe->send.opcode = (u8)opcode;
138	wqe->send.flags = flags;
139	wqe->send.wrid = wrid;
140	wqe->send.r1[0] = 0;
141	wqe->send.r1[1] = 0;
142	wqe->send.r1[2] = 0;
143	wqe->send.len16 = len16;
144}
145
146/* CQE/AE status codes */
147#define T4_ERR_SUCCESS                     0x0
148#define T4_ERR_STAG                        0x1	/* STAG invalid: either the */
149						/* STAG is offlimt, being 0, */
150						/* or STAG_key mismatch */
151#define T4_ERR_PDID                        0x2	/* PDID mismatch */
152#define T4_ERR_QPID                        0x3	/* QPID mismatch */
153#define T4_ERR_ACCESS                      0x4	/* Invalid access right */
154#define T4_ERR_WRAP                        0x5	/* Wrap error */
155#define T4_ERR_BOUND                       0x6	/* base and bounds voilation */
156#define T4_ERR_INVALIDATE_SHARED_MR        0x7	/* attempt to invalidate a  */
157						/* shared memory region */
158#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8	/* attempt to invalidate a  */
159						/* shared memory region */
160#define T4_ERR_ECC                         0x9	/* ECC error detected */
161#define T4_ERR_ECC_PSTAG                   0xA	/* ECC error detected when  */
162						/* reading PSTAG for a MW  */
163						/* Invalidate */
164#define T4_ERR_PBL_ADDR_BOUND              0xB	/* pbl addr out of bounds:  */
165						/* software error */
166#define T4_ERR_SWFLUSH			   0xC	/* SW FLUSHED */
167#define T4_ERR_CRC                         0x10 /* CRC error */
168#define T4_ERR_MARKER                      0x11 /* Marker error */
169#define T4_ERR_PDU_LEN_ERR                 0x12 /* invalid PDU length */
170#define T4_ERR_OUT_OF_RQE                  0x13 /* out of RQE */
171#define T4_ERR_DDP_VERSION                 0x14 /* wrong DDP version */
172#define T4_ERR_RDMA_VERSION                0x15 /* wrong RDMA version */
173#define T4_ERR_OPCODE                      0x16 /* invalid rdma opcode */
174#define T4_ERR_DDP_QUEUE_NUM               0x17 /* invalid ddp queue number */
175#define T4_ERR_MSN                         0x18 /* MSN error */
176#define T4_ERR_TBIT                        0x19 /* tag bit not set correctly */
177#define T4_ERR_MO                          0x1A /* MO not 0 for TERMINATE  */
178						/* or READ_REQ */
179#define T4_ERR_MSN_GAP                     0x1B
180#define T4_ERR_MSN_RANGE                   0x1C
181#define T4_ERR_IRD_OVERFLOW                0x1D
182#define T4_ERR_RQE_ADDR_BOUND              0x1E /* RQE addr out of bounds:  */
183						/* software error */
184#define T4_ERR_INTERNAL_ERR                0x1F /* internal error (opcode  */
185						/* mismatch) */
186/*
187 * CQE defs
188 */
189struct t4_cqe {
190	__be32 header;
191	__be32 len;
192	union {
193		struct {
194			__be32 stag;
195			__be32 msn;
196		} rcqe;
197		struct {
198			u32 nada1;
199			u16 nada2;
200			u16 cidx;
201		} scqe;
202		struct {
203			__be32 wrid_hi;
204			__be32 wrid_low;
205		} gen;
206		u64 drain_cookie;
207	} u;
208	__be64 reserved;
209	__be64 bits_type_ts;
210};
211
212/* macros for flit 0 of the cqe */
213
214#define S_CQE_QPID        12
215#define M_CQE_QPID        0xFFFFF
216#define G_CQE_QPID(x)     ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
217#define V_CQE_QPID(x)	  ((x)<<S_CQE_QPID)
218
219#define S_CQE_SWCQE       11
220#define M_CQE_SWCQE       0x1
221#define G_CQE_SWCQE(x)    ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
222#define V_CQE_SWCQE(x)	  ((x)<<S_CQE_SWCQE)
223
224#define S_CQE_STATUS      5
225#define M_CQE_STATUS      0x1F
226#define G_CQE_STATUS(x)   ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
227#define V_CQE_STATUS(x)   ((x)<<S_CQE_STATUS)
228
229#define S_CQE_TYPE        4
230#define M_CQE_TYPE        0x1
231#define G_CQE_TYPE(x)     ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
232#define V_CQE_TYPE(x)     ((x)<<S_CQE_TYPE)
233
234#define S_CQE_OPCODE      0
235#define M_CQE_OPCODE      0xF
236#define G_CQE_OPCODE(x)   ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
237#define V_CQE_OPCODE(x)   ((x)<<S_CQE_OPCODE)
238
239#define SW_CQE(x)         (G_CQE_SWCQE(be32_to_cpu((x)->header)))
240#define CQE_QPID(x)       (G_CQE_QPID(be32_to_cpu((x)->header)))
241#define CQE_TYPE(x)       (G_CQE_TYPE(be32_to_cpu((x)->header)))
242#define SQ_TYPE(x)	  (CQE_TYPE((x)))
243#define RQ_TYPE(x)	  (!CQE_TYPE((x)))
244#define CQE_STATUS(x)     (G_CQE_STATUS(be32_to_cpu((x)->header)))
245#define CQE_OPCODE(x)     (G_CQE_OPCODE(be32_to_cpu((x)->header)))
246
247#define CQE_SEND_OPCODE(x)(\
248	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
249	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
250	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
251	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
252
253#define CQE_LEN(x)        (be32_to_cpu((x)->len))
254
255/* used for RQ completion processing */
256#define CQE_WRID_STAG(x)  (be32_to_cpu((x)->u.rcqe.stag))
257#define CQE_WRID_MSN(x)   (be32_to_cpu((x)->u.rcqe.msn))
258
259/* used for SQ completion processing */
260#define CQE_WRID_SQ_IDX(x)	((x)->u.scqe.cidx)
261
262/* generic accessor macros */
263#define CQE_WRID_HI(x)		((x)->u.gen.wrid_hi)
264#define CQE_WRID_LOW(x)		((x)->u.gen.wrid_low)
265#define CQE_DRAIN_COOKIE(x)	(x)->u.drain_cookie;
266
267/* macros for flit 3 of the cqe */
268#define S_CQE_GENBIT	63
269#define M_CQE_GENBIT	0x1
270#define G_CQE_GENBIT(x)	(((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
271#define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)
272
273#define S_CQE_OVFBIT	62
274#define M_CQE_OVFBIT	0x1
275#define G_CQE_OVFBIT(x)	((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)
276
277#define S_CQE_IQTYPE	60
278#define M_CQE_IQTYPE	0x3
279#define G_CQE_IQTYPE(x)	((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)
280
281#define M_CQE_TS	0x0fffffffffffffffULL
282#define G_CQE_TS(x)	((x) & M_CQE_TS)
283
284#define CQE_OVFBIT(x)	((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
285#define CQE_GENBIT(x)	((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
286#define CQE_TS(x)	(G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))
287
288struct t4_swsqe {
289	u64			wr_id;
290	struct t4_cqe		cqe;
291	int			read_len;
292	int			opcode;
293	int			complete;
294	int			signaled;
295	u16			idx;
296};
297
298struct t4_sq {
299	union t4_wr *queue;
300	bus_addr_t dma_addr;
301	DECLARE_PCI_UNMAP_ADDR(mapping);
302	unsigned long phys_addr;
303	struct t4_swsqe *sw_sq;
304	struct t4_swsqe *oldest_read;
305	u64 udb;
306	size_t memsize;
307	u32 qid;
308	u16 in_use;
309	u16 size;
310	u16 cidx;
311	u16 pidx;
312	u16 wq_pidx;
313	u16 flags;
314};
315
316struct t4_swrqe {
317	u64 wr_id;
318};
319
320struct t4_rq {
321	union  t4_recv_wr *queue;
322	bus_addr_t dma_addr;
323	DECLARE_PCI_UNMAP_ADDR(mapping);
324	struct t4_swrqe *sw_rq;
325	u64 udb;
326	size_t memsize;
327	u32 qid;
328	u32 msn;
329	u32 rqt_hwaddr;
330	u16 rqt_size;
331	u16 in_use;
332	u16 size;
333	u16 cidx;
334	u16 pidx;
335	u16 wq_pidx;
336};
337
338struct t4_wq {
339	struct t4_sq sq;
340	struct t4_rq rq;
341	void __iomem *db;
342	void __iomem *gts;
343	struct c4iw_rdev *rdev;
344};
345
346static inline int t4_rqes_posted(struct t4_wq *wq)
347{
348	return wq->rq.in_use;
349}
350
351static inline int t4_rq_empty(struct t4_wq *wq)
352{
353	return wq->rq.in_use == 0;
354}
355
356static inline int t4_rq_full(struct t4_wq *wq)
357{
358	return wq->rq.in_use == (wq->rq.size - 1);
359}
360
361static inline u32 t4_rq_avail(struct t4_wq *wq)
362{
363	return wq->rq.size - 1 - wq->rq.in_use;
364}
365
366static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
367{
368	wq->rq.in_use++;
369	if (++wq->rq.pidx == wq->rq.size)
370		wq->rq.pidx = 0;
371	wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
372	if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
373		wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
374}
375
376static inline void t4_rq_consume(struct t4_wq *wq)
377{
378	wq->rq.in_use--;
379	wq->rq.msn++;
380	if (++wq->rq.cidx == wq->rq.size)
381		wq->rq.cidx = 0;
382}
383
384static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
385{
386	return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
387}
388
389static inline u16 t4_rq_wq_size(struct t4_wq *wq)
390{
391		return wq->rq.size * T4_RQ_NUM_SLOTS;
392}
393
394static inline int t4_sq_empty(struct t4_wq *wq)
395{
396	return wq->sq.in_use == 0;
397}
398
399static inline int t4_sq_full(struct t4_wq *wq)
400{
401	return wq->sq.in_use == (wq->sq.size - 1);
402}
403
404static inline u32 t4_sq_avail(struct t4_wq *wq)
405{
406	return wq->sq.size - 1 - wq->sq.in_use;
407}
408
409static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
410{
411	wq->sq.in_use++;
412	if (++wq->sq.pidx == wq->sq.size)
413		wq->sq.pidx = 0;
414	wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
415	if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
416		wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
417}
418
419static inline void t4_sq_consume(struct t4_wq *wq)
420{
421	wq->sq.in_use--;
422	if (++wq->sq.cidx == wq->sq.size)
423		wq->sq.cidx = 0;
424}
425
426static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
427{
428	return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
429}
430
431static inline u16 t4_sq_wq_size(struct t4_wq *wq)
432{
433		return wq->sq.size * T4_SQ_NUM_SLOTS;
434}
435
436static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc)
437{
438	wmb();
439	writel(QID(wq->sq.qid) | PIDX(inc), wq->db);
440}
441
442static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc)
443{
444	wmb();
445	writel(QID(wq->rq.qid) | PIDX(inc), wq->db);
446}
447
448static inline int t4_wq_in_error(struct t4_wq *wq)
449{
450	return wq->rq.queue[wq->rq.size].status.qp_err;
451}
452
453static inline void t4_set_wq_in_error(struct t4_wq *wq)
454{
455	wq->rq.queue[wq->rq.size].status.qp_err = 1;
456}
457
458struct t4_cq {
459	struct t4_cqe *queue;
460	bus_addr_t dma_addr;
461	DECLARE_PCI_UNMAP_ADDR(mapping);
462	struct t4_cqe *sw_queue;
463	void __iomem *gts;
464	struct c4iw_rdev *rdev;
465	u64 ugts;
466	size_t memsize;
467	__be64 bits_type_ts;
468	u32 cqid;
469	u16 size; /* including status page */
470	u16 cidx;
471	u16 sw_pidx;
472	u16 sw_cidx;
473	u16 sw_in_use;
474	u16 cidx_inc;
475	u8 gen;
476	u8 error;
477};
478
479static inline int t4_arm_cq(struct t4_cq *cq, int se)
480{
481	u32 val;
482
483	while (cq->cidx_inc > CIDXINC_MASK) {
484		val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7) |
485		      INGRESSQID(cq->cqid);
486		writel(val, cq->gts);
487		cq->cidx_inc -= CIDXINC_MASK;
488	}
489	val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) |
490	      INGRESSQID(cq->cqid);
491	writel(val, cq->gts);
492	cq->cidx_inc = 0;
493	return 0;
494}
495
496static inline void t4_swcq_produce(struct t4_cq *cq)
497{
498	cq->sw_in_use++;
499	if (++cq->sw_pidx == cq->size)
500		cq->sw_pidx = 0;
501}
502
503static inline void t4_swcq_consume(struct t4_cq *cq)
504{
505	cq->sw_in_use--;
506	if (++cq->sw_cidx == cq->size)
507		cq->sw_cidx = 0;
508}
509
510static inline void t4_hwcq_consume(struct t4_cq *cq)
511{
512	cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
513	if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == M_CIDXINC) {
514		u32 val;
515
516		val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7) |
517		      INGRESSQID(cq->cqid);
518		writel(val, cq->gts);
519		cq->cidx_inc = 0;
520	}
521	if (++cq->cidx == cq->size) {
522		cq->cidx = 0;
523		cq->gen ^= 1;
524	}
525}
526
527static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
528{
529	return (CQE_GENBIT(cqe) == cq->gen);
530}
531
532static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
533{
534	int ret;
535	u16 prev_cidx;
536
537	if (cq->cidx == 0)
538		prev_cidx = cq->size - 1;
539	else
540		prev_cidx = cq->cidx - 1;
541
542	if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
543		ret = -EOVERFLOW;
544		cq->error = 1;
545		printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid);
546	} else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
547		*cqe = &cq->queue[cq->cidx];
548		ret = 0;
549	} else
550		ret = -ENODATA;
551	return ret;
552}
553
554static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
555{
556	if (cq->sw_in_use)
557		return &cq->sw_queue[cq->sw_cidx];
558	return NULL;
559}
560
561static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
562{
563	int ret = 0;
564
565	if (cq->error)
566		ret = -ENODATA;
567	else if (cq->sw_in_use)
568		*cqe = &cq->sw_queue[cq->sw_cidx];
569	else
570		ret = t4_next_hw_cqe(cq, cqe);
571	return ret;
572}
573
574static inline int t4_cq_in_error(struct t4_cq *cq)
575{
576	return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
577}
578
579static inline void t4_set_cq_in_error(struct t4_cq *cq)
580{
581	((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
582}
583#endif
584