mem.c revision 314775
1/* 2 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: stable/11/sys/dev/cxgbe/iw_cxgbe/mem.c 314775 2017-03-06 15:14:59Z np $"); 34 35#include "opt_inet.h" 36 37#ifdef TCP_OFFLOAD 38#include <linux/types.h> 39#include <linux/kref.h> 40#include <rdma/ib_umem.h> 41#include <asm/atomic.h> 42 43#include <common/t4_msg.h> 44#include "iw_cxgbe.h" 45 46#define T4_ULPTX_MIN_IO 32 47#define C4IW_MAX_INLINE_SIZE 96 48 49static int mr_exceeds_hw_limits(struct c4iw_dev *dev, u64 length) 50{ 51 return (is_t4(dev->rdev.adap) || 52 is_t5(dev->rdev.adap)) && 53 length >= 8*1024*1024*1024ULL; 54} 55static int 56write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len, void *data) 57{ 58 struct adapter *sc = rdev->adap; 59 struct ulp_mem_io *ulpmc; 60 struct ulptx_idata *ulpsc; 61 u8 wr_len, *to_dp, *from_dp; 62 int copy_len, num_wqe, i, ret = 0; 63 struct c4iw_wr_wait wr_wait; 64 struct wrqe *wr; 65 u32 cmd; 66 67 cmd = cpu_to_be32(V_ULPTX_CMD(ULP_TX_MEM_WRITE)); 68 if (is_t4(sc)) 69 cmd |= cpu_to_be32(F_ULP_MEMIO_ORDER); 70 else 71 cmd |= cpu_to_be32(F_T5_ULP_MEMIO_IMM); 72 73 addr &= 0x7FFFFFF; 74 CTR3(KTR_IW_CXGBE, "%s addr 0x%x len %u", __func__, addr, len); 75 num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE); 76 c4iw_init_wr_wait(&wr_wait); 77 for (i = 0; i < num_wqe; i++) { 78 79 copy_len = min(len, C4IW_MAX_INLINE_SIZE); 80 wr_len = roundup(sizeof *ulpmc + sizeof *ulpsc + 81 roundup(copy_len, T4_ULPTX_MIN_IO), 16); 82 83 wr = alloc_wrqe(wr_len, &sc->sge.mgmtq); 84 if (wr == NULL) 85 return (0); 86 ulpmc = wrtod(wr); 87 88 memset(ulpmc, 0, wr_len); 89 INIT_ULPTX_WR(ulpmc, wr_len, 0, 0); 90 91 if (i == (num_wqe-1)) { 92 ulpmc->wr.wr_hi = cpu_to_be32(V_FW_WR_OP(FW_ULPTX_WR) | 93 F_FW_WR_COMPL); 94 ulpmc->wr.wr_lo = (__force __be64)(unsigned long) &wr_wait; 95 } else 96 ulpmc->wr.wr_hi = cpu_to_be32(V_FW_WR_OP(FW_ULPTX_WR)); 97 ulpmc->wr.wr_mid = cpu_to_be32( 98 V_FW_WR_LEN16(DIV_ROUND_UP(wr_len, 16))); 99 100 ulpmc->cmd = cmd; 101 ulpmc->dlen = cpu_to_be32(V_ULP_MEMIO_DATA_LEN( 102 DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO))); 103 ulpmc->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(ulpmc->wr), 104 16)); 105 ulpmc->lock_addr = cpu_to_be32(V_ULP_MEMIO_ADDR(addr + i * 3)); 106 107 ulpsc = (struct ulptx_idata *)(ulpmc + 1); 108 ulpsc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM)); 109 ulpsc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO)); 110 111 to_dp = (u8 *)(ulpsc + 1); 112 from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE; 113 if (data) 114 memcpy(to_dp, from_dp, copy_len); 115 else 116 memset(to_dp, 0, copy_len); 117 if (copy_len % T4_ULPTX_MIN_IO) 118 memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO - 119 (copy_len % T4_ULPTX_MIN_IO)); 120 t4_wrq_tx(sc, wr); 121 len -= C4IW_MAX_INLINE_SIZE; 122 } 123 124 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, 0, __func__); 125 return ret; 126} 127 128/* 129 * Build and write a TPT entry. 130 * IN: stag key, pdid, perm, bind_enabled, zbva, to, len, page_size, 131 * pbl_size and pbl_addr 132 * OUT: stag index 133 */ 134static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry, 135 u32 *stag, u8 stag_state, u32 pdid, 136 enum fw_ri_stag_type type, enum fw_ri_mem_perms perm, 137 int bind_enabled, u32 zbva, u64 to, 138 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr) 139{ 140 int err; 141 struct fw_ri_tpte tpt; 142 u32 stag_idx; 143 static atomic_t key; 144 145 if (c4iw_fatal_error(rdev)) 146 return -EIO; 147 148 stag_state = stag_state > 0; 149 stag_idx = (*stag) >> 8; 150 151 if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) { 152 stag_idx = c4iw_get_resource(&rdev->resource.tpt_table); 153 if (!stag_idx) { 154 mutex_lock(&rdev->stats.lock); 155 rdev->stats.stag.fail++; 156 mutex_unlock(&rdev->stats.lock); 157 return -ENOMEM; 158 } 159 mutex_lock(&rdev->stats.lock); 160 rdev->stats.stag.cur += 32; 161 if (rdev->stats.stag.cur > rdev->stats.stag.max) 162 rdev->stats.stag.max = rdev->stats.stag.cur; 163 mutex_unlock(&rdev->stats.lock); 164 *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff); 165 } 166 CTR5(KTR_IW_CXGBE, 167 "%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x", 168 __func__, stag_state, type, pdid, stag_idx); 169 170 /* write TPT entry */ 171 if (reset_tpt_entry) 172 memset(&tpt, 0, sizeof(tpt)); 173 else { 174 tpt.valid_to_pdid = cpu_to_be32(F_FW_RI_TPTE_VALID | 175 V_FW_RI_TPTE_STAGKEY((*stag & M_FW_RI_TPTE_STAGKEY)) | 176 V_FW_RI_TPTE_STAGSTATE(stag_state) | 177 V_FW_RI_TPTE_STAGTYPE(type) | V_FW_RI_TPTE_PDID(pdid)); 178 tpt.locread_to_qpid = cpu_to_be32(V_FW_RI_TPTE_PERM(perm) | 179 (bind_enabled ? F_FW_RI_TPTE_MWBINDEN : 0) | 180 V_FW_RI_TPTE_ADDRTYPE((zbva ? FW_RI_ZERO_BASED_TO : 181 FW_RI_VA_BASED_TO))| 182 V_FW_RI_TPTE_PS(page_size)); 183 tpt.nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32( 184 V_FW_RI_TPTE_PBLADDR(PBL_OFF(rdev, pbl_addr)>>3)); 185 tpt.len_lo = cpu_to_be32((u32)(len & 0xffffffffUL)); 186 tpt.va_hi = cpu_to_be32((u32)(to >> 32)); 187 tpt.va_lo_fbo = cpu_to_be32((u32)(to & 0xffffffffUL)); 188 tpt.dca_mwbcnt_pstag = cpu_to_be32(0); 189 tpt.len_hi = cpu_to_be32((u32)(len >> 32)); 190 } 191 err = write_adapter_mem(rdev, stag_idx + 192 (rdev->adap->vres.stag.start >> 5), 193 sizeof(tpt), &tpt); 194 195 if (reset_tpt_entry) { 196 c4iw_put_resource(&rdev->resource.tpt_table, stag_idx); 197 mutex_lock(&rdev->stats.lock); 198 rdev->stats.stag.cur -= 32; 199 mutex_unlock(&rdev->stats.lock); 200 } 201 return err; 202} 203 204static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl, 205 u32 pbl_addr, u32 pbl_size) 206{ 207 int err; 208 209 CTR4(KTR_IW_CXGBE, "%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d", 210 __func__, pbl_addr, rdev->adap->vres.pbl.start, pbl_size); 211 212 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl); 213 return err; 214} 215 216static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size, 217 u32 pbl_addr) 218{ 219 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 220 pbl_size, pbl_addr); 221} 222 223static int allocate_window(struct c4iw_rdev *rdev, u32 * stag, u32 pdid) 224{ 225 *stag = T4_STAG_UNSET; 226 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0, 227 0UL, 0, 0, 0, 0); 228} 229 230static int deallocate_window(struct c4iw_rdev *rdev, u32 stag) 231{ 232 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0, 233 0); 234} 235 236static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid, 237 u32 pbl_size, u32 pbl_addr) 238{ 239 *stag = T4_STAG_UNSET; 240 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0, 241 0UL, 0, 0, pbl_size, pbl_addr); 242} 243 244static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag) 245{ 246 u32 mmid; 247 248 mhp->attr.state = 1; 249 mhp->attr.stag = stag; 250 mmid = stag >> 8; 251 mhp->ibmr.rkey = mhp->ibmr.lkey = stag; 252 CTR3(KTR_IW_CXGBE, "%s mmid 0x%x mhp %p", __func__, mmid, mhp); 253 return insert_handle(mhp->rhp, &mhp->rhp->mmidr, mhp, mmid); 254} 255 256static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php, 257 struct c4iw_mr *mhp, int shift) 258{ 259 u32 stag = T4_STAG_UNSET; 260 int ret; 261 262 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid, 263 FW_RI_STAG_NSMR, mhp->attr.len ? mhp->attr.perms : 0, 264 mhp->attr.mw_bind_enable, mhp->attr.zbva, 265 mhp->attr.va_fbo, mhp->attr.len ? mhp->attr.len : -1, shift - 12, 266 mhp->attr.pbl_size, mhp->attr.pbl_addr); 267 if (ret) 268 return ret; 269 270 ret = finish_mem_reg(mhp, stag); 271 if (ret) 272 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 273 mhp->attr.pbl_addr); 274 return ret; 275} 276 277static int reregister_mem(struct c4iw_dev *rhp, struct c4iw_pd *php, 278 struct c4iw_mr *mhp, int shift, int npages) 279{ 280 u32 stag; 281 int ret; 282 283 if (npages > mhp->attr.pbl_size) 284 return -ENOMEM; 285 286 stag = mhp->attr.stag; 287 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid, 288 FW_RI_STAG_NSMR, mhp->attr.perms, 289 mhp->attr.mw_bind_enable, mhp->attr.zbva, 290 mhp->attr.va_fbo, mhp->attr.len, shift - 12, 291 mhp->attr.pbl_size, mhp->attr.pbl_addr); 292 if (ret) 293 return ret; 294 295 ret = finish_mem_reg(mhp, stag); 296 if (ret) 297 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 298 mhp->attr.pbl_addr); 299 300 return ret; 301} 302 303static int alloc_pbl(struct c4iw_mr *mhp, int npages) 304{ 305 mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev, 306 npages << 3); 307 308 if (!mhp->attr.pbl_addr) 309 return -ENOMEM; 310 311 mhp->attr.pbl_size = npages; 312 313 return 0; 314} 315 316static int build_phys_page_list(struct ib_phys_buf *buffer_list, 317 int num_phys_buf, u64 *iova_start, 318 u64 *total_size, int *npages, 319 int *shift, __be64 **page_list) 320{ 321 u64 mask; 322 int i, j, n; 323 324 mask = 0; 325 *total_size = 0; 326 for (i = 0; i < num_phys_buf; ++i) { 327 if (i != 0 && buffer_list[i].addr & ~PAGE_MASK) 328 return -EINVAL; 329 if (i != 0 && i != num_phys_buf - 1 && 330 (buffer_list[i].size & ~PAGE_MASK)) 331 return -EINVAL; 332 *total_size += buffer_list[i].size; 333 if (i > 0) 334 mask |= buffer_list[i].addr; 335 else 336 mask |= buffer_list[i].addr & PAGE_MASK; 337 if (i != num_phys_buf - 1) 338 mask |= buffer_list[i].addr + buffer_list[i].size; 339 else 340 mask |= (buffer_list[i].addr + buffer_list[i].size + 341 PAGE_SIZE - 1) & PAGE_MASK; 342 } 343 344 /* Find largest page shift we can use to cover buffers */ 345 for (*shift = PAGE_SHIFT; *shift < 27; ++(*shift)) 346 if ((1ULL << *shift) & mask) 347 break; 348 349 buffer_list[0].size += buffer_list[0].addr & ((1ULL << *shift) - 1); 350 buffer_list[0].addr &= ~0ull << *shift; 351 352 *npages = 0; 353 for (i = 0; i < num_phys_buf; ++i) 354 *npages += (buffer_list[i].size + 355 (1ULL << *shift) - 1) >> *shift; 356 357 if (!*npages) 358 return -EINVAL; 359 360 *page_list = kmalloc(sizeof(u64) * *npages, GFP_KERNEL); 361 if (!*page_list) 362 return -ENOMEM; 363 364 n = 0; 365 for (i = 0; i < num_phys_buf; ++i) 366 for (j = 0; 367 j < (buffer_list[i].size + (1ULL << *shift) - 1) >> *shift; 368 ++j) 369 (*page_list)[n++] = cpu_to_be64(buffer_list[i].addr + 370 ((u64) j << *shift)); 371 372 CTR6(KTR_IW_CXGBE, 373 "%s va 0x%llx mask 0x%llx shift %d len %lld pbl_size %d", __func__, 374 (unsigned long long)*iova_start, (unsigned long long)mask, *shift, 375 (unsigned long long)*total_size, *npages); 376 377 return 0; 378 379} 380 381int c4iw_reregister_phys_mem(struct ib_mr *mr, int mr_rereg_mask, 382 struct ib_pd *pd, struct ib_phys_buf *buffer_list, 383 int num_phys_buf, int acc, u64 *iova_start) 384{ 385 386 struct c4iw_mr mh, *mhp; 387 struct c4iw_pd *php; 388 struct c4iw_dev *rhp; 389 __be64 *page_list = NULL; 390 int shift = 0; 391 u64 total_size = 0; 392 int npages = 0; 393 int ret; 394 395 CTR3(KTR_IW_CXGBE, "%s ib_mr %p ib_pd %p", __func__, mr, pd); 396 397 /* There can be no memory windows */ 398 if (atomic_read(&mr->usecnt)) 399 return -EINVAL; 400 401 mhp = to_c4iw_mr(mr); 402 rhp = mhp->rhp; 403 php = to_c4iw_pd(mr->pd); 404 405 /* make sure we are on the same adapter */ 406 if (rhp != php->rhp) 407 return -EINVAL; 408 409 memcpy(&mh, mhp, sizeof *mhp); 410 411 if (mr_rereg_mask & IB_MR_REREG_PD) 412 php = to_c4iw_pd(pd); 413 if (mr_rereg_mask & IB_MR_REREG_ACCESS) { 414 mh.attr.perms = c4iw_ib_to_tpt_access(acc); 415 mh.attr.mw_bind_enable = (acc & IB_ACCESS_MW_BIND) == 416 IB_ACCESS_MW_BIND; 417 } 418 if (mr_rereg_mask & IB_MR_REREG_TRANS) { 419 ret = build_phys_page_list(buffer_list, num_phys_buf, 420 iova_start, 421 &total_size, &npages, 422 &shift, &page_list); 423 if (ret) 424 return ret; 425 } 426 if (mr_exceeds_hw_limits(rhp, total_size)) { 427 kfree(page_list); 428 return -EINVAL; 429 } 430 ret = reregister_mem(rhp, php, &mh, shift, npages); 431 kfree(page_list); 432 if (ret) 433 return ret; 434 if (mr_rereg_mask & IB_MR_REREG_PD) 435 mhp->attr.pdid = php->pdid; 436 if (mr_rereg_mask & IB_MR_REREG_ACCESS) 437 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 438 if (mr_rereg_mask & IB_MR_REREG_TRANS) { 439 mhp->attr.zbva = 0; 440 mhp->attr.va_fbo = *iova_start; 441 mhp->attr.page_size = shift - 12; 442 mhp->attr.len = (u32) total_size; 443 mhp->attr.pbl_size = npages; 444 } 445 446 return 0; 447} 448 449struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd, 450 struct ib_phys_buf *buffer_list, 451 int num_phys_buf, int acc, u64 *iova_start) 452{ 453 __be64 *page_list; 454 int shift; 455 u64 total_size; 456 int npages; 457 struct c4iw_dev *rhp; 458 struct c4iw_pd *php; 459 struct c4iw_mr *mhp; 460 int ret; 461 462 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd); 463 php = to_c4iw_pd(pd); 464 rhp = php->rhp; 465 466 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 467 if (!mhp) 468 return ERR_PTR(-ENOMEM); 469 470 mhp->rhp = rhp; 471 472 /* First check that we have enough alignment */ 473 if ((*iova_start & ~PAGE_MASK) != (buffer_list[0].addr & ~PAGE_MASK)) { 474 ret = -EINVAL; 475 goto err; 476 } 477 478 if (num_phys_buf > 1 && 479 ((buffer_list[0].addr + buffer_list[0].size) & ~PAGE_MASK)) { 480 ret = -EINVAL; 481 goto err; 482 } 483 484 ret = build_phys_page_list(buffer_list, num_phys_buf, iova_start, 485 &total_size, &npages, &shift, 486 &page_list); 487 if (ret) 488 goto err; 489 490 if (mr_exceeds_hw_limits(rhp, total_size)) { 491 kfree(page_list); 492 ret = -EINVAL; 493 goto err; 494 } 495 ret = alloc_pbl(mhp, npages); 496 if (ret) { 497 kfree(page_list); 498 goto err; 499 } 500 501 ret = write_pbl(&mhp->rhp->rdev, page_list, mhp->attr.pbl_addr, 502 npages); 503 kfree(page_list); 504 if (ret) 505 goto err_pbl; 506 507 mhp->attr.pdid = php->pdid; 508 mhp->attr.zbva = 0; 509 510 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 511 mhp->attr.va_fbo = *iova_start; 512 mhp->attr.page_size = shift - 12; 513 514 mhp->attr.len = (u32) total_size; 515 mhp->attr.pbl_size = npages; 516 ret = register_mem(rhp, php, mhp, shift); 517 if (ret) 518 goto err_pbl; 519 520 return &mhp->ibmr; 521 522err_pbl: 523 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 524 mhp->attr.pbl_size << 3); 525 526err: 527 kfree(mhp); 528 return ERR_PTR(ret); 529 530} 531 532struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc) 533{ 534 struct c4iw_dev *rhp; 535 struct c4iw_pd *php; 536 struct c4iw_mr *mhp; 537 int ret; 538 u32 stag = T4_STAG_UNSET; 539 540 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd); 541 php = to_c4iw_pd(pd); 542 rhp = php->rhp; 543 544 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 545 if (!mhp) 546 return ERR_PTR(-ENOMEM); 547 548 mhp->rhp = rhp; 549 mhp->attr.pdid = php->pdid; 550 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 551 mhp->attr.mw_bind_enable = (acc&IB_ACCESS_MW_BIND) == IB_ACCESS_MW_BIND; 552 mhp->attr.zbva = 0; 553 mhp->attr.va_fbo = 0; 554 mhp->attr.page_size = 0; 555 mhp->attr.len = ~0UL; 556 mhp->attr.pbl_size = 0; 557 558 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid, 559 FW_RI_STAG_NSMR, mhp->attr.perms, 560 mhp->attr.mw_bind_enable, 0, 0, ~0UL, 0, 0, 0); 561 if (ret) 562 goto err1; 563 564 ret = finish_mem_reg(mhp, stag); 565 if (ret) 566 goto err2; 567 return &mhp->ibmr; 568err2: 569 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 570 mhp->attr.pbl_addr); 571err1: 572 kfree(mhp); 573 return ERR_PTR(ret); 574} 575 576struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 577 u64 virt, int acc, struct ib_udata *udata, int mr_id) 578{ 579 __be64 *pages; 580 int shift, n, len; 581 int i, k, entry; 582 int err = 0; 583 struct scatterlist *sg; 584 struct c4iw_dev *rhp; 585 struct c4iw_pd *php; 586 struct c4iw_mr *mhp; 587 588 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd); 589 590 if (length == ~0ULL) 591 return ERR_PTR(-EINVAL); 592 593 if ((length + start) < start) 594 return ERR_PTR(-EINVAL); 595 596 php = to_c4iw_pd(pd); 597 rhp = php->rhp; 598 599 if (mr_exceeds_hw_limits(rhp, length)) 600 return ERR_PTR(-EINVAL); 601 602 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 603 if (!mhp) 604 return ERR_PTR(-ENOMEM); 605 606 mhp->rhp = rhp; 607 608 mhp->umem = ib_umem_get(pd->uobject->context, start, length, acc, 0); 609 if (IS_ERR(mhp->umem)) { 610 err = PTR_ERR(mhp->umem); 611 kfree(mhp); 612 return ERR_PTR(err); 613 } 614 615 shift = ffs(mhp->umem->page_size) - 1; 616 617 n = mhp->umem->nmap; 618 err = alloc_pbl(mhp, n); 619 if (err) 620 goto err; 621 622 pages = (__be64 *) __get_free_page(GFP_KERNEL); 623 if (!pages) { 624 err = -ENOMEM; 625 goto err_pbl; 626 } 627 628 i = n = 0; 629 for_each_sg(mhp->umem->sg_head.sgl, sg, mhp->umem->nmap, entry) { 630 len = sg_dma_len(sg) >> shift; 631 for (k = 0; k < len; ++k) { 632 pages[i++] = cpu_to_be64(sg_dma_address(sg) + 633 mhp->umem->page_size * k); 634 if (i == PAGE_SIZE / sizeof *pages) { 635 err = write_pbl(&mhp->rhp->rdev, 636 pages, 637 mhp->attr.pbl_addr + (n << 3), i); 638 if (err) 639 goto pbl_done; 640 n += i; 641 i = 0; 642 643 } 644 } 645 } 646 647 if (i) 648 err = write_pbl(&mhp->rhp->rdev, pages, 649 mhp->attr.pbl_addr + (n << 3), i); 650 651pbl_done: 652 free_page((unsigned long) pages); 653 if (err) 654 goto err_pbl; 655 656 mhp->attr.pdid = php->pdid; 657 mhp->attr.zbva = 0; 658 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 659 mhp->attr.va_fbo = virt; 660 mhp->attr.page_size = shift - 12; 661 mhp->attr.len = length; 662 663 err = register_mem(rhp, php, mhp, shift); 664 if (err) 665 goto err_pbl; 666 667 return &mhp->ibmr; 668 669err_pbl: 670 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 671 mhp->attr.pbl_size << 3); 672 673err: 674 ib_umem_release(mhp->umem); 675 kfree(mhp); 676 return ERR_PTR(err); 677} 678 679struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type) 680{ 681 struct c4iw_dev *rhp; 682 struct c4iw_pd *php; 683 struct c4iw_mw *mhp; 684 u32 mmid; 685 u32 stag = 0; 686 int ret; 687 688 php = to_c4iw_pd(pd); 689 rhp = php->rhp; 690 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 691 if (!mhp) 692 return ERR_PTR(-ENOMEM); 693 ret = allocate_window(&rhp->rdev, &stag, php->pdid); 694 if (ret) { 695 kfree(mhp); 696 return ERR_PTR(ret); 697 } 698 mhp->rhp = rhp; 699 mhp->attr.pdid = php->pdid; 700 mhp->attr.type = FW_RI_STAG_MW; 701 mhp->attr.stag = stag; 702 mmid = (stag) >> 8; 703 mhp->ibmw.rkey = stag; 704 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) { 705 deallocate_window(&rhp->rdev, mhp->attr.stag); 706 kfree(mhp); 707 return ERR_PTR(-ENOMEM); 708 } 709 CTR4(KTR_IW_CXGBE, "%s mmid 0x%x mhp %p stag 0x%x", __func__, mmid, mhp, 710 stag); 711 return &(mhp->ibmw); 712} 713 714int c4iw_dealloc_mw(struct ib_mw *mw) 715{ 716 struct c4iw_dev *rhp; 717 struct c4iw_mw *mhp; 718 u32 mmid; 719 720 mhp = to_c4iw_mw(mw); 721 rhp = mhp->rhp; 722 mmid = (mw->rkey) >> 8; 723 remove_handle(rhp, &rhp->mmidr, mmid); 724 deallocate_window(&rhp->rdev, mhp->attr.stag); 725 kfree(mhp); 726 CTR4(KTR_IW_CXGBE, "%s ib_mw %p mmid 0x%x ptr %p", __func__, mw, mmid, 727 mhp); 728 return 0; 729} 730 731struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth) 732{ 733 struct c4iw_dev *rhp; 734 struct c4iw_pd *php; 735 struct c4iw_mr *mhp; 736 u32 mmid; 737 u32 stag = 0; 738 int ret = 0; 739 740 php = to_c4iw_pd(pd); 741 rhp = php->rhp; 742 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 743 if (!mhp) { 744 ret = -ENOMEM; 745 goto err; 746 } 747 748 mhp->rhp = rhp; 749 ret = alloc_pbl(mhp, pbl_depth); 750 if (ret) 751 goto err1; 752 mhp->attr.pbl_size = pbl_depth; 753 ret = allocate_stag(&rhp->rdev, &stag, php->pdid, 754 mhp->attr.pbl_size, mhp->attr.pbl_addr); 755 if (ret) 756 goto err2; 757 mhp->attr.pdid = php->pdid; 758 mhp->attr.type = FW_RI_STAG_NSMR; 759 mhp->attr.stag = stag; 760 mhp->attr.state = 1; 761 mmid = (stag) >> 8; 762 mhp->ibmr.rkey = mhp->ibmr.lkey = stag; 763 if (insert_handle(rhp, &rhp->mmidr, mhp, mmid)) { 764 ret = -ENOMEM; 765 goto err3; 766 } 767 768 CTR4(KTR_IW_CXGBE, "%s mmid 0x%x mhp %p stag 0x%x", __func__, mmid, mhp, 769 stag); 770 return &(mhp->ibmr); 771err3: 772 dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size, 773 mhp->attr.pbl_addr); 774err2: 775 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 776 mhp->attr.pbl_size << 3); 777err1: 778 kfree(mhp); 779err: 780 return ERR_PTR(ret); 781} 782 783struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(struct ib_device *device, 784 int page_list_len) 785{ 786 struct c4iw_fr_page_list *c4pl; 787 struct c4iw_dev *dev = to_c4iw_dev(device); 788 bus_addr_t dma_addr; 789 int size = sizeof *c4pl + page_list_len * sizeof(u64); 790 791 c4pl = contigmalloc(size, 792 M_DEVBUF, M_NOWAIT, 0ul, ~0ul, 4096, 0); 793 if (c4pl) 794 dma_addr = vtophys(c4pl); 795 else 796 return ERR_PTR(-ENOMEM); 797 798 pci_unmap_addr_set(c4pl, mapping, dma_addr); 799 c4pl->dma_addr = dma_addr; 800 c4pl->dev = dev; 801 c4pl->size = size; 802 c4pl->ibpl.page_list = (u64 *)(c4pl + 1); 803 c4pl->ibpl.max_page_list_len = page_list_len; 804 805 return &c4pl->ibpl; 806} 807 808void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *ibpl) 809{ 810 struct c4iw_fr_page_list *c4pl = to_c4iw_fr_page_list(ibpl); 811 contigfree(c4pl, c4pl->size, M_DEVBUF); 812} 813 814int c4iw_dereg_mr(struct ib_mr *ib_mr) 815{ 816 struct c4iw_dev *rhp; 817 struct c4iw_mr *mhp; 818 u32 mmid; 819 820 CTR2(KTR_IW_CXGBE, "%s ib_mr %p", __func__, ib_mr); 821 /* There can be no memory windows */ 822 if (atomic_read(&ib_mr->usecnt)) 823 return -EINVAL; 824 825 mhp = to_c4iw_mr(ib_mr); 826 rhp = mhp->rhp; 827 mmid = mhp->attr.stag >> 8; 828 remove_handle(rhp, &rhp->mmidr, mmid); 829 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 830 mhp->attr.pbl_addr); 831 if (mhp->attr.pbl_size) 832 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 833 mhp->attr.pbl_size << 3); 834 if (mhp->kva) 835 kfree((void *) (unsigned long) mhp->kva); 836 if (mhp->umem) 837 ib_umem_release(mhp->umem); 838 CTR3(KTR_IW_CXGBE, "%s mmid 0x%x ptr %p", __func__, mmid, mhp); 839 kfree(mhp); 840 return 0; 841} 842#endif 843