t4fw_interface.h revision 330307
1/*- 2 * Copyright (c) 2012-2017 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/11/sys/dev/cxgbe/firmware/t4fw_interface.h 330307 2018-03-03 02:30:52Z np $ 27 * 28 */ 29 30#ifndef _T4FW_INTERFACE_H_ 31#define _T4FW_INTERFACE_H_ 32 33/****************************************************************************** 34 * R E T U R N V A L U E S 35 ********************************/ 36 37enum fw_retval { 38 FW_SUCCESS = 0, /* completed successfully */ 39 FW_EPERM = 1, /* operation not permitted */ 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ 48 FW_ENODEV = 19, /* no such device */ 49 FW_EINVAL = 22, /* invalid argument */ 50 FW_ENOSPC = 28, /* no space left on device */ 51 FW_ENOSYS = 38, /* functionality not implemented */ 52 FW_ENODATA = 61, /* no data available */ 53 FW_EPROTO = 71, /* protocol error */ 54 FW_EADDRINUSE = 98, /* address already in use */ 55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 56 FW_ENETDOWN = 100, /* network is down */ 57 FW_ENETUNREACH = 101, /* network is unreachable */ 58 FW_ENOBUFS = 105, /* no buffer space available */ 59 FW_ETIMEDOUT = 110, /* timeout */ 60 FW_EINPROGRESS = 115, /* fw internal */ 61 FW_SCSI_ABORT_REQUESTED = 128, /* */ 62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 63 FW_SCSI_ABORTED = 130, /* */ 64 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 65 FW_ERR_LINK_DOWN = 132, /* */ 66 FW_RDEV_NOT_READY = 133, /* */ 67 FW_ERR_RDEV_LOST = 134, /* */ 68 FW_ERR_RDEV_LOGO = 135, /* */ 69 FW_FCOE_NO_XCHG = 136, /* */ 70 FW_SCSI_RSP_ERR = 137, /* */ 71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 73 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 74 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 76 FW_SCSI_IO_BLOCK = 143, /* IO is going to be blocked due to resource failure */ 77}; 78 79/****************************************************************************** 80 * M E M O R Y T Y P E s 81 ******************************/ 82 83enum fw_memtype { 84 FW_MEMTYPE_EDC0 = 0x0, 85 FW_MEMTYPE_EDC1 = 0x1, 86 FW_MEMTYPE_EXTMEM = 0x2, 87 FW_MEMTYPE_FLASH = 0x4, 88 FW_MEMTYPE_INTERNAL = 0x5, 89 FW_MEMTYPE_EXTMEM1 = 0x6, 90 FW_MEMTYPE_HMA = 0x7, 91}; 92 93/****************************************************************************** 94 * W O R K R E Q U E S T s 95 ********************************/ 96 97enum fw_wr_opcodes { 98 FW_FRAG_WR = 0x1d, 99 FW_FILTER_WR = 0x02, 100 FW_ULPTX_WR = 0x04, 101 FW_TP_WR = 0x05, 102 FW_ETH_TX_PKT_WR = 0x08, 103 FW_ETH_TX_PKT2_WR = 0x44, 104 FW_ETH_TX_PKTS_WR = 0x09, 105 FW_ETH_TX_PKTS2_WR = 0x78, 106 FW_ETH_TX_EO_WR = 0x1c, 107 FW_EQ_FLUSH_WR = 0x1b, 108 FW_OFLD_CONNECTION_WR = 0x2f, 109 FW_FLOWC_WR = 0x0a, 110 FW_OFLD_TX_DATA_WR = 0x0b, 111 FW_CMD_WR = 0x10, 112 FW_ETH_TX_PKT_VM_WR = 0x11, 113 FW_RI_RES_WR = 0x0c, 114 FW_RI_RDMA_WRITE_WR = 0x14, 115 FW_RI_SEND_WR = 0x15, 116 FW_RI_RDMA_READ_WR = 0x16, 117 FW_RI_RECV_WR = 0x17, 118 FW_RI_BIND_MW_WR = 0x18, 119 FW_RI_FR_NSMR_WR = 0x19, 120 FW_RI_FR_NSMR_TPTE_WR = 0x20, 121 FW_RI_INV_LSTAG_WR = 0x1a, 122 FW_RI_SEND_IMMEDIATE_WR = 0x15, 123 FW_RI_ATOMIC_WR = 0x16, 124 FW_RI_WR = 0x0d, 125 FW_CHNET_IFCONF_WR = 0x6b, 126 FW_RDEV_WR = 0x38, 127 FW_FOISCSI_NODE_WR = 0x60, 128 FW_FOISCSI_CTRL_WR = 0x6a, 129 FW_FOISCSI_CHAP_WR = 0x6c, 130 FW_FCOE_ELS_CT_WR = 0x30, 131 FW_SCSI_WRITE_WR = 0x31, 132 FW_SCSI_READ_WR = 0x32, 133 FW_SCSI_CMD_WR = 0x33, 134 FW_SCSI_ABRT_CLS_WR = 0x34, 135 FW_SCSI_TGT_ACC_WR = 0x35, 136 FW_SCSI_TGT_XMIT_WR = 0x36, 137 FW_SCSI_TGT_RSP_WR = 0x37, 138 FW_POFCOE_TCB_WR = 0x42, 139 FW_POFCOE_ULPTX_WR = 0x43, 140 FW_ISCSI_TX_DATA_WR = 0x45, 141 FW_PTP_TX_PKT_WR = 0x46, 142 FW_TLSTX_DATA_WR = 0x68, 143 FW_CRYPTO_LOOKASIDE_WR = 0x6d, 144 FW_COISCSI_TGT_WR = 0x70, 145 FW_COISCSI_TGT_CONN_WR = 0x71, 146 FW_COISCSI_TGT_XMIT_WR = 0x72, 147 FW_COISCSI_STATS_WR = 0x73, 148 FW_ISNS_WR = 0x75, 149 FW_ISNS_XMIT_WR = 0x76, 150 FW_FILTER2_WR = 0x77, 151 FW_LASTC2E_WR = 0x80 152}; 153 154/* 155 * Generic work request header flit0 156 */ 157struct fw_wr_hdr { 158 __be32 hi; 159 __be32 lo; 160}; 161 162/* work request opcode (hi) 163 */ 164#define S_FW_WR_OP 24 165#define M_FW_WR_OP 0xff 166#define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 167#define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 168 169/* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 170 */ 171#define S_FW_WR_ATOMIC 23 172#define M_FW_WR_ATOMIC 0x1 173#define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 174#define G_FW_WR_ATOMIC(x) \ 175 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 176#define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 177 178/* flush flag (hi) - firmware flushes flushable work request buffered 179 * in the flow context. 180 */ 181#define S_FW_WR_FLUSH 22 182#define M_FW_WR_FLUSH 0x1 183#define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 184#define G_FW_WR_FLUSH(x) \ 185 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 186#define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 187 188/* completion flag (hi) - firmware generates a cpl_fw6_ack 189 */ 190#define S_FW_WR_COMPL 21 191#define M_FW_WR_COMPL 0x1 192#define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 193#define G_FW_WR_COMPL(x) \ 194 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 195#define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 196 197 198/* work request immediate data lengh (hi) 199 */ 200#define S_FW_WR_IMMDLEN 0 201#define M_FW_WR_IMMDLEN 0xff 202#define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 203#define G_FW_WR_IMMDLEN(x) \ 204 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 205 206/* egress queue status update to associated ingress queue entry (lo) 207 */ 208#define S_FW_WR_EQUIQ 31 209#define M_FW_WR_EQUIQ 0x1 210#define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 211#define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 212#define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 213 214/* egress queue status update to egress queue status entry (lo) 215 */ 216#define S_FW_WR_EQUEQ 30 217#define M_FW_WR_EQUEQ 0x1 218#define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 219#define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 220#define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 221 222/* flow context identifier (lo) 223 */ 224#define S_FW_WR_FLOWID 8 225#define M_FW_WR_FLOWID 0xfffff 226#define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 227#define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 228 229/* length in units of 16-bytes (lo) 230 */ 231#define S_FW_WR_LEN16 0 232#define M_FW_WR_LEN16 0xff 233#define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 234#define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 235 236struct fw_frag_wr { 237 __be32 op_to_fragoff16; 238 __be32 flowid_len16; 239 __be64 r4; 240}; 241 242#define S_FW_FRAG_WR_EOF 15 243#define M_FW_FRAG_WR_EOF 0x1 244#define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 245#define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 246#define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 247 248#define S_FW_FRAG_WR_FRAGOFF16 8 249#define M_FW_FRAG_WR_FRAGOFF16 0x7f 250#define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 251#define G_FW_FRAG_WR_FRAGOFF16(x) \ 252 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 253 254/* valid filter configurations for compressed tuple 255 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 256 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 257 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 258 * OV - Outer VLAN/VNIC_ID, 259*/ 260#define HW_TPL_FR_MT_M_E_P_FC 0x3C3 261#define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 262#define HW_TPL_FR_MT_M_IV_P_FC 0x38B 263#define HW_TPL_FR_MT_M_OV_P_FC 0x387 264#define HW_TPL_FR_MT_E_PR_T 0x370 265#define HW_TPL_FR_MT_E_PR_P_FC 0X363 266#define HW_TPL_FR_MT_E_T_P_FC 0X353 267#define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 268#define HW_TPL_FR_MT_PR_OV_P_FC 0X327 269#define HW_TPL_FR_MT_T_IV_P_FC 0X31B 270#define HW_TPL_FR_MT_T_OV_P_FC 0X317 271#define HW_TPL_FR_M_E_PR_FC 0X2E1 272#define HW_TPL_FR_M_E_T_FC 0X2D1 273#define HW_TPL_FR_M_PR_IV_FC 0X2A9 274#define HW_TPL_FR_M_PR_OV_FC 0X2A5 275#define HW_TPL_FR_M_T_IV_FC 0X299 276#define HW_TPL_FR_M_T_OV_FC 0X295 277#define HW_TPL_FR_E_PR_T_P 0X272 278#define HW_TPL_FR_E_PR_T_FC 0X271 279#define HW_TPL_FR_E_IV_FC 0X249 280#define HW_TPL_FR_E_OV_FC 0X245 281#define HW_TPL_FR_PR_T_IV_FC 0X239 282#define HW_TPL_FR_PR_T_OV_FC 0X235 283#define HW_TPL_FR_IV_OV_FC 0X20D 284#define HW_TPL_MT_M_E_PR 0X1E0 285#define HW_TPL_MT_M_E_T 0X1D0 286#define HW_TPL_MT_E_PR_T_FC 0X171 287#define HW_TPL_MT_E_IV 0X148 288#define HW_TPL_MT_E_OV 0X144 289#define HW_TPL_MT_PR_T_IV 0X138 290#define HW_TPL_MT_PR_T_OV 0X134 291#define HW_TPL_M_E_PR_P 0X0E2 292#define HW_TPL_M_E_T_P 0X0D2 293#define HW_TPL_E_PR_T_P_FC 0X073 294#define HW_TPL_E_IV_P 0X04A 295#define HW_TPL_E_OV_P 0X046 296#define HW_TPL_PR_T_IV_P 0X03A 297#define HW_TPL_PR_T_OV_P 0X036 298 299/* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 300enum fw_filter_wr_cookie { 301 FW_FILTER_WR_SUCCESS, 302 FW_FILTER_WR_FLT_ADDED, 303 FW_FILTER_WR_FLT_DELETED, 304 FW_FILTER_WR_SMT_TBL_FULL, 305 FW_FILTER_WR_EINVAL, 306}; 307 308enum fw_filter_wr_nat_mode { 309 FW_FILTER_WR_NATMODE_NONE = 0, 310 FW_FILTER_WR_NATMODE_DIP , 311 FW_FILTER_WR_NATMODE_DIPDP, 312 FW_FILTER_WR_NATMODE_DIPDPSIP, 313 FW_FILTER_WR_NATMODE_DIPDPSP, 314 FW_FILTER_WR_NATMODE_SIPSP, 315 FW_FILTER_WR_NATMODE_DIPSIPSP, 316 FW_FILTER_WR_NATMODE_FOURTUPLE, 317}; 318 319struct fw_filter_wr { 320 __be32 op_pkd; 321 __be32 len16_pkd; 322 __be64 r3; 323 __be32 tid_to_iq; 324 __be32 del_filter_to_l2tix; 325 __be16 ethtype; 326 __be16 ethtypem; 327 __u8 frag_to_ovlan_vldm; 328 __u8 smac_sel; 329 __be16 rx_chan_rx_rpl_iq; 330 __be32 maci_to_matchtypem; 331 __u8 ptcl; 332 __u8 ptclm; 333 __u8 ttyp; 334 __u8 ttypm; 335 __be16 ivlan; 336 __be16 ivlanm; 337 __be16 ovlan; 338 __be16 ovlanm; 339 __u8 lip[16]; 340 __u8 lipm[16]; 341 __u8 fip[16]; 342 __u8 fipm[16]; 343 __be16 lp; 344 __be16 lpm; 345 __be16 fp; 346 __be16 fpm; 347 __be16 r7; 348 __u8 sma[6]; 349}; 350 351struct fw_filter2_wr { 352 __be32 op_pkd; 353 __be32 len16_pkd; 354 __be64 r3; 355 __be32 tid_to_iq; 356 __be32 del_filter_to_l2tix; 357 __be16 ethtype; 358 __be16 ethtypem; 359 __u8 frag_to_ovlan_vldm; 360 __u8 smac_sel; 361 __be16 rx_chan_rx_rpl_iq; 362 __be32 maci_to_matchtypem; 363 __u8 ptcl; 364 __u8 ptclm; 365 __u8 ttyp; 366 __u8 ttypm; 367 __be16 ivlan; 368 __be16 ivlanm; 369 __be16 ovlan; 370 __be16 ovlanm; 371 __u8 lip[16]; 372 __u8 lipm[16]; 373 __u8 fip[16]; 374 __u8 fipm[16]; 375 __be16 lp; 376 __be16 lpm; 377 __be16 fp; 378 __be16 fpm; 379 __be16 r7; 380 __u8 sma[6]; 381 __be16 r8; 382 __u8 filter_type_swapmac; 383 __u8 natmode_to_ulp_type; 384 __be16 newlport; 385 __be16 newfport; 386 __u8 newlip[16]; 387 __u8 newfip[16]; 388 __be32 natseqcheck; 389 __be32 r9; 390 __be64 r10; 391 __be64 r11; 392 __be64 r12; 393 __be64 r13; 394}; 395 396#define S_FW_FILTER_WR_TID 12 397#define M_FW_FILTER_WR_TID 0xfffff 398#define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 399#define G_FW_FILTER_WR_TID(x) \ 400 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 401 402#define S_FW_FILTER_WR_RQTYPE 11 403#define M_FW_FILTER_WR_RQTYPE 0x1 404#define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 405#define G_FW_FILTER_WR_RQTYPE(x) \ 406 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 407#define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 408 409#define S_FW_FILTER_WR_NOREPLY 10 410#define M_FW_FILTER_WR_NOREPLY 0x1 411#define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 412#define G_FW_FILTER_WR_NOREPLY(x) \ 413 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 414#define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 415 416#define S_FW_FILTER_WR_IQ 0 417#define M_FW_FILTER_WR_IQ 0x3ff 418#define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 419#define G_FW_FILTER_WR_IQ(x) \ 420 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 421 422#define S_FW_FILTER_WR_DEL_FILTER 31 423#define M_FW_FILTER_WR_DEL_FILTER 0x1 424#define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 425#define G_FW_FILTER_WR_DEL_FILTER(x) \ 426 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 427#define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 428 429#define S_FW_FILTER_WR_RPTTID 25 430#define M_FW_FILTER_WR_RPTTID 0x1 431#define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 432#define G_FW_FILTER_WR_RPTTID(x) \ 433 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 434#define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 435 436#define S_FW_FILTER_WR_DROP 24 437#define M_FW_FILTER_WR_DROP 0x1 438#define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 439#define G_FW_FILTER_WR_DROP(x) \ 440 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 441#define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 442 443#define S_FW_FILTER_WR_DIRSTEER 23 444#define M_FW_FILTER_WR_DIRSTEER 0x1 445#define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 446#define G_FW_FILTER_WR_DIRSTEER(x) \ 447 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 448#define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 449 450#define S_FW_FILTER_WR_MASKHASH 22 451#define M_FW_FILTER_WR_MASKHASH 0x1 452#define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 453#define G_FW_FILTER_WR_MASKHASH(x) \ 454 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 455#define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 456 457#define S_FW_FILTER_WR_DIRSTEERHASH 21 458#define M_FW_FILTER_WR_DIRSTEERHASH 0x1 459#define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 460#define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 461 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 462#define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 463 464#define S_FW_FILTER_WR_LPBK 20 465#define M_FW_FILTER_WR_LPBK 0x1 466#define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 467#define G_FW_FILTER_WR_LPBK(x) \ 468 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 469#define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 470 471#define S_FW_FILTER_WR_DMAC 19 472#define M_FW_FILTER_WR_DMAC 0x1 473#define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 474#define G_FW_FILTER_WR_DMAC(x) \ 475 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 476#define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 477 478#define S_FW_FILTER_WR_SMAC 18 479#define M_FW_FILTER_WR_SMAC 0x1 480#define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 481#define G_FW_FILTER_WR_SMAC(x) \ 482 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 483#define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 484 485#define S_FW_FILTER_WR_INSVLAN 17 486#define M_FW_FILTER_WR_INSVLAN 0x1 487#define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 488#define G_FW_FILTER_WR_INSVLAN(x) \ 489 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 490#define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 491 492#define S_FW_FILTER_WR_RMVLAN 16 493#define M_FW_FILTER_WR_RMVLAN 0x1 494#define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 495#define G_FW_FILTER_WR_RMVLAN(x) \ 496 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 497#define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 498 499#define S_FW_FILTER_WR_HITCNTS 15 500#define M_FW_FILTER_WR_HITCNTS 0x1 501#define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 502#define G_FW_FILTER_WR_HITCNTS(x) \ 503 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 504#define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 505 506#define S_FW_FILTER_WR_TXCHAN 13 507#define M_FW_FILTER_WR_TXCHAN 0x3 508#define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 509#define G_FW_FILTER_WR_TXCHAN(x) \ 510 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 511 512#define S_FW_FILTER_WR_PRIO 12 513#define M_FW_FILTER_WR_PRIO 0x1 514#define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 515#define G_FW_FILTER_WR_PRIO(x) \ 516 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 517#define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 518 519#define S_FW_FILTER_WR_L2TIX 0 520#define M_FW_FILTER_WR_L2TIX 0xfff 521#define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 522#define G_FW_FILTER_WR_L2TIX(x) \ 523 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 524 525#define S_FW_FILTER_WR_FRAG 7 526#define M_FW_FILTER_WR_FRAG 0x1 527#define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 528#define G_FW_FILTER_WR_FRAG(x) \ 529 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 530#define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 531 532#define S_FW_FILTER_WR_FRAGM 6 533#define M_FW_FILTER_WR_FRAGM 0x1 534#define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 535#define G_FW_FILTER_WR_FRAGM(x) \ 536 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 537#define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 538 539#define S_FW_FILTER_WR_IVLAN_VLD 5 540#define M_FW_FILTER_WR_IVLAN_VLD 0x1 541#define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 542#define G_FW_FILTER_WR_IVLAN_VLD(x) \ 543 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 544#define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 545 546#define S_FW_FILTER_WR_OVLAN_VLD 4 547#define M_FW_FILTER_WR_OVLAN_VLD 0x1 548#define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 549#define G_FW_FILTER_WR_OVLAN_VLD(x) \ 550 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 551#define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 552 553#define S_FW_FILTER_WR_IVLAN_VLDM 3 554#define M_FW_FILTER_WR_IVLAN_VLDM 0x1 555#define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 556#define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 557 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 558#define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 559 560#define S_FW_FILTER_WR_OVLAN_VLDM 2 561#define M_FW_FILTER_WR_OVLAN_VLDM 0x1 562#define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 563#define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 564 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 565#define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 566 567#define S_FW_FILTER_WR_RX_CHAN 15 568#define M_FW_FILTER_WR_RX_CHAN 0x1 569#define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 570#define G_FW_FILTER_WR_RX_CHAN(x) \ 571 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 572#define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 573 574#define S_FW_FILTER_WR_RX_RPL_IQ 0 575#define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 576#define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 577#define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 578 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 579 580#define S_FW_FILTER2_WR_FILTER_TYPE 1 581#define M_FW_FILTER2_WR_FILTER_TYPE 0x1 582#define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE) 583#define G_FW_FILTER2_WR_FILTER_TYPE(x) \ 584 (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE) 585#define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U) 586 587#define S_FW_FILTER2_WR_SWAPMAC 0 588#define M_FW_FILTER2_WR_SWAPMAC 0x1 589#define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) 590#define G_FW_FILTER2_WR_SWAPMAC(x) \ 591 (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC) 592#define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U) 593 594#define S_FW_FILTER2_WR_NATMODE 5 595#define M_FW_FILTER2_WR_NATMODE 0x7 596#define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 597#define G_FW_FILTER2_WR_NATMODE(x) \ 598 (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE) 599 600#define S_FW_FILTER2_WR_NATFLAGCHECK 4 601#define M_FW_FILTER2_WR_NATFLAGCHECK 0x1 602#define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK) 603#define G_FW_FILTER2_WR_NATFLAGCHECK(x) \ 604 (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK) 605#define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U) 606 607#define S_FW_FILTER2_WR_ULP_TYPE 0 608#define M_FW_FILTER2_WR_ULP_TYPE 0xf 609#define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 610#define G_FW_FILTER2_WR_ULP_TYPE(x) \ 611 (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE) 612 613#define S_FW_FILTER_WR_MACI 23 614#define M_FW_FILTER_WR_MACI 0x1ff 615#define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 616#define G_FW_FILTER_WR_MACI(x) \ 617 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 618 619#define S_FW_FILTER_WR_MACIM 14 620#define M_FW_FILTER_WR_MACIM 0x1ff 621#define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 622#define G_FW_FILTER_WR_MACIM(x) \ 623 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 624 625#define S_FW_FILTER_WR_FCOE 13 626#define M_FW_FILTER_WR_FCOE 0x1 627#define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 628#define G_FW_FILTER_WR_FCOE(x) \ 629 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 630#define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 631 632#define S_FW_FILTER_WR_FCOEM 12 633#define M_FW_FILTER_WR_FCOEM 0x1 634#define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 635#define G_FW_FILTER_WR_FCOEM(x) \ 636 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 637#define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 638 639#define S_FW_FILTER_WR_PORT 9 640#define M_FW_FILTER_WR_PORT 0x7 641#define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 642#define G_FW_FILTER_WR_PORT(x) \ 643 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 644 645#define S_FW_FILTER_WR_PORTM 6 646#define M_FW_FILTER_WR_PORTM 0x7 647#define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 648#define G_FW_FILTER_WR_PORTM(x) \ 649 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 650 651#define S_FW_FILTER_WR_MATCHTYPE 3 652#define M_FW_FILTER_WR_MATCHTYPE 0x7 653#define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 654#define G_FW_FILTER_WR_MATCHTYPE(x) \ 655 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 656 657#define S_FW_FILTER_WR_MATCHTYPEM 0 658#define M_FW_FILTER_WR_MATCHTYPEM 0x7 659#define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 660#define G_FW_FILTER_WR_MATCHTYPEM(x) \ 661 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 662 663struct fw_ulptx_wr { 664 __be32 op_to_compl; 665 __be32 flowid_len16; 666 __u64 cookie; 667}; 668 669struct fw_tp_wr { 670 __be32 op_to_immdlen; 671 __be32 flowid_len16; 672 __u64 cookie; 673}; 674 675struct fw_eth_tx_pkt_wr { 676 __be32 op_immdlen; 677 __be32 equiq_to_len16; 678 __be64 r3; 679}; 680 681#define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 682#define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 683#define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 684#define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 685 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 686 687struct fw_eth_tx_pkt2_wr { 688 __be32 op_immdlen; 689 __be32 equiq_to_len16; 690 __be32 r3; 691 __be32 L4ChkDisable_to_IpHdrLen; 692}; 693 694#define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 695#define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 696#define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 697#define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 698 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 699 700#define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 701#define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 702#define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 703 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 704#define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 705 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 706 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 707#define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 708 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 709 710#define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 711#define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 712#define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 713 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 714#define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 715 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 716 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 717#define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 718 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 719 720#define S_FW_ETH_TX_PKT2_WR_IVLAN 28 721#define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 722#define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 723#define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 724 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 725#define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 726 727#define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 728#define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 729#define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 730#define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 731 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 732 733#define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 734#define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 735#define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 736#define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 737 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 738 739#define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 740#define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 741#define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 742#define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 743 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 744 745struct fw_eth_tx_pkts_wr { 746 __be32 op_pkd; 747 __be32 equiq_to_len16; 748 __be32 r3; 749 __be16 plen; 750 __u8 npkt; 751 __u8 type; 752}; 753 754#define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 755#define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 756#define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 757#define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 758 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 759 760struct fw_eth_tx_pkt_ptp_wr { 761 __be32 op_immdlen; 762 __be32 equiq_to_len16; 763 __be64 r3; 764}; 765 766enum fw_eth_tx_eo_type { 767 FW_ETH_TX_EO_TYPE_UDPSEG, 768 FW_ETH_TX_EO_TYPE_TCPSEG, 769 FW_ETH_TX_EO_TYPE_NVGRESEG, 770 FW_ETH_TX_EO_TYPE_VXLANSEG, 771 FW_ETH_TX_EO_TYPE_GENEVESEG, 772}; 773 774struct fw_eth_tx_eo_wr { 775 __be32 op_immdlen; 776 __be32 equiq_to_len16; 777 __be64 r3; 778 union fw_eth_tx_eo { 779 struct fw_eth_tx_eo_udpseg { 780 __u8 type; 781 __u8 ethlen; 782 __be16 iplen; 783 __u8 udplen; 784 __u8 rtplen; 785 __be16 r4; 786 __be16 mss; 787 __be16 schedpktsize; 788 __be32 plen; 789 } udpseg; 790 struct fw_eth_tx_eo_tcpseg { 791 __u8 type; 792 __u8 ethlen; 793 __be16 iplen; 794 __u8 tcplen; 795 __u8 tsclk_tsoff; 796 __be16 r4; 797 __be16 mss; 798 __be16 r5; 799 __be32 plen; 800 } tcpseg; 801 struct fw_eth_tx_eo_nvgreseg { 802 __u8 type; 803 __u8 iphdroffout; 804 __be16 grehdroff; 805 __be16 iphdroffin; 806 __be16 tcphdroffin; 807 __be16 mss; 808 __be16 r4; 809 __be32 plen; 810 } nvgreseg; 811 struct fw_eth_tx_eo_vxlanseg { 812 __u8 type; 813 __u8 iphdroffout; 814 __be16 vxlanhdroff; 815 __be16 iphdroffin; 816 __be16 tcphdroffin; 817 __be16 mss; 818 __be16 r4; 819 __be32 plen; 820 821 } vxlanseg; 822 struct fw_eth_tx_eo_geneveseg { 823 __u8 type; 824 __u8 iphdroffout; 825 __be16 genevehdroff; 826 __be16 iphdroffin; 827 __be16 tcphdroffin; 828 __be16 mss; 829 __be16 r4; 830 __be32 plen; 831 } geneveseg; 832 } u; 833}; 834 835#define S_FW_ETH_TX_EO_WR_IMMDLEN 0 836#define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 837#define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 838#define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 839 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 840 841#define S_FW_ETH_TX_EO_WR_TSCLK 6 842#define M_FW_ETH_TX_EO_WR_TSCLK 0x3 843#define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 844#define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 845 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 846 847#define S_FW_ETH_TX_EO_WR_TSOFF 0 848#define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 849#define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 850#define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 851 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 852 853struct fw_eq_flush_wr { 854 __u8 opcode; 855 __u8 r1[3]; 856 __be32 equiq_to_len16; 857 __be64 r3; 858}; 859 860struct fw_ofld_connection_wr { 861 __be32 op_compl; 862 __be32 len16_pkd; 863 __u64 cookie; 864 __be64 r2; 865 __be64 r3; 866 struct fw_ofld_connection_le { 867 __be32 version_cpl; 868 __be32 filter; 869 __be32 r1; 870 __be16 lport; 871 __be16 pport; 872 union fw_ofld_connection_leip { 873 struct fw_ofld_connection_le_ipv4 { 874 __be32 pip; 875 __be32 lip; 876 __be64 r0; 877 __be64 r1; 878 __be64 r2; 879 } ipv4; 880 struct fw_ofld_connection_le_ipv6 { 881 __be64 pip_hi; 882 __be64 pip_lo; 883 __be64 lip_hi; 884 __be64 lip_lo; 885 } ipv6; 886 } u; 887 } le; 888 struct fw_ofld_connection_tcb { 889 __be32 t_state_to_astid; 890 __be16 cplrxdataack_cplpassacceptrpl; 891 __be16 rcv_adv; 892 __be32 rcv_nxt; 893 __be32 tx_max; 894 __be64 opt0; 895 __be32 opt2; 896 __be32 r1; 897 __be64 r2; 898 __be64 r3; 899 } tcb; 900}; 901 902#define S_FW_OFLD_CONNECTION_WR_VERSION 31 903#define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 904#define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 905 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 906#define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 907 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 908 M_FW_OFLD_CONNECTION_WR_VERSION) 909#define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 910 911#define S_FW_OFLD_CONNECTION_WR_CPL 30 912#define M_FW_OFLD_CONNECTION_WR_CPL 0x1 913#define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 914#define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 915 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 916#define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 917 918#define S_FW_OFLD_CONNECTION_WR_T_STATE 28 919#define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 920#define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 921 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 922#define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 923 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 924 M_FW_OFLD_CONNECTION_WR_T_STATE) 925 926#define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 927#define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 928#define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 929 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 930#define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 931 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 932 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 933 934#define S_FW_OFLD_CONNECTION_WR_ASTID 0 935#define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 936#define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 937 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 938#define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 939 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 940 941#define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 942#define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 943#define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 944 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 945#define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 946 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 947 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 948#define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 949 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 950 951#define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 952#define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 953#define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 954 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 955#define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 956 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 957 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 958#define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 959 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 960 961enum fw_flowc_mnem_tcpstate { 962 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 963 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 964 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 965 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 966 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 967 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 968 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 969 * will resend FIN - equiv ESTAB 970 */ 971 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 972 * will resend FIN but have 973 * received FIN 974 */ 975 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 976 * will resend FIN but have 977 * received FIN 978 */ 979 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 980 * waiting for FIN 981 */ 982 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 983}; 984 985enum fw_flowc_mnem_eostate { 986 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 987 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 988 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 989 * outstanding payload 990 */ 991 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 992 * discarding outstanding payload 993 */ 994}; 995 996enum fw_flowc_mnem { 997 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 998 FW_FLOWC_MNEM_CH = 1, 999 FW_FLOWC_MNEM_PORT = 2, 1000 FW_FLOWC_MNEM_IQID = 3, 1001 FW_FLOWC_MNEM_SNDNXT = 4, 1002 FW_FLOWC_MNEM_RCVNXT = 5, 1003 FW_FLOWC_MNEM_SNDBUF = 6, 1004 FW_FLOWC_MNEM_MSS = 7, 1005 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 1006 FW_FLOWC_MNEM_TCPSTATE = 9, 1007 FW_FLOWC_MNEM_EOSTATE = 10, 1008 FW_FLOWC_MNEM_SCHEDCLASS = 11, 1009 FW_FLOWC_MNEM_DCBPRIO = 12, 1010 FW_FLOWC_MNEM_SND_SCALE = 13, 1011 FW_FLOWC_MNEM_RCV_SCALE = 14, 1012 FW_FLOWC_MNEM_ULP_MODE = 15, 1013 FW_FLOWC_MNEM_MAX = 16, 1014}; 1015 1016struct fw_flowc_mnemval { 1017 __u8 mnemonic; 1018 __u8 r4[3]; 1019 __be32 val; 1020}; 1021 1022struct fw_flowc_wr { 1023 __be32 op_to_nparams; 1024 __be32 flowid_len16; 1025#ifndef C99_NOT_SUPPORTED 1026 struct fw_flowc_mnemval mnemval[0]; 1027#endif 1028}; 1029 1030#define S_FW_FLOWC_WR_NPARAMS 0 1031#define M_FW_FLOWC_WR_NPARAMS 0xff 1032#define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 1033#define G_FW_FLOWC_WR_NPARAMS(x) \ 1034 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 1035 1036struct fw_ofld_tx_data_wr { 1037 __be32 op_to_immdlen; 1038 __be32 flowid_len16; 1039 __be32 plen; 1040 __be32 lsodisable_to_flags; 1041}; 1042 1043#define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 1044#define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 1045#define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1046 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 1047#define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1048 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 1049 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 1050#define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 1051 1052#define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 1053#define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 1054#define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1055 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1056#define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1057 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1058#define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 1059 1060#define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 1061#define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 1062#define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1063 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1064#define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1065 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 1066 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1067#define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 1068 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 1069 1070#define S_FW_OFLD_TX_DATA_WR_FLAGS 0 1071#define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 1072#define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 1073#define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 1074 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 1075 1076 1077/* Use fw_ofld_tx_data_wr structure */ 1078#define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 1079#define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 1080#define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1081 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1082#define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1083 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1084 1085#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 1086#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 1087#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1088 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1089#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1090 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 1091 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1092#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 1093 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 1094 1095#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 1096#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 1097#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1098 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1099#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1100 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 1101 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1102#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 1103 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1104 1105#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1106#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1107#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1108 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1109#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1110 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1111 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1112#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1113 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1114 1115#define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1116#define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1117#define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1118 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1119#define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1120 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1121 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1122#define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1123 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1124 1125#define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1126#define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1127#define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1128 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1129#define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1130 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1131 1132struct fw_cmd_wr { 1133 __be32 op_dma; 1134 __be32 len16_pkd; 1135 __be64 cookie_daddr; 1136}; 1137 1138#define S_FW_CMD_WR_DMA 17 1139#define M_FW_CMD_WR_DMA 0x1 1140#define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1141#define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1142#define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1143 1144struct fw_eth_tx_pkt_vm_wr { 1145 __be32 op_immdlen; 1146 __be32 equiq_to_len16; 1147 __be32 r3[2]; 1148 __u8 ethmacdst[6]; 1149 __u8 ethmacsrc[6]; 1150 __be16 ethtype; 1151 __be16 vlantci; 1152}; 1153 1154/****************************************************************************** 1155 * R I W O R K R E Q U E S T s 1156 **************************************/ 1157 1158enum fw_ri_wr_opcode { 1159 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1160 FW_RI_READ_REQ = 0x1, 1161 FW_RI_READ_RESP = 0x2, 1162 FW_RI_SEND = 0x3, 1163 FW_RI_SEND_WITH_INV = 0x4, 1164 FW_RI_SEND_WITH_SE = 0x5, 1165 FW_RI_SEND_WITH_SE_INV = 0x6, 1166 FW_RI_TERMINATE = 0x7, 1167 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1168 FW_RI_BIND_MW = 0x9, 1169 FW_RI_FAST_REGISTER = 0xa, 1170 FW_RI_LOCAL_INV = 0xb, 1171 FW_RI_QP_MODIFY = 0xc, 1172 FW_RI_BYPASS = 0xd, 1173 FW_RI_RECEIVE = 0xe, 1174#if 0 1175 FW_RI_SEND_IMMEDIATE = 0x8, 1176 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1177 FW_RI_ATOMIC_REQUEST = 0xa, 1178 FW_RI_ATOMIC_RESPONSE = 0xb, 1179 1180 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1181 FW_RI_FAST_REGISTER = 0xd, 1182 FW_RI_LOCAL_INV = 0xe, 1183#endif 1184 FW_RI_SGE_EC_CR_RETURN = 0xf, 1185 FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT, 1186}; 1187 1188enum fw_ri_wr_flags { 1189 FW_RI_COMPLETION_FLAG = 0x01, 1190 FW_RI_NOTIFICATION_FLAG = 0x02, 1191 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1192 FW_RI_READ_FENCE_FLAG = 0x08, 1193 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1194 FW_RI_RDMA_READ_INVALIDATE = 0x20, 1195 FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40 1196}; 1197 1198enum fw_ri_mpa_attrs { 1199 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1200 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1201 FW_RI_MPA_CRC_ENABLE = 0x04, 1202 FW_RI_MPA_IETF_ENABLE = 0x08 1203}; 1204 1205enum fw_ri_qp_caps { 1206 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1207 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1208 FW_RI_QP_BIND_ENABLE = 0x04, 1209 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1210 FW_RI_QP_STAG0_ENABLE = 0x10, 1211 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1212}; 1213 1214enum fw_ri_addr_type { 1215 FW_RI_ZERO_BASED_TO = 0x00, 1216 FW_RI_VA_BASED_TO = 0x01 1217}; 1218 1219enum fw_ri_mem_perms { 1220 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1221 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1222 FW_RI_MEM_ACCESS_REM = 0x03, 1223 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1224 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1225 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1226}; 1227 1228enum fw_ri_stag_type { 1229 FW_RI_STAG_NSMR = 0x00, 1230 FW_RI_STAG_SMR = 0x01, 1231 FW_RI_STAG_MW = 0x02, 1232 FW_RI_STAG_MW_RELAXED = 0x03 1233}; 1234 1235enum fw_ri_data_op { 1236 FW_RI_DATA_IMMD = 0x81, 1237 FW_RI_DATA_DSGL = 0x82, 1238 FW_RI_DATA_ISGL = 0x83 1239}; 1240 1241enum fw_ri_sgl_depth { 1242 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1243 FW_RI_SGL_DEPTH_MAX_RQ = 4 1244}; 1245 1246enum fw_ri_cqe_err { 1247 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1248 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1249 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1250 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1251 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1252 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1253 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1254 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1255 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1256 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1257 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1258 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1259 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1260 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1261 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1262 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1263 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1264 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1265 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1266 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1267 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1268 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1269 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1270 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1271 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1272 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1273 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1274 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1275 1276}; 1277 1278struct fw_ri_dsge_pair { 1279 __be32 len[2]; 1280 __be64 addr[2]; 1281}; 1282 1283struct fw_ri_dsgl { 1284 __u8 op; 1285 __u8 r1; 1286 __be16 nsge; 1287 __be32 len0; 1288 __be64 addr0; 1289#ifndef C99_NOT_SUPPORTED 1290 struct fw_ri_dsge_pair sge[0]; 1291#endif 1292}; 1293 1294struct fw_ri_sge { 1295 __be32 stag; 1296 __be32 len; 1297 __be64 to; 1298}; 1299 1300struct fw_ri_isgl { 1301 __u8 op; 1302 __u8 r1; 1303 __be16 nsge; 1304 __be32 r2; 1305#ifndef C99_NOT_SUPPORTED 1306 struct fw_ri_sge sge[0]; 1307#endif 1308}; 1309 1310struct fw_ri_immd { 1311 __u8 op; 1312 __u8 r1; 1313 __be16 r2; 1314 __be32 immdlen; 1315#ifndef C99_NOT_SUPPORTED 1316 __u8 data[0]; 1317#endif 1318}; 1319 1320struct fw_ri_tpte { 1321 __be32 valid_to_pdid; 1322 __be32 locread_to_qpid; 1323 __be32 nosnoop_pbladdr; 1324 __be32 len_lo; 1325 __be32 va_hi; 1326 __be32 va_lo_fbo; 1327 __be32 dca_mwbcnt_pstag; 1328 __be32 len_hi; 1329}; 1330 1331#define S_FW_RI_TPTE_VALID 31 1332#define M_FW_RI_TPTE_VALID 0x1 1333#define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1334#define G_FW_RI_TPTE_VALID(x) \ 1335 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1336#define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1337 1338#define S_FW_RI_TPTE_STAGKEY 23 1339#define M_FW_RI_TPTE_STAGKEY 0xff 1340#define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1341#define G_FW_RI_TPTE_STAGKEY(x) \ 1342 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1343 1344#define S_FW_RI_TPTE_STAGSTATE 22 1345#define M_FW_RI_TPTE_STAGSTATE 0x1 1346#define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1347#define G_FW_RI_TPTE_STAGSTATE(x) \ 1348 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1349#define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1350 1351#define S_FW_RI_TPTE_STAGTYPE 20 1352#define M_FW_RI_TPTE_STAGTYPE 0x3 1353#define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1354#define G_FW_RI_TPTE_STAGTYPE(x) \ 1355 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1356 1357#define S_FW_RI_TPTE_PDID 0 1358#define M_FW_RI_TPTE_PDID 0xfffff 1359#define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1360#define G_FW_RI_TPTE_PDID(x) \ 1361 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1362 1363#define S_FW_RI_TPTE_PERM 28 1364#define M_FW_RI_TPTE_PERM 0xf 1365#define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1366#define G_FW_RI_TPTE_PERM(x) \ 1367 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1368 1369#define S_FW_RI_TPTE_REMINVDIS 27 1370#define M_FW_RI_TPTE_REMINVDIS 0x1 1371#define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1372#define G_FW_RI_TPTE_REMINVDIS(x) \ 1373 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1374#define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1375 1376#define S_FW_RI_TPTE_ADDRTYPE 26 1377#define M_FW_RI_TPTE_ADDRTYPE 1 1378#define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1379#define G_FW_RI_TPTE_ADDRTYPE(x) \ 1380 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1381#define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1382 1383#define S_FW_RI_TPTE_MWBINDEN 25 1384#define M_FW_RI_TPTE_MWBINDEN 0x1 1385#define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1386#define G_FW_RI_TPTE_MWBINDEN(x) \ 1387 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1388#define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1389 1390#define S_FW_RI_TPTE_PS 20 1391#define M_FW_RI_TPTE_PS 0x1f 1392#define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1393#define G_FW_RI_TPTE_PS(x) \ 1394 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1395 1396#define S_FW_RI_TPTE_QPID 0 1397#define M_FW_RI_TPTE_QPID 0xfffff 1398#define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1399#define G_FW_RI_TPTE_QPID(x) \ 1400 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1401 1402#define S_FW_RI_TPTE_NOSNOOP 31 1403#define M_FW_RI_TPTE_NOSNOOP 0x1 1404#define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1405#define G_FW_RI_TPTE_NOSNOOP(x) \ 1406 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1407#define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1408 1409#define S_FW_RI_TPTE_PBLADDR 0 1410#define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1411#define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1412#define G_FW_RI_TPTE_PBLADDR(x) \ 1413 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1414 1415#define S_FW_RI_TPTE_DCA 24 1416#define M_FW_RI_TPTE_DCA 0x1f 1417#define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1418#define G_FW_RI_TPTE_DCA(x) \ 1419 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1420 1421#define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1422#define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1423#define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1424 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1425#define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1426 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1427 1428enum fw_ri_cqe_rxtx { 1429 FW_RI_CQE_RXTX_RX = 0x0, 1430 FW_RI_CQE_RXTX_TX = 0x1, 1431}; 1432 1433struct fw_ri_cqe { 1434 union fw_ri_rxtx { 1435 struct fw_ri_scqe { 1436 __be32 qpid_n_stat_rxtx_type; 1437 __be32 plen; 1438 __be32 stag; 1439 __be32 wrid; 1440 } scqe; 1441 struct fw_ri_rcqe { 1442 __be32 qpid_n_stat_rxtx_type; 1443 __be32 plen; 1444 __be32 stag; 1445 __be32 msn; 1446 } rcqe; 1447 struct fw_ri_rcqe_imm { 1448 __be32 qpid_n_stat_rxtx_type; 1449 __be32 plen; 1450 __be32 mo; 1451 __be32 msn; 1452 __u64 imm_data; 1453 } imm_data_rcqe; 1454 } u; 1455}; 1456 1457#define S_FW_RI_CQE_QPID 12 1458#define M_FW_RI_CQE_QPID 0xfffff 1459#define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1460#define G_FW_RI_CQE_QPID(x) \ 1461 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1462 1463#define S_FW_RI_CQE_NOTIFY 10 1464#define M_FW_RI_CQE_NOTIFY 0x1 1465#define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1466#define G_FW_RI_CQE_NOTIFY(x) \ 1467 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1468 1469#define S_FW_RI_CQE_STATUS 5 1470#define M_FW_RI_CQE_STATUS 0x1f 1471#define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1472#define G_FW_RI_CQE_STATUS(x) \ 1473 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1474 1475 1476#define S_FW_RI_CQE_RXTX 4 1477#define M_FW_RI_CQE_RXTX 0x1 1478#define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1479#define G_FW_RI_CQE_RXTX(x) \ 1480 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1481 1482#define S_FW_RI_CQE_TYPE 0 1483#define M_FW_RI_CQE_TYPE 0xf 1484#define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1485#define G_FW_RI_CQE_TYPE(x) \ 1486 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1487 1488enum fw_ri_res_type { 1489 FW_RI_RES_TYPE_SQ, 1490 FW_RI_RES_TYPE_RQ, 1491 FW_RI_RES_TYPE_CQ, 1492 FW_RI_RES_TYPE_SRQ, 1493}; 1494 1495enum fw_ri_res_op { 1496 FW_RI_RES_OP_WRITE, 1497 FW_RI_RES_OP_RESET, 1498}; 1499 1500struct fw_ri_res { 1501 union fw_ri_restype { 1502 struct fw_ri_res_sqrq { 1503 __u8 restype; 1504 __u8 op; 1505 __be16 r3; 1506 __be32 eqid; 1507 __be32 r4[2]; 1508 __be32 fetchszm_to_iqid; 1509 __be32 dcaen_to_eqsize; 1510 __be64 eqaddr; 1511 } sqrq; 1512 struct fw_ri_res_cq { 1513 __u8 restype; 1514 __u8 op; 1515 __be16 r3; 1516 __be32 iqid; 1517 __be32 r4[2]; 1518 __be32 iqandst_to_iqandstindex; 1519 __be16 iqdroprss_to_iqesize; 1520 __be16 iqsize; 1521 __be64 iqaddr; 1522 __be32 iqns_iqro; 1523 __be32 r6_lo; 1524 __be64 r7; 1525 } cq; 1526 struct fw_ri_res_srq { 1527 __u8 restype; 1528 __u8 op; 1529 __be16 r3; 1530 __be32 eqid; 1531 __be32 r4[2]; 1532 __be32 fetchszm_to_iqid; 1533 __be32 dcaen_to_eqsize; 1534 __be64 eqaddr; 1535 __be32 srqid; 1536 __be32 pdid; 1537 __be32 hwsrqsize; 1538 __be32 hwsrqaddr; 1539 } srq; 1540 } u; 1541}; 1542 1543struct fw_ri_res_wr { 1544 __be32 op_nres; 1545 __be32 len16_pkd; 1546 __u64 cookie; 1547#ifndef C99_NOT_SUPPORTED 1548 struct fw_ri_res res[0]; 1549#endif 1550}; 1551 1552#define S_FW_RI_RES_WR_VFN 8 1553#define M_FW_RI_RES_WR_VFN 0xff 1554#define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN) 1555#define G_FW_RI_RES_WR_VFN(x) \ 1556 (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN) 1557 1558#define S_FW_RI_RES_WR_NRES 0 1559#define M_FW_RI_RES_WR_NRES 0xff 1560#define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1561#define G_FW_RI_RES_WR_NRES(x) \ 1562 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1563 1564#define S_FW_RI_RES_WR_FETCHSZM 26 1565#define M_FW_RI_RES_WR_FETCHSZM 0x1 1566#define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1567#define G_FW_RI_RES_WR_FETCHSZM(x) \ 1568 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1569#define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1570 1571#define S_FW_RI_RES_WR_STATUSPGNS 25 1572#define M_FW_RI_RES_WR_STATUSPGNS 0x1 1573#define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1574#define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1575 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1576#define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1577 1578#define S_FW_RI_RES_WR_STATUSPGRO 24 1579#define M_FW_RI_RES_WR_STATUSPGRO 0x1 1580#define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1581#define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1582 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1583#define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1584 1585#define S_FW_RI_RES_WR_FETCHNS 23 1586#define M_FW_RI_RES_WR_FETCHNS 0x1 1587#define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1588#define G_FW_RI_RES_WR_FETCHNS(x) \ 1589 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1590#define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1591 1592#define S_FW_RI_RES_WR_FETCHRO 22 1593#define M_FW_RI_RES_WR_FETCHRO 0x1 1594#define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1595#define G_FW_RI_RES_WR_FETCHRO(x) \ 1596 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1597#define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1598 1599#define S_FW_RI_RES_WR_HOSTFCMODE 20 1600#define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1601#define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1602#define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1603 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1604 1605#define S_FW_RI_RES_WR_CPRIO 19 1606#define M_FW_RI_RES_WR_CPRIO 0x1 1607#define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1608#define G_FW_RI_RES_WR_CPRIO(x) \ 1609 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1610#define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1611 1612#define S_FW_RI_RES_WR_ONCHIP 18 1613#define M_FW_RI_RES_WR_ONCHIP 0x1 1614#define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1615#define G_FW_RI_RES_WR_ONCHIP(x) \ 1616 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1617#define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1618 1619#define S_FW_RI_RES_WR_PCIECHN 16 1620#define M_FW_RI_RES_WR_PCIECHN 0x3 1621#define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1622#define G_FW_RI_RES_WR_PCIECHN(x) \ 1623 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1624 1625#define S_FW_RI_RES_WR_IQID 0 1626#define M_FW_RI_RES_WR_IQID 0xffff 1627#define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1628#define G_FW_RI_RES_WR_IQID(x) \ 1629 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1630 1631#define S_FW_RI_RES_WR_DCAEN 31 1632#define M_FW_RI_RES_WR_DCAEN 0x1 1633#define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1634#define G_FW_RI_RES_WR_DCAEN(x) \ 1635 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1636#define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1637 1638#define S_FW_RI_RES_WR_DCACPU 26 1639#define M_FW_RI_RES_WR_DCACPU 0x1f 1640#define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1641#define G_FW_RI_RES_WR_DCACPU(x) \ 1642 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1643 1644#define S_FW_RI_RES_WR_FBMIN 23 1645#define M_FW_RI_RES_WR_FBMIN 0x7 1646#define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1647#define G_FW_RI_RES_WR_FBMIN(x) \ 1648 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1649 1650#define S_FW_RI_RES_WR_FBMAX 20 1651#define M_FW_RI_RES_WR_FBMAX 0x7 1652#define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1653#define G_FW_RI_RES_WR_FBMAX(x) \ 1654 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1655 1656#define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1657#define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1658#define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1659#define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1660 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1661#define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1662 1663#define S_FW_RI_RES_WR_CIDXFTHRESH 16 1664#define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1665#define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1666#define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1667 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1668 1669#define S_FW_RI_RES_WR_EQSIZE 0 1670#define M_FW_RI_RES_WR_EQSIZE 0xffff 1671#define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1672#define G_FW_RI_RES_WR_EQSIZE(x) \ 1673 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1674 1675#define S_FW_RI_RES_WR_IQANDST 15 1676#define M_FW_RI_RES_WR_IQANDST 0x1 1677#define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1678#define G_FW_RI_RES_WR_IQANDST(x) \ 1679 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1680#define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1681 1682#define S_FW_RI_RES_WR_IQANUS 14 1683#define M_FW_RI_RES_WR_IQANUS 0x1 1684#define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1685#define G_FW_RI_RES_WR_IQANUS(x) \ 1686 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1687#define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1688 1689#define S_FW_RI_RES_WR_IQANUD 12 1690#define M_FW_RI_RES_WR_IQANUD 0x3 1691#define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1692#define G_FW_RI_RES_WR_IQANUD(x) \ 1693 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1694 1695#define S_FW_RI_RES_WR_IQANDSTINDEX 0 1696#define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1697#define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1698#define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1699 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1700 1701#define S_FW_RI_RES_WR_IQDROPRSS 15 1702#define M_FW_RI_RES_WR_IQDROPRSS 0x1 1703#define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1704#define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1705 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1706#define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1707 1708#define S_FW_RI_RES_WR_IQGTSMODE 14 1709#define M_FW_RI_RES_WR_IQGTSMODE 0x1 1710#define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1711#define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1712 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1713#define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1714 1715#define S_FW_RI_RES_WR_IQPCIECH 12 1716#define M_FW_RI_RES_WR_IQPCIECH 0x3 1717#define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1718#define G_FW_RI_RES_WR_IQPCIECH(x) \ 1719 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1720 1721#define S_FW_RI_RES_WR_IQDCAEN 11 1722#define M_FW_RI_RES_WR_IQDCAEN 0x1 1723#define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1724#define G_FW_RI_RES_WR_IQDCAEN(x) \ 1725 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1726#define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1727 1728#define S_FW_RI_RES_WR_IQDCACPU 6 1729#define M_FW_RI_RES_WR_IQDCACPU 0x1f 1730#define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1731#define G_FW_RI_RES_WR_IQDCACPU(x) \ 1732 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1733 1734#define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1735#define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1736#define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1737 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1738#define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1739 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1740 1741#define S_FW_RI_RES_WR_IQO 3 1742#define M_FW_RI_RES_WR_IQO 0x1 1743#define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1744#define G_FW_RI_RES_WR_IQO(x) \ 1745 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1746#define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1747 1748#define S_FW_RI_RES_WR_IQCPRIO 2 1749#define M_FW_RI_RES_WR_IQCPRIO 0x1 1750#define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1751#define G_FW_RI_RES_WR_IQCPRIO(x) \ 1752 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1753#define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1754 1755#define S_FW_RI_RES_WR_IQESIZE 0 1756#define M_FW_RI_RES_WR_IQESIZE 0x3 1757#define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1758#define G_FW_RI_RES_WR_IQESIZE(x) \ 1759 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1760 1761#define S_FW_RI_RES_WR_IQNS 31 1762#define M_FW_RI_RES_WR_IQNS 0x1 1763#define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1764#define G_FW_RI_RES_WR_IQNS(x) \ 1765 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1766#define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1767 1768#define S_FW_RI_RES_WR_IQRO 30 1769#define M_FW_RI_RES_WR_IQRO 0x1 1770#define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1771#define G_FW_RI_RES_WR_IQRO(x) \ 1772 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1773#define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1774 1775struct fw_ri_rdma_write_wr { 1776 __u8 opcode; 1777 __u8 flags; 1778 __u16 wrid; 1779 __u8 r1[3]; 1780 __u8 len16; 1781 __u64 immd_data; 1782 __be32 plen; 1783 __be32 stag_sink; 1784 __be64 to_sink; 1785#ifndef C99_NOT_SUPPORTED 1786 union { 1787 struct fw_ri_immd immd_src[0]; 1788 struct fw_ri_isgl isgl_src[0]; 1789 } u; 1790#endif 1791}; 1792 1793struct fw_ri_send_wr { 1794 __u8 opcode; 1795 __u8 flags; 1796 __u16 wrid; 1797 __u8 r1[3]; 1798 __u8 len16; 1799 __be32 sendop_pkd; 1800 __be32 stag_inv; 1801 __be32 plen; 1802 __be32 r3; 1803 __be64 r4; 1804#ifndef C99_NOT_SUPPORTED 1805 union { 1806 struct fw_ri_immd immd_src[0]; 1807 struct fw_ri_isgl isgl_src[0]; 1808 } u; 1809#endif 1810}; 1811 1812#define S_FW_RI_SEND_WR_SENDOP 0 1813#define M_FW_RI_SEND_WR_SENDOP 0xf 1814#define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1815#define G_FW_RI_SEND_WR_SENDOP(x) \ 1816 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1817 1818struct fw_ri_rdma_read_wr { 1819 __u8 opcode; 1820 __u8 flags; 1821 __u16 wrid; 1822 __u8 r1[3]; 1823 __u8 len16; 1824 __be64 r2; 1825 __be32 stag_sink; 1826 __be32 to_sink_hi; 1827 __be32 to_sink_lo; 1828 __be32 plen; 1829 __be32 stag_src; 1830 __be32 to_src_hi; 1831 __be32 to_src_lo; 1832 __be32 r5; 1833}; 1834 1835struct fw_ri_recv_wr { 1836 __u8 opcode; 1837 __u8 r1; 1838 __u16 wrid; 1839 __u8 r2[3]; 1840 __u8 len16; 1841 struct fw_ri_isgl isgl; 1842}; 1843 1844struct fw_ri_bind_mw_wr { 1845 __u8 opcode; 1846 __u8 flags; 1847 __u16 wrid; 1848 __u8 r1[3]; 1849 __u8 len16; 1850 __u8 qpbinde_to_dcacpu; 1851 __u8 pgsz_shift; 1852 __u8 addr_type; 1853 __u8 mem_perms; 1854 __be32 stag_mr; 1855 __be32 stag_mw; 1856 __be32 r3; 1857 __be64 len_mw; 1858 __be64 va_fbo; 1859 __be64 r4; 1860}; 1861 1862#define S_FW_RI_BIND_MW_WR_QPBINDE 6 1863#define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1864#define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1865#define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1866 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1867#define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1868 1869#define S_FW_RI_BIND_MW_WR_NS 5 1870#define M_FW_RI_BIND_MW_WR_NS 0x1 1871#define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1872#define G_FW_RI_BIND_MW_WR_NS(x) \ 1873 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1874#define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1875 1876#define S_FW_RI_BIND_MW_WR_DCACPU 0 1877#define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1878#define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1879#define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1880 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1881 1882struct fw_ri_fr_nsmr_wr { 1883 __u8 opcode; 1884 __u8 flags; 1885 __u16 wrid; 1886 __u8 r1[3]; 1887 __u8 len16; 1888 __u8 qpbinde_to_dcacpu; 1889 __u8 pgsz_shift; 1890 __u8 addr_type; 1891 __u8 mem_perms; 1892 __be32 stag; 1893 __be32 len_hi; 1894 __be32 len_lo; 1895 __be32 va_hi; 1896 __be32 va_lo_fbo; 1897}; 1898 1899#define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1900#define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1901#define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1902#define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1903 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1904#define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1905 1906#define S_FW_RI_FR_NSMR_WR_NS 5 1907#define M_FW_RI_FR_NSMR_WR_NS 0x1 1908#define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1909#define G_FW_RI_FR_NSMR_WR_NS(x) \ 1910 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1911#define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1912 1913#define S_FW_RI_FR_NSMR_WR_DCACPU 0 1914#define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1915#define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1916#define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1917 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1918 1919struct fw_ri_fr_nsmr_tpte_wr { 1920 __u8 opcode; 1921 __u8 flags; 1922 __u16 wrid; 1923 __u8 r1[3]; 1924 __u8 len16; 1925 __be32 r2; 1926 __be32 stag; 1927 struct fw_ri_tpte tpte; 1928 __be64 pbl[2]; 1929}; 1930 1931struct fw_ri_inv_lstag_wr { 1932 __u8 opcode; 1933 __u8 flags; 1934 __u16 wrid; 1935 __u8 r1[3]; 1936 __u8 len16; 1937 __be32 r2; 1938 __be32 stag_inv; 1939}; 1940 1941struct fw_ri_send_immediate_wr { 1942 __u8 opcode; 1943 __u8 flags; 1944 __u16 wrid; 1945 __u8 r1[3]; 1946 __u8 len16; 1947 __be32 sendimmop_pkd; 1948 __be32 r3; 1949 __be32 plen; 1950 __be32 r4; 1951 __be64 r5; 1952#ifndef C99_NOT_SUPPORTED 1953 struct fw_ri_immd immd_src[0]; 1954#endif 1955}; 1956 1957#define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1958#define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1959#define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1960 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1961#define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1962 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1963 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1964 1965enum fw_ri_atomic_op { 1966 FW_RI_ATOMIC_OP_FETCHADD, 1967 FW_RI_ATOMIC_OP_SWAP, 1968 FW_RI_ATOMIC_OP_CMDSWAP, 1969}; 1970 1971struct fw_ri_atomic_wr { 1972 __u8 opcode; 1973 __u8 flags; 1974 __u16 wrid; 1975 __u8 r1[3]; 1976 __u8 len16; 1977 __be32 atomicop_pkd; 1978 __be64 r3; 1979 __be32 aopcode_pkd; 1980 __be32 reqid; 1981 __be32 stag; 1982 __be32 to_hi; 1983 __be32 to_lo; 1984 __be32 addswap_data_hi; 1985 __be32 addswap_data_lo; 1986 __be32 addswap_mask_hi; 1987 __be32 addswap_mask_lo; 1988 __be32 compare_data_hi; 1989 __be32 compare_data_lo; 1990 __be32 compare_mask_hi; 1991 __be32 compare_mask_lo; 1992 __be32 r5; 1993}; 1994 1995#define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1996#define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1997#define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 1998#define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 1999 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 2000 2001#define S_FW_RI_ATOMIC_WR_AOPCODE 0 2002#define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 2003#define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 2004#define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 2005 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 2006 2007enum fw_ri_type { 2008 FW_RI_TYPE_INIT, 2009 FW_RI_TYPE_FINI, 2010 FW_RI_TYPE_TERMINATE 2011}; 2012 2013enum fw_ri_init_p2ptype { 2014 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 2015 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 2016 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 2017 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 2018 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 2019 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 2020 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 2021}; 2022 2023enum fw_ri_init_rqeqid_srq { 2024 FW_RI_INIT_RQEQID_SRQ = 1 << 31, 2025}; 2026 2027struct fw_ri_wr { 2028 __be32 op_compl; 2029 __be32 flowid_len16; 2030 __u64 cookie; 2031 union fw_ri { 2032 struct fw_ri_init { 2033 __u8 type; 2034 __u8 mpareqbit_p2ptype; 2035 __u8 r4[2]; 2036 __u8 mpa_attrs; 2037 __u8 qp_caps; 2038 __be16 nrqe; 2039 __be32 pdid; 2040 __be32 qpid; 2041 __be32 sq_eqid; 2042 __be32 rq_eqid; 2043 __be32 scqid; 2044 __be32 rcqid; 2045 __be32 ord_max; 2046 __be32 ird_max; 2047 __be32 iss; 2048 __be32 irs; 2049 __be32 hwrqsize; 2050 __be32 hwrqaddr; 2051 __be64 r5; 2052 union fw_ri_init_p2p { 2053 struct fw_ri_rdma_write_wr write; 2054 struct fw_ri_rdma_read_wr read; 2055 struct fw_ri_send_wr send; 2056 } u; 2057 } init; 2058 struct fw_ri_fini { 2059 __u8 type; 2060 __u8 r3[7]; 2061 __be64 r4; 2062 } fini; 2063 struct fw_ri_terminate { 2064 __u8 type; 2065 __u8 r3[3]; 2066 __be32 immdlen; 2067 __u8 termmsg[40]; 2068 } terminate; 2069 } u; 2070}; 2071 2072#define S_FW_RI_WR_MPAREQBIT 7 2073#define M_FW_RI_WR_MPAREQBIT 0x1 2074#define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 2075#define G_FW_RI_WR_MPAREQBIT(x) \ 2076 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 2077#define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 2078 2079#define S_FW_RI_WR_0BRRBIT 6 2080#define M_FW_RI_WR_0BRRBIT 0x1 2081#define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 2082#define G_FW_RI_WR_0BRRBIT(x) \ 2083 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 2084#define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 2085 2086#define S_FW_RI_WR_P2PTYPE 0 2087#define M_FW_RI_WR_P2PTYPE 0xf 2088#define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 2089#define G_FW_RI_WR_P2PTYPE(x) \ 2090 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 2091 2092/****************************************************************************** 2093 * F O i S C S I W O R K R E Q U E S T s 2094 *********************************************/ 2095 2096#define FW_FOISCSI_NAME_MAX_LEN 224 2097#define FW_FOISCSI_ALIAS_MAX_LEN 224 2098#define FW_FOISCSI_KEY_MAX_LEN 64 2099#define FW_FOISCSI_VAL_MAX_LEN 256 2100#define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 2101#define FW_FOISCSI_INIT_NODE_MAX 8 2102 2103enum fw_chnet_ifconf_wr_subop { 2104 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 2105 2106 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 2107 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 2108 2109 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 2110 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 2111 2112 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 2113 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 2114 2115 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 2116 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 2117 2118 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 2119 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 2120 2121 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 2122 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 2123 2124 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 2125 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 2126 2127 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 2128 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 2129 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 2130 2131 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING4, 2132 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING6, 2133 2134 FW_CHNET_IFCONF_WR_SUBOP_MAX, 2135}; 2136 2137struct fw_chnet_ifconf_wr { 2138 __be32 op_compl; 2139 __be32 flowid_len16; 2140 __u64 cookie; 2141 __be32 if_flowid; 2142 __u8 idx; 2143 __u8 subop; 2144 __u8 retval; 2145 __u8 r2; 2146 union { 2147 __be64 r3; 2148 struct fw_chnet_ifconf_ping { 2149 __be16 ping_time; 2150 __u8 ping_rsptype; 2151 __u8 ping_param_rspcode_to_fin_bit; 2152 __u8 ping_pktsize; 2153 __u8 ping_ttl; 2154 __be16 ping_seq; 2155 } ping; 2156 struct fw_chnet_ifconf_mac { 2157 __u8 peer_mac[6]; 2158 __u8 smac_idx; 2159 } mac; 2160 } u; 2161 struct fw_chnet_ifconf_params { 2162 __be32 r0; 2163 __be16 vlanid; 2164 __be16 mtu; 2165 union fw_chnet_ifconf_addr_type { 2166 struct fw_chnet_ifconf_ipv4 { 2167 __be32 addr; 2168 __be32 mask; 2169 __be32 router; 2170 __be32 r0; 2171 __be64 r1; 2172 } ipv4; 2173 struct fw_chnet_ifconf_ipv6 { 2174 __u8 prefix_len; 2175 __u8 r0; 2176 __be16 r1; 2177 __be32 r2; 2178 __be64 addr_hi; 2179 __be64 addr_lo; 2180 __be64 router_hi; 2181 __be64 router_lo; 2182 } ipv6; 2183 } in_attr; 2184 } param; 2185}; 2186 2187#define S_FW_CHNET_IFCONF_WR_PING_MACBIT 1 2188#define M_FW_CHNET_IFCONF_WR_PING_MACBIT 0x1 2189#define V_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \ 2190 ((x) << S_FW_CHNET_IFCONF_WR_PING_MACBIT) 2191#define G_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \ 2192 (((x) >> S_FW_CHNET_IFCONF_WR_PING_MACBIT) & \ 2193 M_FW_CHNET_IFCONF_WR_PING_MACBIT) 2194#define F_FW_CHNET_IFCONF_WR_PING_MACBIT \ 2195 V_FW_CHNET_IFCONF_WR_PING_MACBIT(1U) 2196 2197#define S_FW_CHNET_IFCONF_WR_FIN_BIT 0 2198#define M_FW_CHNET_IFCONF_WR_FIN_BIT 0x1 2199#define V_FW_CHNET_IFCONF_WR_FIN_BIT(x) ((x) << S_FW_CHNET_IFCONF_WR_FIN_BIT) 2200#define G_FW_CHNET_IFCONF_WR_FIN_BIT(x) \ 2201 (((x) >> S_FW_CHNET_IFCONF_WR_FIN_BIT) & M_FW_CHNET_IFCONF_WR_FIN_BIT) 2202#define F_FW_CHNET_IFCONF_WR_FIN_BIT V_FW_CHNET_IFCONF_WR_FIN_BIT(1U) 2203 2204enum fw_foiscsi_node_type { 2205 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 2206 FW_FOISCSI_NODE_TYPE_TARGET, 2207}; 2208 2209enum fw_foiscsi_session_type { 2210 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 2211 FW_FOISCSI_SESSION_TYPE_NORMAL, 2212}; 2213 2214enum fw_foiscsi_auth_policy { 2215 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 2216 FW_FOISCSI_AUTH_POLICY_MUTUAL, 2217}; 2218 2219enum fw_foiscsi_auth_method { 2220 FW_FOISCSI_AUTH_METHOD_NONE = 0, 2221 FW_FOISCSI_AUTH_METHOD_CHAP, 2222 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 2223 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 2224}; 2225 2226enum fw_foiscsi_digest_type { 2227 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 2228 FW_FOISCSI_DIGEST_TYPE_CRC32, 2229 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 2230 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 2231}; 2232 2233enum fw_foiscsi_wr_subop { 2234 FW_FOISCSI_WR_SUBOP_ADD = 1, 2235 FW_FOISCSI_WR_SUBOP_DEL = 2, 2236 FW_FOISCSI_WR_SUBOP_MOD = 4, 2237}; 2238 2239enum fw_coiscsi_stats_wr_subop { 2240 FW_COISCSI_WR_SUBOP_TOT = 1, 2241 FW_COISCSI_WR_SUBOP_MAX = 2, 2242 FW_COISCSI_WR_SUBOP_CUR = 3, 2243 FW_COISCSI_WR_SUBOP_CLR = 4, 2244}; 2245 2246enum fw_foiscsi_ctrl_state { 2247 FW_FOISCSI_CTRL_STATE_FREE = 0, 2248 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 2249 FW_FOISCSI_CTRL_STATE_FAILED, 2250 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 2251 FW_FOISCSI_CTRL_STATE_REDIRECT, 2252}; 2253 2254struct fw_rdev_wr { 2255 __be32 op_to_immdlen; 2256 __be32 alloc_to_len16; 2257 __be64 cookie; 2258 __u8 protocol; 2259 __u8 event_cause; 2260 __u8 cur_state; 2261 __u8 prev_state; 2262 __be32 flags_to_assoc_flowid; 2263 union rdev_entry { 2264 struct fcoe_rdev_entry { 2265 __be32 flowid; 2266 __u8 protocol; 2267 __u8 event_cause; 2268 __u8 flags; 2269 __u8 rjt_reason; 2270 __u8 cur_login_st; 2271 __u8 prev_login_st; 2272 __be16 rcv_fr_sz; 2273 __u8 rd_xfer_rdy_to_rport_type; 2274 __u8 vft_to_qos; 2275 __u8 org_proc_assoc_to_acc_rsp_code; 2276 __u8 enh_disc_to_tgt; 2277 __u8 wwnn[8]; 2278 __u8 wwpn[8]; 2279 __be16 iqid; 2280 __u8 fc_oui[3]; 2281 __u8 r_id[3]; 2282 } fcoe_rdev; 2283 struct iscsi_rdev_entry { 2284 __be32 flowid; 2285 __u8 protocol; 2286 __u8 event_cause; 2287 __u8 flags; 2288 __u8 r3; 2289 __be16 iscsi_opts; 2290 __be16 tcp_opts; 2291 __be16 ip_opts; 2292 __be16 max_rcv_len; 2293 __be16 max_snd_len; 2294 __be16 first_brst_len; 2295 __be16 max_brst_len; 2296 __be16 r4; 2297 __be16 def_time2wait; 2298 __be16 def_time2ret; 2299 __be16 nop_out_intrvl; 2300 __be16 non_scsi_to; 2301 __be16 isid; 2302 __be16 tsid; 2303 __be16 port; 2304 __be16 tpgt; 2305 __u8 r5[6]; 2306 __be16 iqid; 2307 } iscsi_rdev; 2308 } u; 2309}; 2310 2311#define S_FW_RDEV_WR_IMMDLEN 0 2312#define M_FW_RDEV_WR_IMMDLEN 0xff 2313#define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2314#define G_FW_RDEV_WR_IMMDLEN(x) \ 2315 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2316 2317#define S_FW_RDEV_WR_ALLOC 31 2318#define M_FW_RDEV_WR_ALLOC 0x1 2319#define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2320#define G_FW_RDEV_WR_ALLOC(x) \ 2321 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2322#define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2323 2324#define S_FW_RDEV_WR_FREE 30 2325#define M_FW_RDEV_WR_FREE 0x1 2326#define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2327#define G_FW_RDEV_WR_FREE(x) \ 2328 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2329#define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2330 2331#define S_FW_RDEV_WR_MODIFY 29 2332#define M_FW_RDEV_WR_MODIFY 0x1 2333#define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2334#define G_FW_RDEV_WR_MODIFY(x) \ 2335 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2336#define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2337 2338#define S_FW_RDEV_WR_FLOWID 8 2339#define M_FW_RDEV_WR_FLOWID 0xfffff 2340#define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2341#define G_FW_RDEV_WR_FLOWID(x) \ 2342 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2343 2344#define S_FW_RDEV_WR_LEN16 0 2345#define M_FW_RDEV_WR_LEN16 0xff 2346#define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2347#define G_FW_RDEV_WR_LEN16(x) \ 2348 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2349 2350#define S_FW_RDEV_WR_FLAGS 24 2351#define M_FW_RDEV_WR_FLAGS 0xff 2352#define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2353#define G_FW_RDEV_WR_FLAGS(x) \ 2354 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2355 2356#define S_FW_RDEV_WR_GET_NEXT 20 2357#define M_FW_RDEV_WR_GET_NEXT 0xf 2358#define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2359#define G_FW_RDEV_WR_GET_NEXT(x) \ 2360 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2361 2362#define S_FW_RDEV_WR_ASSOC_FLOWID 0 2363#define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2364#define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2365#define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2366 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2367 2368#define S_FW_RDEV_WR_RJT 7 2369#define M_FW_RDEV_WR_RJT 0x1 2370#define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2371#define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2372#define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2373 2374#define S_FW_RDEV_WR_REASON 0 2375#define M_FW_RDEV_WR_REASON 0x7f 2376#define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2377#define G_FW_RDEV_WR_REASON(x) \ 2378 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2379 2380#define S_FW_RDEV_WR_RD_XFER_RDY 7 2381#define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2382#define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2383#define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2384 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2385#define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2386 2387#define S_FW_RDEV_WR_WR_XFER_RDY 6 2388#define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2389#define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2390#define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2391 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2392#define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2393 2394#define S_FW_RDEV_WR_FC_SP 5 2395#define M_FW_RDEV_WR_FC_SP 0x1 2396#define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2397#define G_FW_RDEV_WR_FC_SP(x) \ 2398 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2399#define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2400 2401#define S_FW_RDEV_WR_RPORT_TYPE 0 2402#define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2403#define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2404#define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2405 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2406 2407#define S_FW_RDEV_WR_VFT 7 2408#define M_FW_RDEV_WR_VFT 0x1 2409#define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2410#define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2411#define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2412 2413#define S_FW_RDEV_WR_NPIV 6 2414#define M_FW_RDEV_WR_NPIV 0x1 2415#define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2416#define G_FW_RDEV_WR_NPIV(x) \ 2417 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2418#define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2419 2420#define S_FW_RDEV_WR_CLASS 4 2421#define M_FW_RDEV_WR_CLASS 0x3 2422#define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2423#define G_FW_RDEV_WR_CLASS(x) \ 2424 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2425 2426#define S_FW_RDEV_WR_SEQ_DEL 3 2427#define M_FW_RDEV_WR_SEQ_DEL 0x1 2428#define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2429#define G_FW_RDEV_WR_SEQ_DEL(x) \ 2430 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2431#define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2432 2433#define S_FW_RDEV_WR_PRIO_PREEMP 2 2434#define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2435#define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2436#define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2437 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2438#define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2439 2440#define S_FW_RDEV_WR_PREF 1 2441#define M_FW_RDEV_WR_PREF 0x1 2442#define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2443#define G_FW_RDEV_WR_PREF(x) \ 2444 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2445#define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2446 2447#define S_FW_RDEV_WR_QOS 0 2448#define M_FW_RDEV_WR_QOS 0x1 2449#define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2450#define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2451#define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2452 2453#define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2454#define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2455#define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2456#define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2457 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2458#define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2459 2460#define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2461#define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2462#define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2463#define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2464 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2465#define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2466 2467#define S_FW_RDEV_WR_IMAGE_PAIR 5 2468#define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2469#define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2470#define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2471 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2472#define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2473 2474#define S_FW_RDEV_WR_ACC_RSP_CODE 0 2475#define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2476#define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2477#define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2478 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2479 2480#define S_FW_RDEV_WR_ENH_DISC 7 2481#define M_FW_RDEV_WR_ENH_DISC 0x1 2482#define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2483#define G_FW_RDEV_WR_ENH_DISC(x) \ 2484 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2485#define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2486 2487#define S_FW_RDEV_WR_REC 6 2488#define M_FW_RDEV_WR_REC 0x1 2489#define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2490#define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2491#define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2492 2493#define S_FW_RDEV_WR_TASK_RETRY_ID 5 2494#define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2495#define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2496#define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2497 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2498#define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2499 2500#define S_FW_RDEV_WR_RETRY 4 2501#define M_FW_RDEV_WR_RETRY 0x1 2502#define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2503#define G_FW_RDEV_WR_RETRY(x) \ 2504 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2505#define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2506 2507#define S_FW_RDEV_WR_CONF_CMPL 3 2508#define M_FW_RDEV_WR_CONF_CMPL 0x1 2509#define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2510#define G_FW_RDEV_WR_CONF_CMPL(x) \ 2511 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2512#define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2513 2514#define S_FW_RDEV_WR_DATA_OVLY 2 2515#define M_FW_RDEV_WR_DATA_OVLY 0x1 2516#define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2517#define G_FW_RDEV_WR_DATA_OVLY(x) \ 2518 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2519#define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2520 2521#define S_FW_RDEV_WR_INI 1 2522#define M_FW_RDEV_WR_INI 0x1 2523#define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2524#define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2525#define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2526 2527#define S_FW_RDEV_WR_TGT 0 2528#define M_FW_RDEV_WR_TGT 0x1 2529#define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2530#define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2531#define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2532 2533struct fw_foiscsi_node_wr { 2534 __be32 op_to_immdlen; 2535 __be32 no_sess_recv_to_len16; 2536 __u64 cookie; 2537 __u8 subop; 2538 __u8 status; 2539 __u8 alias_len; 2540 __u8 iqn_len; 2541 __be32 node_flowid; 2542 __be16 nodeid; 2543 __be16 login_retry; 2544 __be16 retry_timeout; 2545 __be16 r3; 2546 __u8 iqn[224]; 2547 __u8 alias[224]; 2548 __be32 isid_tval_to_isid_cval; 2549}; 2550 2551#define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2552#define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2553#define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2554#define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2555 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2556 2557#define S_FW_FOISCSI_NODE_WR_NO_SESS_RECV 28 2558#define M_FW_FOISCSI_NODE_WR_NO_SESS_RECV 0x1 2559#define V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \ 2560 ((x) << S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) 2561#define G_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \ 2562 (((x) >> S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) & \ 2563 M_FW_FOISCSI_NODE_WR_NO_SESS_RECV) 2564#define F_FW_FOISCSI_NODE_WR_NO_SESS_RECV \ 2565 V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(1U) 2566 2567#define S_FW_FOISCSI_NODE_WR_ISID_TVAL 30 2568#define M_FW_FOISCSI_NODE_WR_ISID_TVAL 0x3 2569#define V_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ 2570 ((x) << S_FW_FOISCSI_NODE_WR_ISID_TVAL) 2571#define G_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ 2572 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_TVAL) & M_FW_FOISCSI_NODE_WR_ISID_TVAL) 2573 2574#define S_FW_FOISCSI_NODE_WR_ISID_AVAL 24 2575#define M_FW_FOISCSI_NODE_WR_ISID_AVAL 0x3f 2576#define V_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ 2577 ((x) << S_FW_FOISCSI_NODE_WR_ISID_AVAL) 2578#define G_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ 2579 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_AVAL) & M_FW_FOISCSI_NODE_WR_ISID_AVAL) 2580 2581#define S_FW_FOISCSI_NODE_WR_ISID_BVAL 8 2582#define M_FW_FOISCSI_NODE_WR_ISID_BVAL 0xffff 2583#define V_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ 2584 ((x) << S_FW_FOISCSI_NODE_WR_ISID_BVAL) 2585#define G_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ 2586 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_BVAL) & M_FW_FOISCSI_NODE_WR_ISID_BVAL) 2587 2588#define S_FW_FOISCSI_NODE_WR_ISID_CVAL 0 2589#define M_FW_FOISCSI_NODE_WR_ISID_CVAL 0xff 2590#define V_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ 2591 ((x) << S_FW_FOISCSI_NODE_WR_ISID_CVAL) 2592#define G_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ 2593 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_CVAL) & M_FW_FOISCSI_NODE_WR_ISID_CVAL) 2594 2595struct fw_foiscsi_ctrl_wr { 2596 __be32 op_to_no_fin; 2597 __be32 flowid_len16; 2598 __u64 cookie; 2599 __u8 subop; 2600 __u8 status; 2601 __u8 ctrl_state; 2602 __u8 io_state; 2603 __be32 node_id; 2604 __be32 ctrl_id; 2605 __be32 io_id; 2606 struct fw_foiscsi_sess_attr { 2607 __be32 sess_type_to_erl; 2608 __be16 max_conn; 2609 __be16 max_r2t; 2610 __be16 time2wait; 2611 __be16 time2retain; 2612 __be32 max_burst; 2613 __be32 first_burst; 2614 __be32 r1; 2615 } sess_attr; 2616 struct fw_foiscsi_conn_attr { 2617 __be32 hdigest_to_tcp_ws_en; 2618 __be32 max_rcv_dsl; 2619 __be32 ping_tmo; 2620 __be16 dst_port; 2621 __be16 src_port; 2622 union fw_foiscsi_conn_attr_addr { 2623 struct fw_foiscsi_conn_attr_ipv6 { 2624 __be64 dst_addr[2]; 2625 __be64 src_addr[2]; 2626 } ipv6_addr; 2627 struct fw_foiscsi_conn_attr_ipv4 { 2628 __be32 dst_addr; 2629 __be32 src_addr; 2630 } ipv4_addr; 2631 } u; 2632 } conn_attr; 2633 __u8 tgt_name_len; 2634 __u8 r3[7]; 2635 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2636}; 2637 2638#define S_FW_FOISCSI_CTRL_WR_NO_FIN 0 2639#define M_FW_FOISCSI_CTRL_WR_NO_FIN 0x1 2640#define V_FW_FOISCSI_CTRL_WR_NO_FIN(x) ((x) << S_FW_FOISCSI_CTRL_WR_NO_FIN) 2641#define G_FW_FOISCSI_CTRL_WR_NO_FIN(x) \ 2642 (((x) >> S_FW_FOISCSI_CTRL_WR_NO_FIN) & M_FW_FOISCSI_CTRL_WR_NO_FIN) 2643#define F_FW_FOISCSI_CTRL_WR_NO_FIN V_FW_FOISCSI_CTRL_WR_NO_FIN(1U) 2644 2645#define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2646#define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2647#define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2648 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2649#define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2650 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2651 2652#define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2653#define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2654#define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2655 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2656#define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2657 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2658 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2659#define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2660 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2661 2662#define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2663#define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2664#define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2665 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2666#define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2667 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2668 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2669#define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2670 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2671 2672#define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2673#define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2674#define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2675 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2676#define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2677 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2678 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2679#define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2680 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2681 2682#define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2683#define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2684#define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2685 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2686#define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2687 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2688 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2689#define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2690 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2691 2692#define S_FW_FOISCSI_CTRL_WR_ERL 24 2693#define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2694#define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2695#define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2696 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2697 2698#define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2699#define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2700#define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2701#define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2702 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2703 2704#define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2705#define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2706#define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2707#define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2708 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2709 2710#define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2711#define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2712#define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2713 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2714#define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2715 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2716 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2717 2718#define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2719#define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2720#define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2721 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2722#define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2723 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2724 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2725 2726#define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2727#define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2728#define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2729 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2730#define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2731 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2732 2733#define S_FW_FOISCSI_CTRL_WR_IPV6 20 2734#define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 2735#define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 2736#define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 2737 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 2738#define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 2739 2740#define S_FW_FOISCSI_CTRL_WR_DDP_PGIDX 16 2741#define M_FW_FOISCSI_CTRL_WR_DDP_PGIDX 0xf 2742#define V_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ 2743 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) 2744#define G_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ 2745 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) & M_FW_FOISCSI_CTRL_WR_DDP_PGIDX) 2746 2747#define S_FW_FOISCSI_CTRL_WR_TCP_WS 12 2748#define M_FW_FOISCSI_CTRL_WR_TCP_WS 0xf 2749#define V_FW_FOISCSI_CTRL_WR_TCP_WS(x) ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS) 2750#define G_FW_FOISCSI_CTRL_WR_TCP_WS(x) \ 2751 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS) & M_FW_FOISCSI_CTRL_WR_TCP_WS) 2752 2753#define S_FW_FOISCSI_CTRL_WR_TCP_WS_EN 11 2754#define M_FW_FOISCSI_CTRL_WR_TCP_WS_EN 0x1 2755#define V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \ 2756 ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) 2757#define G_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \ 2758 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) & M_FW_FOISCSI_CTRL_WR_TCP_WS_EN) 2759#define F_FW_FOISCSI_CTRL_WR_TCP_WS_EN V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(1U) 2760 2761struct fw_foiscsi_chap_wr { 2762 __be32 op_to_kv_flag; 2763 __be32 flowid_len16; 2764 __u64 cookie; 2765 __u8 status; 2766 union fw_foiscsi_len { 2767 struct fw_foiscsi_chap_lens { 2768 __u8 id_len; 2769 __u8 sec_len; 2770 } chapl; 2771 struct fw_foiscsi_vend_kv_lens { 2772 __u8 key_len; 2773 __u8 val_len; 2774 } vend_kvl; 2775 } lenu; 2776 __u8 node_type; 2777 __be16 node_id; 2778 __u8 r3[2]; 2779 union fw_foiscsi_chap_vend { 2780 struct fw_foiscsi_chap { 2781 __u8 chap_id[224]; 2782 __u8 chap_sec[128]; 2783 } chap; 2784 struct fw_foiscsi_vend_kv { 2785 __u8 vend_key[64]; 2786 __u8 vend_val[256]; 2787 } vend_kv; 2788 } u; 2789}; 2790 2791#define S_FW_FOISCSI_CHAP_WR_KV_FLAG 20 2792#define M_FW_FOISCSI_CHAP_WR_KV_FLAG 0x1 2793#define V_FW_FOISCSI_CHAP_WR_KV_FLAG(x) ((x) << S_FW_FOISCSI_CHAP_WR_KV_FLAG) 2794#define G_FW_FOISCSI_CHAP_WR_KV_FLAG(x) \ 2795 (((x) >> S_FW_FOISCSI_CHAP_WR_KV_FLAG) & M_FW_FOISCSI_CHAP_WR_KV_FLAG) 2796#define F_FW_FOISCSI_CHAP_WR_KV_FLAG V_FW_FOISCSI_CHAP_WR_KV_FLAG(1U) 2797 2798/****************************************************************************** 2799 * C O i S C S I W O R K R E Q U E S T S 2800 ********************************************/ 2801 2802enum fw_chnet_addr_type { 2803 FW_CHNET_ADDD_TYPE_NONE = 0, 2804 FW_CHNET_ADDR_TYPE_IPV4, 2805 FW_CHNET_ADDR_TYPE_IPV6, 2806}; 2807 2808enum fw_msg_wr_type { 2809 FW_MSG_WR_TYPE_RPL = 0, 2810 FW_MSG_WR_TYPE_ERR, 2811 FW_MSG_WR_TYPE_PLD, 2812}; 2813 2814struct fw_coiscsi_tgt_wr { 2815 __be32 op_compl; 2816 __be32 flowid_len16; 2817 __u64 cookie; 2818 __u8 subop; 2819 __u8 status; 2820 __be16 r4; 2821 __be32 flags; 2822 struct fw_coiscsi_tgt_conn_attr { 2823 __be32 in_tid; 2824 __be16 in_port; 2825 __u8 in_type; 2826 __u8 r6; 2827 union fw_coiscsi_tgt_conn_attr_addr { 2828 struct fw_coiscsi_tgt_conn_attr_in_addr { 2829 __be32 addr; 2830 __be32 r7; 2831 __be32 r8[2]; 2832 } in_addr; 2833 struct fw_coiscsi_tgt_conn_attr_in_addr6 { 2834 __be64 addr[2]; 2835 } in_addr6; 2836 } u; 2837 } conn_attr; 2838}; 2839 2840struct fw_coiscsi_tgt_conn_wr { 2841 __be32 op_compl; 2842 __be32 flowid_len16; 2843 __u64 cookie; 2844 __u8 subop; 2845 __u8 status; 2846 __be16 iq_id; 2847 __be32 in_stid; 2848 __be32 io_id; 2849 __be32 flags_fin; 2850 union { 2851 struct fw_coiscsi_tgt_conn_tcp { 2852 __be16 in_sport; 2853 __be16 in_dport; 2854 __u8 wscale_wsen; 2855 __u8 r4[3]; 2856 union fw_coiscsi_tgt_conn_tcp_addr { 2857 struct fw_coiscsi_tgt_conn_tcp_in_addr { 2858 __be32 saddr; 2859 __be32 daddr; 2860 } in_addr; 2861 struct fw_coiscsi_tgt_conn_tcp_in_addr6 { 2862 __be64 saddr[2]; 2863 __be64 daddr[2]; 2864 } in_addr6; 2865 } u; 2866 } conn_tcp; 2867 struct fw_coiscsi_tgt_conn_stats { 2868 __be32 ddp_reqs; 2869 __be32 ddp_cmpls; 2870 __be16 ddp_aborts; 2871 __be16 ddp_bps; 2872 } stats; 2873 } u; 2874 struct fw_coiscsi_tgt_conn_iscsi { 2875 __be32 hdigest_to_ddp_pgsz; 2876 __be32 tgt_id; 2877 __be16 max_r2t; 2878 __be16 r5; 2879 __be32 max_burst; 2880 __be32 max_rdsl; 2881 __be32 max_tdsl; 2882 __be32 cur_sn; 2883 __be32 r6; 2884 } conn_iscsi; 2885}; 2886 2887#define S_FW_COISCSI_TGT_CONN_WR_FIN 0 2888#define M_FW_COISCSI_TGT_CONN_WR_FIN 0x1 2889#define V_FW_COISCSI_TGT_CONN_WR_FIN(x) ((x) << S_FW_COISCSI_TGT_CONN_WR_FIN) 2890#define G_FW_COISCSI_TGT_CONN_WR_FIN(x) \ 2891 (((x) >> S_FW_COISCSI_TGT_CONN_WR_FIN) & M_FW_COISCSI_TGT_CONN_WR_FIN) 2892#define F_FW_COISCSI_TGT_CONN_WR_FIN V_FW_COISCSI_TGT_CONN_WR_FIN(1U) 2893 2894#define S_FW_COISCSI_TGT_CONN_WR_WSCALE 1 2895#define M_FW_COISCSI_TGT_CONN_WR_WSCALE 0xf 2896#define V_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ 2897 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSCALE) 2898#define G_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ 2899 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSCALE) & \ 2900 M_FW_COISCSI_TGT_CONN_WR_WSCALE) 2901 2902#define S_FW_COISCSI_TGT_CONN_WR_WSEN 0 2903#define M_FW_COISCSI_TGT_CONN_WR_WSEN 0x1 2904#define V_FW_COISCSI_TGT_CONN_WR_WSEN(x) \ 2905 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSEN) 2906#define G_FW_COISCSI_TGT_CONN_WR_WSEN(x) \ 2907 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSEN) & M_FW_COISCSI_TGT_CONN_WR_WSEN) 2908#define F_FW_COISCSI_TGT_CONN_WR_WSEN V_FW_COISCSI_TGT_CONN_WR_WSEN(1U) 2909 2910struct fw_coiscsi_tgt_xmit_wr { 2911 __be32 op_to_immdlen; 2912 union { 2913 struct cmpl_stat { 2914 __be32 cmpl_status_pkd; 2915 } cs; 2916 struct flowid_len { 2917 __be32 flowid_len16; 2918 } fllen; 2919 } u; 2920 __u64 cookie; 2921 __be16 iq_id; 2922 __be16 r3; 2923 __be32 pz_off; 2924 __be32 t_xfer_len; 2925 union { 2926 __be32 tag; 2927 __be32 datasn; 2928 __be32 ddp_status; 2929 } cu; 2930}; 2931 2932#define S_FW_COISCSI_TGT_XMIT_WR_DDGST 23 2933#define M_FW_COISCSI_TGT_XMIT_WR_DDGST 0x1 2934#define V_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \ 2935 ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDGST) 2936#define G_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \ 2937 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDGST) & M_FW_COISCSI_TGT_XMIT_WR_DDGST) 2938#define F_FW_COISCSI_TGT_XMIT_WR_DDGST V_FW_COISCSI_TGT_XMIT_WR_DDGST(1U) 2939 2940#define S_FW_COISCSI_TGT_XMIT_WR_HDGST 22 2941#define M_FW_COISCSI_TGT_XMIT_WR_HDGST 0x1 2942#define V_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \ 2943 ((x) << S_FW_COISCSI_TGT_XMIT_WR_HDGST) 2944#define G_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \ 2945 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_HDGST) & M_FW_COISCSI_TGT_XMIT_WR_HDGST) 2946#define F_FW_COISCSI_TGT_XMIT_WR_HDGST V_FW_COISCSI_TGT_XMIT_WR_HDGST(1U) 2947 2948#define S_FW_COISCSI_TGT_XMIT_WR_DDP 20 2949#define M_FW_COISCSI_TGT_XMIT_WR_DDP 0x1 2950#define V_FW_COISCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDP) 2951#define G_FW_COISCSI_TGT_XMIT_WR_DDP(x) \ 2952 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDP) & M_FW_COISCSI_TGT_XMIT_WR_DDP) 2953#define F_FW_COISCSI_TGT_XMIT_WR_DDP V_FW_COISCSI_TGT_XMIT_WR_DDP(1U) 2954 2955#define S_FW_COISCSI_TGT_XMIT_WR_ABORT 19 2956#define M_FW_COISCSI_TGT_XMIT_WR_ABORT 0x1 2957#define V_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \ 2958 ((x) << S_FW_COISCSI_TGT_XMIT_WR_ABORT) 2959#define G_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \ 2960 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_ABORT) & M_FW_COISCSI_TGT_XMIT_WR_ABORT) 2961#define F_FW_COISCSI_TGT_XMIT_WR_ABORT V_FW_COISCSI_TGT_XMIT_WR_ABORT(1U) 2962 2963#define S_FW_COISCSI_TGT_XMIT_WR_FINAL 18 2964#define M_FW_COISCSI_TGT_XMIT_WR_FINAL 0x1 2965#define V_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \ 2966 ((x) << S_FW_COISCSI_TGT_XMIT_WR_FINAL) 2967#define G_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \ 2968 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_FINAL) & M_FW_COISCSI_TGT_XMIT_WR_FINAL) 2969#define F_FW_COISCSI_TGT_XMIT_WR_FINAL V_FW_COISCSI_TGT_XMIT_WR_FINAL(1U) 2970 2971#define S_FW_COISCSI_TGT_XMIT_WR_PADLEN 16 2972#define M_FW_COISCSI_TGT_XMIT_WR_PADLEN 0x3 2973#define V_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ 2974 ((x) << S_FW_COISCSI_TGT_XMIT_WR_PADLEN) 2975#define G_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ 2976 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_PADLEN) & \ 2977 M_FW_COISCSI_TGT_XMIT_WR_PADLEN) 2978 2979#define S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 15 2980#define M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 0x1 2981#define V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \ 2982 ((x) << S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) 2983#define G_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \ 2984 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) & \ 2985 M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) 2986#define F_FW_COISCSI_TGT_XMIT_WR_INCSTATSN \ 2987 V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(1U) 2988 2989#define S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0 2990#define M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0xff 2991#define V_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2992 ((x) << S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) 2993#define G_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2994 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) & \ 2995 M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) 2996 2997#define S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 8 2998#define M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 0xff 2999#define V_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ 3000 ((x) << S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) 3001#define G_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ 3002 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) & \ 3003 M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) 3004 3005struct fw_coiscsi_stats_wr { 3006 __be32 op_compl; 3007 __be32 flowid_len16; 3008 __u64 cookie; 3009 __u8 subop; 3010 __u8 status; 3011 union fw_coiscsi_stats { 3012 struct fw_coiscsi_resource { 3013 __u8 num_ipv4_tgt; 3014 __u8 num_ipv6_tgt; 3015 __be16 num_l2t_entries; 3016 __be16 num_csocks; 3017 __be16 num_tasks; 3018 __be16 num_ppods_zone[11]; 3019 __be32 num_bufll64; 3020 __u8 r2[12]; 3021 } rsrc; 3022 } u; 3023}; 3024 3025struct fw_isns_wr { 3026 __be32 op_compl; 3027 __be32 flowid_len16; 3028 __u64 cookie; 3029 __u8 subop; 3030 __u8 status; 3031 __be16 iq_id; 3032 __be16 vlanid; 3033 __be16 r4; 3034 struct fw_tcp_conn_attr { 3035 __be32 in_tid; 3036 __be16 in_port; 3037 __u8 in_type; 3038 __u8 r6; 3039 union fw_tcp_conn_attr_addr { 3040 struct fw_tcp_conn_attr_in_addr { 3041 __be32 addr; 3042 __be32 r7; 3043 __be32 r8[2]; 3044 } in_addr; 3045 struct fw_tcp_conn_attr_in_addr6 { 3046 __be64 addr[2]; 3047 } in_addr6; 3048 } u; 3049 } conn_attr; 3050}; 3051 3052struct fw_isns_xmit_wr { 3053 __be32 op_to_immdlen; 3054 __be32 flowid_len16; 3055 __u64 cookie; 3056 __be16 iq_id; 3057 __be16 r4; 3058 __be32 xfer_len; 3059 __be64 r5; 3060}; 3061 3062#define S_FW_ISNS_XMIT_WR_IMMDLEN 0 3063#define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff 3064#define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) 3065#define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ 3066 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN) 3067 3068/****************************************************************************** 3069 * F O F C O E W O R K R E Q U E S T s 3070 *******************************************/ 3071 3072struct fw_fcoe_els_ct_wr { 3073 __be32 op_immdlen; 3074 __be32 flowid_len16; 3075 __be64 cookie; 3076 __be16 iqid; 3077 __u8 tmo_val; 3078 __u8 els_ct_type; 3079 __u8 ctl_pri; 3080 __u8 cp_en_class; 3081 __be16 xfer_cnt; 3082 __u8 fl_to_sp; 3083 __u8 l_id[3]; 3084 __u8 r5; 3085 __u8 r_id[3]; 3086 __be64 rsp_dmaaddr; 3087 __be32 rsp_dmalen; 3088 __be32 r6; 3089}; 3090 3091#define S_FW_FCOE_ELS_CT_WR_OPCODE 24 3092#define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 3093#define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 3094#define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 3095 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 3096 3097#define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 3098#define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 3099#define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 3100#define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 3101 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 3102 3103#define S_FW_FCOE_ELS_CT_WR_FLOWID 8 3104#define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 3105#define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 3106#define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 3107 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 3108 3109#define S_FW_FCOE_ELS_CT_WR_LEN16 0 3110#define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 3111#define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 3112#define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 3113 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 3114 3115#define S_FW_FCOE_ELS_CT_WR_CP_EN 6 3116#define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 3117#define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 3118#define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 3119 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 3120 3121#define S_FW_FCOE_ELS_CT_WR_CLASS 4 3122#define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 3123#define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 3124#define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 3125 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 3126 3127#define S_FW_FCOE_ELS_CT_WR_FL 2 3128#define M_FW_FCOE_ELS_CT_WR_FL 0x1 3129#define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 3130#define G_FW_FCOE_ELS_CT_WR_FL(x) \ 3131 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 3132#define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 3133 3134#define S_FW_FCOE_ELS_CT_WR_NPIV 1 3135#define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 3136#define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 3137#define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 3138 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 3139#define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 3140 3141#define S_FW_FCOE_ELS_CT_WR_SP 0 3142#define M_FW_FCOE_ELS_CT_WR_SP 0x1 3143#define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 3144#define G_FW_FCOE_ELS_CT_WR_SP(x) \ 3145 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 3146#define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 3147 3148/****************************************************************************** 3149 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 3150 *****************************************************************************/ 3151 3152struct fw_scsi_write_wr { 3153 __be32 op_immdlen; 3154 __be32 flowid_len16; 3155 __be64 cookie; 3156 __be16 iqid; 3157 __u8 tmo_val; 3158 __u8 use_xfer_cnt; 3159 union fw_scsi_write_priv { 3160 struct fcoe_write_priv { 3161 __u8 ctl_pri; 3162 __u8 cp_en_class; 3163 __u8 r3_lo[2]; 3164 } fcoe; 3165 struct iscsi_write_priv { 3166 __u8 r3[4]; 3167 } iscsi; 3168 } u; 3169 __be32 xfer_cnt; 3170 __be32 ini_xfer_cnt; 3171 __be64 rsp_dmaaddr; 3172 __be32 rsp_dmalen; 3173 __be32 r4; 3174}; 3175 3176#define S_FW_SCSI_WRITE_WR_OPCODE 24 3177#define M_FW_SCSI_WRITE_WR_OPCODE 0xff 3178#define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 3179#define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 3180 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 3181 3182#define S_FW_SCSI_WRITE_WR_IMMDLEN 0 3183#define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 3184#define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 3185#define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 3186 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 3187 3188#define S_FW_SCSI_WRITE_WR_FLOWID 8 3189#define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 3190#define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 3191#define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 3192 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 3193 3194#define S_FW_SCSI_WRITE_WR_LEN16 0 3195#define M_FW_SCSI_WRITE_WR_LEN16 0xff 3196#define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 3197#define G_FW_SCSI_WRITE_WR_LEN16(x) \ 3198 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 3199 3200#define S_FW_SCSI_WRITE_WR_CP_EN 6 3201#define M_FW_SCSI_WRITE_WR_CP_EN 0x3 3202#define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 3203#define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 3204 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 3205 3206#define S_FW_SCSI_WRITE_WR_CLASS 4 3207#define M_FW_SCSI_WRITE_WR_CLASS 0x3 3208#define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 3209#define G_FW_SCSI_WRITE_WR_CLASS(x) \ 3210 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 3211 3212struct fw_scsi_read_wr { 3213 __be32 op_immdlen; 3214 __be32 flowid_len16; 3215 __be64 cookie; 3216 __be16 iqid; 3217 __u8 tmo_val; 3218 __u8 use_xfer_cnt; 3219 union fw_scsi_read_priv { 3220 struct fcoe_read_priv { 3221 __u8 ctl_pri; 3222 __u8 cp_en_class; 3223 __u8 r3_lo[2]; 3224 } fcoe; 3225 struct iscsi_read_priv { 3226 __u8 r3[4]; 3227 } iscsi; 3228 } u; 3229 __be32 xfer_cnt; 3230 __be32 ini_xfer_cnt; 3231 __be64 rsp_dmaaddr; 3232 __be32 rsp_dmalen; 3233 __be32 r4; 3234}; 3235 3236#define S_FW_SCSI_READ_WR_OPCODE 24 3237#define M_FW_SCSI_READ_WR_OPCODE 0xff 3238#define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 3239#define G_FW_SCSI_READ_WR_OPCODE(x) \ 3240 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 3241 3242#define S_FW_SCSI_READ_WR_IMMDLEN 0 3243#define M_FW_SCSI_READ_WR_IMMDLEN 0xff 3244#define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 3245#define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 3246 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 3247 3248#define S_FW_SCSI_READ_WR_FLOWID 8 3249#define M_FW_SCSI_READ_WR_FLOWID 0xfffff 3250#define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 3251#define G_FW_SCSI_READ_WR_FLOWID(x) \ 3252 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 3253 3254#define S_FW_SCSI_READ_WR_LEN16 0 3255#define M_FW_SCSI_READ_WR_LEN16 0xff 3256#define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 3257#define G_FW_SCSI_READ_WR_LEN16(x) \ 3258 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 3259 3260#define S_FW_SCSI_READ_WR_CP_EN 6 3261#define M_FW_SCSI_READ_WR_CP_EN 0x3 3262#define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 3263#define G_FW_SCSI_READ_WR_CP_EN(x) \ 3264 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 3265 3266#define S_FW_SCSI_READ_WR_CLASS 4 3267#define M_FW_SCSI_READ_WR_CLASS 0x3 3268#define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 3269#define G_FW_SCSI_READ_WR_CLASS(x) \ 3270 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 3271 3272struct fw_scsi_cmd_wr { 3273 __be32 op_immdlen; 3274 __be32 flowid_len16; 3275 __be64 cookie; 3276 __be16 iqid; 3277 __u8 tmo_val; 3278 __u8 r3; 3279 union fw_scsi_cmd_priv { 3280 struct fcoe_cmd_priv { 3281 __u8 ctl_pri; 3282 __u8 cp_en_class; 3283 __u8 r4_lo[2]; 3284 } fcoe; 3285 struct iscsi_cmd_priv { 3286 __u8 r4[4]; 3287 } iscsi; 3288 } u; 3289 __u8 r5[8]; 3290 __be64 rsp_dmaaddr; 3291 __be32 rsp_dmalen; 3292 __be32 r6; 3293}; 3294 3295#define S_FW_SCSI_CMD_WR_OPCODE 24 3296#define M_FW_SCSI_CMD_WR_OPCODE 0xff 3297#define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 3298#define G_FW_SCSI_CMD_WR_OPCODE(x) \ 3299 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 3300 3301#define S_FW_SCSI_CMD_WR_IMMDLEN 0 3302#define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 3303#define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 3304#define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 3305 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 3306 3307#define S_FW_SCSI_CMD_WR_FLOWID 8 3308#define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 3309#define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 3310#define G_FW_SCSI_CMD_WR_FLOWID(x) \ 3311 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 3312 3313#define S_FW_SCSI_CMD_WR_LEN16 0 3314#define M_FW_SCSI_CMD_WR_LEN16 0xff 3315#define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 3316#define G_FW_SCSI_CMD_WR_LEN16(x) \ 3317 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 3318 3319#define S_FW_SCSI_CMD_WR_CP_EN 6 3320#define M_FW_SCSI_CMD_WR_CP_EN 0x3 3321#define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 3322#define G_FW_SCSI_CMD_WR_CP_EN(x) \ 3323 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 3324 3325#define S_FW_SCSI_CMD_WR_CLASS 4 3326#define M_FW_SCSI_CMD_WR_CLASS 0x3 3327#define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 3328#define G_FW_SCSI_CMD_WR_CLASS(x) \ 3329 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 3330 3331struct fw_scsi_abrt_cls_wr { 3332 __be32 op_immdlen; 3333 __be32 flowid_len16; 3334 __be64 cookie; 3335 __be16 iqid; 3336 __u8 tmo_val; 3337 __u8 sub_opcode_to_chk_all_io; 3338 __u8 r3[4]; 3339 __be64 t_cookie; 3340}; 3341 3342#define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 3343#define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 3344#define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 3345#define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 3346 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 3347 3348#define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 3349#define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 3350#define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3351 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3352#define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3353 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3354 3355#define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 3356#define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 3357#define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 3358#define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 3359 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 3360 3361#define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 3362#define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 3363#define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 3364#define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 3365 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 3366 3367#define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 3368#define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 3369#define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3370 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3371#define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3372 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 3373 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3374 3375#define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 3376#define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 3377#define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 3378#define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 3379 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 3380#define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 3381 3382#define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 3383#define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 3384#define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3385 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3386#define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3387 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 3388 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3389#define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 3390 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 3391 3392struct fw_scsi_tgt_acc_wr { 3393 __be32 op_immdlen; 3394 __be32 flowid_len16; 3395 __be64 cookie; 3396 __be16 iqid; 3397 __u8 r3; 3398 __u8 use_burst_len; 3399 union fw_scsi_tgt_acc_priv { 3400 struct fcoe_tgt_acc_priv { 3401 __u8 ctl_pri; 3402 __u8 cp_en_class; 3403 __u8 r4_lo[2]; 3404 } fcoe; 3405 struct iscsi_tgt_acc_priv { 3406 __u8 r4[4]; 3407 } iscsi; 3408 } u; 3409 __be32 burst_len; 3410 __be32 rel_off; 3411 __be64 r5; 3412 __be32 r6; 3413 __be32 tot_xfer_len; 3414}; 3415 3416#define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 3417#define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 3418#define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 3419#define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 3420 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 3421 3422#define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 3423#define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 3424#define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3425#define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 3426 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3427 3428#define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 3429#define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 3430#define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 3431#define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 3432 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 3433 3434#define S_FW_SCSI_TGT_ACC_WR_LEN16 0 3435#define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 3436#define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 3437#define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 3438 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 3439 3440#define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 3441#define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 3442#define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 3443#define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 3444 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 3445 3446#define S_FW_SCSI_TGT_ACC_WR_CLASS 4 3447#define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 3448#define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 3449#define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 3450 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 3451 3452struct fw_scsi_tgt_xmit_wr { 3453 __be32 op_immdlen; 3454 __be32 flowid_len16; 3455 __be64 cookie; 3456 __be16 iqid; 3457 __u8 auto_rsp; 3458 __u8 use_xfer_cnt; 3459 union fw_scsi_tgt_xmit_priv { 3460 struct fcoe_tgt_xmit_priv { 3461 __u8 ctl_pri; 3462 __u8 cp_en_class; 3463 __u8 r3_lo[2]; 3464 } fcoe; 3465 struct iscsi_tgt_xmit_priv { 3466 __u8 r3[4]; 3467 } iscsi; 3468 } u; 3469 __be32 xfer_cnt; 3470 __be32 r4; 3471 __be64 r5; 3472 __be32 r6; 3473 __be32 tot_xfer_len; 3474}; 3475 3476#define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 3477#define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 3478#define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 3479#define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 3480 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 3481 3482#define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 3483#define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 3484#define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3485 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3486#define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3487 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3488 3489#define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 3490#define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 3491#define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 3492#define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 3493 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 3494 3495#define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 3496#define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 3497#define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 3498#define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 3499 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 3500 3501#define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 3502#define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 3503#define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 3504#define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 3505 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 3506 3507#define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 3508#define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 3509#define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 3510#define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 3511 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 3512 3513struct fw_scsi_tgt_rsp_wr { 3514 __be32 op_immdlen; 3515 __be32 flowid_len16; 3516 __be64 cookie; 3517 __be16 iqid; 3518 __u8 r3[2]; 3519 union fw_scsi_tgt_rsp_priv { 3520 struct fcoe_tgt_rsp_priv { 3521 __u8 ctl_pri; 3522 __u8 cp_en_class; 3523 __u8 r4_lo[2]; 3524 } fcoe; 3525 struct iscsi_tgt_rsp_priv { 3526 __u8 r4[4]; 3527 } iscsi; 3528 } u; 3529 __u8 r5[8]; 3530}; 3531 3532#define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 3533#define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 3534#define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 3535#define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 3536 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 3537 3538#define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 3539#define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 3540#define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3541#define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 3542 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3543 3544#define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 3545#define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 3546#define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 3547#define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 3548 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 3549 3550#define S_FW_SCSI_TGT_RSP_WR_LEN16 0 3551#define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 3552#define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 3553#define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 3554 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 3555 3556#define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 3557#define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 3558#define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 3559#define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 3560 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 3561 3562#define S_FW_SCSI_TGT_RSP_WR_CLASS 4 3563#define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 3564#define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 3565#define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 3566 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 3567 3568struct fw_pofcoe_tcb_wr { 3569 __be32 op_compl; 3570 __be32 equiq_to_len16; 3571 __be32 r4; 3572 __be32 xfer_len; 3573 __be32 tid_to_port; 3574 __be16 x_id; 3575 __be16 vlan_id; 3576 __be64 cookie; 3577 __be32 s_id; 3578 __be32 d_id; 3579 __be32 tag; 3580 __be16 r6; 3581 __be16 iqid; 3582}; 3583 3584#define S_FW_POFCOE_TCB_WR_TID 12 3585#define M_FW_POFCOE_TCB_WR_TID 0xfffff 3586#define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 3587#define G_FW_POFCOE_TCB_WR_TID(x) \ 3588 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 3589 3590#define S_FW_POFCOE_TCB_WR_ALLOC 4 3591#define M_FW_POFCOE_TCB_WR_ALLOC 0x1 3592#define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 3593#define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 3594 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 3595#define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 3596 3597#define S_FW_POFCOE_TCB_WR_FREE 3 3598#define M_FW_POFCOE_TCB_WR_FREE 0x1 3599#define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 3600#define G_FW_POFCOE_TCB_WR_FREE(x) \ 3601 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 3602#define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 3603 3604#define S_FW_POFCOE_TCB_WR_PORT 0 3605#define M_FW_POFCOE_TCB_WR_PORT 0x7 3606#define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 3607#define G_FW_POFCOE_TCB_WR_PORT(x) \ 3608 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 3609 3610struct fw_pofcoe_ulptx_wr { 3611 __be32 op_pkd; 3612 __be32 equiq_to_len16; 3613 __u64 cookie; 3614}; 3615 3616/******************************************************************* 3617 * T10 DIF related definition 3618 *******************************************************************/ 3619struct fw_tx_pi_header { 3620 __be16 op_to_inline; 3621 __u8 pi_interval_tag_type; 3622 __u8 num_pi; 3623 __be32 pi_start4_pi_end4; 3624 __u8 tag_gen_enabled_pkd; 3625 __u8 num_pi_dsg; 3626 __be16 app_tag; 3627 __be32 ref_tag; 3628}; 3629 3630#define S_FW_TX_PI_HEADER_OP 8 3631#define M_FW_TX_PI_HEADER_OP 0xff 3632#define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) 3633#define G_FW_TX_PI_HEADER_OP(x) \ 3634 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) 3635 3636#define S_FW_TX_PI_HEADER_ULPTXMORE 7 3637#define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 3638#define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) 3639#define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ 3640 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) 3641#define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) 3642 3643#define S_FW_TX_PI_HEADER_PI_CONTROL 4 3644#define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 3645#define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) 3646#define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ 3647 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) 3648 3649#define S_FW_TX_PI_HEADER_GUARD_TYPE 2 3650#define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 3651#define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) 3652#define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ 3653 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) 3654#define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) 3655 3656#define S_FW_TX_PI_HEADER_VALIDATE 1 3657#define M_FW_TX_PI_HEADER_VALIDATE 0x1 3658#define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) 3659#define G_FW_TX_PI_HEADER_VALIDATE(x) \ 3660 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) 3661#define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) 3662 3663#define S_FW_TX_PI_HEADER_INLINE 0 3664#define M_FW_TX_PI_HEADER_INLINE 0x1 3665#define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) 3666#define G_FW_TX_PI_HEADER_INLINE(x) \ 3667 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) 3668#define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) 3669 3670#define S_FW_TX_PI_HEADER_PI_INTERVAL 7 3671#define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 3672#define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3673 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) 3674#define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3675 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) 3676#define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) 3677 3678#define S_FW_TX_PI_HEADER_TAG_TYPE 5 3679#define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 3680#define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) 3681#define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ 3682 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) 3683 3684#define S_FW_TX_PI_HEADER_PI_START4 22 3685#define M_FW_TX_PI_HEADER_PI_START4 0x3ff 3686#define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) 3687#define G_FW_TX_PI_HEADER_PI_START4(x) \ 3688 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) 3689 3690#define S_FW_TX_PI_HEADER_PI_END4 0 3691#define M_FW_TX_PI_HEADER_PI_END4 0x3fffff 3692#define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) 3693#define G_FW_TX_PI_HEADER_PI_END4(x) \ 3694 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) 3695 3696#define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 3697#define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 3698#define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3699 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3700#define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3701 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ 3702 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3703 3704enum fw_pi_error_type { 3705 FW_PI_ERROR_GUARD_CHECK_FAILED = 0, 3706}; 3707 3708struct fw_pi_error { 3709 __be32 err_type_pkd; 3710 __be32 flowid_len16; 3711 __be16 r2; 3712 __be16 app_tag; 3713 __be32 ref_tag; 3714 __be32 pisc[4]; 3715}; 3716 3717#define S_FW_PI_ERROR_ERR_TYPE 24 3718#define M_FW_PI_ERROR_ERR_TYPE 0xff 3719#define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) 3720#define G_FW_PI_ERROR_ERR_TYPE(x) \ 3721 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) 3722 3723struct fw_tlstx_data_wr { 3724 __be32 op_to_immdlen; 3725 __be32 flowid_len16; 3726 __be32 plen; 3727 __be32 lsodisable_to_flags; 3728 __be32 r5; 3729 __be32 ctxloc_to_exp; 3730 __be16 mfs; 3731 __be16 adjustedplen_pkd; 3732 __be16 expinplenmax_pkd; 3733 __u8 pdusinplenmax_pkd; 3734 __u8 r10; 3735}; 3736 3737#define S_FW_TLSTX_DATA_WR_OPCODE 24 3738#define M_FW_TLSTX_DATA_WR_OPCODE 0xff 3739#define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE) 3740#define G_FW_TLSTX_DATA_WR_OPCODE(x) \ 3741 (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE) 3742 3743#define S_FW_TLSTX_DATA_WR_COMPL 21 3744#define M_FW_TLSTX_DATA_WR_COMPL 0x1 3745#define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL) 3746#define G_FW_TLSTX_DATA_WR_COMPL(x) \ 3747 (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL) 3748#define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U) 3749 3750#define S_FW_TLSTX_DATA_WR_IMMDLEN 0 3751#define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff 3752#define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN) 3753#define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \ 3754 (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN) 3755 3756#define S_FW_TLSTX_DATA_WR_FLOWID 8 3757#define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff 3758#define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID) 3759#define G_FW_TLSTX_DATA_WR_FLOWID(x) \ 3760 (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID) 3761 3762#define S_FW_TLSTX_DATA_WR_LEN16 0 3763#define M_FW_TLSTX_DATA_WR_LEN16 0xff 3764#define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16) 3765#define G_FW_TLSTX_DATA_WR_LEN16(x) \ 3766 (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16) 3767 3768#define S_FW_TLSTX_DATA_WR_LSODISABLE 31 3769#define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1 3770#define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3771 ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE) 3772#define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3773 (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE) 3774#define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U) 3775 3776#define S_FW_TLSTX_DATA_WR_ALIGNPLD 30 3777#define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1 3778#define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD) 3779#define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \ 3780 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD) 3781#define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U) 3782 3783#define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29 3784#define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1 3785#define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3786 ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3787#define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3788 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \ 3789 M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3790#define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U) 3791 3792#define S_FW_TLSTX_DATA_WR_FLAGS 0 3793#define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff 3794#define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS) 3795#define G_FW_TLSTX_DATA_WR_FLAGS(x) \ 3796 (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS) 3797 3798#define S_FW_TLSTX_DATA_WR_CTXLOC 30 3799#define M_FW_TLSTX_DATA_WR_CTXLOC 0x3 3800#define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC) 3801#define G_FW_TLSTX_DATA_WR_CTXLOC(x) \ 3802 (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC) 3803 3804#define S_FW_TLSTX_DATA_WR_IVDSGL 29 3805#define M_FW_TLSTX_DATA_WR_IVDSGL 0x1 3806#define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL) 3807#define G_FW_TLSTX_DATA_WR_IVDSGL(x) \ 3808 (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL) 3809#define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U) 3810 3811#define S_FW_TLSTX_DATA_WR_KEYSIZE 24 3812#define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f 3813#define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE) 3814#define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \ 3815 (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE) 3816 3817#define S_FW_TLSTX_DATA_WR_NUMIVS 14 3818#define M_FW_TLSTX_DATA_WR_NUMIVS 0xff 3819#define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS) 3820#define G_FW_TLSTX_DATA_WR_NUMIVS(x) \ 3821 (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS) 3822 3823#define S_FW_TLSTX_DATA_WR_EXP 0 3824#define M_FW_TLSTX_DATA_WR_EXP 0x3fff 3825#define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP) 3826#define G_FW_TLSTX_DATA_WR_EXP(x) \ 3827 (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP) 3828 3829#define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1 3830#define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff 3831#define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3832 ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3833#define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 3834 (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \ 3835 M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 3836 3837#define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4 3838#define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff 3839#define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3840 ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3841#define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 3842 (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \ 3843 M_FW_TLSTX_DATA_WR_EXPINPLENMAX) 3844 3845#define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2 3846#define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f 3847#define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3848 ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3849#define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 3850 (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \ 3851 M_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 3852 3853struct fw_crypto_lookaside_wr { 3854 __be32 op_to_cctx_size; 3855 __be32 len16_pkd; 3856 __be32 session_id; 3857 __be32 rx_chid_to_rx_q_id; 3858 __be32 key_addr; 3859 __be32 pld_size_hash_size; 3860 __be64 cookie; 3861}; 3862 3863#define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24 3864#define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff 3865#define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3866 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3867#define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3868 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \ 3869 M_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3870 3871#define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23 3872#define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1 3873#define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3874 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3875#define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3876 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \ 3877 M_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3878#define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U) 3879 3880#define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15 3881#define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff 3882#define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 3883 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 3884#define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 3885 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \ 3886 M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 3887 3888#define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5 3889#define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3 3890#define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 3891 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 3892#define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 3893 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \ 3894 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 3895 3896#define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0 3897#define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f 3898#define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 3899 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 3900#define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 3901 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \ 3902 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 3903 3904#define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0 3905#define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff 3906#define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 3907 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16) 3908#define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 3909 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \ 3910 M_FW_CRYPTO_LOOKASIDE_WR_LEN16) 3911 3912#define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29 3913#define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3 3914#define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 3915 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 3916#define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 3917 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \ 3918 M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 3919 3920#define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27 3921#define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3 3922#define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 3923 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB) 3924#define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 3925 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB) 3926 3927#define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25 3928#define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3 3929#define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 3930 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH) 3931#define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 3932 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \ 3933 M_FW_CRYPTO_LOOKASIDE_WR_PHASH) 3934 3935#define S_FW_CRYPTO_LOOKASIDE_WR_IV 23 3936#define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3 3937#define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 3938 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV) 3939#define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 3940 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV) 3941 3942#define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15 3943#define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff 3944#define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 3945 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 3946#define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 3947 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\ 3948 M_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 3949 3950#define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10 3951#define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3 3952#define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 3953 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 3954#define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 3955 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \ 3956 M_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 3957 3958#define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0 3959#define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff 3960#define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 3961 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 3962#define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 3963 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \ 3964 M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 3965 3966#define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24 3967#define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff 3968#define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 3969 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 3970#define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 3971 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \ 3972 M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 3973 3974#define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17 3975#define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f 3976#define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 3977 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 3978#define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 3979 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \ 3980 M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 3981 3982/****************************************************************************** 3983 * C O M M A N D s 3984 *********************/ 3985 3986/* 3987 * The maximum length of time, in miliseconds, that we expect any firmware 3988 * command to take to execute and return a reply to the host. The RESET 3989 * and INITIALIZE commands can take a fair amount of time to execute but 3990 * most execute in far less time than this maximum. This constant is used 3991 * by host software to determine how long to wait for a firmware command 3992 * reply before declaring the firmware as dead/unreachable ... 3993 */ 3994#define FW_CMD_MAX_TIMEOUT 10000 3995 3996/* 3997 * If a host driver does a HELLO and discovers that there's already a MASTER 3998 * selected, we may have to wait for that MASTER to finish issuing RESET, 3999 * configuration and INITIALIZE commands. Also, there's a possibility that 4000 * our own HELLO may get lost if it happens right as the MASTER is issuign a 4001 * RESET command, so we need to be willing to make a few retries of our HELLO. 4002 */ 4003#define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 4004#define FW_CMD_HELLO_RETRIES 3 4005 4006enum fw_cmd_opcodes { 4007 FW_LDST_CMD = 0x01, 4008 FW_RESET_CMD = 0x03, 4009 FW_HELLO_CMD = 0x04, 4010 FW_BYE_CMD = 0x05, 4011 FW_INITIALIZE_CMD = 0x06, 4012 FW_CAPS_CONFIG_CMD = 0x07, 4013 FW_PARAMS_CMD = 0x08, 4014 FW_PFVF_CMD = 0x09, 4015 FW_IQ_CMD = 0x10, 4016 FW_EQ_MNGT_CMD = 0x11, 4017 FW_EQ_ETH_CMD = 0x12, 4018 FW_EQ_CTRL_CMD = 0x13, 4019 FW_EQ_OFLD_CMD = 0x21, 4020 FW_VI_CMD = 0x14, 4021 FW_VI_MAC_CMD = 0x15, 4022 FW_VI_RXMODE_CMD = 0x16, 4023 FW_VI_ENABLE_CMD = 0x17, 4024 FW_VI_STATS_CMD = 0x1a, 4025 FW_ACL_MAC_CMD = 0x18, 4026 FW_ACL_VLAN_CMD = 0x19, 4027 FW_PORT_CMD = 0x1b, 4028 FW_PORT_STATS_CMD = 0x1c, 4029 FW_PORT_LB_STATS_CMD = 0x1d, 4030 FW_PORT_TRACE_CMD = 0x1e, 4031 FW_PORT_TRACE_MMAP_CMD = 0x1f, 4032 FW_RSS_IND_TBL_CMD = 0x20, 4033 FW_RSS_GLB_CONFIG_CMD = 0x22, 4034 FW_RSS_VI_CONFIG_CMD = 0x23, 4035 FW_SCHED_CMD = 0x24, 4036 FW_DEVLOG_CMD = 0x25, 4037 FW_WATCHDOG_CMD = 0x27, 4038 FW_CLIP_CMD = 0x28, 4039 FW_CHNET_IFACE_CMD = 0x26, 4040 FW_FCOE_RES_INFO_CMD = 0x31, 4041 FW_FCOE_LINK_CMD = 0x32, 4042 FW_FCOE_VNP_CMD = 0x33, 4043 FW_FCOE_SPARAMS_CMD = 0x35, 4044 FW_FCOE_STATS_CMD = 0x37, 4045 FW_FCOE_FCF_CMD = 0x38, 4046 FW_DCB_IEEE_CMD = 0x3a, 4047 FW_DIAG_CMD = 0x3d, 4048 FW_PTP_CMD = 0x3e, 4049 FW_HMA_CMD = 0x3f, 4050 FW_LASTC2E_CMD = 0x40, 4051 FW_ERROR_CMD = 0x80, 4052 FW_DEBUG_CMD = 0x81, 4053}; 4054 4055enum fw_cmd_cap { 4056 FW_CMD_CAP_PF = 0x01, 4057 FW_CMD_CAP_DMAQ = 0x02, 4058 FW_CMD_CAP_PORT = 0x04, 4059 FW_CMD_CAP_PORTPROMISC = 0x08, 4060 FW_CMD_CAP_PORTSTATS = 0x10, 4061 FW_CMD_CAP_VF = 0x80, 4062}; 4063 4064/* 4065 * Generic command header flit0 4066 */ 4067struct fw_cmd_hdr { 4068 __be32 hi; 4069 __be32 lo; 4070}; 4071 4072#define S_FW_CMD_OP 24 4073#define M_FW_CMD_OP 0xff 4074#define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 4075#define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 4076 4077#define S_FW_CMD_REQUEST 23 4078#define M_FW_CMD_REQUEST 0x1 4079#define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 4080#define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 4081#define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 4082 4083#define S_FW_CMD_READ 22 4084#define M_FW_CMD_READ 0x1 4085#define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 4086#define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 4087#define F_FW_CMD_READ V_FW_CMD_READ(1U) 4088 4089#define S_FW_CMD_WRITE 21 4090#define M_FW_CMD_WRITE 0x1 4091#define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 4092#define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 4093#define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 4094 4095#define S_FW_CMD_EXEC 20 4096#define M_FW_CMD_EXEC 0x1 4097#define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 4098#define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 4099#define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 4100 4101#define S_FW_CMD_RAMASK 20 4102#define M_FW_CMD_RAMASK 0xf 4103#define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 4104#define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 4105 4106#define S_FW_CMD_RETVAL 8 4107#define M_FW_CMD_RETVAL 0xff 4108#define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 4109#define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 4110 4111#define S_FW_CMD_LEN16 0 4112#define M_FW_CMD_LEN16 0xff 4113#define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 4114#define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 4115 4116#define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 4117 4118/* 4119 * address spaces 4120 */ 4121enum fw_ldst_addrspc { 4122 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 4123 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 4124 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 4125 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 4126 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 4127 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 4128 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 4129 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 4130 FW_LDST_ADDRSPC_MDIO = 0x0018, 4131 FW_LDST_ADDRSPC_MPS = 0x0020, 4132 FW_LDST_ADDRSPC_FUNC = 0x0028, 4133 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 4134 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 4135 FW_LDST_ADDRSPC_LE = 0x0030, 4136 FW_LDST_ADDRSPC_I2C = 0x0038, 4137 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 4138 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 4139 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 4140 FW_LDST_ADDRSPC_CIM_Q = 0x0048, 4141}; 4142 4143/* 4144 * MDIO VSC8634 register access control field 4145 */ 4146enum fw_ldst_mdio_vsc8634_aid { 4147 FW_LDST_MDIO_VS_STANDARD, 4148 FW_LDST_MDIO_VS_EXTENDED, 4149 FW_LDST_MDIO_VS_GPIO 4150}; 4151 4152enum fw_ldst_mps_fid { 4153 FW_LDST_MPS_ATRB, 4154 FW_LDST_MPS_RPLC 4155}; 4156 4157enum fw_ldst_func_access_ctl { 4158 FW_LDST_FUNC_ACC_CTL_VIID, 4159 FW_LDST_FUNC_ACC_CTL_FID 4160}; 4161 4162enum fw_ldst_func_mod_index { 4163 FW_LDST_FUNC_MPS 4164}; 4165 4166struct fw_ldst_cmd { 4167 __be32 op_to_addrspace; 4168 __be32 cycles_to_len16; 4169 union fw_ldst { 4170 struct fw_ldst_addrval { 4171 __be32 addr; 4172 __be32 val; 4173 } addrval; 4174 struct fw_ldst_idctxt { 4175 __be32 physid; 4176 __be32 msg_ctxtflush; 4177 __be32 ctxt_data7; 4178 __be32 ctxt_data6; 4179 __be32 ctxt_data5; 4180 __be32 ctxt_data4; 4181 __be32 ctxt_data3; 4182 __be32 ctxt_data2; 4183 __be32 ctxt_data1; 4184 __be32 ctxt_data0; 4185 } idctxt; 4186 struct fw_ldst_mdio { 4187 __be16 paddr_mmd; 4188 __be16 raddr; 4189 __be16 vctl; 4190 __be16 rval; 4191 } mdio; 4192 struct fw_ldst_cim_rq { 4193 __u8 req_first64[8]; 4194 __u8 req_second64[8]; 4195 __u8 resp_first64[8]; 4196 __u8 resp_second64[8]; 4197 __be32 r3[2]; 4198 } cim_rq; 4199 union fw_ldst_mps { 4200 struct fw_ldst_mps_rplc { 4201 __be16 fid_idx; 4202 __be16 rplcpf_pkd; 4203 __be32 rplc255_224; 4204 __be32 rplc223_192; 4205 __be32 rplc191_160; 4206 __be32 rplc159_128; 4207 __be32 rplc127_96; 4208 __be32 rplc95_64; 4209 __be32 rplc63_32; 4210 __be32 rplc31_0; 4211 } rplc; 4212 struct fw_ldst_mps_atrb { 4213 __be16 fid_mpsid; 4214 __be16 r2[3]; 4215 __be32 r3[2]; 4216 __be32 r4; 4217 __be32 atrb; 4218 __be16 vlan[16]; 4219 } atrb; 4220 } mps; 4221 struct fw_ldst_func { 4222 __u8 access_ctl; 4223 __u8 mod_index; 4224 __be16 ctl_id; 4225 __be32 offset; 4226 __be64 data0; 4227 __be64 data1; 4228 } func; 4229 struct fw_ldst_pcie { 4230 __u8 ctrl_to_fn; 4231 __u8 bnum; 4232 __u8 r; 4233 __u8 ext_r; 4234 __u8 select_naccess; 4235 __u8 pcie_fn; 4236 __be16 nset_pkd; 4237 __be32 data[12]; 4238 } pcie; 4239 struct fw_ldst_i2c_deprecated { 4240 __u8 pid_pkd; 4241 __u8 base; 4242 __u8 boffset; 4243 __u8 data; 4244 __be32 r9; 4245 } i2c_deprecated; 4246 struct fw_ldst_i2c { 4247 __u8 pid; 4248 __u8 did; 4249 __u8 boffset; 4250 __u8 blen; 4251 __be32 r9; 4252 __u8 data[48]; 4253 } i2c; 4254 struct fw_ldst_le { 4255 __be32 index; 4256 __be32 r9; 4257 __u8 val[33]; 4258 __u8 r11[7]; 4259 } le; 4260 } u; 4261}; 4262 4263#define S_FW_LDST_CMD_ADDRSPACE 0 4264#define M_FW_LDST_CMD_ADDRSPACE 0xff 4265#define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 4266#define G_FW_LDST_CMD_ADDRSPACE(x) \ 4267 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 4268 4269#define S_FW_LDST_CMD_CYCLES 16 4270#define M_FW_LDST_CMD_CYCLES 0xffff 4271#define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 4272#define G_FW_LDST_CMD_CYCLES(x) \ 4273 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 4274 4275#define S_FW_LDST_CMD_MSG 31 4276#define M_FW_LDST_CMD_MSG 0x1 4277#define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 4278#define G_FW_LDST_CMD_MSG(x) \ 4279 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 4280#define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 4281 4282#define S_FW_LDST_CMD_CTXTFLUSH 30 4283#define M_FW_LDST_CMD_CTXTFLUSH 0x1 4284#define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 4285#define G_FW_LDST_CMD_CTXTFLUSH(x) \ 4286 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 4287#define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 4288 4289#define S_FW_LDST_CMD_PADDR 8 4290#define M_FW_LDST_CMD_PADDR 0x1f 4291#define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 4292#define G_FW_LDST_CMD_PADDR(x) \ 4293 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 4294 4295#define S_FW_LDST_CMD_MMD 0 4296#define M_FW_LDST_CMD_MMD 0x1f 4297#define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 4298#define G_FW_LDST_CMD_MMD(x) \ 4299 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 4300 4301#define S_FW_LDST_CMD_FID 15 4302#define M_FW_LDST_CMD_FID 0x1 4303#define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 4304#define G_FW_LDST_CMD_FID(x) \ 4305 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 4306#define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 4307 4308#define S_FW_LDST_CMD_IDX 0 4309#define M_FW_LDST_CMD_IDX 0x7fff 4310#define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) 4311#define G_FW_LDST_CMD_IDX(x) \ 4312 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) 4313 4314#define S_FW_LDST_CMD_RPLCPF 0 4315#define M_FW_LDST_CMD_RPLCPF 0xff 4316#define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 4317#define G_FW_LDST_CMD_RPLCPF(x) \ 4318 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 4319 4320#define S_FW_LDST_CMD_MPSID 0 4321#define M_FW_LDST_CMD_MPSID 0x7fff 4322#define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) 4323#define G_FW_LDST_CMD_MPSID(x) \ 4324 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) 4325 4326#define S_FW_LDST_CMD_CTRL 7 4327#define M_FW_LDST_CMD_CTRL 0x1 4328#define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 4329#define G_FW_LDST_CMD_CTRL(x) \ 4330 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 4331#define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 4332 4333#define S_FW_LDST_CMD_LC 4 4334#define M_FW_LDST_CMD_LC 0x1 4335#define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 4336#define G_FW_LDST_CMD_LC(x) \ 4337 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 4338#define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 4339 4340#define S_FW_LDST_CMD_AI 3 4341#define M_FW_LDST_CMD_AI 0x1 4342#define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 4343#define G_FW_LDST_CMD_AI(x) \ 4344 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 4345#define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 4346 4347#define S_FW_LDST_CMD_FN 0 4348#define M_FW_LDST_CMD_FN 0x7 4349#define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 4350#define G_FW_LDST_CMD_FN(x) \ 4351 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 4352 4353#define S_FW_LDST_CMD_SELECT 4 4354#define M_FW_LDST_CMD_SELECT 0xf 4355#define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 4356#define G_FW_LDST_CMD_SELECT(x) \ 4357 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 4358 4359#define S_FW_LDST_CMD_NACCESS 0 4360#define M_FW_LDST_CMD_NACCESS 0xf 4361#define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 4362#define G_FW_LDST_CMD_NACCESS(x) \ 4363 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 4364 4365#define S_FW_LDST_CMD_NSET 14 4366#define M_FW_LDST_CMD_NSET 0x3 4367#define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 4368#define G_FW_LDST_CMD_NSET(x) \ 4369 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 4370 4371#define S_FW_LDST_CMD_PID 6 4372#define M_FW_LDST_CMD_PID 0x3 4373#define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 4374#define G_FW_LDST_CMD_PID(x) \ 4375 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 4376 4377struct fw_reset_cmd { 4378 __be32 op_to_write; 4379 __be32 retval_len16; 4380 __be32 val; 4381 __be32 halt_pkd; 4382}; 4383 4384#define S_FW_RESET_CMD_HALT 31 4385#define M_FW_RESET_CMD_HALT 0x1 4386#define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 4387#define G_FW_RESET_CMD_HALT(x) \ 4388 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 4389#define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 4390 4391enum { 4392 FW_HELLO_CMD_STAGE_OS = 0, 4393 FW_HELLO_CMD_STAGE_PREOS0 = 1, 4394 FW_HELLO_CMD_STAGE_PREOS1 = 2, 4395 FW_HELLO_CMD_STAGE_POSTOS = 3, 4396}; 4397 4398struct fw_hello_cmd { 4399 __be32 op_to_write; 4400 __be32 retval_len16; 4401 __be32 err_to_clearinit; 4402 __be32 fwrev; 4403}; 4404 4405#define S_FW_HELLO_CMD_ERR 31 4406#define M_FW_HELLO_CMD_ERR 0x1 4407#define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 4408#define G_FW_HELLO_CMD_ERR(x) \ 4409 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 4410#define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 4411 4412#define S_FW_HELLO_CMD_INIT 30 4413#define M_FW_HELLO_CMD_INIT 0x1 4414#define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 4415#define G_FW_HELLO_CMD_INIT(x) \ 4416 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 4417#define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 4418 4419#define S_FW_HELLO_CMD_MASTERDIS 29 4420#define M_FW_HELLO_CMD_MASTERDIS 0x1 4421#define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 4422#define G_FW_HELLO_CMD_MASTERDIS(x) \ 4423 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 4424#define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 4425 4426#define S_FW_HELLO_CMD_MASTERFORCE 28 4427#define M_FW_HELLO_CMD_MASTERFORCE 0x1 4428#define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 4429#define G_FW_HELLO_CMD_MASTERFORCE(x) \ 4430 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 4431#define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 4432 4433#define S_FW_HELLO_CMD_MBMASTER 24 4434#define M_FW_HELLO_CMD_MBMASTER 0xf 4435#define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 4436#define G_FW_HELLO_CMD_MBMASTER(x) \ 4437 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 4438 4439#define S_FW_HELLO_CMD_MBASYNCNOTINT 23 4440#define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 4441#define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 4442#define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 4443 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 4444#define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 4445 4446#define S_FW_HELLO_CMD_MBASYNCNOT 20 4447#define M_FW_HELLO_CMD_MBASYNCNOT 0x7 4448#define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 4449#define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 4450 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 4451 4452#define S_FW_HELLO_CMD_STAGE 17 4453#define M_FW_HELLO_CMD_STAGE 0x7 4454#define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 4455#define G_FW_HELLO_CMD_STAGE(x) \ 4456 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 4457 4458#define S_FW_HELLO_CMD_CLEARINIT 16 4459#define M_FW_HELLO_CMD_CLEARINIT 0x1 4460#define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 4461#define G_FW_HELLO_CMD_CLEARINIT(x) \ 4462 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 4463#define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 4464 4465struct fw_bye_cmd { 4466 __be32 op_to_write; 4467 __be32 retval_len16; 4468 __be64 r3; 4469}; 4470 4471struct fw_initialize_cmd { 4472 __be32 op_to_write; 4473 __be32 retval_len16; 4474 __be64 r3; 4475}; 4476 4477enum fw_caps_config_hm { 4478 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 4479 FW_CAPS_CONFIG_HM_PL = 0x00000002, 4480 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 4481 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 4482 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 4483 FW_CAPS_CONFIG_HM_TP = 0x00000020, 4484 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 4485 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 4486 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 4487 FW_CAPS_CONFIG_HM_MC = 0x00000200, 4488 FW_CAPS_CONFIG_HM_LE = 0x00000400, 4489 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 4490 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 4491 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 4492 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 4493 FW_CAPS_CONFIG_HM_MI = 0x00008000, 4494 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 4495 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 4496 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 4497 FW_CAPS_CONFIG_HM_MA = 0x00080000, 4498 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 4499 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 4500 FW_CAPS_CONFIG_HM_UART = 0x00400000, 4501 FW_CAPS_CONFIG_HM_SF = 0x00800000, 4502}; 4503 4504/* 4505 * The VF Register Map. 4506 * 4507 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 4508 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 4509 * the Slice to Module Map Table (see below) in the Physical Function Register 4510 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 4511 * and Offset registers in the PF Register Map. The MBDATA base address is 4512 * quite constrained as it determines the Mailbox Data addresses for both PFs 4513 * and VFs, and therefore must fit in both the VF and PF Register Maps without 4514 * overlapping other registers. 4515 */ 4516#define FW_T4VF_SGE_BASE_ADDR 0x0000 4517#define FW_T4VF_MPS_BASE_ADDR 0x0100 4518#define FW_T4VF_PL_BASE_ADDR 0x0200 4519#define FW_T4VF_MBDATA_BASE_ADDR 0x0240 4520#define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */ 4521#define FW_T4VF_CIM_BASE_ADDR 0x0300 4522 4523#define FW_T4VF_REGMAP_START 0x0000 4524#define FW_T4VF_REGMAP_SIZE 0x0400 4525 4526enum fw_caps_config_nbm { 4527 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 4528 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 4529}; 4530 4531enum fw_caps_config_link { 4532 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 4533 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 4534 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 4535}; 4536 4537enum fw_caps_config_switch { 4538 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 4539 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 4540}; 4541 4542enum fw_caps_config_nic { 4543 FW_CAPS_CONFIG_NIC = 0x00000001, 4544 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 4545 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 4546 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 4547 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 4548 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 4549 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 4550}; 4551 4552enum fw_caps_config_toe { 4553 FW_CAPS_CONFIG_TOE = 0x00000001, 4554}; 4555 4556enum fw_caps_config_rdma { 4557 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 4558 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 4559}; 4560 4561enum fw_caps_config_iscsi { 4562 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 4563 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 4564 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 4565 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 4566 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 4567 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 4568 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, 4569 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080, 4570 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100, 4571}; 4572 4573enum fw_caps_config_crypto { 4574 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001, 4575 FW_CAPS_CONFIG_TLSKEYS = 0x00000002, 4576}; 4577 4578enum fw_caps_config_fcoe { 4579 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 4580 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 4581 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 4582 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 4583 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 4584}; 4585 4586enum fw_memtype_cf { 4587 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 4588 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 4589 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 4590 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 4591 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 4592 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 4593}; 4594 4595struct fw_caps_config_cmd { 4596 __be32 op_to_write; 4597 __be32 cfvalid_to_len16; 4598 __be32 r2; 4599 __be32 hwmbitmap; 4600 __be16 nbmcaps; 4601 __be16 linkcaps; 4602 __be16 switchcaps; 4603 __be16 r3; 4604 __be16 niccaps; 4605 __be16 toecaps; 4606 __be16 rdmacaps; 4607 __be16 cryptocaps; 4608 __be16 iscsicaps; 4609 __be16 fcoecaps; 4610 __be32 cfcsum; 4611 __be32 finiver; 4612 __be32 finicsum; 4613}; 4614 4615#define S_FW_CAPS_CONFIG_CMD_CFVALID 27 4616#define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 4617#define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 4618#define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 4619 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 4620#define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 4621 4622#define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 4623#define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 4624#define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4625 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4626#define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4627 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 4628 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4629 4630#define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 4631#define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 4632#define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4633 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4634#define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4635 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 4636 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4637 4638/* 4639 * params command mnemonics 4640 */ 4641enum fw_params_mnem { 4642 FW_PARAMS_MNEM_DEV = 1, /* device params */ 4643 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 4644 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 4645 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 4646 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 4647 FW_PARAMS_MNEM_LAST 4648}; 4649 4650/* 4651 * device parameters 4652 */ 4653enum fw_params_param_dev { 4654 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 4655 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 4656 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 4657 * allocated by the device's 4658 * Lookup Engine 4659 */ 4660 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 4661 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 4662 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 4663 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 4664 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 4665 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 4666 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 4667 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 4668 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 4669 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 4670 FW_PARAMS_PARAM_DEV_CF = 0x0D, 4671 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 4672 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 4673 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 4674 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 4675 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 4676 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 4677 */ 4678 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 4679 */ 4680 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 4681 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 4682 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 4683 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 4684 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, 4685 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 4686 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 4687 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 4688 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 4689 4690 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 4691 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F, 4692 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20, 4693 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21, 4694 FW_PARAMS_PARAM_DEV_RING_BACKBONE = 0x22, 4695 FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23, 4696}; 4697 4698/* 4699 * dev bypass parameters; actions and modes 4700 */ 4701enum fw_params_param_dev_bypass { 4702 4703 /* actions 4704 */ 4705 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 4706 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 4707 4708 /* modes 4709 */ 4710 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 4711 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 4712 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 4713}; 4714 4715enum fw_params_param_dev_phyfw { 4716 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 4717 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 4718}; 4719 4720enum fw_params_param_dev_diag { 4721 FW_PARAM_DEV_DIAG_TMP = 0x00, 4722 FW_PARAM_DEV_DIAG_VDD = 0x01, 4723}; 4724 4725enum fw_params_param_dev_fwcache { 4726 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 4727 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 4728}; 4729 4730/* 4731 * physical and virtual function parameters 4732 */ 4733enum fw_params_param_pfvf { 4734 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 4735 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 4736 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 4737 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 4738 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 4739 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 4740 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 4741 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 4742 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 4743 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 4744 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 4745 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 4746 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 4747 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 4748 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 4749 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 4750 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 4751 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 4752 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 4753 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 4754 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 4755 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 4756 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 4757 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 4758 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 4759 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 4760 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 4761 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 4762 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 4763 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 4764 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 4765 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 4766 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 4767 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 4768 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 4769 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 4770 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 4771 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 4772 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 4773 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 4774 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 4775 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 4776 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 4777 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 4778 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 4779 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 4780 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 4781 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 4782 FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38, 4783 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 4784 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 4785 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B, 4786 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C, 4787}; 4788 4789/* 4790 * dma queue parameters 4791 */ 4792enum fw_params_param_dmaq { 4793 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 4794 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 4795 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 4796 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03, 4797 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 4798 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 4799 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 4800 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 4801 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14, 4802 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 4803 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30 4804}; 4805 4806/* 4807 * chnet parameters 4808 */ 4809enum fw_params_param_chnet { 4810 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, 4811}; 4812 4813enum fw_params_param_chnet_flags { 4814 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, 4815 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, 4816 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, 4817}; 4818 4819#define S_FW_PARAMS_MNEM 24 4820#define M_FW_PARAMS_MNEM 0xff 4821#define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 4822#define G_FW_PARAMS_MNEM(x) \ 4823 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 4824 4825#define S_FW_PARAMS_PARAM_X 16 4826#define M_FW_PARAMS_PARAM_X 0xff 4827#define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 4828#define G_FW_PARAMS_PARAM_X(x) \ 4829 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 4830 4831#define S_FW_PARAMS_PARAM_Y 8 4832#define M_FW_PARAMS_PARAM_Y 0xff 4833#define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 4834#define G_FW_PARAMS_PARAM_Y(x) \ 4835 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 4836 4837#define S_FW_PARAMS_PARAM_Z 0 4838#define M_FW_PARAMS_PARAM_Z 0xff 4839#define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 4840#define G_FW_PARAMS_PARAM_Z(x) \ 4841 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 4842 4843#define S_FW_PARAMS_PARAM_XYZ 0 4844#define M_FW_PARAMS_PARAM_XYZ 0xffffff 4845#define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 4846#define G_FW_PARAMS_PARAM_XYZ(x) \ 4847 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 4848 4849#define S_FW_PARAMS_PARAM_YZ 0 4850#define M_FW_PARAMS_PARAM_YZ 0xffff 4851#define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 4852#define G_FW_PARAMS_PARAM_YZ(x) \ 4853 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 4854 4855#define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31 4856#define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1 4857#define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4858 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4859#define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4860 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \ 4861 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4862 4863#define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24 4864#define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3 4865#define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4866 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4867#define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4868 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \ 4869 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4870 4871#define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0 4872#define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff 4873#define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4874 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4875#define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4876 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4877 4878#define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29 4879#define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7 4880#define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 4881 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 4882#define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 4883 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \ 4884 M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 4885 4886#define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0 4887#define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff 4888#define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 4889 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 4890#define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 4891 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \ 4892 M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 4893 4894struct fw_params_cmd { 4895 __be32 op_to_vfn; 4896 __be32 retval_len16; 4897 struct fw_params_param { 4898 __be32 mnem; 4899 __be32 val; 4900 } param[7]; 4901}; 4902 4903#define S_FW_PARAMS_CMD_PFN 8 4904#define M_FW_PARAMS_CMD_PFN 0x7 4905#define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 4906#define G_FW_PARAMS_CMD_PFN(x) \ 4907 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 4908 4909#define S_FW_PARAMS_CMD_VFN 0 4910#define M_FW_PARAMS_CMD_VFN 0xff 4911#define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 4912#define G_FW_PARAMS_CMD_VFN(x) \ 4913 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 4914 4915struct fw_pfvf_cmd { 4916 __be32 op_to_vfn; 4917 __be32 retval_len16; 4918 __be32 niqflint_niq; 4919 __be32 type_to_neq; 4920 __be32 tc_to_nexactf; 4921 __be32 r_caps_to_nethctrl; 4922 __be16 nricq; 4923 __be16 nriqp; 4924 __be32 r4; 4925}; 4926 4927#define S_FW_PFVF_CMD_PFN 8 4928#define M_FW_PFVF_CMD_PFN 0x7 4929#define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 4930#define G_FW_PFVF_CMD_PFN(x) \ 4931 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 4932 4933#define S_FW_PFVF_CMD_VFN 0 4934#define M_FW_PFVF_CMD_VFN 0xff 4935#define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 4936#define G_FW_PFVF_CMD_VFN(x) \ 4937 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 4938 4939#define S_FW_PFVF_CMD_NIQFLINT 20 4940#define M_FW_PFVF_CMD_NIQFLINT 0xfff 4941#define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 4942#define G_FW_PFVF_CMD_NIQFLINT(x) \ 4943 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 4944 4945#define S_FW_PFVF_CMD_NIQ 0 4946#define M_FW_PFVF_CMD_NIQ 0xfffff 4947#define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 4948#define G_FW_PFVF_CMD_NIQ(x) \ 4949 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 4950 4951#define S_FW_PFVF_CMD_TYPE 31 4952#define M_FW_PFVF_CMD_TYPE 0x1 4953#define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 4954#define G_FW_PFVF_CMD_TYPE(x) \ 4955 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 4956#define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 4957 4958#define S_FW_PFVF_CMD_CMASK 24 4959#define M_FW_PFVF_CMD_CMASK 0xf 4960#define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 4961#define G_FW_PFVF_CMD_CMASK(x) \ 4962 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 4963 4964#define S_FW_PFVF_CMD_PMASK 20 4965#define M_FW_PFVF_CMD_PMASK 0xf 4966#define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 4967#define G_FW_PFVF_CMD_PMASK(x) \ 4968 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 4969 4970#define S_FW_PFVF_CMD_NEQ 0 4971#define M_FW_PFVF_CMD_NEQ 0xfffff 4972#define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 4973#define G_FW_PFVF_CMD_NEQ(x) \ 4974 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 4975 4976#define S_FW_PFVF_CMD_TC 24 4977#define M_FW_PFVF_CMD_TC 0xff 4978#define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 4979#define G_FW_PFVF_CMD_TC(x) \ 4980 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 4981 4982#define S_FW_PFVF_CMD_NVI 16 4983#define M_FW_PFVF_CMD_NVI 0xff 4984#define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 4985#define G_FW_PFVF_CMD_NVI(x) \ 4986 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 4987 4988#define S_FW_PFVF_CMD_NEXACTF 0 4989#define M_FW_PFVF_CMD_NEXACTF 0xffff 4990#define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 4991#define G_FW_PFVF_CMD_NEXACTF(x) \ 4992 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 4993 4994#define S_FW_PFVF_CMD_R_CAPS 24 4995#define M_FW_PFVF_CMD_R_CAPS 0xff 4996#define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 4997#define G_FW_PFVF_CMD_R_CAPS(x) \ 4998 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 4999 5000#define S_FW_PFVF_CMD_WX_CAPS 16 5001#define M_FW_PFVF_CMD_WX_CAPS 0xff 5002#define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 5003#define G_FW_PFVF_CMD_WX_CAPS(x) \ 5004 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 5005 5006#define S_FW_PFVF_CMD_NETHCTRL 0 5007#define M_FW_PFVF_CMD_NETHCTRL 0xffff 5008#define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 5009#define G_FW_PFVF_CMD_NETHCTRL(x) \ 5010 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 5011 5012/* 5013 * ingress queue type; the first 1K ingress queues can have associated 0, 5014 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 5015 * capabilities 5016 */ 5017enum fw_iq_type { 5018 FW_IQ_TYPE_FL_INT_CAP, 5019 FW_IQ_TYPE_NO_FL_INT_CAP, 5020 FW_IQ_TYPE_VF_CQ 5021}; 5022 5023struct fw_iq_cmd { 5024 __be32 op_to_vfn; 5025 __be32 alloc_to_len16; 5026 __be16 physiqid; 5027 __be16 iqid; 5028 __be16 fl0id; 5029 __be16 fl1id; 5030 __be32 type_to_iqandstindex; 5031 __be16 iqdroprss_to_iqesize; 5032 __be16 iqsize; 5033 __be64 iqaddr; 5034 __be32 iqns_to_fl0congen; 5035 __be16 fl0dcaen_to_fl0cidxfthresh; 5036 __be16 fl0size; 5037 __be64 fl0addr; 5038 __be32 fl1cngchmap_to_fl1congen; 5039 __be16 fl1dcaen_to_fl1cidxfthresh; 5040 __be16 fl1size; 5041 __be64 fl1addr; 5042}; 5043 5044#define S_FW_IQ_CMD_PFN 8 5045#define M_FW_IQ_CMD_PFN 0x7 5046#define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 5047#define G_FW_IQ_CMD_PFN(x) \ 5048 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 5049 5050#define S_FW_IQ_CMD_VFN 0 5051#define M_FW_IQ_CMD_VFN 0xff 5052#define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 5053#define G_FW_IQ_CMD_VFN(x) \ 5054 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 5055 5056#define S_FW_IQ_CMD_ALLOC 31 5057#define M_FW_IQ_CMD_ALLOC 0x1 5058#define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 5059#define G_FW_IQ_CMD_ALLOC(x) \ 5060 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 5061#define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 5062 5063#define S_FW_IQ_CMD_FREE 30 5064#define M_FW_IQ_CMD_FREE 0x1 5065#define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 5066#define G_FW_IQ_CMD_FREE(x) \ 5067 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 5068#define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 5069 5070#define S_FW_IQ_CMD_MODIFY 29 5071#define M_FW_IQ_CMD_MODIFY 0x1 5072#define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 5073#define G_FW_IQ_CMD_MODIFY(x) \ 5074 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 5075#define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 5076 5077#define S_FW_IQ_CMD_IQSTART 28 5078#define M_FW_IQ_CMD_IQSTART 0x1 5079#define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 5080#define G_FW_IQ_CMD_IQSTART(x) \ 5081 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 5082#define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 5083 5084#define S_FW_IQ_CMD_IQSTOP 27 5085#define M_FW_IQ_CMD_IQSTOP 0x1 5086#define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 5087#define G_FW_IQ_CMD_IQSTOP(x) \ 5088 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 5089#define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 5090 5091#define S_FW_IQ_CMD_TYPE 29 5092#define M_FW_IQ_CMD_TYPE 0x7 5093#define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 5094#define G_FW_IQ_CMD_TYPE(x) \ 5095 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 5096 5097#define S_FW_IQ_CMD_IQASYNCH 28 5098#define M_FW_IQ_CMD_IQASYNCH 0x1 5099#define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 5100#define G_FW_IQ_CMD_IQASYNCH(x) \ 5101 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 5102#define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 5103 5104#define S_FW_IQ_CMD_VIID 16 5105#define M_FW_IQ_CMD_VIID 0xfff 5106#define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 5107#define G_FW_IQ_CMD_VIID(x) \ 5108 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 5109 5110#define S_FW_IQ_CMD_IQANDST 15 5111#define M_FW_IQ_CMD_IQANDST 0x1 5112#define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 5113#define G_FW_IQ_CMD_IQANDST(x) \ 5114 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 5115#define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 5116 5117#define S_FW_IQ_CMD_IQANUS 14 5118#define M_FW_IQ_CMD_IQANUS 0x1 5119#define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 5120#define G_FW_IQ_CMD_IQANUS(x) \ 5121 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 5122#define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 5123 5124#define S_FW_IQ_CMD_IQANUD 12 5125#define M_FW_IQ_CMD_IQANUD 0x3 5126#define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 5127#define G_FW_IQ_CMD_IQANUD(x) \ 5128 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 5129 5130#define S_FW_IQ_CMD_IQANDSTINDEX 0 5131#define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 5132#define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 5133#define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 5134 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 5135 5136#define S_FW_IQ_CMD_IQDROPRSS 15 5137#define M_FW_IQ_CMD_IQDROPRSS 0x1 5138#define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 5139#define G_FW_IQ_CMD_IQDROPRSS(x) \ 5140 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 5141#define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 5142 5143#define S_FW_IQ_CMD_IQGTSMODE 14 5144#define M_FW_IQ_CMD_IQGTSMODE 0x1 5145#define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 5146#define G_FW_IQ_CMD_IQGTSMODE(x) \ 5147 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 5148#define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 5149 5150#define S_FW_IQ_CMD_IQPCIECH 12 5151#define M_FW_IQ_CMD_IQPCIECH 0x3 5152#define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 5153#define G_FW_IQ_CMD_IQPCIECH(x) \ 5154 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 5155 5156#define S_FW_IQ_CMD_IQDCAEN 11 5157#define M_FW_IQ_CMD_IQDCAEN 0x1 5158#define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 5159#define G_FW_IQ_CMD_IQDCAEN(x) \ 5160 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 5161#define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 5162 5163#define S_FW_IQ_CMD_IQDCACPU 6 5164#define M_FW_IQ_CMD_IQDCACPU 0x1f 5165#define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 5166#define G_FW_IQ_CMD_IQDCACPU(x) \ 5167 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 5168 5169#define S_FW_IQ_CMD_IQINTCNTTHRESH 4 5170#define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 5171#define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 5172#define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 5173 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 5174 5175#define S_FW_IQ_CMD_IQO 3 5176#define M_FW_IQ_CMD_IQO 0x1 5177#define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 5178#define G_FW_IQ_CMD_IQO(x) \ 5179 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 5180#define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 5181 5182#define S_FW_IQ_CMD_IQCPRIO 2 5183#define M_FW_IQ_CMD_IQCPRIO 0x1 5184#define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 5185#define G_FW_IQ_CMD_IQCPRIO(x) \ 5186 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 5187#define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 5188 5189#define S_FW_IQ_CMD_IQESIZE 0 5190#define M_FW_IQ_CMD_IQESIZE 0x3 5191#define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 5192#define G_FW_IQ_CMD_IQESIZE(x) \ 5193 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 5194 5195#define S_FW_IQ_CMD_IQNS 31 5196#define M_FW_IQ_CMD_IQNS 0x1 5197#define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 5198#define G_FW_IQ_CMD_IQNS(x) \ 5199 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 5200#define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 5201 5202#define S_FW_IQ_CMD_IQRO 30 5203#define M_FW_IQ_CMD_IQRO 0x1 5204#define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 5205#define G_FW_IQ_CMD_IQRO(x) \ 5206 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 5207#define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 5208 5209#define S_FW_IQ_CMD_IQFLINTIQHSEN 28 5210#define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 5211#define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 5212#define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 5213 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 5214 5215#define S_FW_IQ_CMD_IQFLINTCONGEN 27 5216#define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 5217#define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 5218#define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 5219 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 5220#define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 5221 5222#define S_FW_IQ_CMD_IQFLINTISCSIC 26 5223#define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 5224#define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 5225#define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 5226 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 5227#define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 5228 5229#define S_FW_IQ_CMD_FL0CNGCHMAP 20 5230#define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 5231#define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 5232#define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 5233 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 5234 5235#define S_FW_IQ_CMD_FL0CONGDROP 16 5236#define M_FW_IQ_CMD_FL0CONGDROP 0x1 5237#define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) 5238#define G_FW_IQ_CMD_FL0CONGDROP(x) \ 5239 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) 5240#define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) 5241 5242#define S_FW_IQ_CMD_FL0CACHELOCK 15 5243#define M_FW_IQ_CMD_FL0CACHELOCK 0x1 5244#define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 5245#define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 5246 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 5247#define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 5248 5249#define S_FW_IQ_CMD_FL0DBP 14 5250#define M_FW_IQ_CMD_FL0DBP 0x1 5251#define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 5252#define G_FW_IQ_CMD_FL0DBP(x) \ 5253 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 5254#define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 5255 5256#define S_FW_IQ_CMD_FL0DATANS 13 5257#define M_FW_IQ_CMD_FL0DATANS 0x1 5258#define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 5259#define G_FW_IQ_CMD_FL0DATANS(x) \ 5260 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 5261#define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 5262 5263#define S_FW_IQ_CMD_FL0DATARO 12 5264#define M_FW_IQ_CMD_FL0DATARO 0x1 5265#define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 5266#define G_FW_IQ_CMD_FL0DATARO(x) \ 5267 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 5268#define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 5269 5270#define S_FW_IQ_CMD_FL0CONGCIF 11 5271#define M_FW_IQ_CMD_FL0CONGCIF 0x1 5272#define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 5273#define G_FW_IQ_CMD_FL0CONGCIF(x) \ 5274 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 5275#define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 5276 5277#define S_FW_IQ_CMD_FL0ONCHIP 10 5278#define M_FW_IQ_CMD_FL0ONCHIP 0x1 5279#define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 5280#define G_FW_IQ_CMD_FL0ONCHIP(x) \ 5281 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 5282#define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 5283 5284#define S_FW_IQ_CMD_FL0STATUSPGNS 9 5285#define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 5286#define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 5287#define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 5288 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 5289#define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 5290 5291#define S_FW_IQ_CMD_FL0STATUSPGRO 8 5292#define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 5293#define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 5294#define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 5295 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 5296#define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 5297 5298#define S_FW_IQ_CMD_FL0FETCHNS 7 5299#define M_FW_IQ_CMD_FL0FETCHNS 0x1 5300#define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 5301#define G_FW_IQ_CMD_FL0FETCHNS(x) \ 5302 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 5303#define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 5304 5305#define S_FW_IQ_CMD_FL0FETCHRO 6 5306#define M_FW_IQ_CMD_FL0FETCHRO 0x1 5307#define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 5308#define G_FW_IQ_CMD_FL0FETCHRO(x) \ 5309 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 5310#define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 5311 5312#define S_FW_IQ_CMD_FL0HOSTFCMODE 4 5313#define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 5314#define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 5315#define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 5316 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 5317 5318#define S_FW_IQ_CMD_FL0CPRIO 3 5319#define M_FW_IQ_CMD_FL0CPRIO 0x1 5320#define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 5321#define G_FW_IQ_CMD_FL0CPRIO(x) \ 5322 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 5323#define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 5324 5325#define S_FW_IQ_CMD_FL0PADEN 2 5326#define M_FW_IQ_CMD_FL0PADEN 0x1 5327#define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 5328#define G_FW_IQ_CMD_FL0PADEN(x) \ 5329 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 5330#define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 5331 5332#define S_FW_IQ_CMD_FL0PACKEN 1 5333#define M_FW_IQ_CMD_FL0PACKEN 0x1 5334#define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 5335#define G_FW_IQ_CMD_FL0PACKEN(x) \ 5336 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 5337#define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 5338 5339#define S_FW_IQ_CMD_FL0CONGEN 0 5340#define M_FW_IQ_CMD_FL0CONGEN 0x1 5341#define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 5342#define G_FW_IQ_CMD_FL0CONGEN(x) \ 5343 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 5344#define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 5345 5346#define S_FW_IQ_CMD_FL0DCAEN 15 5347#define M_FW_IQ_CMD_FL0DCAEN 0x1 5348#define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 5349#define G_FW_IQ_CMD_FL0DCAEN(x) \ 5350 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 5351#define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 5352 5353#define S_FW_IQ_CMD_FL0DCACPU 10 5354#define M_FW_IQ_CMD_FL0DCACPU 0x1f 5355#define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 5356#define G_FW_IQ_CMD_FL0DCACPU(x) \ 5357 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 5358 5359#define S_FW_IQ_CMD_FL0FBMIN 7 5360#define M_FW_IQ_CMD_FL0FBMIN 0x7 5361#define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 5362#define G_FW_IQ_CMD_FL0FBMIN(x) \ 5363 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 5364 5365#define S_FW_IQ_CMD_FL0FBMAX 4 5366#define M_FW_IQ_CMD_FL0FBMAX 0x7 5367#define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 5368#define G_FW_IQ_CMD_FL0FBMAX(x) \ 5369 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 5370 5371#define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 5372#define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 5373#define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 5374#define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 5375 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 5376#define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 5377 5378#define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 5379#define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 5380#define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 5381#define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 5382 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 5383 5384#define S_FW_IQ_CMD_FL1CNGCHMAP 20 5385#define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 5386#define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 5387#define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 5388 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 5389 5390#define S_FW_IQ_CMD_FL1CONGDROP 16 5391#define M_FW_IQ_CMD_FL1CONGDROP 0x1 5392#define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) 5393#define G_FW_IQ_CMD_FL1CONGDROP(x) \ 5394 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) 5395#define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) 5396 5397#define S_FW_IQ_CMD_FL1CACHELOCK 15 5398#define M_FW_IQ_CMD_FL1CACHELOCK 0x1 5399#define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 5400#define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 5401 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 5402#define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 5403 5404#define S_FW_IQ_CMD_FL1DBP 14 5405#define M_FW_IQ_CMD_FL1DBP 0x1 5406#define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 5407#define G_FW_IQ_CMD_FL1DBP(x) \ 5408 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 5409#define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 5410 5411#define S_FW_IQ_CMD_FL1DATANS 13 5412#define M_FW_IQ_CMD_FL1DATANS 0x1 5413#define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 5414#define G_FW_IQ_CMD_FL1DATANS(x) \ 5415 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 5416#define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 5417 5418#define S_FW_IQ_CMD_FL1DATARO 12 5419#define M_FW_IQ_CMD_FL1DATARO 0x1 5420#define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 5421#define G_FW_IQ_CMD_FL1DATARO(x) \ 5422 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 5423#define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 5424 5425#define S_FW_IQ_CMD_FL1CONGCIF 11 5426#define M_FW_IQ_CMD_FL1CONGCIF 0x1 5427#define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 5428#define G_FW_IQ_CMD_FL1CONGCIF(x) \ 5429 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 5430#define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 5431 5432#define S_FW_IQ_CMD_FL1ONCHIP 10 5433#define M_FW_IQ_CMD_FL1ONCHIP 0x1 5434#define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 5435#define G_FW_IQ_CMD_FL1ONCHIP(x) \ 5436 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 5437#define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 5438 5439#define S_FW_IQ_CMD_FL1STATUSPGNS 9 5440#define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 5441#define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 5442#define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 5443 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 5444#define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 5445 5446#define S_FW_IQ_CMD_FL1STATUSPGRO 8 5447#define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 5448#define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 5449#define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 5450 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 5451#define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 5452 5453#define S_FW_IQ_CMD_FL1FETCHNS 7 5454#define M_FW_IQ_CMD_FL1FETCHNS 0x1 5455#define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 5456#define G_FW_IQ_CMD_FL1FETCHNS(x) \ 5457 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 5458#define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 5459 5460#define S_FW_IQ_CMD_FL1FETCHRO 6 5461#define M_FW_IQ_CMD_FL1FETCHRO 0x1 5462#define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 5463#define G_FW_IQ_CMD_FL1FETCHRO(x) \ 5464 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 5465#define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 5466 5467#define S_FW_IQ_CMD_FL1HOSTFCMODE 4 5468#define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 5469#define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 5470#define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 5471 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 5472 5473#define S_FW_IQ_CMD_FL1CPRIO 3 5474#define M_FW_IQ_CMD_FL1CPRIO 0x1 5475#define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 5476#define G_FW_IQ_CMD_FL1CPRIO(x) \ 5477 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 5478#define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 5479 5480#define S_FW_IQ_CMD_FL1PADEN 2 5481#define M_FW_IQ_CMD_FL1PADEN 0x1 5482#define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 5483#define G_FW_IQ_CMD_FL1PADEN(x) \ 5484 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 5485#define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 5486 5487#define S_FW_IQ_CMD_FL1PACKEN 1 5488#define M_FW_IQ_CMD_FL1PACKEN 0x1 5489#define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 5490#define G_FW_IQ_CMD_FL1PACKEN(x) \ 5491 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 5492#define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 5493 5494#define S_FW_IQ_CMD_FL1CONGEN 0 5495#define M_FW_IQ_CMD_FL1CONGEN 0x1 5496#define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 5497#define G_FW_IQ_CMD_FL1CONGEN(x) \ 5498 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 5499#define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 5500 5501#define S_FW_IQ_CMD_FL1DCAEN 15 5502#define M_FW_IQ_CMD_FL1DCAEN 0x1 5503#define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 5504#define G_FW_IQ_CMD_FL1DCAEN(x) \ 5505 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 5506#define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 5507 5508#define S_FW_IQ_CMD_FL1DCACPU 10 5509#define M_FW_IQ_CMD_FL1DCACPU 0x1f 5510#define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 5511#define G_FW_IQ_CMD_FL1DCACPU(x) \ 5512 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 5513 5514#define S_FW_IQ_CMD_FL1FBMIN 7 5515#define M_FW_IQ_CMD_FL1FBMIN 0x7 5516#define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 5517#define G_FW_IQ_CMD_FL1FBMIN(x) \ 5518 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 5519 5520#define S_FW_IQ_CMD_FL1FBMAX 4 5521#define M_FW_IQ_CMD_FL1FBMAX 0x7 5522#define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 5523#define G_FW_IQ_CMD_FL1FBMAX(x) \ 5524 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 5525 5526#define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 5527#define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 5528#define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 5529#define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 5530 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 5531#define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 5532 5533#define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 5534#define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 5535#define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 5536#define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 5537 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 5538 5539struct fw_eq_mngt_cmd { 5540 __be32 op_to_vfn; 5541 __be32 alloc_to_len16; 5542 __be32 cmpliqid_eqid; 5543 __be32 physeqid_pkd; 5544 __be32 fetchszm_to_iqid; 5545 __be32 dcaen_to_eqsize; 5546 __be64 eqaddr; 5547}; 5548 5549#define S_FW_EQ_MNGT_CMD_PFN 8 5550#define M_FW_EQ_MNGT_CMD_PFN 0x7 5551#define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 5552#define G_FW_EQ_MNGT_CMD_PFN(x) \ 5553 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 5554 5555#define S_FW_EQ_MNGT_CMD_VFN 0 5556#define M_FW_EQ_MNGT_CMD_VFN 0xff 5557#define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 5558#define G_FW_EQ_MNGT_CMD_VFN(x) \ 5559 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 5560 5561#define S_FW_EQ_MNGT_CMD_ALLOC 31 5562#define M_FW_EQ_MNGT_CMD_ALLOC 0x1 5563#define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 5564#define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 5565 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 5566#define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 5567 5568#define S_FW_EQ_MNGT_CMD_FREE 30 5569#define M_FW_EQ_MNGT_CMD_FREE 0x1 5570#define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 5571#define G_FW_EQ_MNGT_CMD_FREE(x) \ 5572 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 5573#define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 5574 5575#define S_FW_EQ_MNGT_CMD_MODIFY 29 5576#define M_FW_EQ_MNGT_CMD_MODIFY 0x1 5577#define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 5578#define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 5579 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 5580#define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 5581 5582#define S_FW_EQ_MNGT_CMD_EQSTART 28 5583#define M_FW_EQ_MNGT_CMD_EQSTART 0x1 5584#define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 5585#define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 5586 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 5587#define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 5588 5589#define S_FW_EQ_MNGT_CMD_EQSTOP 27 5590#define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 5591#define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 5592#define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 5593 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 5594#define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 5595 5596#define S_FW_EQ_MNGT_CMD_CMPLIQID 20 5597#define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 5598#define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 5599#define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 5600 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 5601 5602#define S_FW_EQ_MNGT_CMD_EQID 0 5603#define M_FW_EQ_MNGT_CMD_EQID 0xfffff 5604#define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 5605#define G_FW_EQ_MNGT_CMD_EQID(x) \ 5606 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 5607 5608#define S_FW_EQ_MNGT_CMD_PHYSEQID 0 5609#define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 5610#define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 5611#define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 5612 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 5613 5614#define S_FW_EQ_MNGT_CMD_FETCHSZM 26 5615#define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 5616#define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 5617#define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 5618 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 5619#define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 5620 5621#define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 5622#define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 5623#define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 5624#define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 5625 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 5626#define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 5627 5628#define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 5629#define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 5630#define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 5631#define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 5632 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 5633#define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 5634 5635#define S_FW_EQ_MNGT_CMD_FETCHNS 23 5636#define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 5637#define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 5638#define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 5639 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 5640#define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 5641 5642#define S_FW_EQ_MNGT_CMD_FETCHRO 22 5643#define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 5644#define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 5645#define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 5646 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 5647#define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 5648 5649#define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 5650#define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 5651#define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 5652#define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 5653 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 5654 5655#define S_FW_EQ_MNGT_CMD_CPRIO 19 5656#define M_FW_EQ_MNGT_CMD_CPRIO 0x1 5657#define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 5658#define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 5659 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 5660#define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 5661 5662#define S_FW_EQ_MNGT_CMD_ONCHIP 18 5663#define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 5664#define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 5665#define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 5666 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 5667#define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 5668 5669#define S_FW_EQ_MNGT_CMD_PCIECHN 16 5670#define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 5671#define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 5672#define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 5673 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 5674 5675#define S_FW_EQ_MNGT_CMD_IQID 0 5676#define M_FW_EQ_MNGT_CMD_IQID 0xffff 5677#define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 5678#define G_FW_EQ_MNGT_CMD_IQID(x) \ 5679 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 5680 5681#define S_FW_EQ_MNGT_CMD_DCAEN 31 5682#define M_FW_EQ_MNGT_CMD_DCAEN 0x1 5683#define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 5684#define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 5685 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 5686#define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 5687 5688#define S_FW_EQ_MNGT_CMD_DCACPU 26 5689#define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 5690#define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 5691#define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 5692 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 5693 5694#define S_FW_EQ_MNGT_CMD_FBMIN 23 5695#define M_FW_EQ_MNGT_CMD_FBMIN 0x7 5696#define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 5697#define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 5698 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 5699 5700#define S_FW_EQ_MNGT_CMD_FBMAX 20 5701#define M_FW_EQ_MNGT_CMD_FBMAX 0x7 5702#define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 5703#define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 5704 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 5705 5706#define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 5707#define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 5708#define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5709 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5710#define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5711 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5712#define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 5713 5714#define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 5715#define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 5716#define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5717#define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 5718 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5719 5720#define S_FW_EQ_MNGT_CMD_EQSIZE 0 5721#define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 5722#define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 5723#define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 5724 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 5725 5726struct fw_eq_eth_cmd { 5727 __be32 op_to_vfn; 5728 __be32 alloc_to_len16; 5729 __be32 eqid_pkd; 5730 __be32 physeqid_pkd; 5731 __be32 fetchszm_to_iqid; 5732 __be32 dcaen_to_eqsize; 5733 __be64 eqaddr; 5734 __be32 autoequiqe_to_viid; 5735 __be32 r8_lo; 5736 __be64 r9; 5737}; 5738 5739#define S_FW_EQ_ETH_CMD_PFN 8 5740#define M_FW_EQ_ETH_CMD_PFN 0x7 5741#define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 5742#define G_FW_EQ_ETH_CMD_PFN(x) \ 5743 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 5744 5745#define S_FW_EQ_ETH_CMD_VFN 0 5746#define M_FW_EQ_ETH_CMD_VFN 0xff 5747#define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 5748#define G_FW_EQ_ETH_CMD_VFN(x) \ 5749 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 5750 5751#define S_FW_EQ_ETH_CMD_ALLOC 31 5752#define M_FW_EQ_ETH_CMD_ALLOC 0x1 5753#define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 5754#define G_FW_EQ_ETH_CMD_ALLOC(x) \ 5755 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 5756#define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 5757 5758#define S_FW_EQ_ETH_CMD_FREE 30 5759#define M_FW_EQ_ETH_CMD_FREE 0x1 5760#define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 5761#define G_FW_EQ_ETH_CMD_FREE(x) \ 5762 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 5763#define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 5764 5765#define S_FW_EQ_ETH_CMD_MODIFY 29 5766#define M_FW_EQ_ETH_CMD_MODIFY 0x1 5767#define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 5768#define G_FW_EQ_ETH_CMD_MODIFY(x) \ 5769 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 5770#define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 5771 5772#define S_FW_EQ_ETH_CMD_EQSTART 28 5773#define M_FW_EQ_ETH_CMD_EQSTART 0x1 5774#define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 5775#define G_FW_EQ_ETH_CMD_EQSTART(x) \ 5776 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 5777#define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 5778 5779#define S_FW_EQ_ETH_CMD_EQSTOP 27 5780#define M_FW_EQ_ETH_CMD_EQSTOP 0x1 5781#define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 5782#define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 5783 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 5784#define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 5785 5786#define S_FW_EQ_ETH_CMD_EQID 0 5787#define M_FW_EQ_ETH_CMD_EQID 0xfffff 5788#define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 5789#define G_FW_EQ_ETH_CMD_EQID(x) \ 5790 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 5791 5792#define S_FW_EQ_ETH_CMD_PHYSEQID 0 5793#define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 5794#define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 5795#define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 5796 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 5797 5798#define S_FW_EQ_ETH_CMD_FETCHSZM 26 5799#define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 5800#define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 5801#define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 5802 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 5803#define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 5804 5805#define S_FW_EQ_ETH_CMD_STATUSPGNS 25 5806#define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 5807#define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 5808#define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 5809 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 5810#define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 5811 5812#define S_FW_EQ_ETH_CMD_STATUSPGRO 24 5813#define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 5814#define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 5815#define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 5816 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 5817#define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 5818 5819#define S_FW_EQ_ETH_CMD_FETCHNS 23 5820#define M_FW_EQ_ETH_CMD_FETCHNS 0x1 5821#define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 5822#define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 5823 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 5824#define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 5825 5826#define S_FW_EQ_ETH_CMD_FETCHRO 22 5827#define M_FW_EQ_ETH_CMD_FETCHRO 0x1 5828#define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 5829#define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 5830 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 5831#define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 5832 5833#define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 5834#define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 5835#define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 5836#define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 5837 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 5838 5839#define S_FW_EQ_ETH_CMD_CPRIO 19 5840#define M_FW_EQ_ETH_CMD_CPRIO 0x1 5841#define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 5842#define G_FW_EQ_ETH_CMD_CPRIO(x) \ 5843 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 5844#define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 5845 5846#define S_FW_EQ_ETH_CMD_ONCHIP 18 5847#define M_FW_EQ_ETH_CMD_ONCHIP 0x1 5848#define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 5849#define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 5850 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 5851#define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 5852 5853#define S_FW_EQ_ETH_CMD_PCIECHN 16 5854#define M_FW_EQ_ETH_CMD_PCIECHN 0x3 5855#define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 5856#define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 5857 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 5858 5859#define S_FW_EQ_ETH_CMD_IQID 0 5860#define M_FW_EQ_ETH_CMD_IQID 0xffff 5861#define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 5862#define G_FW_EQ_ETH_CMD_IQID(x) \ 5863 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 5864 5865#define S_FW_EQ_ETH_CMD_DCAEN 31 5866#define M_FW_EQ_ETH_CMD_DCAEN 0x1 5867#define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 5868#define G_FW_EQ_ETH_CMD_DCAEN(x) \ 5869 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 5870#define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 5871 5872#define S_FW_EQ_ETH_CMD_DCACPU 26 5873#define M_FW_EQ_ETH_CMD_DCACPU 0x1f 5874#define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 5875#define G_FW_EQ_ETH_CMD_DCACPU(x) \ 5876 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 5877 5878#define S_FW_EQ_ETH_CMD_FBMIN 23 5879#define M_FW_EQ_ETH_CMD_FBMIN 0x7 5880#define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 5881#define G_FW_EQ_ETH_CMD_FBMIN(x) \ 5882 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 5883 5884#define S_FW_EQ_ETH_CMD_FBMAX 20 5885#define M_FW_EQ_ETH_CMD_FBMAX 0x7 5886#define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 5887#define G_FW_EQ_ETH_CMD_FBMAX(x) \ 5888 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 5889 5890#define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 5891#define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 5892#define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 5893#define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 5894 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 5895#define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 5896 5897#define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 5898#define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 5899#define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 5900#define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 5901 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 5902 5903#define S_FW_EQ_ETH_CMD_EQSIZE 0 5904#define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 5905#define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 5906#define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 5907 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 5908 5909#define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 5910#define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 5911#define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 5912#define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 5913 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 5914#define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 5915 5916#define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 5917#define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 5918#define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 5919#define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 5920 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 5921#define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 5922 5923#define S_FW_EQ_ETH_CMD_VIID 16 5924#define M_FW_EQ_ETH_CMD_VIID 0xfff 5925#define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 5926#define G_FW_EQ_ETH_CMD_VIID(x) \ 5927 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 5928 5929struct fw_eq_ctrl_cmd { 5930 __be32 op_to_vfn; 5931 __be32 alloc_to_len16; 5932 __be32 cmpliqid_eqid; 5933 __be32 physeqid_pkd; 5934 __be32 fetchszm_to_iqid; 5935 __be32 dcaen_to_eqsize; 5936 __be64 eqaddr; 5937}; 5938 5939#define S_FW_EQ_CTRL_CMD_PFN 8 5940#define M_FW_EQ_CTRL_CMD_PFN 0x7 5941#define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 5942#define G_FW_EQ_CTRL_CMD_PFN(x) \ 5943 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 5944 5945#define S_FW_EQ_CTRL_CMD_VFN 0 5946#define M_FW_EQ_CTRL_CMD_VFN 0xff 5947#define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 5948#define G_FW_EQ_CTRL_CMD_VFN(x) \ 5949 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 5950 5951#define S_FW_EQ_CTRL_CMD_ALLOC 31 5952#define M_FW_EQ_CTRL_CMD_ALLOC 0x1 5953#define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 5954#define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 5955 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 5956#define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 5957 5958#define S_FW_EQ_CTRL_CMD_FREE 30 5959#define M_FW_EQ_CTRL_CMD_FREE 0x1 5960#define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 5961#define G_FW_EQ_CTRL_CMD_FREE(x) \ 5962 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 5963#define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 5964 5965#define S_FW_EQ_CTRL_CMD_MODIFY 29 5966#define M_FW_EQ_CTRL_CMD_MODIFY 0x1 5967#define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 5968#define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 5969 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 5970#define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 5971 5972#define S_FW_EQ_CTRL_CMD_EQSTART 28 5973#define M_FW_EQ_CTRL_CMD_EQSTART 0x1 5974#define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 5975#define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 5976 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 5977#define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 5978 5979#define S_FW_EQ_CTRL_CMD_EQSTOP 27 5980#define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 5981#define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 5982#define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 5983 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 5984#define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 5985 5986#define S_FW_EQ_CTRL_CMD_CMPLIQID 20 5987#define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 5988#define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 5989#define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 5990 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 5991 5992#define S_FW_EQ_CTRL_CMD_EQID 0 5993#define M_FW_EQ_CTRL_CMD_EQID 0xfffff 5994#define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 5995#define G_FW_EQ_CTRL_CMD_EQID(x) \ 5996 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 5997 5998#define S_FW_EQ_CTRL_CMD_PHYSEQID 0 5999#define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 6000#define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 6001#define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 6002 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 6003 6004#define S_FW_EQ_CTRL_CMD_FETCHSZM 26 6005#define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 6006#define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 6007#define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 6008 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 6009#define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 6010 6011#define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 6012#define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 6013#define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 6014#define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 6015 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 6016#define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 6017 6018#define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 6019#define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 6020#define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 6021#define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 6022 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 6023#define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 6024 6025#define S_FW_EQ_CTRL_CMD_FETCHNS 23 6026#define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 6027#define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 6028#define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 6029 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 6030#define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 6031 6032#define S_FW_EQ_CTRL_CMD_FETCHRO 22 6033#define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 6034#define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 6035#define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 6036 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 6037#define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 6038 6039#define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 6040#define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 6041#define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 6042#define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 6043 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 6044 6045#define S_FW_EQ_CTRL_CMD_CPRIO 19 6046#define M_FW_EQ_CTRL_CMD_CPRIO 0x1 6047#define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 6048#define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 6049 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 6050#define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 6051 6052#define S_FW_EQ_CTRL_CMD_ONCHIP 18 6053#define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 6054#define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 6055#define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 6056 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 6057#define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 6058 6059#define S_FW_EQ_CTRL_CMD_PCIECHN 16 6060#define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 6061#define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 6062#define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 6063 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 6064 6065#define S_FW_EQ_CTRL_CMD_IQID 0 6066#define M_FW_EQ_CTRL_CMD_IQID 0xffff 6067#define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 6068#define G_FW_EQ_CTRL_CMD_IQID(x) \ 6069 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 6070 6071#define S_FW_EQ_CTRL_CMD_DCAEN 31 6072#define M_FW_EQ_CTRL_CMD_DCAEN 0x1 6073#define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 6074#define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 6075 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 6076#define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 6077 6078#define S_FW_EQ_CTRL_CMD_DCACPU 26 6079#define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 6080#define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 6081#define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 6082 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 6083 6084#define S_FW_EQ_CTRL_CMD_FBMIN 23 6085#define M_FW_EQ_CTRL_CMD_FBMIN 0x7 6086#define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 6087#define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 6088 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 6089 6090#define S_FW_EQ_CTRL_CMD_FBMAX 20 6091#define M_FW_EQ_CTRL_CMD_FBMAX 0x7 6092#define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 6093#define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 6094 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 6095 6096#define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 6097#define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 6098#define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6099 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6100#define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6101 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6102#define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 6103 6104#define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 6105#define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 6106#define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6107#define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 6108 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6109 6110#define S_FW_EQ_CTRL_CMD_EQSIZE 0 6111#define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 6112#define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 6113#define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 6114 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 6115 6116struct fw_eq_ofld_cmd { 6117 __be32 op_to_vfn; 6118 __be32 alloc_to_len16; 6119 __be32 eqid_pkd; 6120 __be32 physeqid_pkd; 6121 __be32 fetchszm_to_iqid; 6122 __be32 dcaen_to_eqsize; 6123 __be64 eqaddr; 6124}; 6125 6126#define S_FW_EQ_OFLD_CMD_PFN 8 6127#define M_FW_EQ_OFLD_CMD_PFN 0x7 6128#define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 6129#define G_FW_EQ_OFLD_CMD_PFN(x) \ 6130 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 6131 6132#define S_FW_EQ_OFLD_CMD_VFN 0 6133#define M_FW_EQ_OFLD_CMD_VFN 0xff 6134#define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 6135#define G_FW_EQ_OFLD_CMD_VFN(x) \ 6136 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 6137 6138#define S_FW_EQ_OFLD_CMD_ALLOC 31 6139#define M_FW_EQ_OFLD_CMD_ALLOC 0x1 6140#define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 6141#define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 6142 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 6143#define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 6144 6145#define S_FW_EQ_OFLD_CMD_FREE 30 6146#define M_FW_EQ_OFLD_CMD_FREE 0x1 6147#define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 6148#define G_FW_EQ_OFLD_CMD_FREE(x) \ 6149 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 6150#define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 6151 6152#define S_FW_EQ_OFLD_CMD_MODIFY 29 6153#define M_FW_EQ_OFLD_CMD_MODIFY 0x1 6154#define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 6155#define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 6156 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 6157#define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 6158 6159#define S_FW_EQ_OFLD_CMD_EQSTART 28 6160#define M_FW_EQ_OFLD_CMD_EQSTART 0x1 6161#define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 6162#define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 6163 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 6164#define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 6165 6166#define S_FW_EQ_OFLD_CMD_EQSTOP 27 6167#define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 6168#define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 6169#define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 6170 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 6171#define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 6172 6173#define S_FW_EQ_OFLD_CMD_EQID 0 6174#define M_FW_EQ_OFLD_CMD_EQID 0xfffff 6175#define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 6176#define G_FW_EQ_OFLD_CMD_EQID(x) \ 6177 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 6178 6179#define S_FW_EQ_OFLD_CMD_PHYSEQID 0 6180#define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 6181#define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 6182#define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 6183 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 6184 6185#define S_FW_EQ_OFLD_CMD_FETCHSZM 26 6186#define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 6187#define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 6188#define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 6189 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 6190#define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 6191 6192#define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 6193#define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 6194#define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 6195#define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 6196 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 6197#define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 6198 6199#define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 6200#define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 6201#define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 6202#define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 6203 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 6204#define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 6205 6206#define S_FW_EQ_OFLD_CMD_FETCHNS 23 6207#define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 6208#define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 6209#define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 6210 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 6211#define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 6212 6213#define S_FW_EQ_OFLD_CMD_FETCHRO 22 6214#define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 6215#define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 6216#define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 6217 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 6218#define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 6219 6220#define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 6221#define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 6222#define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 6223#define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 6224 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 6225 6226#define S_FW_EQ_OFLD_CMD_CPRIO 19 6227#define M_FW_EQ_OFLD_CMD_CPRIO 0x1 6228#define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 6229#define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 6230 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 6231#define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 6232 6233#define S_FW_EQ_OFLD_CMD_ONCHIP 18 6234#define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 6235#define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 6236#define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 6237 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 6238#define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 6239 6240#define S_FW_EQ_OFLD_CMD_PCIECHN 16 6241#define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 6242#define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 6243#define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 6244 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 6245 6246#define S_FW_EQ_OFLD_CMD_IQID 0 6247#define M_FW_EQ_OFLD_CMD_IQID 0xffff 6248#define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 6249#define G_FW_EQ_OFLD_CMD_IQID(x) \ 6250 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 6251 6252#define S_FW_EQ_OFLD_CMD_DCAEN 31 6253#define M_FW_EQ_OFLD_CMD_DCAEN 0x1 6254#define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 6255#define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 6256 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 6257#define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 6258 6259#define S_FW_EQ_OFLD_CMD_DCACPU 26 6260#define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 6261#define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 6262#define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 6263 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 6264 6265#define S_FW_EQ_OFLD_CMD_FBMIN 23 6266#define M_FW_EQ_OFLD_CMD_FBMIN 0x7 6267#define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 6268#define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 6269 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 6270 6271#define S_FW_EQ_OFLD_CMD_FBMAX 20 6272#define M_FW_EQ_OFLD_CMD_FBMAX 0x7 6273#define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 6274#define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 6275 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 6276 6277#define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 6278#define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 6279#define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6280 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6281#define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6282 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6283#define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 6284 6285#define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 6286#define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 6287#define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6288#define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 6289 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6290 6291#define S_FW_EQ_OFLD_CMD_EQSIZE 0 6292#define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 6293#define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 6294#define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 6295 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 6296 6297/* Macros for VIID parsing: 6298 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 6299#define S_FW_VIID_PFN 8 6300#define M_FW_VIID_PFN 0x7 6301#define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 6302#define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 6303 6304#define S_FW_VIID_VIVLD 7 6305#define M_FW_VIID_VIVLD 0x1 6306#define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 6307#define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 6308 6309#define S_FW_VIID_VIN 0 6310#define M_FW_VIID_VIN 0x7F 6311#define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 6312#define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 6313 6314enum fw_vi_func { 6315 FW_VI_FUNC_ETH, 6316 FW_VI_FUNC_OFLD, 6317 FW_VI_FUNC_IWARP, 6318 FW_VI_FUNC_OPENISCSI, 6319 FW_VI_FUNC_OPENFCOE, 6320 FW_VI_FUNC_FOISCSI, 6321 FW_VI_FUNC_FOFCOE, 6322 FW_VI_FUNC_FW, 6323}; 6324 6325struct fw_vi_cmd { 6326 __be32 op_to_vfn; 6327 __be32 alloc_to_len16; 6328 __be16 type_to_viid; 6329 __u8 mac[6]; 6330 __u8 portid_pkd; 6331 __u8 nmac; 6332 __u8 nmac0[6]; 6333 __be16 norss_rsssize; 6334 __u8 nmac1[6]; 6335 __be16 idsiiq_pkd; 6336 __u8 nmac2[6]; 6337 __be16 idseiq_pkd; 6338 __u8 nmac3[6]; 6339 __be64 r9; 6340 __be64 r10; 6341}; 6342 6343#define S_FW_VI_CMD_PFN 8 6344#define M_FW_VI_CMD_PFN 0x7 6345#define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 6346#define G_FW_VI_CMD_PFN(x) \ 6347 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 6348 6349#define S_FW_VI_CMD_VFN 0 6350#define M_FW_VI_CMD_VFN 0xff 6351#define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 6352#define G_FW_VI_CMD_VFN(x) \ 6353 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 6354 6355#define S_FW_VI_CMD_ALLOC 31 6356#define M_FW_VI_CMD_ALLOC 0x1 6357#define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 6358#define G_FW_VI_CMD_ALLOC(x) \ 6359 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 6360#define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 6361 6362#define S_FW_VI_CMD_FREE 30 6363#define M_FW_VI_CMD_FREE 0x1 6364#define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 6365#define G_FW_VI_CMD_FREE(x) \ 6366 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 6367#define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 6368 6369#define S_FW_VI_CMD_TYPE 15 6370#define M_FW_VI_CMD_TYPE 0x1 6371#define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 6372#define G_FW_VI_CMD_TYPE(x) \ 6373 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 6374#define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 6375 6376#define S_FW_VI_CMD_FUNC 12 6377#define M_FW_VI_CMD_FUNC 0x7 6378#define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 6379#define G_FW_VI_CMD_FUNC(x) \ 6380 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 6381 6382#define S_FW_VI_CMD_VIID 0 6383#define M_FW_VI_CMD_VIID 0xfff 6384#define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 6385#define G_FW_VI_CMD_VIID(x) \ 6386 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 6387 6388#define S_FW_VI_CMD_PORTID 4 6389#define M_FW_VI_CMD_PORTID 0xf 6390#define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 6391#define G_FW_VI_CMD_PORTID(x) \ 6392 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 6393 6394#define S_FW_VI_CMD_NORSS 11 6395#define M_FW_VI_CMD_NORSS 0x1 6396#define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 6397#define G_FW_VI_CMD_NORSS(x) \ 6398 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 6399#define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 6400 6401#define S_FW_VI_CMD_RSSSIZE 0 6402#define M_FW_VI_CMD_RSSSIZE 0x7ff 6403#define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 6404#define G_FW_VI_CMD_RSSSIZE(x) \ 6405 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 6406 6407#define S_FW_VI_CMD_IDSIIQ 0 6408#define M_FW_VI_CMD_IDSIIQ 0x3ff 6409#define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 6410#define G_FW_VI_CMD_IDSIIQ(x) \ 6411 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 6412 6413#define S_FW_VI_CMD_IDSEIQ 0 6414#define M_FW_VI_CMD_IDSEIQ 0x3ff 6415#define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 6416#define G_FW_VI_CMD_IDSEIQ(x) \ 6417 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 6418 6419/* Special VI_MAC command index ids */ 6420#define FW_VI_MAC_ADD_MAC 0x3FF 6421#define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 6422#define FW_VI_MAC_MAC_BASED_FREE 0x3FD 6423 6424enum fw_vi_mac_smac { 6425 FW_VI_MAC_MPS_TCAM_ENTRY, 6426 FW_VI_MAC_MPS_TCAM_ONLY, 6427 FW_VI_MAC_SMT_ONLY, 6428 FW_VI_MAC_SMT_AND_MPSTCAM 6429}; 6430 6431enum fw_vi_mac_result { 6432 FW_VI_MAC_R_SUCCESS, 6433 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 6434 FW_VI_MAC_R_SMAC_FAIL, 6435 FW_VI_MAC_R_F_ACL_CHECK 6436}; 6437 6438enum fw_vi_mac_entry_types { 6439 FW_VI_MAC_TYPE_EXACTMAC, 6440 FW_VI_MAC_TYPE_HASHVEC, 6441 FW_VI_MAC_TYPE_RAW, 6442 FW_VI_MAC_TYPE_EXACTMAC_VNI, 6443}; 6444 6445struct fw_vi_mac_cmd { 6446 __be32 op_to_viid; 6447 __be32 freemacs_to_len16; 6448 union fw_vi_mac { 6449 struct fw_vi_mac_exact { 6450 __be16 valid_to_idx; 6451 __u8 macaddr[6]; 6452 } exact[7]; 6453 struct fw_vi_mac_hash { 6454 __be64 hashvec; 6455 } hash; 6456 struct fw_vi_mac_raw { 6457 __be32 raw_idx_pkd; 6458 __be32 data0_pkd; 6459 __be32 data1[2]; 6460 __be64 data0m_pkd; 6461 __be32 data1m[2]; 6462 } raw; 6463 struct fw_vi_mac_vni { 6464 __be16 valid_to_idx; 6465 __u8 macaddr[6]; 6466 __be16 r7; 6467 __u8 macaddr_mask[6]; 6468 __be32 lookup_type_to_vni; 6469 __be32 vni_mask_pkd; 6470 } exact_vni[2]; 6471 } u; 6472}; 6473 6474#define S_FW_VI_MAC_CMD_VIID 0 6475#define M_FW_VI_MAC_CMD_VIID 0xfff 6476#define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 6477#define G_FW_VI_MAC_CMD_VIID(x) \ 6478 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 6479 6480#define S_FW_VI_MAC_CMD_FREEMACS 31 6481#define M_FW_VI_MAC_CMD_FREEMACS 0x1 6482#define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 6483#define G_FW_VI_MAC_CMD_FREEMACS(x) \ 6484 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 6485#define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 6486 6487#define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 6488#define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7 6489#define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 6490#define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \ 6491 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE) 6492 6493#define S_FW_VI_MAC_CMD_HASHUNIEN 22 6494#define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 6495#define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 6496#define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 6497 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 6498#define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 6499 6500#define S_FW_VI_MAC_CMD_VALID 15 6501#define M_FW_VI_MAC_CMD_VALID 0x1 6502#define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 6503#define G_FW_VI_MAC_CMD_VALID(x) \ 6504 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 6505#define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 6506 6507#define S_FW_VI_MAC_CMD_PRIO 12 6508#define M_FW_VI_MAC_CMD_PRIO 0x7 6509#define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 6510#define G_FW_VI_MAC_CMD_PRIO(x) \ 6511 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 6512 6513#define S_FW_VI_MAC_CMD_SMAC_RESULT 10 6514#define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 6515#define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 6516#define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 6517 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 6518 6519#define S_FW_VI_MAC_CMD_IDX 0 6520#define M_FW_VI_MAC_CMD_IDX 0x3ff 6521#define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 6522#define G_FW_VI_MAC_CMD_IDX(x) \ 6523 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 6524 6525#define S_FW_VI_MAC_CMD_RAW_IDX 16 6526#define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 6527#define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 6528#define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 6529 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 6530 6531#define S_FW_VI_MAC_CMD_DATA0 0 6532#define M_FW_VI_MAC_CMD_DATA0 0xffff 6533#define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0) 6534#define G_FW_VI_MAC_CMD_DATA0(x) \ 6535 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0) 6536 6537#define S_FW_VI_MAC_CMD_LOOKUP_TYPE 31 6538#define M_FW_VI_MAC_CMD_LOOKUP_TYPE 0x1 6539#define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x) ((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE) 6540#define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x) \ 6541 (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE) 6542#define F_FW_VI_MAC_CMD_LOOKUP_TYPE V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U) 6543 6544#define S_FW_VI_MAC_CMD_DIP_HIT 30 6545#define M_FW_VI_MAC_CMD_DIP_HIT 0x1 6546#define V_FW_VI_MAC_CMD_DIP_HIT(x) ((x) << S_FW_VI_MAC_CMD_DIP_HIT) 6547#define G_FW_VI_MAC_CMD_DIP_HIT(x) \ 6548 (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT) 6549#define F_FW_VI_MAC_CMD_DIP_HIT V_FW_VI_MAC_CMD_DIP_HIT(1U) 6550 6551#define S_FW_VI_MAC_CMD_VNI 0 6552#define M_FW_VI_MAC_CMD_VNI 0xffffff 6553#define V_FW_VI_MAC_CMD_VNI(x) ((x) << S_FW_VI_MAC_CMD_VNI) 6554#define G_FW_VI_MAC_CMD_VNI(x) \ 6555 (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI) 6556 6557#define S_FW_VI_MAC_CMD_VNI_MASK 0 6558#define M_FW_VI_MAC_CMD_VNI_MASK 0xffffff 6559#define V_FW_VI_MAC_CMD_VNI_MASK(x) ((x) << S_FW_VI_MAC_CMD_VNI_MASK) 6560#define G_FW_VI_MAC_CMD_VNI_MASK(x) \ 6561 (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK) 6562 6563/* T4 max MTU supported */ 6564#define T4_MAX_MTU_SUPPORTED 9600 6565#define FW_RXMODE_MTU_NO_CHG 65535 6566 6567struct fw_vi_rxmode_cmd { 6568 __be32 op_to_viid; 6569 __be32 retval_len16; 6570 __be32 mtu_to_vlanexen; 6571 __be32 r4_lo; 6572}; 6573 6574#define S_FW_VI_RXMODE_CMD_VIID 0 6575#define M_FW_VI_RXMODE_CMD_VIID 0xfff 6576#define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 6577#define G_FW_VI_RXMODE_CMD_VIID(x) \ 6578 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 6579 6580#define S_FW_VI_RXMODE_CMD_MTU 16 6581#define M_FW_VI_RXMODE_CMD_MTU 0xffff 6582#define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 6583#define G_FW_VI_RXMODE_CMD_MTU(x) \ 6584 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 6585 6586#define S_FW_VI_RXMODE_CMD_PROMISCEN 14 6587#define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 6588#define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 6589#define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 6590 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 6591 6592#define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 6593#define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 6594#define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6595 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 6596#define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6597 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 6598 6599#define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 6600#define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 6601#define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6602 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 6603#define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6604 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 6605 6606#define S_FW_VI_RXMODE_CMD_VLANEXEN 8 6607#define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 6608#define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 6609#define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 6610 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 6611 6612struct fw_vi_enable_cmd { 6613 __be32 op_to_viid; 6614 __be32 ien_to_len16; 6615 __be16 blinkdur; 6616 __be16 r3; 6617 __be32 r4; 6618}; 6619 6620#define S_FW_VI_ENABLE_CMD_VIID 0 6621#define M_FW_VI_ENABLE_CMD_VIID 0xfff 6622#define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 6623#define G_FW_VI_ENABLE_CMD_VIID(x) \ 6624 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 6625 6626#define S_FW_VI_ENABLE_CMD_IEN 31 6627#define M_FW_VI_ENABLE_CMD_IEN 0x1 6628#define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 6629#define G_FW_VI_ENABLE_CMD_IEN(x) \ 6630 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 6631#define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 6632 6633#define S_FW_VI_ENABLE_CMD_EEN 30 6634#define M_FW_VI_ENABLE_CMD_EEN 0x1 6635#define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 6636#define G_FW_VI_ENABLE_CMD_EEN(x) \ 6637 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 6638#define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 6639 6640#define S_FW_VI_ENABLE_CMD_LED 29 6641#define M_FW_VI_ENABLE_CMD_LED 0x1 6642#define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 6643#define G_FW_VI_ENABLE_CMD_LED(x) \ 6644 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 6645#define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 6646 6647#define S_FW_VI_ENABLE_CMD_DCB_INFO 28 6648#define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 6649#define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 6650#define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 6651 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 6652#define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 6653 6654/* VI VF stats offset definitions */ 6655#define VI_VF_NUM_STATS 16 6656enum fw_vi_stats_vf_index { 6657 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 6658 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 6659 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 6660 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 6661 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 6662 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 6663 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 6664 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 6665 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 6666 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 6667 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 6668 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 6669 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 6670 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 6671 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 6672 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 6673}; 6674 6675/* VI PF stats offset definitions */ 6676#define VI_PF_NUM_STATS 17 6677enum fw_vi_stats_pf_index { 6678 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 6679 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 6680 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 6681 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 6682 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 6683 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 6684 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 6685 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 6686 FW_VI_PF_STAT_RX_BYTES_IX, 6687 FW_VI_PF_STAT_RX_FRAMES_IX, 6688 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 6689 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 6690 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 6691 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 6692 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 6693 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 6694 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 6695}; 6696 6697struct fw_vi_stats_cmd { 6698 __be32 op_to_viid; 6699 __be32 retval_len16; 6700 union fw_vi_stats { 6701 struct fw_vi_stats_ctl { 6702 __be16 nstats_ix; 6703 __be16 r6; 6704 __be32 r7; 6705 __be64 stat0; 6706 __be64 stat1; 6707 __be64 stat2; 6708 __be64 stat3; 6709 __be64 stat4; 6710 __be64 stat5; 6711 } ctl; 6712 struct fw_vi_stats_pf { 6713 __be64 tx_bcast_bytes; 6714 __be64 tx_bcast_frames; 6715 __be64 tx_mcast_bytes; 6716 __be64 tx_mcast_frames; 6717 __be64 tx_ucast_bytes; 6718 __be64 tx_ucast_frames; 6719 __be64 tx_offload_bytes; 6720 __be64 tx_offload_frames; 6721 __be64 rx_pf_bytes; 6722 __be64 rx_pf_frames; 6723 __be64 rx_bcast_bytes; 6724 __be64 rx_bcast_frames; 6725 __be64 rx_mcast_bytes; 6726 __be64 rx_mcast_frames; 6727 __be64 rx_ucast_bytes; 6728 __be64 rx_ucast_frames; 6729 __be64 rx_err_frames; 6730 } pf; 6731 struct fw_vi_stats_vf { 6732 __be64 tx_bcast_bytes; 6733 __be64 tx_bcast_frames; 6734 __be64 tx_mcast_bytes; 6735 __be64 tx_mcast_frames; 6736 __be64 tx_ucast_bytes; 6737 __be64 tx_ucast_frames; 6738 __be64 tx_drop_frames; 6739 __be64 tx_offload_bytes; 6740 __be64 tx_offload_frames; 6741 __be64 rx_bcast_bytes; 6742 __be64 rx_bcast_frames; 6743 __be64 rx_mcast_bytes; 6744 __be64 rx_mcast_frames; 6745 __be64 rx_ucast_bytes; 6746 __be64 rx_ucast_frames; 6747 __be64 rx_err_frames; 6748 } vf; 6749 } u; 6750}; 6751 6752#define S_FW_VI_STATS_CMD_VIID 0 6753#define M_FW_VI_STATS_CMD_VIID 0xfff 6754#define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 6755#define G_FW_VI_STATS_CMD_VIID(x) \ 6756 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 6757 6758#define S_FW_VI_STATS_CMD_NSTATS 12 6759#define M_FW_VI_STATS_CMD_NSTATS 0x7 6760#define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 6761#define G_FW_VI_STATS_CMD_NSTATS(x) \ 6762 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 6763 6764#define S_FW_VI_STATS_CMD_IX 0 6765#define M_FW_VI_STATS_CMD_IX 0x1f 6766#define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 6767#define G_FW_VI_STATS_CMD_IX(x) \ 6768 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 6769 6770struct fw_acl_mac_cmd { 6771 __be32 op_to_vfn; 6772 __be32 en_to_len16; 6773 __u8 nmac; 6774 __u8 r3[7]; 6775 __be16 r4; 6776 __u8 macaddr0[6]; 6777 __be16 r5; 6778 __u8 macaddr1[6]; 6779 __be16 r6; 6780 __u8 macaddr2[6]; 6781 __be16 r7; 6782 __u8 macaddr3[6]; 6783}; 6784 6785#define S_FW_ACL_MAC_CMD_PFN 8 6786#define M_FW_ACL_MAC_CMD_PFN 0x7 6787#define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 6788#define G_FW_ACL_MAC_CMD_PFN(x) \ 6789 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 6790 6791#define S_FW_ACL_MAC_CMD_VFN 0 6792#define M_FW_ACL_MAC_CMD_VFN 0xff 6793#define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 6794#define G_FW_ACL_MAC_CMD_VFN(x) \ 6795 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 6796 6797#define S_FW_ACL_MAC_CMD_EN 31 6798#define M_FW_ACL_MAC_CMD_EN 0x1 6799#define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 6800#define G_FW_ACL_MAC_CMD_EN(x) \ 6801 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 6802#define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 6803 6804struct fw_acl_vlan_cmd { 6805 __be32 op_to_vfn; 6806 __be32 en_to_len16; 6807 __u8 nvlan; 6808 __u8 dropnovlan_fm; 6809 __u8 r3_lo[6]; 6810 __be16 vlanid[16]; 6811}; 6812 6813#define S_FW_ACL_VLAN_CMD_PFN 8 6814#define M_FW_ACL_VLAN_CMD_PFN 0x7 6815#define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 6816#define G_FW_ACL_VLAN_CMD_PFN(x) \ 6817 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 6818 6819#define S_FW_ACL_VLAN_CMD_VFN 0 6820#define M_FW_ACL_VLAN_CMD_VFN 0xff 6821#define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 6822#define G_FW_ACL_VLAN_CMD_VFN(x) \ 6823 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 6824 6825#define S_FW_ACL_VLAN_CMD_EN 31 6826#define M_FW_ACL_VLAN_CMD_EN 0x1 6827#define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 6828#define G_FW_ACL_VLAN_CMD_EN(x) \ 6829 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 6830#define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 6831 6832#define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 6833#define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 6834#define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 6835#define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 6836 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 6837#define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 6838 6839#define S_FW_ACL_VLAN_CMD_FM 6 6840#define M_FW_ACL_VLAN_CMD_FM 0x1 6841#define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 6842#define G_FW_ACL_VLAN_CMD_FM(x) \ 6843 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 6844#define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 6845 6846/* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ 6847enum fw_port_cap { 6848 FW_PORT_CAP_SPEED_100M = 0x0001, 6849 FW_PORT_CAP_SPEED_1G = 0x0002, 6850 FW_PORT_CAP_SPEED_25G = 0x0004, 6851 FW_PORT_CAP_SPEED_10G = 0x0008, 6852 FW_PORT_CAP_SPEED_40G = 0x0010, 6853 FW_PORT_CAP_SPEED_100G = 0x0020, 6854 FW_PORT_CAP_FC_RX = 0x0040, 6855 FW_PORT_CAP_FC_TX = 0x0080, 6856 FW_PORT_CAP_ANEG = 0x0100, 6857 FW_PORT_CAP_MDIX = 0x0200, 6858 FW_PORT_CAP_MDIAUTO = 0x0400, 6859 FW_PORT_CAP_FEC_RS = 0x0800, 6860 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 6861 FW_PORT_CAP_FEC_RESERVED = 0x2000, 6862 FW_PORT_CAP_802_3_PAUSE = 0x4000, 6863 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 6864}; 6865 6866#define S_FW_PORT_CAP_SPEED 0 6867#define M_FW_PORT_CAP_SPEED 0x3f 6868#define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 6869#define G_FW_PORT_CAP_SPEED(x) \ 6870 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 6871 6872#define S_FW_PORT_CAP_FC 6 6873#define M_FW_PORT_CAP_FC 0x3 6874#define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 6875#define G_FW_PORT_CAP_FC(x) \ 6876 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 6877 6878#define S_FW_PORT_CAP_ANEG 8 6879#define M_FW_PORT_CAP_ANEG 0x1 6880#define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 6881#define G_FW_PORT_CAP_ANEG(x) \ 6882 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 6883 6884#define S_FW_PORT_CAP_FEC 11 6885#define M_FW_PORT_CAP_FEC 0x7 6886#define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC) 6887#define G_FW_PORT_CAP_FEC(x) \ 6888 (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC) 6889 6890#define S_FW_PORT_CAP_802_3 14 6891#define M_FW_PORT_CAP_802_3 0x3 6892#define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) 6893#define G_FW_PORT_CAP_802_3(x) \ 6894 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) 6895 6896enum fw_port_mdi { 6897 FW_PORT_CAP_MDI_UNCHANGED, 6898 FW_PORT_CAP_MDI_AUTO, 6899 FW_PORT_CAP_MDI_F_STRAIGHT, 6900 FW_PORT_CAP_MDI_F_CROSSOVER 6901}; 6902 6903#define S_FW_PORT_CAP_MDI 9 6904#define M_FW_PORT_CAP_MDI 3 6905#define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 6906#define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 6907 6908/* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 6909#define FW_PORT_CAP32_SPEED_100M 0x00000001UL 6910#define FW_PORT_CAP32_SPEED_1G 0x00000002UL 6911#define FW_PORT_CAP32_SPEED_10G 0x00000004UL 6912#define FW_PORT_CAP32_SPEED_25G 0x00000008UL 6913#define FW_PORT_CAP32_SPEED_40G 0x00000010UL 6914#define FW_PORT_CAP32_SPEED_50G 0x00000020UL 6915#define FW_PORT_CAP32_SPEED_100G 0x00000040UL 6916#define FW_PORT_CAP32_SPEED_200G 0x00000080UL 6917#define FW_PORT_CAP32_SPEED_400G 0x00000100UL 6918#define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL 6919#define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL 6920#define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL 6921#define FW_PORT_CAP32_RESERVED1 0x0000f000UL 6922#define FW_PORT_CAP32_FC_RX 0x00010000UL 6923#define FW_PORT_CAP32_FC_TX 0x00020000UL 6924#define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 6925#define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 6926#define FW_PORT_CAP32_ANEG 0x00100000UL 6927#define FW_PORT_CAP32_MDIX 0x00200000UL 6928#define FW_PORT_CAP32_MDIAUTO 0x00400000UL 6929#define FW_PORT_CAP32_FEC_RS 0x00800000UL 6930#define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 6931#define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL 6932#define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL 6933#define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL 6934#define FW_PORT_CAP32_RESERVED2 0xf0000000UL 6935 6936#define S_FW_PORT_CAP32_SPEED 0 6937#define M_FW_PORT_CAP32_SPEED 0xfff 6938#define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED) 6939#define G_FW_PORT_CAP32_SPEED(x) \ 6940 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED) 6941 6942#define S_FW_PORT_CAP32_FC 16 6943#define M_FW_PORT_CAP32_FC 0x3 6944#define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC) 6945#define G_FW_PORT_CAP32_FC(x) \ 6946 (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC) 6947 6948#define S_FW_PORT_CAP32_802_3 18 6949#define M_FW_PORT_CAP32_802_3 0x3 6950#define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3) 6951#define G_FW_PORT_CAP32_802_3(x) \ 6952 (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3) 6953 6954#define S_FW_PORT_CAP32_ANEG 20 6955#define M_FW_PORT_CAP32_ANEG 0x1 6956#define V_FW_PORT_CAP32_ANEG(x) ((x) << S_FW_PORT_CAP32_ANEG) 6957#define G_FW_PORT_CAP32_ANEG(x) \ 6958 (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG) 6959 6960enum fw_port_mdi32 { 6961 FW_PORT_CAP32_MDI_UNCHANGED, 6962 FW_PORT_CAP32_MDI_AUTO, 6963 FW_PORT_CAP32_MDI_F_STRAIGHT, 6964 FW_PORT_CAP32_MDI_F_CROSSOVER 6965}; 6966 6967#define S_FW_PORT_CAP32_MDI 21 6968#define M_FW_PORT_CAP32_MDI 3 6969#define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI) 6970#define G_FW_PORT_CAP32_MDI(x) \ 6971 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI) 6972 6973#define S_FW_PORT_CAP32_FEC 23 6974#define M_FW_PORT_CAP32_FEC 0x1f 6975#define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC) 6976#define G_FW_PORT_CAP32_FEC(x) \ 6977 (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC) 6978 6979/* macros to isolate various 32-bit Port Capabilities sub-fields */ 6980#define CAP32_SPEED(__cap32) \ 6981 (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) & __cap32) 6982 6983#define CAP32_FEC(__cap32) \ 6984 (V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32) 6985 6986enum fw_port_action { 6987 FW_PORT_ACTION_L1_CFG = 0x0001, 6988 FW_PORT_ACTION_L2_CFG = 0x0002, 6989 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 6990 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 6991 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 6992 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 6993 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 6994 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 6995 FW_PORT_ACTION_L1_CFG32 = 0x0009, 6996 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 6997 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 6998 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 6999 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 7000 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 7001 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 7002 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 7003 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 7004 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 7005 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 7006 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 7007 FW_PORT_ACTION_PHY_RESET = 0x0040, 7008 FW_PORT_ACTION_PMA_RESET = 0x0041, 7009 FW_PORT_ACTION_PCS_RESET = 0x0042, 7010 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 7011 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 7012 FW_PORT_ACTION_AN_RESET = 0x0045, 7013}; 7014 7015enum fw_port_l2cfg_ctlbf { 7016 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 7017 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 7018 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 7019 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 7020 FW_PORT_L2_CTLBF_IVLAN = 0x10, 7021 FW_PORT_L2_CTLBF_TXIPG = 0x20, 7022 FW_PORT_L2_CTLBF_MTU = 0x40 7023}; 7024 7025enum fw_dcb_app_tlv_sf { 7026 FW_DCB_APP_SF_ETHERTYPE, 7027 FW_DCB_APP_SF_SOCKET_TCP, 7028 FW_DCB_APP_SF_SOCKET_UDP, 7029 FW_DCB_APP_SF_SOCKET_ALL, 7030}; 7031 7032enum fw_port_dcb_versions { 7033 FW_PORT_DCB_VER_UNKNOWN, 7034 FW_PORT_DCB_VER_CEE1D0, 7035 FW_PORT_DCB_VER_CEE1D01, 7036 FW_PORT_DCB_VER_IEEE, 7037 FW_PORT_DCB_VER_AUTO=7 7038}; 7039 7040enum fw_port_dcb_cfg { 7041 FW_PORT_DCB_CFG_PG = 0x01, 7042 FW_PORT_DCB_CFG_PFC = 0x02, 7043 FW_PORT_DCB_CFG_APPL = 0x04 7044}; 7045 7046enum fw_port_dcb_cfg_rc { 7047 FW_PORT_DCB_CFG_SUCCESS = 0x0, 7048 FW_PORT_DCB_CFG_ERROR = 0x1 7049}; 7050 7051enum fw_port_dcb_type { 7052 FW_PORT_DCB_TYPE_PGID = 0x00, 7053 FW_PORT_DCB_TYPE_PGRATE = 0x01, 7054 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 7055 FW_PORT_DCB_TYPE_PFC = 0x03, 7056 FW_PORT_DCB_TYPE_APP_ID = 0x04, 7057 FW_PORT_DCB_TYPE_CONTROL = 0x05, 7058}; 7059 7060enum fw_port_dcb_feature_state { 7061 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 7062 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 7063 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 7064 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 7065}; 7066 7067enum fw_port_diag_ops { 7068 FW_PORT_DIAGS_TEMP = 0x00, 7069 FW_PORT_DIAGS_TX_POWER = 0x01, 7070 FW_PORT_DIAGS_RX_POWER = 0x02, 7071 FW_PORT_DIAGS_TX_DIS = 0x03, 7072}; 7073 7074struct fw_port_cmd { 7075 __be32 op_to_portid; 7076 __be32 action_to_len16; 7077 union fw_port { 7078 struct fw_port_l1cfg { 7079 __be32 rcap; 7080 __be32 r; 7081 } l1cfg; 7082 struct fw_port_l2cfg { 7083 __u8 ctlbf; 7084 __u8 ovlan3_to_ivlan0; 7085 __be16 ivlantype; 7086 __be16 txipg_force_pinfo; 7087 __be16 mtu; 7088 __be16 ovlan0mask; 7089 __be16 ovlan0type; 7090 __be16 ovlan1mask; 7091 __be16 ovlan1type; 7092 __be16 ovlan2mask; 7093 __be16 ovlan2type; 7094 __be16 ovlan3mask; 7095 __be16 ovlan3type; 7096 } l2cfg; 7097 struct fw_port_info { 7098 __be32 lstatus_to_modtype; 7099 __be16 pcap; 7100 __be16 acap; 7101 __be16 mtu; 7102 __u8 cbllen; 7103 __u8 auxlinfo; 7104 __u8 dcbxdis_pkd; 7105 __u8 r8_lo; 7106 __be16 lpacap; 7107 __be64 r9; 7108 } info; 7109 struct fw_port_diags { 7110 __u8 diagop; 7111 __u8 r[3]; 7112 __be32 diagval; 7113 } diags; 7114 union fw_port_dcb { 7115 struct fw_port_dcb_pgid { 7116 __u8 type; 7117 __u8 apply_pkd; 7118 __u8 r10_lo[2]; 7119 __be32 pgid; 7120 __be64 r11; 7121 } pgid; 7122 struct fw_port_dcb_pgrate { 7123 __u8 type; 7124 __u8 apply_pkd; 7125 __u8 r10_lo[5]; 7126 __u8 num_tcs_supported; 7127 __u8 pgrate[8]; 7128 __u8 tsa[8]; 7129 } pgrate; 7130 struct fw_port_dcb_priorate { 7131 __u8 type; 7132 __u8 apply_pkd; 7133 __u8 r10_lo[6]; 7134 __u8 strict_priorate[8]; 7135 } priorate; 7136 struct fw_port_dcb_pfc { 7137 __u8 type; 7138 __u8 pfcen; 7139 __u8 r10[5]; 7140 __u8 max_pfc_tcs; 7141 __be64 r11; 7142 } pfc; 7143 struct fw_port_app_priority { 7144 __u8 type; 7145 __u8 r10[2]; 7146 __u8 idx; 7147 __u8 user_prio_map; 7148 __u8 sel_field; 7149 __be16 protocolid; 7150 __be64 r12; 7151 } app_priority; 7152 struct fw_port_dcb_control { 7153 __u8 type; 7154 __u8 all_syncd_pkd; 7155 __be16 dcb_version_to_app_state; 7156 __be32 r11; 7157 __be64 r12; 7158 } control; 7159 } dcb; 7160 struct fw_port_l1cfg32 { 7161 __be32 rcap32; 7162 __be32 r; 7163 } l1cfg32; 7164 struct fw_port_info32 { 7165 __be32 lstatus32_to_cbllen32; 7166 __be32 auxlinfo32_mtu32; 7167 __be32 linkattr32; 7168 __be32 pcaps32; 7169 __be32 acaps32; 7170 __be32 lpacaps32; 7171 } info32; 7172 } u; 7173}; 7174 7175#define S_FW_PORT_CMD_READ 22 7176#define M_FW_PORT_CMD_READ 0x1 7177#define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 7178#define G_FW_PORT_CMD_READ(x) \ 7179 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 7180#define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 7181 7182#define S_FW_PORT_CMD_PORTID 0 7183#define M_FW_PORT_CMD_PORTID 0xf 7184#define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 7185#define G_FW_PORT_CMD_PORTID(x) \ 7186 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 7187 7188#define S_FW_PORT_CMD_ACTION 16 7189#define M_FW_PORT_CMD_ACTION 0xffff 7190#define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 7191#define G_FW_PORT_CMD_ACTION(x) \ 7192 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 7193 7194#define S_FW_PORT_CMD_OVLAN3 7 7195#define M_FW_PORT_CMD_OVLAN3 0x1 7196#define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 7197#define G_FW_PORT_CMD_OVLAN3(x) \ 7198 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 7199#define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 7200 7201#define S_FW_PORT_CMD_OVLAN2 6 7202#define M_FW_PORT_CMD_OVLAN2 0x1 7203#define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 7204#define G_FW_PORT_CMD_OVLAN2(x) \ 7205 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 7206#define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 7207 7208#define S_FW_PORT_CMD_OVLAN1 5 7209#define M_FW_PORT_CMD_OVLAN1 0x1 7210#define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 7211#define G_FW_PORT_CMD_OVLAN1(x) \ 7212 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 7213#define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 7214 7215#define S_FW_PORT_CMD_OVLAN0 4 7216#define M_FW_PORT_CMD_OVLAN0 0x1 7217#define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 7218#define G_FW_PORT_CMD_OVLAN0(x) \ 7219 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 7220#define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 7221 7222#define S_FW_PORT_CMD_IVLAN0 3 7223#define M_FW_PORT_CMD_IVLAN0 0x1 7224#define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 7225#define G_FW_PORT_CMD_IVLAN0(x) \ 7226 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 7227#define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 7228 7229#define S_FW_PORT_CMD_TXIPG 3 7230#define M_FW_PORT_CMD_TXIPG 0x1fff 7231#define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 7232#define G_FW_PORT_CMD_TXIPG(x) \ 7233 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 7234 7235#define S_FW_PORT_CMD_FORCE_PINFO 0 7236#define M_FW_PORT_CMD_FORCE_PINFO 0x1 7237#define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 7238#define G_FW_PORT_CMD_FORCE_PINFO(x) \ 7239 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 7240#define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 7241 7242#define S_FW_PORT_CMD_LSTATUS 31 7243#define M_FW_PORT_CMD_LSTATUS 0x1 7244#define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 7245#define G_FW_PORT_CMD_LSTATUS(x) \ 7246 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 7247#define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 7248 7249#define S_FW_PORT_CMD_LSPEED 24 7250#define M_FW_PORT_CMD_LSPEED 0x3f 7251#define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 7252#define G_FW_PORT_CMD_LSPEED(x) \ 7253 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 7254 7255#define S_FW_PORT_CMD_TXPAUSE 23 7256#define M_FW_PORT_CMD_TXPAUSE 0x1 7257#define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 7258#define G_FW_PORT_CMD_TXPAUSE(x) \ 7259 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 7260#define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 7261 7262#define S_FW_PORT_CMD_RXPAUSE 22 7263#define M_FW_PORT_CMD_RXPAUSE 0x1 7264#define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 7265#define G_FW_PORT_CMD_RXPAUSE(x) \ 7266 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 7267#define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 7268 7269#define S_FW_PORT_CMD_MDIOCAP 21 7270#define M_FW_PORT_CMD_MDIOCAP 0x1 7271#define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 7272#define G_FW_PORT_CMD_MDIOCAP(x) \ 7273 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 7274#define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 7275 7276#define S_FW_PORT_CMD_MDIOADDR 16 7277#define M_FW_PORT_CMD_MDIOADDR 0x1f 7278#define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 7279#define G_FW_PORT_CMD_MDIOADDR(x) \ 7280 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 7281 7282#define S_FW_PORT_CMD_LPTXPAUSE 15 7283#define M_FW_PORT_CMD_LPTXPAUSE 0x1 7284#define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 7285#define G_FW_PORT_CMD_LPTXPAUSE(x) \ 7286 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 7287#define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 7288 7289#define S_FW_PORT_CMD_LPRXPAUSE 14 7290#define M_FW_PORT_CMD_LPRXPAUSE 0x1 7291#define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 7292#define G_FW_PORT_CMD_LPRXPAUSE(x) \ 7293 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 7294#define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 7295 7296#define S_FW_PORT_CMD_PTYPE 8 7297#define M_FW_PORT_CMD_PTYPE 0x1f 7298#define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 7299#define G_FW_PORT_CMD_PTYPE(x) \ 7300 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 7301 7302#define S_FW_PORT_CMD_LINKDNRC 5 7303#define M_FW_PORT_CMD_LINKDNRC 0x7 7304#define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 7305#define G_FW_PORT_CMD_LINKDNRC(x) \ 7306 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 7307 7308#define S_FW_PORT_CMD_MODTYPE 0 7309#define M_FW_PORT_CMD_MODTYPE 0x1f 7310#define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 7311#define G_FW_PORT_CMD_MODTYPE(x) \ 7312 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 7313 7314#define S_FW_PORT_AUXLINFO_KX4 2 7315#define M_FW_PORT_AUXLINFO_KX4 0x1 7316#define V_FW_PORT_AUXLINFO_KX4(x) \ 7317 ((x) << S_FW_PORT_AUXLINFO_KX4) 7318#define G_FW_PORT_AUXLINFO_KX4(x) \ 7319 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 7320#define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 7321 7322#define S_FW_PORT_AUXLINFO_KR 1 7323#define M_FW_PORT_AUXLINFO_KR 0x1 7324#define V_FW_PORT_AUXLINFO_KR(x) \ 7325 ((x) << S_FW_PORT_AUXLINFO_KR) 7326#define G_FW_PORT_AUXLINFO_KR(x) \ 7327 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 7328#define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 7329 7330#define S_FW_PORT_CMD_DCBXDIS 7 7331#define M_FW_PORT_CMD_DCBXDIS 0x1 7332#define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 7333#define G_FW_PORT_CMD_DCBXDIS(x) \ 7334 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 7335#define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 7336 7337#define S_FW_PORT_CMD_APPLY 7 7338#define M_FW_PORT_CMD_APPLY 0x1 7339#define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 7340#define G_FW_PORT_CMD_APPLY(x) \ 7341 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 7342#define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 7343 7344#define S_FW_PORT_CMD_ALL_SYNCD 7 7345#define M_FW_PORT_CMD_ALL_SYNCD 0x1 7346#define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 7347#define G_FW_PORT_CMD_ALL_SYNCD(x) \ 7348 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 7349#define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 7350 7351#define S_FW_PORT_CMD_DCB_VERSION 12 7352#define M_FW_PORT_CMD_DCB_VERSION 0x7 7353#define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) 7354#define G_FW_PORT_CMD_DCB_VERSION(x) \ 7355 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) 7356 7357#define S_FW_PORT_CMD_PFC_STATE 8 7358#define M_FW_PORT_CMD_PFC_STATE 0xf 7359#define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 7360#define G_FW_PORT_CMD_PFC_STATE(x) \ 7361 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 7362 7363#define S_FW_PORT_CMD_ETS_STATE 4 7364#define M_FW_PORT_CMD_ETS_STATE 0xf 7365#define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 7366#define G_FW_PORT_CMD_ETS_STATE(x) \ 7367 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 7368 7369#define S_FW_PORT_CMD_APP_STATE 0 7370#define M_FW_PORT_CMD_APP_STATE 0xf 7371#define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 7372#define G_FW_PORT_CMD_APP_STATE(x) \ 7373 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 7374 7375#define S_FW_PORT_CMD_LSTATUS32 31 7376#define M_FW_PORT_CMD_LSTATUS32 0x1 7377#define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32) 7378#define G_FW_PORT_CMD_LSTATUS32(x) \ 7379 (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32) 7380#define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U) 7381 7382#define S_FW_PORT_CMD_LINKDNRC32 28 7383#define M_FW_PORT_CMD_LINKDNRC32 0x7 7384#define V_FW_PORT_CMD_LINKDNRC32(x) ((x) << S_FW_PORT_CMD_LINKDNRC32) 7385#define G_FW_PORT_CMD_LINKDNRC32(x) \ 7386 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32) 7387 7388#define S_FW_PORT_CMD_DCBXDIS32 27 7389#define M_FW_PORT_CMD_DCBXDIS32 0x1 7390#define V_FW_PORT_CMD_DCBXDIS32(x) ((x) << S_FW_PORT_CMD_DCBXDIS32) 7391#define G_FW_PORT_CMD_DCBXDIS32(x) \ 7392 (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32) 7393#define F_FW_PORT_CMD_DCBXDIS32 V_FW_PORT_CMD_DCBXDIS32(1U) 7394 7395#define S_FW_PORT_CMD_MDIOCAP32 26 7396#define M_FW_PORT_CMD_MDIOCAP32 0x1 7397#define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32) 7398#define G_FW_PORT_CMD_MDIOCAP32(x) \ 7399 (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32) 7400#define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U) 7401 7402#define S_FW_PORT_CMD_MDIOADDR32 21 7403#define M_FW_PORT_CMD_MDIOADDR32 0x1f 7404#define V_FW_PORT_CMD_MDIOADDR32(x) ((x) << S_FW_PORT_CMD_MDIOADDR32) 7405#define G_FW_PORT_CMD_MDIOADDR32(x) \ 7406 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32) 7407 7408#define S_FW_PORT_CMD_PORTTYPE32 13 7409#define M_FW_PORT_CMD_PORTTYPE32 0xff 7410#define V_FW_PORT_CMD_PORTTYPE32(x) ((x) << S_FW_PORT_CMD_PORTTYPE32) 7411#define G_FW_PORT_CMD_PORTTYPE32(x) \ 7412 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32) 7413 7414#define S_FW_PORT_CMD_MODTYPE32 8 7415#define M_FW_PORT_CMD_MODTYPE32 0x1f 7416#define V_FW_PORT_CMD_MODTYPE32(x) ((x) << S_FW_PORT_CMD_MODTYPE32) 7417#define G_FW_PORT_CMD_MODTYPE32(x) \ 7418 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32) 7419 7420#define S_FW_PORT_CMD_CBLLEN32 0 7421#define M_FW_PORT_CMD_CBLLEN32 0xff 7422#define V_FW_PORT_CMD_CBLLEN32(x) ((x) << S_FW_PORT_CMD_CBLLEN32) 7423#define G_FW_PORT_CMD_CBLLEN32(x) \ 7424 (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32) 7425 7426#define S_FW_PORT_CMD_AUXLINFO32 24 7427#define M_FW_PORT_CMD_AUXLINFO32 0xff 7428#define V_FW_PORT_CMD_AUXLINFO32(x) ((x) << S_FW_PORT_CMD_AUXLINFO32) 7429#define G_FW_PORT_CMD_AUXLINFO32(x) \ 7430 (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32) 7431 7432#define S_FW_PORT_AUXLINFO32_KX4 2 7433#define M_FW_PORT_AUXLINFO32_KX4 0x1 7434#define V_FW_PORT_AUXLINFO32_KX4(x) \ 7435 ((x) << S_FW_PORT_AUXLINFO32_KX4) 7436#define G_FW_PORT_AUXLINFO32_KX4(x) \ 7437 (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4) 7438#define F_FW_PORT_AUXLINFO32_KX4 V_FW_PORT_AUXLINFO32_KX4(1U) 7439 7440#define S_FW_PORT_AUXLINFO32_KR 1 7441#define M_FW_PORT_AUXLINFO32_KR 0x1 7442#define V_FW_PORT_AUXLINFO32_KR(x) \ 7443 ((x) << S_FW_PORT_AUXLINFO32_KR) 7444#define G_FW_PORT_AUXLINFO32_KR(x) \ 7445 (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR) 7446#define F_FW_PORT_AUXLINFO32_KR V_FW_PORT_AUXLINFO32_KR(1U) 7447 7448#define S_FW_PORT_CMD_MTU32 0 7449#define M_FW_PORT_CMD_MTU32 0xffff 7450#define V_FW_PORT_CMD_MTU32(x) ((x) << S_FW_PORT_CMD_MTU32) 7451#define G_FW_PORT_CMD_MTU32(x) \ 7452 (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32) 7453 7454/* 7455 * These are configured into the VPD and hence tools that generate 7456 * VPD may use this enumeration. 7457 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 7458 * 7459 * REMEMBER: 7460 * Update the Common Code t4_hw.c:t4_get_port_type_description() 7461 * with any new Firmware Port Technology Types! 7462 */ 7463enum fw_port_type { 7464 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 7465 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 7466 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 7467 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ 7468 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ 7469 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 7470 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 7471 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 7472 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 7473 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 7474 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 7475 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 7476 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 7477 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 7478 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 7479 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 7480 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */ 7481 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ 7482 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */ 7483 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ 7484 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ 7485 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ 7486 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 7487}; 7488 7489/* These are read from module's EEPROM and determined once the 7490 module is inserted. */ 7491enum fw_port_module_type { 7492 FW_PORT_MOD_TYPE_NA = 0x0, 7493 FW_PORT_MOD_TYPE_LR = 0x1, 7494 FW_PORT_MOD_TYPE_SR = 0x2, 7495 FW_PORT_MOD_TYPE_ER = 0x3, 7496 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 7497 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 7498 FW_PORT_MOD_TYPE_LRM = 0x6, 7499 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 7500 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 7501 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 7502 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 7503}; 7504 7505/* used by FW and tools may use this to generate VPD */ 7506enum fw_port_mod_sub_type { 7507 FW_PORT_MOD_SUB_TYPE_NA, 7508 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 7509 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 7510 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 7511 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 7512 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 7513 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 7514 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, 7515 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 7516 7517 /* 7518 * The following will never been in the VPD. They are TWINAX cable 7519 * lengths decoded from SFP+ module i2c PROMs. These should almost 7520 * certainly go somewhere else ... 7521 */ 7522 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 7523 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 7524 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 7525 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 7526}; 7527 7528/* link down reason codes (3b) */ 7529enum fw_port_link_dn_rc { 7530 FW_PORT_LINK_DN_RC_NONE, 7531 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 7532 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 7533 FW_PORT_LINK_DN_RESERVED3, 7534 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 7535 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 7536 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 7537 FW_PORT_LINK_DN_RESERVED7 7538}; 7539enum fw_port_stats_tx_index { 7540 FW_STAT_TX_PORT_BYTES_IX = 0, 7541 FW_STAT_TX_PORT_FRAMES_IX, 7542 FW_STAT_TX_PORT_BCAST_IX, 7543 FW_STAT_TX_PORT_MCAST_IX, 7544 FW_STAT_TX_PORT_UCAST_IX, 7545 FW_STAT_TX_PORT_ERROR_IX, 7546 FW_STAT_TX_PORT_64B_IX, 7547 FW_STAT_TX_PORT_65B_127B_IX, 7548 FW_STAT_TX_PORT_128B_255B_IX, 7549 FW_STAT_TX_PORT_256B_511B_IX, 7550 FW_STAT_TX_PORT_512B_1023B_IX, 7551 FW_STAT_TX_PORT_1024B_1518B_IX, 7552 FW_STAT_TX_PORT_1519B_MAX_IX, 7553 FW_STAT_TX_PORT_DROP_IX, 7554 FW_STAT_TX_PORT_PAUSE_IX, 7555 FW_STAT_TX_PORT_PPP0_IX, 7556 FW_STAT_TX_PORT_PPP1_IX, 7557 FW_STAT_TX_PORT_PPP2_IX, 7558 FW_STAT_TX_PORT_PPP3_IX, 7559 FW_STAT_TX_PORT_PPP4_IX, 7560 FW_STAT_TX_PORT_PPP5_IX, 7561 FW_STAT_TX_PORT_PPP6_IX, 7562 FW_STAT_TX_PORT_PPP7_IX, 7563 FW_NUM_PORT_TX_STATS 7564}; 7565 7566enum fw_port_stat_rx_index { 7567 FW_STAT_RX_PORT_BYTES_IX = 0, 7568 FW_STAT_RX_PORT_FRAMES_IX, 7569 FW_STAT_RX_PORT_BCAST_IX, 7570 FW_STAT_RX_PORT_MCAST_IX, 7571 FW_STAT_RX_PORT_UCAST_IX, 7572 FW_STAT_RX_PORT_MTU_ERROR_IX, 7573 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 7574 FW_STAT_RX_PORT_CRC_ERROR_IX, 7575 FW_STAT_RX_PORT_LEN_ERROR_IX, 7576 FW_STAT_RX_PORT_SYM_ERROR_IX, 7577 FW_STAT_RX_PORT_64B_IX, 7578 FW_STAT_RX_PORT_65B_127B_IX, 7579 FW_STAT_RX_PORT_128B_255B_IX, 7580 FW_STAT_RX_PORT_256B_511B_IX, 7581 FW_STAT_RX_PORT_512B_1023B_IX, 7582 FW_STAT_RX_PORT_1024B_1518B_IX, 7583 FW_STAT_RX_PORT_1519B_MAX_IX, 7584 FW_STAT_RX_PORT_PAUSE_IX, 7585 FW_STAT_RX_PORT_PPP0_IX, 7586 FW_STAT_RX_PORT_PPP1_IX, 7587 FW_STAT_RX_PORT_PPP2_IX, 7588 FW_STAT_RX_PORT_PPP3_IX, 7589 FW_STAT_RX_PORT_PPP4_IX, 7590 FW_STAT_RX_PORT_PPP5_IX, 7591 FW_STAT_RX_PORT_PPP6_IX, 7592 FW_STAT_RX_PORT_PPP7_IX, 7593 FW_STAT_RX_PORT_LESS_64B_IX, 7594 FW_STAT_RX_PORT_MAC_ERROR_IX, 7595 FW_NUM_PORT_RX_STATS 7596}; 7597/* port stats */ 7598#define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ 7599 FW_NUM_PORT_RX_STATS) 7600 7601 7602struct fw_port_stats_cmd { 7603 __be32 op_to_portid; 7604 __be32 retval_len16; 7605 union fw_port_stats { 7606 struct fw_port_stats_ctl { 7607 __u8 nstats_bg_bm; 7608 __u8 tx_ix; 7609 __be16 r6; 7610 __be32 r7; 7611 __be64 stat0; 7612 __be64 stat1; 7613 __be64 stat2; 7614 __be64 stat3; 7615 __be64 stat4; 7616 __be64 stat5; 7617 } ctl; 7618 struct fw_port_stats_all { 7619 __be64 tx_bytes; 7620 __be64 tx_frames; 7621 __be64 tx_bcast; 7622 __be64 tx_mcast; 7623 __be64 tx_ucast; 7624 __be64 tx_error; 7625 __be64 tx_64b; 7626 __be64 tx_65b_127b; 7627 __be64 tx_128b_255b; 7628 __be64 tx_256b_511b; 7629 __be64 tx_512b_1023b; 7630 __be64 tx_1024b_1518b; 7631 __be64 tx_1519b_max; 7632 __be64 tx_drop; 7633 __be64 tx_pause; 7634 __be64 tx_ppp0; 7635 __be64 tx_ppp1; 7636 __be64 tx_ppp2; 7637 __be64 tx_ppp3; 7638 __be64 tx_ppp4; 7639 __be64 tx_ppp5; 7640 __be64 tx_ppp6; 7641 __be64 tx_ppp7; 7642 __be64 rx_bytes; 7643 __be64 rx_frames; 7644 __be64 rx_bcast; 7645 __be64 rx_mcast; 7646 __be64 rx_ucast; 7647 __be64 rx_mtu_error; 7648 __be64 rx_mtu_crc_error; 7649 __be64 rx_crc_error; 7650 __be64 rx_len_error; 7651 __be64 rx_sym_error; 7652 __be64 rx_64b; 7653 __be64 rx_65b_127b; 7654 __be64 rx_128b_255b; 7655 __be64 rx_256b_511b; 7656 __be64 rx_512b_1023b; 7657 __be64 rx_1024b_1518b; 7658 __be64 rx_1519b_max; 7659 __be64 rx_pause; 7660 __be64 rx_ppp0; 7661 __be64 rx_ppp1; 7662 __be64 rx_ppp2; 7663 __be64 rx_ppp3; 7664 __be64 rx_ppp4; 7665 __be64 rx_ppp5; 7666 __be64 rx_ppp6; 7667 __be64 rx_ppp7; 7668 __be64 rx_less_64b; 7669 __be64 rx_bg_drop; 7670 __be64 rx_bg_trunc; 7671 } all; 7672 } u; 7673}; 7674 7675#define S_FW_PORT_STATS_CMD_NSTATS 4 7676#define M_FW_PORT_STATS_CMD_NSTATS 0x7 7677#define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 7678#define G_FW_PORT_STATS_CMD_NSTATS(x) \ 7679 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 7680 7681#define S_FW_PORT_STATS_CMD_BG_BM 0 7682#define M_FW_PORT_STATS_CMD_BG_BM 0x3 7683#define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 7684#define G_FW_PORT_STATS_CMD_BG_BM(x) \ 7685 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 7686 7687#define S_FW_PORT_STATS_CMD_TX 7 7688#define M_FW_PORT_STATS_CMD_TX 0x1 7689#define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 7690#define G_FW_PORT_STATS_CMD_TX(x) \ 7691 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 7692#define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 7693 7694#define S_FW_PORT_STATS_CMD_IX 0 7695#define M_FW_PORT_STATS_CMD_IX 0x3f 7696#define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 7697#define G_FW_PORT_STATS_CMD_IX(x) \ 7698 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 7699 7700/* port loopback stats */ 7701#define FW_NUM_LB_STATS 14 7702enum fw_port_lb_stats_index { 7703 FW_STAT_LB_PORT_BYTES_IX, 7704 FW_STAT_LB_PORT_FRAMES_IX, 7705 FW_STAT_LB_PORT_BCAST_IX, 7706 FW_STAT_LB_PORT_MCAST_IX, 7707 FW_STAT_LB_PORT_UCAST_IX, 7708 FW_STAT_LB_PORT_ERROR_IX, 7709 FW_STAT_LB_PORT_64B_IX, 7710 FW_STAT_LB_PORT_65B_127B_IX, 7711 FW_STAT_LB_PORT_128B_255B_IX, 7712 FW_STAT_LB_PORT_256B_511B_IX, 7713 FW_STAT_LB_PORT_512B_1023B_IX, 7714 FW_STAT_LB_PORT_1024B_1518B_IX, 7715 FW_STAT_LB_PORT_1519B_MAX_IX, 7716 FW_STAT_LB_PORT_DROP_FRAMES_IX 7717}; 7718 7719struct fw_port_lb_stats_cmd { 7720 __be32 op_to_lbport; 7721 __be32 retval_len16; 7722 union fw_port_lb_stats { 7723 struct fw_port_lb_stats_ctl { 7724 __u8 nstats_bg_bm; 7725 __u8 ix_pkd; 7726 __be16 r6; 7727 __be32 r7; 7728 __be64 stat0; 7729 __be64 stat1; 7730 __be64 stat2; 7731 __be64 stat3; 7732 __be64 stat4; 7733 __be64 stat5; 7734 } ctl; 7735 struct fw_port_lb_stats_all { 7736 __be64 tx_bytes; 7737 __be64 tx_frames; 7738 __be64 tx_bcast; 7739 __be64 tx_mcast; 7740 __be64 tx_ucast; 7741 __be64 tx_error; 7742 __be64 tx_64b; 7743 __be64 tx_65b_127b; 7744 __be64 tx_128b_255b; 7745 __be64 tx_256b_511b; 7746 __be64 tx_512b_1023b; 7747 __be64 tx_1024b_1518b; 7748 __be64 tx_1519b_max; 7749 __be64 rx_lb_drop; 7750 __be64 rx_lb_trunc; 7751 } all; 7752 } u; 7753}; 7754 7755#define S_FW_PORT_LB_STATS_CMD_LBPORT 0 7756#define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 7757#define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7758 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 7759#define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7760 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 7761 7762#define S_FW_PORT_LB_STATS_CMD_NSTATS 4 7763#define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 7764#define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7765 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 7766#define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7767 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 7768 7769#define S_FW_PORT_LB_STATS_CMD_BG_BM 0 7770#define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 7771#define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 7772#define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 7773 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 7774 7775#define S_FW_PORT_LB_STATS_CMD_IX 0 7776#define M_FW_PORT_LB_STATS_CMD_IX 0xf 7777#define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 7778#define G_FW_PORT_LB_STATS_CMD_IX(x) \ 7779 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 7780 7781/* Trace related defines */ 7782#define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 7783#define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 7784 7785struct fw_port_trace_cmd { 7786 __be32 op_to_portid; 7787 __be32 retval_len16; 7788 __be16 traceen_to_pciech; 7789 __be16 qnum; 7790 __be32 r5; 7791}; 7792 7793#define S_FW_PORT_TRACE_CMD_PORTID 0 7794#define M_FW_PORT_TRACE_CMD_PORTID 0xf 7795#define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 7796#define G_FW_PORT_TRACE_CMD_PORTID(x) \ 7797 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 7798 7799#define S_FW_PORT_TRACE_CMD_TRACEEN 15 7800#define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 7801#define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 7802#define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 7803 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 7804#define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 7805 7806#define S_FW_PORT_TRACE_CMD_FLTMODE 14 7807#define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 7808#define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 7809#define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 7810 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 7811#define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 7812 7813#define S_FW_PORT_TRACE_CMD_DUPLEN 13 7814#define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 7815#define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 7816#define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 7817 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 7818#define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 7819 7820#define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 7821#define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 7822#define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 7823 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 7824#define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 7825 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 7826 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 7827 7828#define S_FW_PORT_TRACE_CMD_PCIECH 6 7829#define M_FW_PORT_TRACE_CMD_PCIECH 0x3 7830#define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 7831#define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 7832 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 7833 7834struct fw_port_trace_mmap_cmd { 7835 __be32 op_to_portid; 7836 __be32 retval_len16; 7837 __be32 fid_to_skipoffset; 7838 __be32 minpktsize_capturemax; 7839 __u8 map[224]; 7840}; 7841 7842#define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 7843#define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 7844#define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 7845 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 7846#define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 7847 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 7848 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 7849 7850#define S_FW_PORT_TRACE_MMAP_CMD_FID 30 7851#define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 7852#define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 7853#define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 7854 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 7855 7856#define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 7857#define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 7858#define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 7859 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 7860#define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 7861 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 7862 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 7863#define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 7864 7865#define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 7866#define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 7867#define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 7868 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 7869#define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 7870 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 7871 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 7872#define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 7873 7874#define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 7875#define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 7876#define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 7877 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 7878#define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 7879 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 7880 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 7881 7882#define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 7883#define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 7884#define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 7885 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 7886#define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 7887 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 7888 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 7889 7890#define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 7891#define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 7892#define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 7893 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 7894#define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 7895 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 7896 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 7897 7898#define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 7899#define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 7900#define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 7901 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 7902#define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 7903 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 7904 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 7905 7906enum fw_ptp_subop { 7907 7908 /* none */ 7909 FW_PTP_SC_INIT_TIMER = 0x00, 7910 FW_PTP_SC_TX_TYPE = 0x01, 7911 7912 /* init */ 7913 FW_PTP_SC_RXTIME_STAMP = 0x08, 7914 FW_PTP_SC_RDRX_TYPE = 0x09, 7915 7916 /* ts */ 7917 FW_PTP_SC_ADJ_FREQ = 0x10, 7918 FW_PTP_SC_ADJ_TIME = 0x11, 7919 FW_PTP_SC_ADJ_FTIME = 0x12, 7920 FW_PTP_SC_WALL_CLOCK = 0x13, 7921 FW_PTP_SC_GET_TIME = 0x14, 7922 FW_PTP_SC_SET_TIME = 0x15, 7923}; 7924 7925struct fw_ptp_cmd { 7926 __be32 op_to_portid; 7927 __be32 retval_len16; 7928 union fw_ptp { 7929 struct fw_ptp_sc { 7930 __u8 sc; 7931 __u8 r3[7]; 7932 } scmd; 7933 struct fw_ptp_init { 7934 __u8 sc; 7935 __u8 txchan; 7936 __be16 absid; 7937 __be16 mode; 7938 __be16 r3; 7939 } init; 7940 struct fw_ptp_ts { 7941 __u8 sc; 7942 __u8 sign; 7943 __be16 r3; 7944 __be32 ppb; 7945 __be64 tm; 7946 } ts; 7947 } u; 7948 __be64 r3; 7949}; 7950 7951#define S_FW_PTP_CMD_PORTID 0 7952#define M_FW_PTP_CMD_PORTID 0xf 7953#define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) 7954#define G_FW_PTP_CMD_PORTID(x) \ 7955 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) 7956 7957struct fw_rss_ind_tbl_cmd { 7958 __be32 op_to_viid; 7959 __be32 retval_len16; 7960 __be16 niqid; 7961 __be16 startidx; 7962 __be32 r3; 7963 __be32 iq0_to_iq2; 7964 __be32 iq3_to_iq5; 7965 __be32 iq6_to_iq8; 7966 __be32 iq9_to_iq11; 7967 __be32 iq12_to_iq14; 7968 __be32 iq15_to_iq17; 7969 __be32 iq18_to_iq20; 7970 __be32 iq21_to_iq23; 7971 __be32 iq24_to_iq26; 7972 __be32 iq27_to_iq29; 7973 __be32 iq30_iq31; 7974 __be32 r15_lo; 7975}; 7976 7977#define S_FW_RSS_IND_TBL_CMD_VIID 0 7978#define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 7979#define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 7980#define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 7981 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 7982 7983#define S_FW_RSS_IND_TBL_CMD_IQ0 20 7984#define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 7985#define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 7986#define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 7987 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 7988 7989#define S_FW_RSS_IND_TBL_CMD_IQ1 10 7990#define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 7991#define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 7992#define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 7993 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 7994 7995#define S_FW_RSS_IND_TBL_CMD_IQ2 0 7996#define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 7997#define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 7998#define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 7999 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 8000 8001#define S_FW_RSS_IND_TBL_CMD_IQ3 20 8002#define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 8003#define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 8004#define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 8005 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 8006 8007#define S_FW_RSS_IND_TBL_CMD_IQ4 10 8008#define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 8009#define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 8010#define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 8011 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 8012 8013#define S_FW_RSS_IND_TBL_CMD_IQ5 0 8014#define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 8015#define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 8016#define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 8017 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 8018 8019#define S_FW_RSS_IND_TBL_CMD_IQ6 20 8020#define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 8021#define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 8022#define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 8023 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 8024 8025#define S_FW_RSS_IND_TBL_CMD_IQ7 10 8026#define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 8027#define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 8028#define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 8029 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 8030 8031#define S_FW_RSS_IND_TBL_CMD_IQ8 0 8032#define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 8033#define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 8034#define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 8035 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 8036 8037#define S_FW_RSS_IND_TBL_CMD_IQ9 20 8038#define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 8039#define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 8040#define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 8041 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 8042 8043#define S_FW_RSS_IND_TBL_CMD_IQ10 10 8044#define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 8045#define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 8046#define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 8047 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 8048 8049#define S_FW_RSS_IND_TBL_CMD_IQ11 0 8050#define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 8051#define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 8052#define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 8053 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 8054 8055#define S_FW_RSS_IND_TBL_CMD_IQ12 20 8056#define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 8057#define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 8058#define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 8059 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 8060 8061#define S_FW_RSS_IND_TBL_CMD_IQ13 10 8062#define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 8063#define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 8064#define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 8065 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 8066 8067#define S_FW_RSS_IND_TBL_CMD_IQ14 0 8068#define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 8069#define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 8070#define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 8071 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 8072 8073#define S_FW_RSS_IND_TBL_CMD_IQ15 20 8074#define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 8075#define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 8076#define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 8077 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 8078 8079#define S_FW_RSS_IND_TBL_CMD_IQ16 10 8080#define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 8081#define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 8082#define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 8083 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 8084 8085#define S_FW_RSS_IND_TBL_CMD_IQ17 0 8086#define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 8087#define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 8088#define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 8089 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 8090 8091#define S_FW_RSS_IND_TBL_CMD_IQ18 20 8092#define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 8093#define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 8094#define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 8095 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 8096 8097#define S_FW_RSS_IND_TBL_CMD_IQ19 10 8098#define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 8099#define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 8100#define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 8101 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 8102 8103#define S_FW_RSS_IND_TBL_CMD_IQ20 0 8104#define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 8105#define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 8106#define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 8107 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 8108 8109#define S_FW_RSS_IND_TBL_CMD_IQ21 20 8110#define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 8111#define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 8112#define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 8113 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 8114 8115#define S_FW_RSS_IND_TBL_CMD_IQ22 10 8116#define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 8117#define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 8118#define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 8119 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 8120 8121#define S_FW_RSS_IND_TBL_CMD_IQ23 0 8122#define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 8123#define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 8124#define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 8125 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 8126 8127#define S_FW_RSS_IND_TBL_CMD_IQ24 20 8128#define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 8129#define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 8130#define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 8131 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 8132 8133#define S_FW_RSS_IND_TBL_CMD_IQ25 10 8134#define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 8135#define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 8136#define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 8137 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 8138 8139#define S_FW_RSS_IND_TBL_CMD_IQ26 0 8140#define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 8141#define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 8142#define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 8143 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 8144 8145#define S_FW_RSS_IND_TBL_CMD_IQ27 20 8146#define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 8147#define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 8148#define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 8149 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 8150 8151#define S_FW_RSS_IND_TBL_CMD_IQ28 10 8152#define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 8153#define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 8154#define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 8155 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 8156 8157#define S_FW_RSS_IND_TBL_CMD_IQ29 0 8158#define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 8159#define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 8160#define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 8161 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 8162 8163#define S_FW_RSS_IND_TBL_CMD_IQ30 20 8164#define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 8165#define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 8166#define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 8167 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 8168 8169#define S_FW_RSS_IND_TBL_CMD_IQ31 10 8170#define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 8171#define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 8172#define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 8173 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 8174 8175struct fw_rss_glb_config_cmd { 8176 __be32 op_to_write; 8177 __be32 retval_len16; 8178 union fw_rss_glb_config { 8179 struct fw_rss_glb_config_manual { 8180 __be32 mode_pkd; 8181 __be32 r3; 8182 __be64 r4; 8183 __be64 r5; 8184 } manual; 8185 struct fw_rss_glb_config_basicvirtual { 8186 __be32 mode_keymode; 8187 __be32 synmapen_to_hashtoeplitz; 8188 __be64 r8; 8189 __be64 r9; 8190 } basicvirtual; 8191 } u; 8192}; 8193 8194#define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 8195#define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 8196#define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 8197#define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 8198 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 8199 8200#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 8201#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 8202#define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 8203 8204#define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26 8205#define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3 8206#define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8207 ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8208#define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 8209 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \ 8210 M_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 8211 8212#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0 8213#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1 8214#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2 8215#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3 8216 8217#define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 8218#define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 8219#define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8220 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8221#define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 8222 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 8223 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 8224#define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 8225 8226#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 8227#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 8228#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8229 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8230#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 8231 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 8232 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 8233#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 8234 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 8235 8236#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 8237#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 8238#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8239 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8240#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 8241 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 8242 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 8243#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 8244 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 8245 8246#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 8247#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 8248#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8249 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8250#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 8251 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 8252 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 8253#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 8254 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 8255 8256#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 8257#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 8258#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8259 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8260#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 8261 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 8262 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 8263#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 8264 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 8265 8266#define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 8267#define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 8268#define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8269 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8270#define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 8271 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 8272 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 8273#define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 8274 8275#define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 8276#define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 8277#define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8278 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8279#define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 8280 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 8281 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 8282#define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 8283 8284#define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 8285#define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 8286#define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8287 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8288#define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 8289 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 8290 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8291#define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 8292 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 8293 8294#define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 8295#define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 8296#define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8297 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8298#define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8299 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 8300 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8301#define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 8302 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 8303 8304struct fw_rss_vi_config_cmd { 8305 __be32 op_to_viid; 8306 __be32 retval_len16; 8307 union fw_rss_vi_config { 8308 struct fw_rss_vi_config_manual { 8309 __be64 r3; 8310 __be64 r4; 8311 __be64 r5; 8312 } manual; 8313 struct fw_rss_vi_config_basicvirtual { 8314 __be32 r6; 8315 __be32 defaultq_to_udpen; 8316 __be32 secretkeyidx_pkd; 8317 __be32 secretkeyxor; 8318 __be64 r10; 8319 } basicvirtual; 8320 } u; 8321}; 8322 8323#define S_FW_RSS_VI_CONFIG_CMD_VIID 0 8324#define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 8325#define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 8326#define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 8327 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 8328 8329#define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 8330#define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 8331#define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8332 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8333#define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8334 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 8335 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8336 8337#define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 8338#define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 8339#define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8340 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8341#define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8342 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 8343 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8344#define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 8345 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 8346 8347#define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 8348#define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 8349#define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8350 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8351#define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8352 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 8353 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8354#define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 8355 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 8356 8357#define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 8358#define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 8359#define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8360 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8361#define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8362 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 8363 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8364#define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 8365 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 8366 8367#define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 8368#define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 8369#define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8370 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8371#define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8372 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 8373 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8374#define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 8375 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 8376 8377#define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 8378#define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 8379#define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 8380#define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 8381 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 8382#define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 8383 8384#define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0 8385#define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf 8386#define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8387 ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 8388#define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 8389 (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \ 8390 M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 8391 8392enum fw_sched_sc { 8393 FW_SCHED_SC_CONFIG = 0, 8394 FW_SCHED_SC_PARAMS = 1, 8395}; 8396 8397enum fw_sched_type { 8398 FW_SCHED_TYPE_PKTSCHED = 0, 8399 FW_SCHED_TYPE_STREAMSCHED = 1, 8400}; 8401 8402enum fw_sched_params_level { 8403 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 8404 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 8405 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 8406}; 8407 8408enum fw_sched_params_mode { 8409 FW_SCHED_PARAMS_MODE_CLASS = 0, 8410 FW_SCHED_PARAMS_MODE_FLOW = 1, 8411}; 8412 8413enum fw_sched_params_unit { 8414 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 8415 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 8416}; 8417 8418enum fw_sched_params_rate { 8419 FW_SCHED_PARAMS_RATE_REL = 0, 8420 FW_SCHED_PARAMS_RATE_ABS = 1, 8421}; 8422 8423struct fw_sched_cmd { 8424 __be32 op_to_write; 8425 __be32 retval_len16; 8426 union fw_sched { 8427 struct fw_sched_config { 8428 __u8 sc; 8429 __u8 type; 8430 __u8 minmaxen; 8431 __u8 r3[5]; 8432 __u8 nclasses[4]; 8433 __be32 r4; 8434 } config; 8435 struct fw_sched_params { 8436 __u8 sc; 8437 __u8 type; 8438 __u8 level; 8439 __u8 mode; 8440 __u8 unit; 8441 __u8 rate; 8442 __u8 ch; 8443 __u8 cl; 8444 __be32 min; 8445 __be32 max; 8446 __be16 weight; 8447 __be16 pktsize; 8448 __be16 burstsize; 8449 __be16 r4; 8450 } params; 8451 } u; 8452}; 8453 8454/* 8455 * length of the formatting string 8456 */ 8457#define FW_DEVLOG_FMT_LEN 192 8458 8459/* 8460 * maximum number of the formatting string parameters 8461 */ 8462#define FW_DEVLOG_FMT_PARAMS_NUM 8 8463 8464/* 8465 * priority levels 8466 */ 8467enum fw_devlog_level { 8468 FW_DEVLOG_LEVEL_EMERG = 0x0, 8469 FW_DEVLOG_LEVEL_CRIT = 0x1, 8470 FW_DEVLOG_LEVEL_ERR = 0x2, 8471 FW_DEVLOG_LEVEL_NOTICE = 0x3, 8472 FW_DEVLOG_LEVEL_INFO = 0x4, 8473 FW_DEVLOG_LEVEL_DEBUG = 0x5, 8474 FW_DEVLOG_LEVEL_MAX = 0x5, 8475}; 8476 8477/* 8478 * facilities that may send a log message 8479 */ 8480enum fw_devlog_facility { 8481 FW_DEVLOG_FACILITY_CORE = 0x00, 8482 FW_DEVLOG_FACILITY_CF = 0x01, 8483 FW_DEVLOG_FACILITY_SCHED = 0x02, 8484 FW_DEVLOG_FACILITY_TIMER = 0x04, 8485 FW_DEVLOG_FACILITY_RES = 0x06, 8486 FW_DEVLOG_FACILITY_HW = 0x08, 8487 FW_DEVLOG_FACILITY_FLR = 0x10, 8488 FW_DEVLOG_FACILITY_DMAQ = 0x12, 8489 FW_DEVLOG_FACILITY_PHY = 0x14, 8490 FW_DEVLOG_FACILITY_MAC = 0x16, 8491 FW_DEVLOG_FACILITY_PORT = 0x18, 8492 FW_DEVLOG_FACILITY_VI = 0x1A, 8493 FW_DEVLOG_FACILITY_FILTER = 0x1C, 8494 FW_DEVLOG_FACILITY_ACL = 0x1E, 8495 FW_DEVLOG_FACILITY_TM = 0x20, 8496 FW_DEVLOG_FACILITY_QFC = 0x22, 8497 FW_DEVLOG_FACILITY_DCB = 0x24, 8498 FW_DEVLOG_FACILITY_ETH = 0x26, 8499 FW_DEVLOG_FACILITY_OFLD = 0x28, 8500 FW_DEVLOG_FACILITY_RI = 0x2A, 8501 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 8502 FW_DEVLOG_FACILITY_FCOE = 0x2E, 8503 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 8504 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 8505 FW_DEVLOG_FACILITY_CHNET = 0x34, 8506 FW_DEVLOG_FACILITY_COISCSI = 0x36, 8507 FW_DEVLOG_FACILITY_MAX = 0x38, 8508}; 8509 8510/* 8511 * log message format 8512 */ 8513struct fw_devlog_e { 8514 __be64 timestamp; 8515 __be32 seqno; 8516 __be16 reserved1; 8517 __u8 level; 8518 __u8 facility; 8519 __u8 fmt[FW_DEVLOG_FMT_LEN]; 8520 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 8521 __be32 reserved3[4]; 8522}; 8523 8524struct fw_devlog_cmd { 8525 __be32 op_to_write; 8526 __be32 retval_len16; 8527 __u8 level; 8528 __u8 r2[7]; 8529 __be32 memtype_devlog_memaddr16_devlog; 8530 __be32 memsize_devlog; 8531 __be32 r3[2]; 8532}; 8533 8534#define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 8535#define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 8536#define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8537 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8538#define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8539 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8540 8541#define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 8542#define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 8543#define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8544 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8545#define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8546 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 8547 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8548 8549enum fw_watchdog_actions { 8550 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 8551 FW_WATCHDOG_ACTION_FLR = 1, 8552 FW_WATCHDOG_ACTION_BYPASS = 2, 8553 FW_WATCHDOG_ACTION_TMPCHK = 3, 8554 FW_WATCHDOG_ACTION_PAUSEOFF = 4, 8555 8556 FW_WATCHDOG_ACTION_MAX = 5, 8557}; 8558 8559#define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 8560 8561struct fw_watchdog_cmd { 8562 __be32 op_to_vfn; 8563 __be32 retval_len16; 8564 __be32 timeout; 8565 __be32 action; 8566}; 8567 8568#define S_FW_WATCHDOG_CMD_PFN 8 8569#define M_FW_WATCHDOG_CMD_PFN 0x7 8570#define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 8571#define G_FW_WATCHDOG_CMD_PFN(x) \ 8572 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 8573 8574#define S_FW_WATCHDOG_CMD_VFN 0 8575#define M_FW_WATCHDOG_CMD_VFN 0xff 8576#define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 8577#define G_FW_WATCHDOG_CMD_VFN(x) \ 8578 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 8579 8580struct fw_clip_cmd { 8581 __be32 op_to_write; 8582 __be32 alloc_to_len16; 8583 __be64 ip_hi; 8584 __be64 ip_lo; 8585 __be32 r4[2]; 8586}; 8587 8588#define S_FW_CLIP_CMD_ALLOC 31 8589#define M_FW_CLIP_CMD_ALLOC 0x1 8590#define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 8591#define G_FW_CLIP_CMD_ALLOC(x) \ 8592 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 8593#define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 8594 8595#define S_FW_CLIP_CMD_FREE 30 8596#define M_FW_CLIP_CMD_FREE 0x1 8597#define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 8598#define G_FW_CLIP_CMD_FREE(x) \ 8599 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 8600#define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 8601 8602/****************************************************************************** 8603 * F O i S C S I C O M M A N D s 8604 **************************************/ 8605 8606#define FW_CHNET_IFACE_ADDR_MAX 3 8607 8608enum fw_chnet_iface_cmd_subop { 8609 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 8610 8611 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 8612 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 8613 8614 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 8615 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 8616 8617 FW_CHNET_IFACE_CMD_SUBOP_MAX, 8618}; 8619 8620struct fw_chnet_iface_cmd { 8621 __be32 op_to_portid; 8622 __be32 retval_len16; 8623 __u8 subop; 8624 __u8 r2[3]; 8625 __be32 ifid_ifstate; 8626 __be16 mtu; 8627 __be16 vlanid; 8628 __be32 r3; 8629 __be16 r4; 8630 __u8 mac[6]; 8631}; 8632 8633#define S_FW_CHNET_IFACE_CMD_PORTID 0 8634#define M_FW_CHNET_IFACE_CMD_PORTID 0xf 8635#define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 8636#define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 8637 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 8638 8639#define S_FW_CHNET_IFACE_CMD_IFID 8 8640#define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 8641#define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 8642#define G_FW_CHNET_IFACE_CMD_IFID(x) \ 8643 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 8644 8645#define S_FW_CHNET_IFACE_CMD_IFSTATE 0 8646#define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 8647#define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 8648#define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 8649 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 8650 8651struct fw_fcoe_res_info_cmd { 8652 __be32 op_to_read; 8653 __be32 retval_len16; 8654 __be16 e_d_tov; 8655 __be16 r_a_tov_seq; 8656 __be16 r_a_tov_els; 8657 __be16 r_r_tov; 8658 __be32 max_xchgs; 8659 __be32 max_ssns; 8660 __be32 used_xchgs; 8661 __be32 used_ssns; 8662 __be32 max_fcfs; 8663 __be32 max_vnps; 8664 __be32 used_fcfs; 8665 __be32 used_vnps; 8666}; 8667 8668struct fw_fcoe_link_cmd { 8669 __be32 op_to_portid; 8670 __be32 retval_len16; 8671 __be32 sub_opcode_fcfi; 8672 __u8 r3; 8673 __u8 lstatus; 8674 __be16 flags; 8675 __u8 r4; 8676 __u8 set_vlan; 8677 __be16 vlan_id; 8678 __be32 vnpi_pkd; 8679 __be16 r6; 8680 __u8 phy_mac[6]; 8681 __u8 vnport_wwnn[8]; 8682 __u8 vnport_wwpn[8]; 8683}; 8684 8685#define S_FW_FCOE_LINK_CMD_PORTID 0 8686#define M_FW_FCOE_LINK_CMD_PORTID 0xf 8687#define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 8688#define G_FW_FCOE_LINK_CMD_PORTID(x) \ 8689 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 8690 8691#define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 8692#define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 8693#define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 8694 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 8695#define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 8696 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 8697 8698#define S_FW_FCOE_LINK_CMD_FCFI 0 8699#define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 8700#define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 8701#define G_FW_FCOE_LINK_CMD_FCFI(x) \ 8702 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 8703 8704#define S_FW_FCOE_LINK_CMD_VNPI 0 8705#define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 8706#define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 8707#define G_FW_FCOE_LINK_CMD_VNPI(x) \ 8708 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 8709 8710struct fw_fcoe_vnp_cmd { 8711 __be32 op_to_fcfi; 8712 __be32 alloc_to_len16; 8713 __be32 gen_wwn_to_vnpi; 8714 __be32 vf_id; 8715 __be16 iqid; 8716 __u8 vnport_mac[6]; 8717 __u8 vnport_wwnn[8]; 8718 __u8 vnport_wwpn[8]; 8719 __u8 cmn_srv_parms[16]; 8720 __u8 clsp_word_0_1[8]; 8721}; 8722 8723#define S_FW_FCOE_VNP_CMD_FCFI 0 8724#define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 8725#define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 8726#define G_FW_FCOE_VNP_CMD_FCFI(x) \ 8727 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 8728 8729#define S_FW_FCOE_VNP_CMD_ALLOC 31 8730#define M_FW_FCOE_VNP_CMD_ALLOC 0x1 8731#define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 8732#define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 8733 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 8734#define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 8735 8736#define S_FW_FCOE_VNP_CMD_FREE 30 8737#define M_FW_FCOE_VNP_CMD_FREE 0x1 8738#define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 8739#define G_FW_FCOE_VNP_CMD_FREE(x) \ 8740 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 8741#define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 8742 8743#define S_FW_FCOE_VNP_CMD_MODIFY 29 8744#define M_FW_FCOE_VNP_CMD_MODIFY 0x1 8745#define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 8746#define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 8747 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 8748#define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 8749 8750#define S_FW_FCOE_VNP_CMD_GEN_WWN 22 8751#define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 8752#define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 8753#define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 8754 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 8755#define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 8756 8757#define S_FW_FCOE_VNP_CMD_PERSIST 21 8758#define M_FW_FCOE_VNP_CMD_PERSIST 0x1 8759#define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 8760#define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 8761 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 8762#define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 8763 8764#define S_FW_FCOE_VNP_CMD_VFID_EN 20 8765#define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 8766#define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 8767#define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 8768 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 8769#define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 8770 8771#define S_FW_FCOE_VNP_CMD_VNPI 0 8772#define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 8773#define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 8774#define G_FW_FCOE_VNP_CMD_VNPI(x) \ 8775 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 8776 8777struct fw_fcoe_sparams_cmd { 8778 __be32 op_to_portid; 8779 __be32 retval_len16; 8780 __u8 r3[7]; 8781 __u8 cos; 8782 __u8 lport_wwnn[8]; 8783 __u8 lport_wwpn[8]; 8784 __u8 cmn_srv_parms[16]; 8785 __u8 cls_srv_parms[16]; 8786}; 8787 8788#define S_FW_FCOE_SPARAMS_CMD_PORTID 0 8789#define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 8790#define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 8791#define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 8792 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 8793 8794struct fw_fcoe_stats_cmd { 8795 __be32 op_to_flowid; 8796 __be32 free_to_len16; 8797 union fw_fcoe_stats { 8798 struct fw_fcoe_stats_ctl { 8799 __u8 nstats_port; 8800 __u8 port_valid_ix; 8801 __be16 r6; 8802 __be32 r7; 8803 __be64 stat0; 8804 __be64 stat1; 8805 __be64 stat2; 8806 __be64 stat3; 8807 __be64 stat4; 8808 __be64 stat5; 8809 } ctl; 8810 struct fw_fcoe_port_stats { 8811 __be64 tx_bcast_bytes; 8812 __be64 tx_bcast_frames; 8813 __be64 tx_mcast_bytes; 8814 __be64 tx_mcast_frames; 8815 __be64 tx_ucast_bytes; 8816 __be64 tx_ucast_frames; 8817 __be64 tx_drop_frames; 8818 __be64 tx_offload_bytes; 8819 __be64 tx_offload_frames; 8820 __be64 rx_bcast_bytes; 8821 __be64 rx_bcast_frames; 8822 __be64 rx_mcast_bytes; 8823 __be64 rx_mcast_frames; 8824 __be64 rx_ucast_bytes; 8825 __be64 rx_ucast_frames; 8826 __be64 rx_err_frames; 8827 } port_stats; 8828 struct fw_fcoe_fcf_stats { 8829 __be32 fip_tx_bytes; 8830 __be32 fip_tx_fr; 8831 __be64 fcf_ka; 8832 __be64 mcast_adv_rcvd; 8833 __be16 ucast_adv_rcvd; 8834 __be16 sol_sent; 8835 __be16 vlan_req; 8836 __be16 vlan_rpl; 8837 __be16 clr_vlink; 8838 __be16 link_down; 8839 __be16 link_up; 8840 __be16 logo; 8841 __be16 flogi_req; 8842 __be16 flogi_rpl; 8843 __be16 fdisc_req; 8844 __be16 fdisc_rpl; 8845 __be16 fka_prd_chg; 8846 __be16 fc_map_chg; 8847 __be16 vfid_chg; 8848 __u8 no_fka_req; 8849 __u8 no_vnp; 8850 } fcf_stats; 8851 struct fw_fcoe_pcb_stats { 8852 __be64 tx_bytes; 8853 __be64 tx_frames; 8854 __be64 rx_bytes; 8855 __be64 rx_frames; 8856 __be32 vnp_ka; 8857 __be32 unsol_els_rcvd; 8858 __be64 unsol_cmd_rcvd; 8859 __be16 implicit_logo; 8860 __be16 flogi_inv_sparm; 8861 __be16 fdisc_inv_sparm; 8862 __be16 flogi_rjt; 8863 __be16 fdisc_rjt; 8864 __be16 no_ssn; 8865 __be16 mac_flt_fail; 8866 __be16 inv_fr_rcvd; 8867 } pcb_stats; 8868 struct fw_fcoe_scb_stats { 8869 __be64 tx_bytes; 8870 __be64 tx_frames; 8871 __be64 rx_bytes; 8872 __be64 rx_frames; 8873 __be32 host_abrt_req; 8874 __be32 adap_auto_abrt; 8875 __be32 adap_abrt_rsp; 8876 __be32 host_ios_req; 8877 __be16 ssn_offl_ios; 8878 __be16 ssn_not_rdy_ios; 8879 __u8 rx_data_ddp_err; 8880 __u8 ddp_flt_set_err; 8881 __be16 rx_data_fr_err; 8882 __u8 bad_st_abrt_req; 8883 __u8 no_io_abrt_req; 8884 __u8 abort_tmo; 8885 __u8 abort_tmo_2; 8886 __be32 abort_req; 8887 __u8 no_ppod_res_tmo; 8888 __u8 bp_tmo; 8889 __u8 adap_auto_cls; 8890 __u8 no_io_cls_req; 8891 __be32 host_cls_req; 8892 __be64 unsol_cmd_rcvd; 8893 __be32 plogi_req_rcvd; 8894 __be32 prli_req_rcvd; 8895 __be16 logo_req_rcvd; 8896 __be16 prlo_req_rcvd; 8897 __be16 plogi_rjt_rcvd; 8898 __be16 prli_rjt_rcvd; 8899 __be32 adisc_req_rcvd; 8900 __be32 rscn_rcvd; 8901 __be32 rrq_req_rcvd; 8902 __be32 unsol_els_rcvd; 8903 __u8 adisc_rjt_rcvd; 8904 __u8 scr_rjt; 8905 __u8 ct_rjt; 8906 __u8 inval_bls_rcvd; 8907 __be32 ba_rjt_rcvd; 8908 } scb_stats; 8909 } u; 8910}; 8911 8912#define S_FW_FCOE_STATS_CMD_FLOWID 0 8913#define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 8914#define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 8915#define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 8916 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 8917 8918#define S_FW_FCOE_STATS_CMD_FREE 30 8919#define M_FW_FCOE_STATS_CMD_FREE 0x1 8920#define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 8921#define G_FW_FCOE_STATS_CMD_FREE(x) \ 8922 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 8923#define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 8924 8925#define S_FW_FCOE_STATS_CMD_NSTATS 4 8926#define M_FW_FCOE_STATS_CMD_NSTATS 0x7 8927#define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 8928#define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 8929 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 8930 8931#define S_FW_FCOE_STATS_CMD_PORT 0 8932#define M_FW_FCOE_STATS_CMD_PORT 0x3 8933#define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 8934#define G_FW_FCOE_STATS_CMD_PORT(x) \ 8935 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 8936 8937#define S_FW_FCOE_STATS_CMD_PORT_VALID 7 8938#define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 8939#define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 8940 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 8941#define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 8942 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 8943#define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 8944 8945#define S_FW_FCOE_STATS_CMD_IX 0 8946#define M_FW_FCOE_STATS_CMD_IX 0x3f 8947#define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 8948#define G_FW_FCOE_STATS_CMD_IX(x) \ 8949 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 8950 8951struct fw_fcoe_fcf_cmd { 8952 __be32 op_to_fcfi; 8953 __be32 retval_len16; 8954 __be16 priority_pkd; 8955 __u8 mac[6]; 8956 __u8 name_id[8]; 8957 __u8 fabric[8]; 8958 __be16 vf_id; 8959 __be16 max_fcoe_size; 8960 __u8 vlan_id; 8961 __u8 fc_map[3]; 8962 __be32 fka_adv; 8963 __be32 r6; 8964 __u8 r7_hi; 8965 __u8 fpma_to_portid; 8966 __u8 spma_mac[6]; 8967 __be64 r8; 8968}; 8969 8970#define S_FW_FCOE_FCF_CMD_FCFI 0 8971#define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 8972#define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 8973#define G_FW_FCOE_FCF_CMD_FCFI(x) \ 8974 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 8975 8976#define S_FW_FCOE_FCF_CMD_PRIORITY 0 8977#define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 8978#define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 8979#define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 8980 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 8981 8982#define S_FW_FCOE_FCF_CMD_FPMA 6 8983#define M_FW_FCOE_FCF_CMD_FPMA 0x1 8984#define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 8985#define G_FW_FCOE_FCF_CMD_FPMA(x) \ 8986 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 8987#define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 8988 8989#define S_FW_FCOE_FCF_CMD_SPMA 5 8990#define M_FW_FCOE_FCF_CMD_SPMA 0x1 8991#define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 8992#define G_FW_FCOE_FCF_CMD_SPMA(x) \ 8993 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 8994#define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 8995 8996#define S_FW_FCOE_FCF_CMD_LOGIN 4 8997#define M_FW_FCOE_FCF_CMD_LOGIN 0x1 8998#define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 8999#define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 9000 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 9001#define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 9002 9003#define S_FW_FCOE_FCF_CMD_PORTID 0 9004#define M_FW_FCOE_FCF_CMD_PORTID 0xf 9005#define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 9006#define G_FW_FCOE_FCF_CMD_PORTID(x) \ 9007 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 9008 9009/****************************************************************************** 9010 * E R R O R a n d D E B U G C O M M A N D s 9011 ******************************************************/ 9012 9013enum fw_error_type { 9014 FW_ERROR_TYPE_EXCEPTION = 0x0, 9015 FW_ERROR_TYPE_HWMODULE = 0x1, 9016 FW_ERROR_TYPE_WR = 0x2, 9017 FW_ERROR_TYPE_ACL = 0x3, 9018}; 9019 9020enum fw_dcb_ieee_locations { 9021 FW_IEEE_LOC_LOCAL, 9022 FW_IEEE_LOC_PEER, 9023 FW_IEEE_LOC_OPERATIONAL, 9024}; 9025 9026struct fw_dcb_ieee_cmd { 9027 __be32 op_to_location; 9028 __be32 changed_to_len16; 9029 union fw_dcbx_stats { 9030 struct fw_dcbx_pfc_stats_ieee { 9031 __be32 pfc_mbc_pkd; 9032 __be32 pfc_willing_to_pfc_en; 9033 } dcbx_pfc_stats; 9034 struct fw_dcbx_ets_stats_ieee { 9035 __be32 cbs_to_ets_max_tc; 9036 __be32 pg_table; 9037 __u8 pg_percent[8]; 9038 __u8 tsa[8]; 9039 } dcbx_ets_stats; 9040 struct fw_dcbx_app_stats_ieee { 9041 __be32 num_apps_pkd; 9042 __be32 r6; 9043 __be32 app[4]; 9044 } dcbx_app_stats; 9045 struct fw_dcbx_control { 9046 __be32 multi_peer_invalidated; 9047 __u8 version; 9048 __u8 r6[3]; 9049 } dcbx_control; 9050 } u; 9051}; 9052 9053#define S_FW_DCB_IEEE_CMD_PORT 8 9054#define M_FW_DCB_IEEE_CMD_PORT 0x7 9055#define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT) 9056#define G_FW_DCB_IEEE_CMD_PORT(x) \ 9057 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT) 9058 9059#define S_FW_DCB_IEEE_CMD_FEATURE 2 9060#define M_FW_DCB_IEEE_CMD_FEATURE 0x7 9061#define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE) 9062#define G_FW_DCB_IEEE_CMD_FEATURE(x) \ 9063 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE) 9064 9065#define S_FW_DCB_IEEE_CMD_LOCATION 0 9066#define M_FW_DCB_IEEE_CMD_LOCATION 0x3 9067#define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION) 9068#define G_FW_DCB_IEEE_CMD_LOCATION(x) \ 9069 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION) 9070 9071#define S_FW_DCB_IEEE_CMD_CHANGED 20 9072#define M_FW_DCB_IEEE_CMD_CHANGED 0x1 9073#define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED) 9074#define G_FW_DCB_IEEE_CMD_CHANGED(x) \ 9075 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED) 9076#define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U) 9077 9078#define S_FW_DCB_IEEE_CMD_RECEIVED 19 9079#define M_FW_DCB_IEEE_CMD_RECEIVED 0x1 9080#define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED) 9081#define G_FW_DCB_IEEE_CMD_RECEIVED(x) \ 9082 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED) 9083#define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U) 9084 9085#define S_FW_DCB_IEEE_CMD_APPLY 18 9086#define M_FW_DCB_IEEE_CMD_APPLY 0x1 9087#define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY) 9088#define G_FW_DCB_IEEE_CMD_APPLY(x) \ 9089 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY) 9090#define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U) 9091 9092#define S_FW_DCB_IEEE_CMD_DISABLED 17 9093#define M_FW_DCB_IEEE_CMD_DISABLED 0x1 9094#define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED) 9095#define G_FW_DCB_IEEE_CMD_DISABLED(x) \ 9096 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED) 9097#define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U) 9098 9099#define S_FW_DCB_IEEE_CMD_MORE 16 9100#define M_FW_DCB_IEEE_CMD_MORE 0x1 9101#define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE) 9102#define G_FW_DCB_IEEE_CMD_MORE(x) \ 9103 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE) 9104#define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U) 9105 9106#define S_FW_DCB_IEEE_CMD_PFC_MBC 0 9107#define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1 9108#define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC) 9109#define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \ 9110 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC) 9111#define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U) 9112 9113#define S_FW_DCB_IEEE_CMD_PFC_WILLING 16 9114#define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1 9115#define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 9116 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING) 9117#define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 9118 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING) 9119#define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U) 9120 9121#define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8 9122#define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff 9123#define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC) 9124#define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \ 9125 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC) 9126 9127#define S_FW_DCB_IEEE_CMD_PFC_EN 0 9128#define M_FW_DCB_IEEE_CMD_PFC_EN 0xff 9129#define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN) 9130#define G_FW_DCB_IEEE_CMD_PFC_EN(x) \ 9131 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN) 9132 9133#define S_FW_DCB_IEEE_CMD_CBS 16 9134#define M_FW_DCB_IEEE_CMD_CBS 0x1 9135#define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS) 9136#define G_FW_DCB_IEEE_CMD_CBS(x) \ 9137 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS) 9138#define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U) 9139 9140#define S_FW_DCB_IEEE_CMD_ETS_WILLING 8 9141#define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1 9142#define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 9143 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING) 9144#define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 9145 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING) 9146#define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U) 9147 9148#define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0 9149#define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff 9150#define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC) 9151#define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \ 9152 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC) 9153 9154#define S_FW_DCB_IEEE_CMD_NUM_APPS 0 9155#define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7 9156#define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS) 9157#define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \ 9158 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS) 9159 9160#define S_FW_DCB_IEEE_CMD_MULTI_PEER 31 9161#define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1 9162#define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER) 9163#define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \ 9164 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER) 9165#define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U) 9166 9167#define S_FW_DCB_IEEE_CMD_INVALIDATED 30 9168#define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1 9169#define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9170 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED) 9171#define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 9172 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED) 9173#define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U) 9174 9175/* Hand-written */ 9176#define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16 9177#define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff 9178#define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9179#define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \ 9180 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL) 9181 9182#define S_FW_DCB_IEEE_CMD_APP_SELECT 3 9183#define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7 9184#define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT) 9185#define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \ 9186 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT) 9187 9188#define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0 9189#define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7 9190#define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY) 9191#define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \ 9192 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY) 9193 9194 9195struct fw_error_cmd { 9196 __be32 op_to_type; 9197 __be32 len16_pkd; 9198 union fw_error { 9199 struct fw_error_exception { 9200 __be32 info[6]; 9201 } exception; 9202 struct fw_error_hwmodule { 9203 __be32 regaddr; 9204 __be32 regval; 9205 } hwmodule; 9206 struct fw_error_wr { 9207 __be16 cidx; 9208 __be16 pfn_vfn; 9209 __be32 eqid; 9210 __u8 wrhdr[16]; 9211 } wr; 9212 struct fw_error_acl { 9213 __be16 cidx; 9214 __be16 pfn_vfn; 9215 __be32 eqid; 9216 __be16 mv_pkd; 9217 __u8 val[6]; 9218 __be64 r4; 9219 } acl; 9220 } u; 9221}; 9222 9223#define S_FW_ERROR_CMD_FATAL 4 9224#define M_FW_ERROR_CMD_FATAL 0x1 9225#define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 9226#define G_FW_ERROR_CMD_FATAL(x) \ 9227 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 9228#define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 9229 9230#define S_FW_ERROR_CMD_TYPE 0 9231#define M_FW_ERROR_CMD_TYPE 0xf 9232#define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 9233#define G_FW_ERROR_CMD_TYPE(x) \ 9234 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 9235 9236#define S_FW_ERROR_CMD_PFN 8 9237#define M_FW_ERROR_CMD_PFN 0x7 9238#define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9239#define G_FW_ERROR_CMD_PFN(x) \ 9240 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9241 9242#define S_FW_ERROR_CMD_VFN 0 9243#define M_FW_ERROR_CMD_VFN 0xff 9244#define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9245#define G_FW_ERROR_CMD_VFN(x) \ 9246 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9247 9248#define S_FW_ERROR_CMD_PFN 8 9249#define M_FW_ERROR_CMD_PFN 0x7 9250#define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 9251#define G_FW_ERROR_CMD_PFN(x) \ 9252 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 9253 9254#define S_FW_ERROR_CMD_VFN 0 9255#define M_FW_ERROR_CMD_VFN 0xff 9256#define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 9257#define G_FW_ERROR_CMD_VFN(x) \ 9258 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 9259 9260#define S_FW_ERROR_CMD_MV 15 9261#define M_FW_ERROR_CMD_MV 0x1 9262#define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 9263#define G_FW_ERROR_CMD_MV(x) \ 9264 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 9265#define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 9266 9267struct fw_debug_cmd { 9268 __be32 op_type; 9269 __be32 len16_pkd; 9270 union fw_debug { 9271 struct fw_debug_assert { 9272 __be32 fcid; 9273 __be32 line; 9274 __be32 x; 9275 __be32 y; 9276 __u8 filename_0_7[8]; 9277 __u8 filename_8_15[8]; 9278 __be64 r3; 9279 } assert; 9280 struct fw_debug_prt { 9281 __be16 dprtstridx; 9282 __be16 r3[3]; 9283 __be32 dprtstrparam0; 9284 __be32 dprtstrparam1; 9285 __be32 dprtstrparam2; 9286 __be32 dprtstrparam3; 9287 } prt; 9288 } u; 9289}; 9290 9291#define S_FW_DEBUG_CMD_TYPE 0 9292#define M_FW_DEBUG_CMD_TYPE 0xff 9293#define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 9294#define G_FW_DEBUG_CMD_TYPE(x) \ 9295 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 9296 9297enum fw_diag_cmd_type { 9298 FW_DIAG_CMD_TYPE_OFLDIAG = 0, 9299}; 9300 9301enum fw_diag_cmd_ofldiag_op { 9302 FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0, 9303 FW_DIAG_CMD_OFLDIAG_TEST_START, 9304 FW_DIAG_CMD_OFLDIAG_TEST_STOP, 9305 FW_DIAG_CMD_OFLDIAG_TEST_STATUS, 9306}; 9307 9308enum fw_diag_cmd_ofldiag_status { 9309 FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0, 9310 FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING, 9311 FW_DIAG_CMD_OFLDIAG_STATUS_FAILED, 9312 FW_DIAG_CMD_OFLDIAG_STATUS_PASSED, 9313}; 9314 9315struct fw_diag_cmd { 9316 __be32 op_type; 9317 __be32 len16_pkd; 9318 union fw_diag_test { 9319 struct fw_diag_test_ofldiag { 9320 __u8 test_op; 9321 __u8 r3; 9322 __be16 test_status; 9323 __be32 duration; 9324 } ofldiag; 9325 } u; 9326}; 9327 9328#define S_FW_DIAG_CMD_TYPE 0 9329#define M_FW_DIAG_CMD_TYPE 0xff 9330#define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE) 9331#define G_FW_DIAG_CMD_TYPE(x) \ 9332 (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE) 9333 9334struct fw_hma_cmd { 9335 __be32 op_pkd; 9336 __be32 retval_len16; 9337 __be32 mode_to_pcie_params; 9338 __be32 naddr_size; 9339 __be32 addr_size_pkd; 9340 __be32 r6; 9341 __be64 phy_address[5]; 9342}; 9343 9344#define S_FW_HMA_CMD_MODE 31 9345#define M_FW_HMA_CMD_MODE 0x1 9346#define V_FW_HMA_CMD_MODE(x) ((x) << S_FW_HMA_CMD_MODE) 9347#define G_FW_HMA_CMD_MODE(x) \ 9348 (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE) 9349#define F_FW_HMA_CMD_MODE V_FW_HMA_CMD_MODE(1U) 9350 9351#define S_FW_HMA_CMD_SOC 30 9352#define M_FW_HMA_CMD_SOC 0x1 9353#define V_FW_HMA_CMD_SOC(x) ((x) << S_FW_HMA_CMD_SOC) 9354#define G_FW_HMA_CMD_SOC(x) (((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC) 9355#define F_FW_HMA_CMD_SOC V_FW_HMA_CMD_SOC(1U) 9356 9357#define S_FW_HMA_CMD_EOC 29 9358#define M_FW_HMA_CMD_EOC 0x1 9359#define V_FW_HMA_CMD_EOC(x) ((x) << S_FW_HMA_CMD_EOC) 9360#define G_FW_HMA_CMD_EOC(x) (((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC) 9361#define F_FW_HMA_CMD_EOC V_FW_HMA_CMD_EOC(1U) 9362 9363#define S_FW_HMA_CMD_PCIE_PARAMS 0 9364#define M_FW_HMA_CMD_PCIE_PARAMS 0x7ffffff 9365#define V_FW_HMA_CMD_PCIE_PARAMS(x) ((x) << S_FW_HMA_CMD_PCIE_PARAMS) 9366#define G_FW_HMA_CMD_PCIE_PARAMS(x) \ 9367 (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS) 9368 9369#define S_FW_HMA_CMD_NADDR 12 9370#define M_FW_HMA_CMD_NADDR 0x3f 9371#define V_FW_HMA_CMD_NADDR(x) ((x) << S_FW_HMA_CMD_NADDR) 9372#define G_FW_HMA_CMD_NADDR(x) \ 9373 (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR) 9374 9375#define S_FW_HMA_CMD_SIZE 0 9376#define M_FW_HMA_CMD_SIZE 0xfff 9377#define V_FW_HMA_CMD_SIZE(x) ((x) << S_FW_HMA_CMD_SIZE) 9378#define G_FW_HMA_CMD_SIZE(x) \ 9379 (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE) 9380 9381#define S_FW_HMA_CMD_ADDR_SIZE 11 9382#define M_FW_HMA_CMD_ADDR_SIZE 0x1fffff 9383#define V_FW_HMA_CMD_ADDR_SIZE(x) ((x) << S_FW_HMA_CMD_ADDR_SIZE) 9384#define G_FW_HMA_CMD_ADDR_SIZE(x) \ 9385 (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE) 9386 9387/****************************************************************************** 9388 * P C I E F W R E G I S T E R 9389 **************************************/ 9390 9391enum pcie_fw_eval { 9392 PCIE_FW_EVAL_CRASH = 0, 9393 PCIE_FW_EVAL_PREP = 1, 9394 PCIE_FW_EVAL_CONF = 2, 9395 PCIE_FW_EVAL_INIT = 3, 9396 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 9397 PCIE_FW_EVAL_OVERHEAT = 5, 9398 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 9399}; 9400 9401/** 9402 * Register definitions for the PCIE_FW register which the firmware uses 9403 * to retain status across RESETs. This register should be considered 9404 * as a READ-ONLY register for Host Software and only to be used to 9405 * track firmware initialization/error state, etc. 9406 */ 9407#define S_PCIE_FW_ERR 31 9408#define M_PCIE_FW_ERR 0x1 9409#define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 9410#define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 9411#define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 9412 9413#define S_PCIE_FW_INIT 30 9414#define M_PCIE_FW_INIT 0x1 9415#define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 9416#define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 9417#define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 9418 9419#define S_PCIE_FW_HALT 29 9420#define M_PCIE_FW_HALT 0x1 9421#define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 9422#define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 9423#define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 9424 9425#define S_PCIE_FW_EVAL 24 9426#define M_PCIE_FW_EVAL 0x7 9427#define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 9428#define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 9429 9430#define S_PCIE_FW_STAGE 21 9431#define M_PCIE_FW_STAGE 0x7 9432#define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 9433#define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 9434 9435#define S_PCIE_FW_ASYNCNOT_VLD 20 9436#define M_PCIE_FW_ASYNCNOT_VLD 0x1 9437#define V_PCIE_FW_ASYNCNOT_VLD(x) \ 9438 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 9439#define G_PCIE_FW_ASYNCNOT_VLD(x) \ 9440 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 9441#define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 9442 9443#define S_PCIE_FW_ASYNCNOTINT 19 9444#define M_PCIE_FW_ASYNCNOTINT 0x1 9445#define V_PCIE_FW_ASYNCNOTINT(x) \ 9446 ((x) << S_PCIE_FW_ASYNCNOTINT) 9447#define G_PCIE_FW_ASYNCNOTINT(x) \ 9448 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 9449#define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 9450 9451#define S_PCIE_FW_ASYNCNOT 16 9452#define M_PCIE_FW_ASYNCNOT 0x7 9453#define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 9454#define G_PCIE_FW_ASYNCNOT(x) \ 9455 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 9456 9457#define S_PCIE_FW_MASTER_VLD 15 9458#define M_PCIE_FW_MASTER_VLD 0x1 9459#define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 9460#define G_PCIE_FW_MASTER_VLD(x) \ 9461 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 9462#define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 9463 9464#define S_PCIE_FW_MASTER 12 9465#define M_PCIE_FW_MASTER 0x7 9466#define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 9467#define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 9468 9469#define S_PCIE_FW_RESET_VLD 11 9470#define M_PCIE_FW_RESET_VLD 0x1 9471#define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 9472#define G_PCIE_FW_RESET_VLD(x) \ 9473 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 9474#define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 9475 9476#define S_PCIE_FW_RESET 8 9477#define M_PCIE_FW_RESET 0x7 9478#define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 9479#define G_PCIE_FW_RESET(x) \ 9480 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 9481 9482#define S_PCIE_FW_REGISTERED 0 9483#define M_PCIE_FW_REGISTERED 0xff 9484#define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 9485#define G_PCIE_FW_REGISTERED(x) \ 9486 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 9487 9488 9489/****************************************************************************** 9490 * P C I E F W P F 0 R E G I S T E R 9491 **********************************************/ 9492 9493/* 9494 * this register is available as 32-bit of persistent storage (across 9495 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 9496 * will not write it) 9497 */ 9498 9499 9500/****************************************************************************** 9501 * P C I E F W P F 7 R E G I S T E R 9502 **********************************************/ 9503 9504/* 9505 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to 9506 * access the "devlog" which needing to contact firmware. The encoding is 9507 * mostly the same as that returned by the DEVLOG command except for the size 9508 * which is encoded as the number of entries in multiples-1 of 128 here rather 9509 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 9510 * and 15 means 2048. This of course in turn constrains the allowed values 9511 * for the devlog size ... 9512 */ 9513#define PCIE_FW_PF_DEVLOG 7 9514 9515#define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 9516#define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf 9517#define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9518 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) 9519#define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9520 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ 9521 M_PCIE_FW_PF_DEVLOG_NENTRIES128) 9522 9523#define S_PCIE_FW_PF_DEVLOG_ADDR16 4 9524#define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff 9525#define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) 9526#define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ 9527 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) 9528 9529#define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 9530#define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf 9531#define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) 9532#define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ 9533 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) 9534 9535 9536/****************************************************************************** 9537 * B I N A R Y H E A D E R F O R M A T 9538 **********************************************/ 9539 9540/* 9541 * firmware binary header format 9542 */ 9543struct fw_hdr { 9544 __u8 ver; 9545 __u8 chip; /* terminator chip family */ 9546 __be16 len512; /* bin length in units of 512-bytes */ 9547 __be32 fw_ver; /* firmware version */ 9548 __be32 tp_microcode_ver; /* tcp processor microcode version */ 9549 __u8 intfver_nic; 9550 __u8 intfver_vnic; 9551 __u8 intfver_ofld; 9552 __u8 intfver_ri; 9553 __u8 intfver_iscsipdu; 9554 __u8 intfver_iscsi; 9555 __u8 intfver_fcoepdu; 9556 __u8 intfver_fcoe; 9557 __u32 reserved2; 9558 __u32 reserved3; 9559 __be32 magic; /* runtime or bootstrap fw */ 9560 __be32 flags; 9561 __be32 reserved6[23]; 9562}; 9563 9564enum fw_hdr_chip { 9565 FW_HDR_CHIP_T4, 9566 FW_HDR_CHIP_T5, 9567 FW_HDR_CHIP_T6 9568}; 9569 9570#define S_FW_HDR_FW_VER_MAJOR 24 9571#define M_FW_HDR_FW_VER_MAJOR 0xff 9572#define V_FW_HDR_FW_VER_MAJOR(x) \ 9573 ((x) << S_FW_HDR_FW_VER_MAJOR) 9574#define G_FW_HDR_FW_VER_MAJOR(x) \ 9575 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 9576 9577#define S_FW_HDR_FW_VER_MINOR 16 9578#define M_FW_HDR_FW_VER_MINOR 0xff 9579#define V_FW_HDR_FW_VER_MINOR(x) \ 9580 ((x) << S_FW_HDR_FW_VER_MINOR) 9581#define G_FW_HDR_FW_VER_MINOR(x) \ 9582 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 9583 9584#define S_FW_HDR_FW_VER_MICRO 8 9585#define M_FW_HDR_FW_VER_MICRO 0xff 9586#define V_FW_HDR_FW_VER_MICRO(x) \ 9587 ((x) << S_FW_HDR_FW_VER_MICRO) 9588#define G_FW_HDR_FW_VER_MICRO(x) \ 9589 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 9590 9591#define S_FW_HDR_FW_VER_BUILD 0 9592#define M_FW_HDR_FW_VER_BUILD 0xff 9593#define V_FW_HDR_FW_VER_BUILD(x) \ 9594 ((x) << S_FW_HDR_FW_VER_BUILD) 9595#define G_FW_HDR_FW_VER_BUILD(x) \ 9596 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 9597 9598enum { 9599 T4FW_VERSION_MAJOR = 0x01, 9600 T4FW_VERSION_MINOR = 0x10, 9601 T4FW_VERSION_MICRO = 0x3f, 9602 T4FW_VERSION_BUILD = 0x00, 9603 9604 T5FW_VERSION_MAJOR = 0x01, 9605 T5FW_VERSION_MINOR = 0x10, 9606 T5FW_VERSION_MICRO = 0x3f, 9607 T5FW_VERSION_BUILD = 0x00, 9608 9609 T6FW_VERSION_MAJOR = 0x01, 9610 T6FW_VERSION_MINOR = 0x10, 9611 T6FW_VERSION_MICRO = 0x3f, 9612 T6FW_VERSION_BUILD = 0x00, 9613}; 9614 9615enum { 9616 /* T4 9617 */ 9618 T4FW_HDR_INTFVER_NIC = 0x00, 9619 T4FW_HDR_INTFVER_VNIC = 0x00, 9620 T4FW_HDR_INTFVER_OFLD = 0x00, 9621 T4FW_HDR_INTFVER_RI = 0x00, 9622 T4FW_HDR_INTFVER_ISCSIPDU= 0x00, 9623 T4FW_HDR_INTFVER_ISCSI = 0x00, 9624 T4FW_HDR_INTFVER_FCOEPDU = 0x00, 9625 T4FW_HDR_INTFVER_FCOE = 0x00, 9626 9627 /* T5 9628 */ 9629 T5FW_HDR_INTFVER_NIC = 0x00, 9630 T5FW_HDR_INTFVER_VNIC = 0x00, 9631 T5FW_HDR_INTFVER_OFLD = 0x00, 9632 T5FW_HDR_INTFVER_RI = 0x00, 9633 T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 9634 T5FW_HDR_INTFVER_ISCSI = 0x00, 9635 T5FW_HDR_INTFVER_FCOEPDU= 0x00, 9636 T5FW_HDR_INTFVER_FCOE = 0x00, 9637 9638 /* T6 9639 */ 9640 T6FW_HDR_INTFVER_NIC = 0x00, 9641 T6FW_HDR_INTFVER_VNIC = 0x00, 9642 T6FW_HDR_INTFVER_OFLD = 0x00, 9643 T6FW_HDR_INTFVER_RI = 0x00, 9644 T6FW_HDR_INTFVER_ISCSIPDU= 0x00, 9645 T6FW_HDR_INTFVER_ISCSI = 0x00, 9646 T6FW_HDR_INTFVER_FCOEPDU= 0x00, 9647 T6FW_HDR_INTFVER_FCOE = 0x00, 9648}; 9649 9650enum { 9651 FW_HDR_MAGIC_RUNTIME = 0x00000000, 9652 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 9653}; 9654 9655enum fw_hdr_flags { 9656 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 9657}; 9658 9659/* 9660 * External PHY firmware binary header format 9661 */ 9662struct fw_ephy_hdr { 9663 __u8 ver; 9664 __u8 reserved; 9665 __be16 len512; /* bin length in units of 512-bytes */ 9666 __be32 magic; 9667 9668 __be16 vendor_id; 9669 __be16 device_id; 9670 __be32 version; 9671 9672 __be32 reserved1[4]; 9673}; 9674 9675enum { 9676 FW_EPHY_HDR_MAGIC = 0x65706879, 9677}; 9678 9679struct fw_ifconf_dhcp_info { 9680 __be32 addr; 9681 __be32 mask; 9682 __be16 vlanid; 9683 __be16 mtu; 9684 __be32 gw; 9685 __u8 op; 9686 __u8 len; 9687 __u8 data[270]; 9688}; 9689 9690#endif /* _T4FW_INTERFACE_H_ */ 9691