1228561Snp# Chelsio T4 Factory Default configuration file. 2228561Snp# 3319269Snp# Copyright (C) 2010-2017 Chelsio Communications. All rights reserved. 4228561Snp# 5237436Snp# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF 6237436Snp# THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT 7237436Snp# IN PHYSICAL DAMAGE TO T4 ADAPTERS. 8228561Snp 9228561Snp# This file provides the default, power-on configuration for 4-port T4-based 10228561Snp# adapters shipped from the factory. These defaults are designed to address 11228561Snp# the needs of the vast majority of T4 customers. The basic idea is to have 12228561Snp# a default configuration which allows a customer to plug a T4 adapter in and 13228561Snp# have it work regardless of OS, driver or application except in the most 14228561Snp# unusual and/or demanding customer applications. 15228561Snp# 16228561Snp# Many of the T4 resources which are described by this configuration are 17228561Snp# finite. This requires balancing the configuration/operation needs of 18228561Snp# device drivers across OSes and a large number of customer application. 19228561Snp# 20298976Spfg# Some of the more important resources to allocate and their constaints are: 21228561Snp# 1. Virtual Interfaces: 128. 22228561Snp# 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions 23228561Snp# must use a power of 2 Ingress Queues. 24228561Snp# 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a 25228561Snp# power of 2 Egress Queues. 26228561Snp# 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV 27228561Snp# Virtual Functions based off of a Physical Function all get the 28228561Snp# same umber of MSI-X Vectors as the base Physical Function. 29228561Snp# Additionally, regardless of whether Virtual Functions are enabled or 30228561Snp# not, their MSI-X "needs" are counted by the PCI-E implementation. 31228561Snp# And finally, all Physical Funcations capable of supporting Virtual 32228561Snp# Functions (PF0-3) must have the same number of configured TotalVFs in 33228561Snp# their SR-IOV Capabilities. 34228561Snp# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 35228561Snp# address matching on Ingress Packets. 36228561Snp# 37228561Snp# Some of the important OS/Driver resource needs are: 38228561Snp# 6. Some OS Drivers will manage all resources through a single Physical 39228561Snp# Function (currently PF0 but it could be any Physical Function). Thus, 40228561Snp# this "Unified PF" will need to have enough resources allocated to it 41228561Snp# to allow for this. And because of the MSI-X resource allocation 42228561Snp# constraints mentioned above, this probably means we'll either have to 43228561Snp# severely limit the TotalVFs if we continue to use PF0 as the Unified PF 44228561Snp# or we'll need to move the Unified PF into the PF4-7 range since those 45228561Snp# Physical Functions don't have any Virtual Functions associated with 46228561Snp# them. 47228561Snp# 7. Some OS Drivers will manage different ports and functions (NIC, 48228561Snp# storage, etc.) on different Physical Functions. For example, NIC 49228561Snp# functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc. 50228561Snp# 51228561Snp# Some of the customer application needs which need to be accommodated: 52228561Snp# 8. Some customers will want to support large CPU count systems with 53228561Snp# good scaling. Thus, we'll need to accommodate a number of 54228561Snp# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 55228561Snp# to be involved per port and per application function. For example, 56228561Snp# in the case where all ports and application functions will be 57228561Snp# managed via a single Unified PF and we want to accommodate scaling up 58228561Snp# to 8 CPUs, we would want: 59228561Snp# 60228561Snp# 4 ports * 61228561Snp# 3 application functions (NIC, FCoE, iSCSI) per port * 62228561Snp# 8 Ingress Queue/MSI-X Vectors per application function 63228561Snp# 64228561Snp# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 65228561Snp# (Plus a few for Firmware Event Queues, etc.) 66228561Snp# 67228561Snp# 9. Some customers will want to use T4's PCI-E SR-IOV Capability to allow 68228561Snp# Virtual Machines to directly access T4 functionality via SR-IOV 69228561Snp# Virtual Functions and "PCI Device Passthrough" -- this is especially 70228561Snp# true for the NIC application functionality. (Note that there is 71228561Snp# currently no ability to use the TOE, FCoE, iSCSI, etc. via Virtual 72228561Snp# Functions so this is in fact solely limited to NIC.) 73228561Snp# 74228561Snp 75228561Snp 76228561Snp# Global configuration settings. 77228561Snp# 78228561Snp[global] 79228561Snp rss_glb_config_mode = basicvirtual 80228561Snp rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 81228561Snp 82228561Snp # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 83228561Snp # Page Size and a 64B L1 Cache Line Size. It programs the 84228561Snp # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 85228561Snp # If a Master PF Driver finds itself on a machine with different 86228561Snp # parameters, then the Master PF Driver is responsible for initializing 87228561Snp # these parameters to appropriate values. 88228561Snp # 89228561Snp # Notes: 90228561Snp # 1. The Free List Buffer Sizes below are raw and the firmware will 91228561Snp # round them up to the Ingress Padding Boundary. 92228561Snp # 2. The SGE Timer Values below are expressed below in microseconds. 93228561Snp # The firmware will convert these values to Core Clock Ticks when 94228561Snp # it processes the configuration parameters. 95228561Snp # 96228561Snp reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL 97228561Snp reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 98228561Snp reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 99228561Snp reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 100228561Snp reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 101228561Snp reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 102228561Snp reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 103228561Snp reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 104228561Snp reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 105228561Snp reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 106228561Snp reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 107228561Snp reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 108228561Snp reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS 109228561Snp reg[0x10a8] = 0x2000/0x2000 # SGE_DOORBELL_CONTROL 110228561Snp sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 111228561Snp 112256459Snp # enable TP_OUT_CONFIG.IPIDSPLITMODE 113256459Snp reg[0x7d04] = 0x00010000/0x00010000 114256459Snp 115296249Snp # disable TP_PARA_REG3.RxFragEn 116296249Snp reg[0x7d6c] = 0x00000000/0x00007000 117296249Snp 118285527Snp reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 119228561Snp 120256459Snp # TP_VLAN_PRI_MAP to select filter tuples 121256459Snp # filter tuples : fragmentation, mpshittype, macmatch, ethertype, 122256459Snp # protocol, tos, vlan, vnic_id, port, fcoe 123256459Snp # valid filterModes are described the Terminator 4 Data Book 124237436Snp filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe 125228561Snp 126256459Snp # filter tuples enforced in LE active region (equal to or subset of filterMode) 127256459Snp filterMask = protocol, fcoe 128256459Snp 129228561Snp # Percentage of dynamic memory (in either the EDRAM or external MEM) 130228561Snp # to use for TP RX payload 131285527Snp tp_pmrx = 34 132228561Snp 133228561Snp # TP RX payload page size 134228561Snp tp_pmrx_pagesize = 64K 135228561Snp 136252661Snp # TP number of RX channels 137252661Snp tp_nrxch = 0 # 0 (auto) = 1 138252661Snp 139228561Snp # Percentage of dynamic memory (in either the EDRAM or external MEM) 140228561Snp # to use for TP TX payload 141285527Snp tp_pmtx = 32 142228561Snp 143228561Snp # TP TX payload page size 144228561Snp tp_pmtx_pagesize = 64K 145228561Snp 146252661Snp # TP number of TX channels 147252661Snp tp_ntxch = 0 # 0 (auto) = equal number of ports 148252661Snp 149256459Snp # TP OFLD MTUs 150256459Snp tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 151256459Snp 152285527Snp # ULPRX iSCSI Page Sizes 153285527Snp reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K 154285527Snp 155228561Snp# Some "definitions" to make the rest of this a bit more readable. We support 156228561Snp# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 157228561Snp# per function per port ... 158228561Snp# 159228561Snp# NMSIX = 1088 # available MSI-X Vectors 160228561Snp# NVI = 128 # available Virtual Interfaces 161228561Snp# NMPSTCAM = 336 # MPS TCAM entries 162228561Snp# 163228561Snp# NPORTS = 4 # ports 164228561Snp# NCPUS = 8 # CPUs we want to support scalably 165228561Snp# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 166228561Snp 167228561Snp# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 168228561Snp# PF" which many OS Drivers will use to manage most or all functions. 169228561Snp# 170228561Snp# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 171228561Snp# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 172228561Snp# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 173228561Snp# will be specified as the "Ingress Queue Asynchronous Destination Index." 174228561Snp# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 175228561Snp# than or equal to the number of Ingress Queues ... 176228561Snp# 177228561Snp# NVI_NIC = 4 # NIC access to NPORTS 178228561Snp# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 179228561Snp# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 180228561Snp# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 181228561Snp# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 182228561Snp# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 183228561Snp# 184228561Snp# NVI_OFLD = 0 # Offload uses NIC function to access ports 185228561Snp# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 186228561Snp# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 187228561Snp# NEQ_OFLD = 16 # Offload Egress Queues (FL) 188228561Snp# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 189228561Snp# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 190228561Snp# 191228561Snp# NVI_RDMA = 0 # RDMA uses NIC function to access ports 192228561Snp# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 193228561Snp# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 194228561Snp# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 195228561Snp# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 196228561Snp# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 197228561Snp# 198228561Snp# NEQ_WD = 128 # Wire Direct TX Queues and FLs 199228561Snp# NETHCTRL_WD = 64 # Wire Direct TX Queues 200228561Snp# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 201228561Snp# 202228561Snp# NVI_ISCSI = 4 # ISCSI access to NPORTS 203228561Snp# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 204228561Snp# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 205228561Snp# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 206228561Snp# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 207228561Snp# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 208228561Snp# 209228561Snp# NVI_FCOE = 4 # FCOE access to NPORTS 210228561Snp# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 211228561Snp# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 212228561Snp# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 213228561Snp# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 214228561Snp# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 215228561Snp 216228561Snp# Two extra Ingress Queues per function for Firmware Events and Forwarded 217228561Snp# Interrupts, and two extra interrupts per function for Firmware Events (or a 218228561Snp# Forwarded Interrupt Queue) and General Interrupts per function. 219228561Snp# 220228561Snp# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 221228561Snp# # Forwarded Interrupts 222228561Snp# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 223228561Snp# # General Interrupts 224228561Snp 225228561Snp# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 226228561Snp# their interrupts forwarded to another set of Forwarded Interrupt Queues. 227228561Snp# 228228561Snp# NVI_HYPERV = 16 # VMs we want to support 229228561Snp# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 230228561Snp# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 231228561Snp# NEQ_HYPERV = 32 # VIQs Free Lists 232228561Snp# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 233228561Snp# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 234228561Snp 235228561Snp# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 236228561Snp# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 237228561Snp# 238228561Snp# NVI_UNIFIED = 28 239228561Snp# NFLIQ_UNIFIED = 106 240228561Snp# NETHCTRL_UNIFIED = 32 241228561Snp# NEQ_UNIFIED = 124 242228561Snp# NMPSTCAM_UNIFIED = 40 243228561Snp# 244228561Snp# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 245228561Snp# that up to 128 to make sure the Unified PF doesn't run out of resources. 246228561Snp# 247228561Snp# NMSIX_UNIFIED = 128 248228561Snp# 249228561Snp# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 250228561Snp# which is 34 but they're probably safe with 32. 251228561Snp# 252228561Snp# NMSIX_STORAGE = 32 253228561Snp 254228561Snp# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 255228561Snp# associated with it. Thus, the MSI-X Vector allocations we give to the 256228561Snp# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 257228561Snp# provision many more Virtual Functions than we can if the UnifiedPF were 258228561Snp# one of PF0-3. 259228561Snp# 260228561Snp 261228561Snp# All of the below PCI-E parameters are actually stored in various *_init.txt 262228561Snp# files. We include them below essentially as comments. 263228561Snp# 264228561Snp# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated 265228561Snp# ports 0-3. 266228561Snp# 267228561Snp# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 268228561Snp# 269228561Snp# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 270228561Snp# storage applications across all four possible ports. 271228561Snp# 272228561Snp# Additionally, since the UnifiedPF isn't one of the per-port Physical 273228561Snp# Functions, we give the UnifiedPF and the PF0-3 Physical Functions 274228561Snp# different PCI Device IDs which will allow Unified and Per-Port Drivers 275228561Snp# to directly select the type of Physical Function to which they wish to be 276228561Snp# attached. 277228561Snp# 278298976Spfg# Note that the actual values used for the PCI-E Intelectual Property will be 279228561Snp# 1 less than those below since that's the way it "counts" things. For 280228561Snp# readability, we use the number we actually mean ... 281228561Snp# 282228561Snp# PF0_INT = 8 # NCPUS 283228561Snp# PF1_INT = 8 # NCPUS 284228561Snp# PF2_INT = 8 # NCPUS 285228561Snp# PF3_INT = 8 # NCPUS 286228561Snp# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 287228561Snp# 288228561Snp# PF4_INT = 128 # NMSIX_UNIFIED 289228561Snp# PF5_INT = 32 # NMSIX_STORAGE 290228561Snp# PF6_INT = 32 # NMSIX_STORAGE 291228561Snp# PF7_INT = 0 # Nothing Assigned 292228561Snp# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 293228561Snp# 294228561Snp# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 295228561Snp# 296228561Snp# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 297228561Snp# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 298228561Snp# 299228561Snp# NVF = 16 300228561Snp 301228561Snp# For those OSes which manage different ports on different PFs, we need 302228561Snp# only enough resources to support a single port's NIC application functions 303228561Snp# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 304228561Snp# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 305228561Snp# managed on the "storage PFs" (see below). 306228561Snp# 307228561Snp[function "0"] 308228561Snp nvf = 16 # NVF on this function 309228561Snp wx_caps = all # write/execute permissions for all commands 310228561Snp r_caps = all # read permissions for all commands 311228561Snp nvi = 1 # 1 port 312228561Snp niqflint = 8 # NCPUS "Queue Sets" 313228561Snp nethctrl = 8 # NCPUS "Queue Sets" 314228561Snp neq = 16 # niqflint + nethctrl Egress Queues 315228561Snp nexactf = 8 # number of exact MPSTCAM MAC filters 316228561Snp cmask = all # access to all channels 317228561Snp pmask = 0x1 # access to only one port 318228561Snp 319228561Snp[function "1"] 320228561Snp nvf = 16 # NVF on this function 321228561Snp wx_caps = all # write/execute permissions for all commands 322228561Snp r_caps = all # read permissions for all commands 323228561Snp nvi = 1 # 1 port 324228561Snp niqflint = 8 # NCPUS "Queue Sets" 325228561Snp nethctrl = 8 # NCPUS "Queue Sets" 326228561Snp neq = 16 # niqflint + nethctrl Egress Queues 327228561Snp nexactf = 8 # number of exact MPSTCAM MAC filters 328228561Snp cmask = all # access to all channels 329228561Snp pmask = 0x2 # access to only one port 330228561Snp 331228561Snp[function "2"] 332228561Snp nvf = 16 # NVF on this function 333228561Snp wx_caps = all # write/execute permissions for all commands 334228561Snp r_caps = all # read permissions for all commands 335228561Snp nvi = 1 # 1 port 336228561Snp niqflint = 8 # NCPUS "Queue Sets" 337228561Snp nethctrl = 8 # NCPUS "Queue Sets" 338228561Snp neq = 16 # niqflint + nethctrl Egress Queues 339228561Snp nexactf = 8 # number of exact MPSTCAM MAC filters 340228561Snp cmask = all # access to all channels 341228561Snp pmask = 0x4 # access to only one port 342228561Snp 343228561Snp[function "3"] 344228561Snp nvf = 16 # NVF on this function 345228561Snp wx_caps = all # write/execute permissions for all commands 346228561Snp r_caps = all # read permissions for all commands 347228561Snp nvi = 1 # 1 port 348228561Snp niqflint = 8 # NCPUS "Queue Sets" 349228561Snp nethctrl = 8 # NCPUS "Queue Sets" 350228561Snp neq = 16 # niqflint + nethctrl Egress Queues 351228561Snp nexactf = 8 # number of exact MPSTCAM MAC filters 352228561Snp cmask = all # access to all channels 353228561Snp pmask = 0x8 # access to only one port 354228561Snp 355228561Snp# Some OS Drivers manage all application functions for all ports via PF4. 356228561Snp# Thus we need to provide a large number of resources here. For Egress 357228561Snp# Queues we need to account for both TX Queues as well as Free List Queues 358228561Snp# (because the host is responsible for producing Free List Buffers for the 359228561Snp# hardware to consume). 360228561Snp# 361228561Snp[function "4"] 362228561Snp wx_caps = all # write/execute permissions for all commands 363228561Snp r_caps = all # read permissions for all commands 364228561Snp nvi = 28 # NVI_UNIFIED 365228561Snp niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD 366237436Snp nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD 367237436Snp neq = 256 # NEQ_UNIFIED + NEQ_WD 368228561Snp nexactf = 40 # NMPSTCAM_UNIFIED 369228561Snp cmask = all # access to all channels 370228561Snp pmask = all # access to all four ports ... 371237436Snp nethofld = 1024 # number of user mode ethernet flow contexts 372228561Snp nroute = 32 # number of routing region entries 373228561Snp nclip = 32 # number of clip region entries 374237436Snp nfilter = 496 # number of filter region entries 375237436Snp nserver = 496 # number of server region entries 376237436Snp nhash = 12288 # number of hash region entries 377228561Snp protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu 378237436Snp tp_l2t = 3072 379256459Snp tp_ddp = 3 380228561Snp tp_ddp_iscsi = 2 381256459Snp tp_stag = 3 382256459Snp tp_pbl = 10 383256459Snp tp_rq = 13 384228561Snp 385228561Snp# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 386228561Snp# need to have Virtual Interfaces on each of the four ports with up to NCPUS 387228561Snp# "Queue Sets" each. 388228561Snp# 389228561Snp[function "5"] 390228561Snp wx_caps = all # write/execute permissions for all commands 391228561Snp r_caps = all # read permissions for all commands 392228561Snp nvi = 4 # NPORTS 393228561Snp niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 394228561Snp nethctrl = 32 # NPORTS*NCPUS 395228561Snp neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 396228561Snp nexactf = 4 # NPORTS 397228561Snp cmask = all # access to all channels 398228561Snp pmask = all # access to all four ports ... 399237436Snp nserver = 16 400237436Snp nhash = 2048 401285527Snp tp_l2t = 1020 402237436Snp protocol = iscsi_initiator_fofld 403237436Snp tp_ddp_iscsi = 2 404237436Snp iscsi_ntask = 2048 405237436Snp iscsi_nsess = 2048 406237436Snp iscsi_nconn_per_session = 1 407237436Snp iscsi_ninitiator_instance = 64 408228561Snp 409228561Snp[function "6"] 410228561Snp wx_caps = all # write/execute permissions for all commands 411228561Snp r_caps = all # read permissions for all commands 412228561Snp nvi = 4 # NPORTS 413228561Snp niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 414228561Snp nethctrl = 32 # NPORTS*NCPUS 415228561Snp neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) 416228561Snp nexactf = 32 # NPORTS + adding 28 exact entries for FCoE 417228561Snp # which is OK since < MIN(SUM PF0..3, PF4) 418228561Snp # and we never load PF0..3 and PF4 concurrently 419228561Snp cmask = all # access to all channels 420228561Snp pmask = all # access to all four ports ... 421237436Snp nhash = 2048 422285527Snp tp_l2t = 4 423228561Snp protocol = fcoe_initiator 424256459Snp tp_ddp = 1 425228561Snp fcoe_nfcf = 16 426228561Snp fcoe_nvnp = 32 427228561Snp fcoe_nssn = 1024 428228561Snp 429237436Snp# The following function, 1023, is not an actual PCIE function but is used to 430237436Snp# configure and reserve firmware internal resources that come from the global 431237436Snp# resource pool. 432237436Snp# 433237436Snp[function "1023"] 434237436Snp wx_caps = all # write/execute permissions for all commands 435237436Snp r_caps = all # read permissions for all commands 436237436Snp nvi = 4 # NVI_UNIFIED 437237436Snp cmask = all # access to all channels 438237436Snp pmask = all # access to all four ports ... 439237436Snp nexactf = 8 # NPORTS + DCBX + 440237436Snp nfilter = 16 # number of filter region entries 441237436Snp 442228561Snp# For Virtual functions, we only allow NIC functionality and we only allow 443228561Snp# access to one port (1 << PF). Note that because of limitations in the 444228561Snp# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 445228561Snp# and GTS registers, the number of Ingress and Egress Queues must be a power 446228561Snp# of 2. 447228561Snp# 448228561Snp[function "0/*"] # NVF 449228561Snp wx_caps = 0x82 # DMAQ | VF 450228561Snp r_caps = 0x86 # DMAQ | VF | PORT 451228561Snp nvi = 1 # 1 port 452228561Snp niqflint = 4 # 2 "Queue Sets" + NXIQ 453228561Snp nethctrl = 2 # 2 "Queue Sets" 454228561Snp neq = 4 # 2 "Queue Sets" * 2 455228561Snp nexactf = 4 456228561Snp cmask = all # access to all channels 457228561Snp pmask = 0x1 # access to only one port ... 458228561Snp 459228561Snp[function "1/*"] # NVF 460228561Snp wx_caps = 0x82 # DMAQ | VF 461228561Snp r_caps = 0x86 # DMAQ | VF | PORT 462228561Snp nvi = 1 # 1 port 463228561Snp niqflint = 4 # 2 "Queue Sets" + NXIQ 464228561Snp nethctrl = 2 # 2 "Queue Sets" 465228561Snp neq = 4 # 2 "Queue Sets" * 2 466228561Snp nexactf = 4 467228561Snp cmask = all # access to all channels 468228561Snp pmask = 0x2 # access to only one port ... 469228561Snp 470228561Snp[function "2/*"] # NVF 471228561Snp wx_caps = 0x82 # DMAQ | VF 472228561Snp r_caps = 0x86 # DMAQ | VF | PORT 473228561Snp nvi = 1 # 1 port 474228561Snp niqflint = 4 # 2 "Queue Sets" + NXIQ 475228561Snp nethctrl = 2 # 2 "Queue Sets" 476228561Snp neq = 4 # 2 "Queue Sets" * 2 477228561Snp nexactf = 4 478228561Snp cmask = all # access to all channels 479228561Snp pmask = 0x4 # access to only one port ... 480228561Snp 481228561Snp[function "3/*"] # NVF 482228561Snp wx_caps = 0x82 # DMAQ | VF 483228561Snp r_caps = 0x86 # DMAQ | VF | PORT 484228561Snp nvi = 1 # 1 port 485228561Snp niqflint = 4 # 2 "Queue Sets" + NXIQ 486228561Snp nethctrl = 2 # 2 "Queue Sets" 487228561Snp neq = 4 # 2 "Queue Sets" * 2 488228561Snp nexactf = 4 489228561Snp cmask = all # access to all channels 490228561Snp pmask = 0x8 # access to only one port ... 491228561Snp 492228561Snp# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 493228561Snp# for packets from the wire as well as the loopback path of the L2 switch. The 494228561Snp# folling params control how the buffer memory is distributed and the L2 flow 495228561Snp# control settings: 496228561Snp# 497228561Snp# bg_mem: %-age of mem to use for port/buffer group 498228561Snp# lpbk_mem: %-age of port/bg mem to use for loopback 499228561Snp# hwm: high watermark; bytes available when starting to send pause 500228561Snp# frames (in units of 0.1 MTU) 501228561Snp# lwm: low watermark; bytes remaining when sending 'unpause' frame 502228561Snp# (in inuits of 0.1 MTU) 503228561Snp# dwm: minimum delta between high and low watermark (in units of 100 504228561Snp# Bytes) 505228561Snp# 506267757Snp# 507267757Snp 508228561Snp[port "0"] 509228561Snp dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload 510228561Snp bg_mem = 25 511228561Snp lpbk_mem = 25 512228561Snp hwm = 30 513228561Snp lwm = 15 514228561Snp dwm = 30 515267757Snp dcb_app_tlv[0] = 0x8906, ethertype, 3 516267757Snp dcb_app_tlv[1] = 0x8914, ethertype, 3 517267757Snp dcb_app_tlv[2] = 3260, socketnum, 5 518228561Snp 519228561Snp[port "1"] 520228561Snp dcb = ppp, dcbx 521228561Snp bg_mem = 25 522228561Snp lpbk_mem = 25 523228561Snp hwm = 30 524228561Snp lwm = 15 525228561Snp dwm = 30 526267757Snp dcb_app_tlv[0] = 0x8906, ethertype, 3 527267757Snp dcb_app_tlv[1] = 0x8914, ethertype, 3 528267757Snp dcb_app_tlv[2] = 3260, socketnum, 5 529228561Snp 530228561Snp[port "2"] 531228561Snp dcb = ppp, dcbx 532228561Snp bg_mem = 25 533228561Snp lpbk_mem = 25 534228561Snp hwm = 30 535228561Snp lwm = 15 536228561Snp dwm = 30 537267757Snp dcb_app_tlv[0] = 0x8906, ethertype, 3 538267757Snp dcb_app_tlv[1] = 0x8914, ethertype, 3 539267757Snp dcb_app_tlv[2] = 3260, socketnum, 5 540228561Snp 541228561Snp[port "3"] 542228561Snp dcb = ppp, dcbx 543228561Snp bg_mem = 25 544228561Snp lpbk_mem = 25 545228561Snp hwm = 30 546228561Snp lwm = 15 547228561Snp dwm = 30 548267757Snp dcb_app_tlv[0] = 0x8906, ethertype, 3 549267757Snp dcb_app_tlv[1] = 0x8914, ethertype, 3 550267757Snp dcb_app_tlv[2] = 3260, socketnum, 5 551228561Snp 552228561Snp[fini] 553319269Snp version = 0x01000028 554319269Snp checksum = 0x5ceab421 555228561Snp 556228561Snp# Total resources used by above allocations: 557228561Snp# Virtual Interfaces: 104 558228561Snp# Ingress Queues/w Free Lists and Interrupts: 526 559228561Snp# Egress Queues: 702 560228561Snp# MPS TCAM Entries: 336 561228561Snp# MSI-X Vectors: 736 562228561Snp# Virtual Functions: 64 563228561Snp# 564228561Snp# $FreeBSD: stable/11/sys/dev/cxgbe/firmware/t4fw_cfg_uwire.txt 319269 2017-05-31 00:16:05Z np $ 565228561Snp# 566