1322014Snp/*- 2322014Snp * Copyright (c) 2017 Chelsio Communications, Inc. 3322014Snp * All rights reserved. 4322014Snp * 5322014Snp * Redistribution and use in source and binary forms, with or without 6322014Snp * modification, are permitted provided that the following conditions 7322014Snp * are met: 8322014Snp * 1. Redistributions of source code must retain the above copyright 9322014Snp * notice, this list of conditions and the following disclaimer. 10322014Snp * 2. Redistributions in binary form must reproduce the above copyright 11322014Snp * notice, this list of conditions and the following disclaimer in the 12322014Snp * documentation and/or other materials provided with the distribution. 13322014Snp * 14322014Snp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15322014Snp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16322014Snp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17322014Snp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18322014Snp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19322014Snp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20322014Snp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21322014Snp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22322014Snp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23322014Snp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24322014Snp * SUCH DAMAGE. 25322014Snp */ 26322014Snp 27322014Snp#include <sys/cdefs.h> 28322014Snp__FBSDID("$FreeBSD: stable/11/sys/dev/cxgbe/cudbg/cudbg_wtp.c 322014 2017-08-03 14:43:30Z np $"); 29322014Snp 30322014Snp#include <sys/types.h> 31322014Snp#include <sys/param.h> 32322014Snp 33322014Snp#include "common/common.h" 34322014Snp#include "common/t4_regs.h" 35322014Snp#include "cudbg.h" 36322014Snp#include "cudbg_lib_common.h" 37322014Snp#include "cudbg_entity.h" 38322014Snp 39322014Snpint collect_wtp_data(struct cudbg_init *pdbg_init, 40322014Snp struct cudbg_buffer *dbg_buff, 41322014Snp struct cudbg_error *cudbg_err); 42322014Snp/*SGE_DEBUG Registers.*/ 43322014Snp#define TP_MIB_SIZE 0x5e 44322014Snp 45322014Snpstruct sge_debug_reg_data { 46322014Snp /*indx0*/ 47322014Snp u32 reserved1:4; 48322014Snp u32 reserved2:4; 49322014Snp u32 debug_uP_SOP_cnt:4; 50322014Snp u32 debug_uP_EOP_cnt:4; 51322014Snp u32 debug_CIM_SOP1_cnt:4; 52322014Snp u32 debug_CIM_EOP1_cnt:4; 53322014Snp u32 debug_CIM_SOP0_cnt:4; 54322014Snp u32 debug_CIM_EOP0_cnt:4; 55322014Snp 56322014Snp /*indx1*/ 57322014Snp u32 reserved3:32; 58322014Snp 59322014Snp /*indx2*/ 60322014Snp u32 debug_T_Rx_SOP1_cnt:4; 61322014Snp u32 debug_T_Rx_EOP1_cnt:4; 62322014Snp u32 debug_T_Rx_SOP0_cnt:4; 63322014Snp u32 debug_T_Rx_EOP0_cnt:4; 64322014Snp u32 debug_U_Rx_SOP1_cnt:4; 65322014Snp u32 debug_U_Rx_EOP1_cnt:4; 66322014Snp u32 debug_U_Rx_SOP0_cnt:4; 67322014Snp u32 debug_U_Rx_EOP0_cnt:4; 68322014Snp 69322014Snp /*indx3*/ 70322014Snp u32 reserved4:32; 71322014Snp 72322014Snp /*indx4*/ 73322014Snp u32 debug_UD_Rx_SOP3_cnt:4; 74322014Snp u32 debug_UD_Rx_EOP3_cnt:4; 75322014Snp u32 debug_UD_Rx_SOP2_cnt:4; 76322014Snp u32 debug_UD_Rx_EOP2_cnt:4; 77322014Snp u32 debug_UD_Rx_SOP1_cnt:4; 78322014Snp u32 debug_UD_Rx_EOP1_cnt:4; 79322014Snp u32 debug_UD_Rx_SOP0_cnt:4; 80322014Snp u32 debug_UD_Rx_EOP0_cnt:4; 81322014Snp 82322014Snp /*indx5*/ 83322014Snp u32 reserved5:32; 84322014Snp 85322014Snp /*indx6*/ 86322014Snp u32 debug_U_Tx_SOP3_cnt:4; 87322014Snp u32 debug_U_Tx_EOP3_cnt:4; 88322014Snp u32 debug_U_Tx_SOP2_cnt:4; 89322014Snp u32 debug_U_Tx_EOP2_cnt:4; 90322014Snp u32 debug_U_Tx_SOP1_cnt:4; 91322014Snp u32 debug_U_Tx_EOP1_cnt:4; 92322014Snp u32 debug_U_Tx_SOP0_cnt:4; 93322014Snp u32 debug_U_Tx_EOP0_cnt:4; 94322014Snp 95322014Snp /*indx7*/ 96322014Snp u32 reserved6:32; 97322014Snp 98322014Snp /*indx8*/ 99322014Snp u32 debug_PC_Rsp_SOP1_cnt:4; 100322014Snp u32 debug_PC_Rsp_EOP1_cnt:4; 101322014Snp u32 debug_PC_Rsp_SOP0_cnt:4; 102322014Snp u32 debug_PC_Rsp_EOP0_cnt:4; 103322014Snp u32 debug_PC_Req_SOP1_cnt:4; 104322014Snp u32 debug_PC_Req_EOP1_cnt:4; 105322014Snp u32 debug_PC_Req_SOP0_cnt:4; 106322014Snp u32 debug_PC_Req_EOP0_cnt:4; 107322014Snp 108322014Snp /*indx9*/ 109322014Snp u32 reserved7:32; 110322014Snp 111322014Snp /*indx10*/ 112322014Snp u32 debug_PD_Req_SOP3_cnt:4; 113322014Snp u32 debug_PD_Req_EOP3_cnt:4; 114322014Snp u32 debug_PD_Req_SOP2_cnt:4; 115322014Snp u32 debug_PD_Req_EOP2_cnt:4; 116322014Snp u32 debug_PD_Req_SOP1_cnt:4; 117322014Snp u32 debug_PD_Req_EOP1_cnt:4; 118322014Snp u32 debug_PD_Req_SOP0_cnt:4; 119322014Snp u32 debug_PD_Req_EOP0_cnt:4; 120322014Snp 121322014Snp /*indx11*/ 122322014Snp u32 reserved8:32; 123322014Snp 124322014Snp /*indx12*/ 125322014Snp u32 debug_PD_Rsp_SOP3_cnt:4; 126322014Snp u32 debug_PD_Rsp_EOP3_cnt:4; 127322014Snp u32 debug_PD_Rsp_SOP2_cnt:4; 128322014Snp u32 debug_PD_Rsp_EOP2_cnt:4; 129322014Snp u32 debug_PD_Rsp_SOP1_cnt:4; 130322014Snp u32 debug_PD_Rsp_EOP1_cnt:4; 131322014Snp u32 debug_PD_Rsp_SOP0_cnt:4; 132322014Snp u32 debug_PD_Rsp_EOP0_cnt:4; 133322014Snp 134322014Snp /*indx13*/ 135322014Snp u32 reserved9:32; 136322014Snp 137322014Snp /*indx14*/ 138322014Snp u32 debug_CPLSW_TP_Rx_SOP1_cnt:4; 139322014Snp u32 debug_CPLSW_TP_Rx_EOP1_cnt:4; 140322014Snp u32 debug_CPLSW_TP_Rx_SOP0_cnt:4; 141322014Snp u32 debug_CPLSW_TP_Rx_EOP0_cnt:4; 142322014Snp u32 debug_CPLSW_CIM_SOP1_cnt:4; 143322014Snp u32 debug_CPLSW_CIM_EOP1_cnt:4; 144322014Snp u32 debug_CPLSW_CIM_SOP0_cnt:4; 145322014Snp u32 debug_CPLSW_CIM_EOP0_cnt:4; 146322014Snp 147322014Snp /*indx15*/ 148322014Snp u32 reserved10:32; 149322014Snp 150322014Snp /*indx16*/ 151322014Snp u32 debug_PD_Req_Rd3_cnt:4; 152322014Snp u32 debug_PD_Req_Rd2_cnt:4; 153322014Snp u32 debug_PD_Req_Rd1_cnt:4; 154322014Snp u32 debug_PD_Req_Rd0_cnt:4; 155322014Snp u32 debug_PD_Req_Int3_cnt:4; 156322014Snp u32 debug_PD_Req_Int2_cnt:4; 157322014Snp u32 debug_PD_Req_Int1_cnt:4; 158322014Snp u32 debug_PD_Req_Int0_cnt:4; 159322014Snp 160322014Snp}; 161322014Snp 162322014Snpstruct tp_mib_type tp_mib[] = { 163322014Snp {"tp_mib_mac_in_err_0", 0x0}, 164322014Snp {"tp_mib_mac_in_err_1", 0x1}, 165322014Snp {"tp_mib_mac_in_err_2", 0x2}, 166322014Snp {"tp_mib_mac_in_err_3", 0x3}, 167322014Snp {"tp_mib_hdr_in_err_0", 0x4}, 168322014Snp {"tp_mib_hdr_in_err_1", 0x5}, 169322014Snp {"tp_mib_hdr_in_err_2", 0x6}, 170322014Snp {"tp_mib_hdr_in_err_3", 0x7}, 171322014Snp {"tp_mib_tcp_in_err_0", 0x8}, 172322014Snp {"tp_mib_tcp_in_err_1", 0x9}, 173322014Snp {"tp_mib_tcp_in_err_2", 0xa}, 174322014Snp {"tp_mib_tcp_in_err_3", 0xb}, 175322014Snp {"tp_mib_tcp_out_rst", 0xc}, 176322014Snp {"tp_mib_tcp_in_seg_hi", 0x10}, 177322014Snp {"tp_mib_tcp_in_seg_lo", 0x11}, 178322014Snp {"tp_mib_tcp_out_seg_hi", 0x12}, 179322014Snp {"tp_mib_tcp_out_seg_lo", 0x13}, 180322014Snp {"tp_mib_tcp_rxt_seg_hi", 0x14}, 181322014Snp {"tp_mib_tcp_rxt_seg_lo", 0x15}, 182322014Snp {"tp_mib_tnl_cng_drop_0", 0x18}, 183322014Snp {"tp_mib_tnl_cng_drop_1", 0x19}, 184322014Snp {"tp_mib_tnl_cng_drop_2", 0x1a}, 185322014Snp {"tp_mib_tnl_cng_drop_3", 0x1b}, 186322014Snp {"tp_mib_ofd_chn_drop_0", 0x1c}, 187322014Snp {"tp_mib_ofd_chn_drop_1", 0x1d}, 188322014Snp {"tp_mib_ofd_chn_drop_2", 0x1e}, 189322014Snp {"tp_mib_ofd_chn_drop_3", 0x1f}, 190322014Snp {"tp_mib_tnl_out_pkt_0", 0x20}, 191322014Snp {"tp_mib_tnl_out_pkt_1", 0x21}, 192322014Snp {"tp_mib_tnl_out_pkt_2", 0x22}, 193322014Snp {"tp_mib_tnl_out_pkt_3", 0x23}, 194322014Snp {"tp_mib_tnl_in_pkt_0", 0x24}, 195322014Snp {"tp_mib_tnl_in_pkt_1", 0x25}, 196322014Snp {"tp_mib_tnl_in_pkt_2", 0x26}, 197322014Snp {"tp_mib_tnl_in_pkt_3", 0x27}, 198322014Snp {"tp_mib_tcp_v6in_err_0", 0x28}, 199322014Snp {"tp_mib_tcp_v6in_err_1", 0x29}, 200322014Snp {"tp_mib_tcp_v6in_err_2", 0x2a}, 201322014Snp {"tp_mib_tcp_v6in_err_3", 0x2b}, 202322014Snp {"tp_mib_tcp_v6out_rst", 0x2c}, 203322014Snp {"tp_mib_tcp_v6in_seg_hi", 0x30}, 204322014Snp {"tp_mib_tcp_v6in_seg_lo", 0x31}, 205322014Snp {"tp_mib_tcp_v6out_seg_hi", 0x32}, 206322014Snp {"tp_mib_tcp_v6out_seg_lo", 0x33}, 207322014Snp {"tp_mib_tcp_v6rxt_seg_hi", 0x34}, 208322014Snp {"tp_mib_tcp_v6rxt_seg_lo", 0x35}, 209322014Snp {"tp_mib_ofd_arp_drop", 0x36}, 210322014Snp {"tp_mib_ofd_dfr_drop", 0x37}, 211322014Snp {"tp_mib_cpl_in_req_0", 0x38}, 212322014Snp {"tp_mib_cpl_in_req_1", 0x39}, 213322014Snp {"tp_mib_cpl_in_req_2", 0x3a}, 214322014Snp {"tp_mib_cpl_in_req_3", 0x3b}, 215322014Snp {"tp_mib_cpl_out_rsp_0", 0x3c}, 216322014Snp {"tp_mib_cpl_out_rsp_1", 0x3d}, 217322014Snp {"tp_mib_cpl_out_rsp_2", 0x3e}, 218322014Snp {"tp_mib_cpl_out_rsp_3", 0x3f}, 219322014Snp {"tp_mib_tnl_lpbk_0", 0x40}, 220322014Snp {"tp_mib_tnl_lpbk_1", 0x41}, 221322014Snp {"tp_mib_tnl_lpbk_2", 0x42}, 222322014Snp {"tp_mib_tnl_lpbk_3", 0x43}, 223322014Snp {"tp_mib_tnl_drop_0", 0x44}, 224322014Snp {"tp_mib_tnl_drop_1", 0x45}, 225322014Snp {"tp_mib_tnl_drop_2", 0x46}, 226322014Snp {"tp_mib_tnl_drop_3", 0x47}, 227322014Snp {"tp_mib_fcoe_ddp_0", 0x48}, 228322014Snp {"tp_mib_fcoe_ddp_1", 0x49}, 229322014Snp {"tp_mib_fcoe_ddp_2", 0x4a}, 230322014Snp {"tp_mib_fcoe_ddp_3", 0x4b}, 231322014Snp {"tp_mib_fcoe_drop_0", 0x4c}, 232322014Snp {"tp_mib_fcoe_drop_1", 0x4d}, 233322014Snp {"tp_mib_fcoe_drop_2", 0x4e}, 234322014Snp {"tp_mib_fcoe_drop_3", 0x4f}, 235322014Snp {"tp_mib_fcoe_byte_0_hi", 0x50}, 236322014Snp {"tp_mib_fcoe_byte_0_lo", 0x51}, 237322014Snp {"tp_mib_fcoe_byte_1_hi", 0x52}, 238322014Snp {"tp_mib_fcoe_byte_1_lo", 0x53}, 239322014Snp {"tp_mib_fcoe_byte_2_hi", 0x54}, 240322014Snp {"tp_mib_fcoe_byte_2_lo", 0x55}, 241322014Snp {"tp_mib_fcoe_byte_3_hi", 0x56}, 242322014Snp {"tp_mib_fcoe_byte_3_lo", 0x57}, 243322014Snp {"tp_mib_ofd_vln_drop_0", 0x58}, 244322014Snp {"tp_mib_ofd_vln_drop_1", 0x59}, 245322014Snp {"tp_mib_ofd_vln_drop_2", 0x5a}, 246322014Snp {"tp_mib_ofd_vln_drop_3", 0x5b}, 247322014Snp {"tp_mib_usm_pkts", 0x5c}, 248322014Snp {"tp_mib_usm_drop", 0x5d}, 249322014Snp {"tp_mib_usm_bytes_hi", 0x5e}, 250322014Snp {"tp_mib_usm_bytes_lo", 0x5f}, 251322014Snp {"tp_mib_tid_del", 0x60}, 252322014Snp {"tp_mib_tid_inv", 0x61}, 253322014Snp {"tp_mib_tid_act", 0x62}, 254322014Snp {"tp_mib_tid_pas", 0x63}, 255322014Snp {"tp_mib_rqe_dfr_mod", 0x64}, 256322014Snp {"tp_mib_rqe_dfr_pkt", 0x65} 257322014Snp}; 258322014Snp 259322014Snpstatic u32 read_sge_debug_data(struct cudbg_init *pdbg_init, u32 *sge_dbg_reg) 260322014Snp{ 261322014Snp struct adapter *padap = pdbg_init->adap; 262322014Snp u32 value; 263322014Snp int i = 0; 264322014Snp 265322014Snp for (i = 0; i <= 15; i++) { 266322014Snp t4_write_reg(padap, A_SGE_DEBUG_INDEX, (u32)i); 267322014Snp value = t4_read_reg(padap, A_SGE_DEBUG_DATA_LOW); 268322014Snp /*printf("LOW 0x%08x\n", value);*/ 269322014Snp sge_dbg_reg[(i << 1) | 1] = HTONL_NIBBLE(value); 270322014Snp value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH); 271322014Snp /*printf("HIGH 0x%08x\n", value);*/ 272322014Snp sge_dbg_reg[(i << 1)] = HTONL_NIBBLE(value); 273322014Snp } 274322014Snp return 0; 275322014Snp} 276322014Snp 277322014Snpstatic u32 read_tp_mib_data(struct cudbg_init *pdbg_init, 278322014Snp struct tp_mib_data **ppTp_Mib) 279322014Snp{ 280322014Snp struct adapter *padap = pdbg_init->adap; 281322014Snp u32 i = 0; 282322014Snp 283322014Snp for (i = 0; i < TP_MIB_SIZE; i++) { 284322014Snp t4_tp_mib_read(padap, &tp_mib[i].value, 1, 285322014Snp (u32)tp_mib[i].addr, true); 286322014Snp } 287322014Snp *ppTp_Mib = (struct tp_mib_data *)&tp_mib[0]; 288322014Snp 289322014Snp return 0; 290322014Snp} 291322014Snp 292322014Snpstatic int t5_wtp_data(struct cudbg_init *pdbg_init, 293322014Snp struct cudbg_buffer *dbg_buff, 294322014Snp struct cudbg_error *cudbg_err) 295322014Snp{ 296322014Snp struct adapter *padap = pdbg_init->adap; 297322014Snp struct sge_debug_reg_data *sge_dbg_reg = NULL; 298322014Snp struct cudbg_buffer scratch_buff; 299322014Snp struct tp_mib_data *ptp_mib = NULL; 300322014Snp struct wtp_data *wtp; 301322014Snp u32 Sge_Dbg[32] = {0}; 302322014Snp u32 value = 0; 303322014Snp u32 i = 0; 304322014Snp u32 drop = 0; 305322014Snp u32 err = 0; 306322014Snp u32 offset; 307322014Snp int rc = 0; 308322014Snp 309322014Snp rc = get_scratch_buff(dbg_buff, sizeof(struct wtp_data), &scratch_buff); 310322014Snp 311322014Snp if (rc) 312322014Snp goto err; 313322014Snp 314322014Snp offset = scratch_buff.offset; 315322014Snp wtp = (struct wtp_data *)((char *)scratch_buff.data + offset); 316322014Snp 317322014Snp read_sge_debug_data(pdbg_init, Sge_Dbg); 318322014Snp read_tp_mib_data(pdbg_init, &ptp_mib); 319322014Snp 320322014Snp sge_dbg_reg = (struct sge_debug_reg_data *) &Sge_Dbg[0]; 321322014Snp 322322014Snp /*#######################################################################*/ 323322014Snp /*# TX PATH, starting from pcie*/ 324322014Snp /*#######################################################################*/ 325322014Snp 326322014Snp /* Get Reqests of commmands from SGE to PCIE*/ 327322014Snp 328322014Snp wtp->sge_pcie_cmd_req.sop[0] = sge_dbg_reg->debug_PC_Req_SOP0_cnt; 329322014Snp wtp->sge_pcie_cmd_req.sop[1] = sge_dbg_reg->debug_PC_Req_SOP1_cnt; 330322014Snp 331322014Snp wtp->sge_pcie_cmd_req.eop[0] = sge_dbg_reg->debug_PC_Req_EOP0_cnt; 332322014Snp wtp->sge_pcie_cmd_req.eop[1] = sge_dbg_reg->debug_PC_Req_EOP1_cnt; 333322014Snp 334322014Snp /* Get Reqests of commmands from PCIE to core*/ 335322014Snp value = t4_read_reg(padap, A_PCIE_CMDR_REQ_CNT); 336322014Snp 337322014Snp wtp->pcie_core_cmd_req.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/ 338322014Snp wtp->pcie_core_cmd_req.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/ 339322014Snp /* there is no EOP for this, so we fake it.*/ 340322014Snp wtp->pcie_core_cmd_req.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/ 341322014Snp wtp->pcie_core_cmd_req.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/ 342322014Snp 343322014Snp /* Get DMA stats*/ 344322014Snp for (i = 0; i < 4; i++) { 345322014Snp value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT3 + (i * 0x10)); 346322014Snp wtp->pcie_t5_dma_stat3.sop[i] = value & 0xFF; 347322014Snp wtp->pcie_t5_dma_stat3.eop[i] = ((value >> 16) & 0xFF); 348322014Snp } 349322014Snp 350322014Snp /* Get SGE debug data high index 6*/ 351322014Snp value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_6); 352322014Snp wtp->sge_debug_data_high_index_6.sop[0] = ((value >> 4) & 0x0F); 353322014Snp wtp->sge_debug_data_high_index_6.eop[0] = ((value >> 0) & 0x0F); 354322014Snp wtp->sge_debug_data_high_index_6.sop[1] = ((value >> 12) & 0x0F); 355322014Snp wtp->sge_debug_data_high_index_6.eop[1] = ((value >> 8) & 0x0F); 356322014Snp wtp->sge_debug_data_high_index_6.sop[2] = ((value >> 20) & 0x0F); 357322014Snp wtp->sge_debug_data_high_index_6.eop[2] = ((value >> 16) & 0x0F); 358322014Snp wtp->sge_debug_data_high_index_6.sop[3] = ((value >> 28) & 0x0F); 359322014Snp wtp->sge_debug_data_high_index_6.eop[3] = ((value >> 24) & 0x0F); 360322014Snp 361322014Snp /* Get SGE debug data high index 3*/ 362322014Snp value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_3); 363322014Snp wtp->sge_debug_data_high_index_3.sop[0] = ((value >> 4) & 0x0F); 364322014Snp wtp->sge_debug_data_high_index_3.eop[0] = ((value >> 0) & 0x0F); 365322014Snp wtp->sge_debug_data_high_index_3.sop[1] = ((value >> 12) & 0x0F); 366322014Snp wtp->sge_debug_data_high_index_3.eop[1] = ((value >> 8) & 0x0F); 367322014Snp wtp->sge_debug_data_high_index_3.sop[2] = ((value >> 20) & 0x0F); 368322014Snp wtp->sge_debug_data_high_index_3.eop[2] = ((value >> 16) & 0x0F); 369322014Snp wtp->sge_debug_data_high_index_3.sop[3] = ((value >> 28) & 0x0F); 370322014Snp wtp->sge_debug_data_high_index_3.eop[3] = ((value >> 24) & 0x0F); 371322014Snp 372322014Snp /* Get ULP SE CNT CHx*/ 373322014Snp for (i = 0; i < 4; i++) { 374322014Snp value = t4_read_reg(padap, A_ULP_TX_SE_CNT_CH0 + (i * 4)); 375322014Snp wtp->ulp_se_cnt_chx.sop[i] = ((value >> 28) & 0x0F); 376322014Snp wtp->ulp_se_cnt_chx.eop[i] = ((value >> 24) & 0x0F); 377322014Snp } 378322014Snp 379322014Snp /* Get MAC PORTx PKT COUNT*/ 380322014Snp for (i = 0; i < 4; i++) { 381322014Snp value = t4_read_reg(padap, 0x3081c + ((i * 4) << 12)); 382322014Snp wtp->mac_portx_pkt_count.sop[i] = ((value >> 24) & 0xFF); 383322014Snp wtp->mac_portx_pkt_count.eop[i] = ((value >> 16) & 0xFF); 384322014Snp wtp->mac_porrx_pkt_count.sop[i] = ((value >> 8) & 0xFF); 385322014Snp wtp->mac_porrx_pkt_count.eop[i] = ((value >> 0) & 0xFF); 386322014Snp } 387322014Snp 388322014Snp /* Get mac portx aFramesTransmittedok*/ 389322014Snp for (i = 0; i < 4; i++) { 390322014Snp value = t4_read_reg(padap, 0x30a80 + ((i * 4) << 12)); 391322014Snp wtp->mac_portx_aframestra_ok.sop[i] = (value & 0xFF); 392322014Snp wtp->mac_portx_aframestra_ok.eop[i] = (value & 0xFF); 393322014Snp } 394322014Snp 395322014Snp /* Get command respones from core to PCIE*/ 396322014Snp value = t4_read_reg(padap, A_PCIE_CMDR_RSP_CNT); 397322014Snp 398322014Snp wtp->core_pcie_cmd_rsp.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/ 399322014Snp wtp->core_pcie_cmd_rsp.sop[1] = ((value >> 16) & 0xFF); /*bit 16:23*/ 400322014Snp 401322014Snp wtp->core_pcie_cmd_rsp.eop[0] = ((value >> 8) & 0xFF); /*bit 8:15*/ 402322014Snp wtp->core_pcie_cmd_rsp.eop[1] = ((value >> 24) & 0xFF); /*bit 24:31*/ 403322014Snp 404322014Snp /*Get command Resposes from PCIE to SGE*/ 405322014Snp wtp->pcie_sge_cmd_rsp.sop[0] = sge_dbg_reg->debug_PC_Rsp_SOP0_cnt; 406322014Snp wtp->pcie_sge_cmd_rsp.sop[1] = sge_dbg_reg->debug_PC_Rsp_SOP1_cnt; 407322014Snp 408322014Snp wtp->pcie_sge_cmd_rsp.eop[0] = sge_dbg_reg->debug_PC_Rsp_EOP0_cnt; 409322014Snp wtp->pcie_sge_cmd_rsp.eop[1] = sge_dbg_reg->debug_PC_Rsp_EOP1_cnt; 410322014Snp 411322014Snp /* Get commands sent from SGE to CIM/uP*/ 412322014Snp wtp->sge_cim.sop[0] = sge_dbg_reg->debug_CIM_SOP0_cnt; 413322014Snp wtp->sge_cim.sop[1] = sge_dbg_reg->debug_CIM_SOP1_cnt; 414322014Snp 415322014Snp wtp->sge_cim.eop[0] = sge_dbg_reg->debug_CIM_EOP0_cnt; 416322014Snp wtp->sge_cim.eop[1] = sge_dbg_reg->debug_CIM_EOP1_cnt; 417322014Snp 418322014Snp /* Get Reqests of data from PCIE by SGE*/ 419322014Snp wtp->utx_sge_dma_req.sop[0] = sge_dbg_reg->debug_UD_Rx_SOP0_cnt; 420322014Snp wtp->utx_sge_dma_req.sop[1] = sge_dbg_reg->debug_UD_Rx_SOP1_cnt; 421322014Snp wtp->utx_sge_dma_req.sop[2] = sge_dbg_reg->debug_UD_Rx_SOP2_cnt; 422322014Snp wtp->utx_sge_dma_req.sop[3] = sge_dbg_reg->debug_UD_Rx_SOP3_cnt; 423322014Snp 424322014Snp wtp->utx_sge_dma_req.eop[0] = sge_dbg_reg->debug_UD_Rx_EOP0_cnt; 425322014Snp wtp->utx_sge_dma_req.eop[1] = sge_dbg_reg->debug_UD_Rx_EOP1_cnt; 426322014Snp wtp->utx_sge_dma_req.eop[2] = sge_dbg_reg->debug_UD_Rx_EOP2_cnt; 427322014Snp wtp->utx_sge_dma_req.eop[3] = sge_dbg_reg->debug_UD_Rx_EOP3_cnt; 428322014Snp 429322014Snp /* Get Reqests of data from PCIE by SGE*/ 430322014Snp wtp->sge_pcie_dma_req.sop[0] = sge_dbg_reg->debug_PD_Req_Rd0_cnt; 431322014Snp wtp->sge_pcie_dma_req.sop[1] = sge_dbg_reg->debug_PD_Req_Rd1_cnt; 432322014Snp wtp->sge_pcie_dma_req.sop[2] = sge_dbg_reg->debug_PD_Req_Rd2_cnt; 433322014Snp wtp->sge_pcie_dma_req.sop[3] = sge_dbg_reg->debug_PD_Req_Rd3_cnt; 434322014Snp /*no EOP's, so fake it.*/ 435322014Snp wtp->sge_pcie_dma_req.eop[0] = sge_dbg_reg->debug_PD_Req_Rd0_cnt; 436322014Snp wtp->sge_pcie_dma_req.eop[1] = sge_dbg_reg->debug_PD_Req_Rd1_cnt; 437322014Snp wtp->sge_pcie_dma_req.eop[2] = sge_dbg_reg->debug_PD_Req_Rd2_cnt; 438322014Snp wtp->sge_pcie_dma_req.eop[3] = sge_dbg_reg->debug_PD_Req_Rd3_cnt; 439322014Snp 440322014Snp /* Get Reqests of data from PCIE to core*/ 441322014Snp value = t4_read_reg(padap, A_PCIE_DMAR_REQ_CNT); 442322014Snp 443322014Snp wtp->pcie_core_dma_req.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/ 444322014Snp wtp->pcie_core_dma_req.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/ 445322014Snp wtp->pcie_core_dma_req.sop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/ 446322014Snp wtp->pcie_core_dma_req.sop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/ 447322014Snp /* There is no eop so fake it.*/ 448322014Snp wtp->pcie_core_dma_req.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/ 449322014Snp wtp->pcie_core_dma_req.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/ 450322014Snp wtp->pcie_core_dma_req.eop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/ 451322014Snp wtp->pcie_core_dma_req.eop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/ 452322014Snp 453322014Snp /* Get data responses from core to PCIE*/ 454322014Snp value = t4_read_reg(padap, A_PCIE_DMAR_RSP_SOP_CNT); 455322014Snp 456322014Snp wtp->core_pcie_dma_rsp.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/ 457322014Snp wtp->core_pcie_dma_rsp.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/ 458322014Snp wtp->core_pcie_dma_rsp.sop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/ 459322014Snp wtp->core_pcie_dma_rsp.sop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/ 460322014Snp 461322014Snp value = t4_read_reg(padap, A_PCIE_DMAR_RSP_EOP_CNT); 462322014Snp 463322014Snp wtp->core_pcie_dma_rsp.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/ 464322014Snp wtp->core_pcie_dma_rsp.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/ 465322014Snp wtp->core_pcie_dma_rsp.eop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/ 466322014Snp wtp->core_pcie_dma_rsp.eop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/ 467322014Snp 468322014Snp /* Get PCIE_DATA to SGE*/ 469322014Snp wtp->pcie_sge_dma_rsp.sop[0] = sge_dbg_reg->debug_PD_Rsp_SOP0_cnt; 470322014Snp wtp->pcie_sge_dma_rsp.sop[1] = sge_dbg_reg->debug_PD_Rsp_SOP1_cnt; 471322014Snp wtp->pcie_sge_dma_rsp.sop[2] = sge_dbg_reg->debug_PD_Rsp_SOP2_cnt; 472322014Snp wtp->pcie_sge_dma_rsp.sop[3] = sge_dbg_reg->debug_PD_Rsp_SOP3_cnt; 473322014Snp 474322014Snp wtp->pcie_sge_dma_rsp.eop[0] = sge_dbg_reg->debug_PD_Rsp_EOP0_cnt; 475322014Snp wtp->pcie_sge_dma_rsp.eop[1] = sge_dbg_reg->debug_PD_Rsp_EOP1_cnt; 476322014Snp wtp->pcie_sge_dma_rsp.eop[2] = sge_dbg_reg->debug_PD_Rsp_EOP2_cnt; 477322014Snp wtp->pcie_sge_dma_rsp.eop[3] = sge_dbg_reg->debug_PD_Rsp_EOP3_cnt; 478322014Snp 479322014Snp /*Get SGE to ULP_TX*/ 480322014Snp wtp->sge_utx.sop[0] = sge_dbg_reg->debug_U_Tx_SOP0_cnt; 481322014Snp wtp->sge_utx.sop[1] = sge_dbg_reg->debug_U_Tx_SOP1_cnt; 482322014Snp wtp->sge_utx.sop[2] = sge_dbg_reg->debug_U_Tx_SOP2_cnt; 483322014Snp wtp->sge_utx.sop[3] = sge_dbg_reg->debug_U_Tx_SOP3_cnt; 484322014Snp 485322014Snp wtp->sge_utx.eop[0] = sge_dbg_reg->debug_U_Tx_EOP0_cnt; 486322014Snp wtp->sge_utx.eop[1] = sge_dbg_reg->debug_U_Tx_EOP1_cnt; 487322014Snp wtp->sge_utx.eop[2] = sge_dbg_reg->debug_U_Tx_EOP2_cnt; 488322014Snp wtp->sge_utx.eop[3] = sge_dbg_reg->debug_U_Tx_EOP3_cnt; 489322014Snp 490322014Snp /* Get ULP_TX to TP*/ 491322014Snp for (i = 0; i < 4; i++) { 492322014Snp value = t4_read_reg(padap, (A_ULP_TX_SE_CNT_CH0 + (i*4))); 493322014Snp 494322014Snp wtp->utx_tp.sop[i] = ((value >> 28) & 0xF); /*bits 28:31*/ 495322014Snp wtp->utx_tp.eop[i] = ((value >> 24) & 0xF); /*bits 24:27*/ 496322014Snp } 497322014Snp 498322014Snp /* Get TP_DBG_CSIDE registers*/ 499322014Snp for (i = 0; i < 4; i++) { 500322014Snp t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_RX0 + i), 501322014Snp true); 502322014Snp 503322014Snp wtp->utx_tpcside.sop[i] = ((value >> 28) & 0xF);/*bits 28:31*/ 504322014Snp wtp->utx_tpcside.eop[i] = ((value >> 24) & 0xF);/*bits 24:27*/ 505322014Snp wtp->tpcside_rxpld.sop[i] = ((value >> 20) & 0xF);/*bits 20:23*/ 506322014Snp wtp->tpcside_rxpld.eop[i] = ((value >> 16) & 0xF);/*bits 16:19*/ 507322014Snp wtp->tpcside_rxarb.sop[i] = ((value >> 12) & 0xF);/*bits 12:15*/ 508322014Snp wtp->tpcside_rxarb.eop[i] = ((value >> 8) & 0xF); /*bits 8:11*/ 509322014Snp wtp->tpcside_rxcpl.sop[i] = ((value >> 4) & 0xF); /*bits 4:7*/ 510322014Snp wtp->tpcside_rxcpl.eop[i] = ((value >> 0) & 0xF); /*bits 0:3*/ 511322014Snp } 512322014Snp 513322014Snp /* TP_DBG_ESIDE*/ 514322014Snp for (i = 0; i < 4; i++) { 515322014Snp t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i), 516322014Snp true); 517322014Snp 518322014Snp wtp->tpeside_mps.sop[i] = ((value >> 28) & 0xF); /*bits 28:31*/ 519322014Snp wtp->tpeside_mps.eop[i] = ((value >> 24) & 0xF); /*bits 24:27*/ 520322014Snp wtp->tpeside_pm.sop[i] = ((value >> 20) & 0xF); /*bits 20:23*/ 521322014Snp wtp->tpeside_pm.eop[i] = ((value >> 16) & 0xF); /*bits 16:19*/ 522322014Snp wtp->mps_tpeside.sop[i] = ((value >> 12) & 0xF); /*bits 12:15*/ 523322014Snp wtp->mps_tpeside.eop[i] = ((value >> 8) & 0xF); /*bits 8:11*/ 524322014Snp wtp->tpeside_pld.sop[i] = ((value >> 4) & 0xF); /*bits 4:7*/ 525322014Snp wtp->tpeside_pld.eop[i] = ((value >> 0) & 0xF); /*bits 0:3*/ 526322014Snp 527322014Snp } 528322014Snp 529322014Snp /*PCIE CMD STAT2*/ 530322014Snp for (i = 0; i < 3; i++) { 531322014Snp value = t4_read_reg(padap, 0x5988 + (i * 0x10)); 532322014Snp wtp->pcie_cmd_stat2.sop[i] = value & 0xFF; 533322014Snp wtp->pcie_cmd_stat2.eop[i] = value & 0xFF; 534322014Snp } 535322014Snp 536322014Snp /*PCIE cmd stat3*/ 537322014Snp for (i = 0; i < 3; i++) { 538322014Snp value = t4_read_reg(padap, 0x598c + (i * 0x10)); 539322014Snp wtp->pcie_cmd_stat3.sop[i] = value & 0xFF; 540322014Snp wtp->pcie_cmd_stat3.eop[i] = value & 0xFF; 541322014Snp } 542322014Snp 543322014Snp /* ULP_RX input/output*/ 544322014Snp for (i = 0; i < 2; i++) { 545322014Snp value = t4_read_reg(padap, (A_ULP_RX_SE_CNT_CH0 + (i*4))); 546322014Snp 547322014Snp wtp->pmrx_ulprx.sop[i] = ((value >> 4) & 0xF); /*bits 4:7*/ 548322014Snp wtp->pmrx_ulprx.eop[i] = ((value >> 0) & 0xF); /*bits 0:3*/ 549322014Snp wtp->ulprx_tpcside.sop[i] = ((value >> 28) & 0xF);/*bits 28:31*/ 550322014Snp wtp->ulprx_tpcside.eop[i] = ((value >> 24) & 0xF);/*bits 24:27*/ 551322014Snp } 552322014Snp 553322014Snp /* Get the MPS input from TP*/ 554322014Snp drop = 0; 555322014Snp for (i = 0; i < 2; i++) { 556322014Snp value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_TP01 + (i << 2))); 557322014Snp wtp->tp_mps.sop[(i*2)] = ((value >> 8) & 0xFF); /*bit 8:15*/ 558322014Snp wtp->tp_mps.eop[(i*2)] = ((value >> 0) & 0xFF); /*bit 0:7*/ 559322014Snp wtp->tp_mps.sop[(i*2) + 1] = ((value >> 24) & 0xFF);/*bit 24:31 560322014Snp */ 561322014Snp wtp->tp_mps.eop[(i*2) + 1] = ((value >> 16) & 0xFF);/*bit 16:23 562322014Snp */ 563322014Snp } 564322014Snp drop = ptp_mib->TP_MIB_OFD_ARP_DROP.value; 565322014Snp drop += ptp_mib->TP_MIB_OFD_DFR_DROP.value; 566322014Snp 567322014Snp drop += ptp_mib->TP_MIB_TNL_DROP_0.value; 568322014Snp drop += ptp_mib->TP_MIB_TNL_DROP_1.value; 569322014Snp drop += ptp_mib->TP_MIB_TNL_DROP_2.value; 570322014Snp drop += ptp_mib->TP_MIB_TNL_DROP_3.value; 571322014Snp 572322014Snp wtp->tp_mps.drops = drop; 573322014Snp 574322014Snp /* Get the MPS output to the MAC's*/ 575322014Snp drop = 0; 576322014Snp for (i = 0; i < 2; i++) { 577322014Snp value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_MAC01 + (i << 2))); 578322014Snp wtp->mps_xgm.sop[(i*2)] = ((value >> 8) & 0xFF);/*bit 8:15*/ 579322014Snp wtp->mps_xgm.eop[(i*2)] = ((value >> 0) & 0xFF);/*bit 0:7*/ 580322014Snp wtp->mps_xgm.sop[(i*2) + 1] = ((value >> 24) & 0xFF);/*bit 24:31 581322014Snp */ 582322014Snp wtp->mps_xgm.eop[(i*2) + 1] = ((value >> 16) & 0xFF);/*bit 16:23 583322014Snp */ 584322014Snp } 585322014Snp for (i = 0; i < 4; i++) { 586322014Snp value = t4_read_reg(padap, 587322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_TX_PORT_DROP_L) + 588322014Snp (i * T5_PORT_STRIDE))); 589322014Snp drop += value; 590322014Snp } 591322014Snp wtp->mps_xgm.drops = (drop & 0xFF); 592322014Snp 593322014Snp /* Get the SOP/EOP counters into and out of MAC. [JHANEL] I think this 594322014Snp * is*/ 595322014Snp /* clear on read, so you have to read both TX and RX path at same 596322014Snp * time.*/ 597322014Snp drop = 0; 598322014Snp for (i = 0; i < 4; i++) { 599322014Snp value = t4_read_reg(padap, 600322014Snp (T5_PORT0_REG(A_MAC_PORT_PKT_COUNT) + 601322014Snp (i * T5_PORT_STRIDE))); 602322014Snp 603322014Snp wtp->tx_xgm_xgm.sop[i] = ((value >> 24) & 0xFF); /*bit 24:31*/ 604322014Snp wtp->tx_xgm_xgm.eop[i] = ((value >> 16) & 0xFF); /*bit 16:23*/ 605322014Snp wtp->rx_xgm_xgm.sop[i] = ((value >> 8) & 0xFF); /*bit 8:15*/ 606322014Snp wtp->rx_xgm_xgm.eop[i] = ((value >> 0) & 0xFF); /*bit 0:7*/ 607322014Snp } 608322014Snp 609322014Snp /* Get the MAC's output to the wire*/ 610322014Snp drop = 0; 611322014Snp for (i = 0; i < 4; i++) { 612322014Snp value = t4_read_reg(padap, 613322014Snp (T5_PORT0_REG(A_MAC_PORT_AFRAMESTRANSMITTEDOK) + 614322014Snp (i * T5_PORT_STRIDE))); 615322014Snp wtp->xgm_wire.sop[i] = (value); 616322014Snp wtp->xgm_wire.eop[i] = (value); /* No EOP for XGMAC, so fake 617322014Snp it.*/ 618322014Snp } 619322014Snp 620322014Snp /*########################################################################*/ 621322014Snp /*# RX PATH, starting from wire*/ 622322014Snp /*########################################################################*/ 623322014Snp 624322014Snp /* Add up the wire input to the MAC*/ 625322014Snp drop = 0; 626322014Snp for (i = 0; i < 4; i++) { 627322014Snp value = t4_read_reg(padap, 628322014Snp (T5_PORT0_REG(A_MAC_PORT_AFRAMESRECEIVEDOK) + 629322014Snp (i * T5_PORT_STRIDE))); 630322014Snp 631322014Snp wtp->wire_xgm.sop[i] = (value); 632322014Snp wtp->wire_xgm.eop[i] = (value); /* No EOP for XGMAC, so fake 633322014Snp it.*/ 634322014Snp } 635322014Snp 636322014Snp /* Already read the rx_xgm_xgm when reading TX path.*/ 637322014Snp 638322014Snp /* Add up SOP/EOP's on all 8 MPS buffer channels*/ 639322014Snp drop = 0; 640322014Snp for (i = 0; i < 8; i++) { 641322014Snp value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_IN0 + (i << 2))); 642322014Snp 643322014Snp wtp->xgm_mps.sop[i] = ((value >> 8) & 0xFF); /*bits 8:15*/ 644322014Snp wtp->xgm_mps.eop[i] = ((value >> 0) & 0xFF); /*bits 0:7*/ 645322014Snp } 646322014Snp for (i = 0; i < 4; i++) { 647322014Snp value = t4_read_reg(padap, (A_MPS_RX_CLS_DROP_CNT0 + (i << 2))); 648322014Snp /* typo in JHANEL's code.*/ 649322014Snp drop += (value & 0xFFFF) + ((value >> 16) & 0xFFFF); 650322014Snp } 651322014Snp wtp->xgm_mps.cls_drop = drop & 0xFF; 652322014Snp 653322014Snp /* Add up the overflow drops on all 4 ports.*/ 654322014Snp drop = 0; 655322014Snp for (i = 0; i < 4; i++) { 656322014Snp value = t4_read_reg(padap, 657322014Snp (A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + 658322014Snp (i << 3))); 659322014Snp drop += value; 660322014Snp value = t4_read_reg(padap, 661322014Snp (A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + 662322014Snp (i << 2))); 663322014Snp value = t4_read_reg(padap, 664322014Snp (A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L + 665322014Snp (i << 3))); 666322014Snp drop += value; 667322014Snp value = t4_read_reg(padap, 668322014Snp (A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + 669322014Snp (i << 2))); 670322014Snp 671322014Snp value = t4_read_reg(padap, 672322014Snp (A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + 673322014Snp (i << 3))); 674322014Snp drop += value; 675322014Snp value = t4_read_reg(padap, 676322014Snp (A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + 677322014Snp (i << 3))); 678322014Snp value = t4_read_reg(padap, 679322014Snp (A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L + 680322014Snp (i << 3))); 681322014Snp drop += value; 682322014Snp value = t4_read_reg(padap, 683322014Snp (A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + 684322014Snp (i << 3))); 685322014Snp 686322014Snp value = t4_read_reg(padap, 687322014Snp T5_PORT0_REG(A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES) + 688322014Snp (i * T5_PORT_STRIDE)); 689322014Snp drop += value; 690322014Snp } 691322014Snp wtp->xgm_mps.drop = (drop & 0xFF); 692322014Snp 693322014Snp /* Add up the MPS errors that should result in dropped packets*/ 694322014Snp err = 0; 695322014Snp for (i = 0; i < 4; i++) { 696322014Snp 697322014Snp value = t4_read_reg(padap, 698322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L) + 699322014Snp (i * T5_PORT_STRIDE))); 700322014Snp err += value; 701322014Snp value = t4_read_reg(padap, 702322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L) + 703322014Snp (i * T5_PORT_STRIDE) + 4)); 704322014Snp 705322014Snp value = t4_read_reg(padap, 706322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L) + 707322014Snp (i * T5_PORT_STRIDE))); 708322014Snp err += value; 709322014Snp value = t4_read_reg(padap, 710322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L) + 711322014Snp (i * T5_PORT_STRIDE) + 4)); 712322014Snp 713322014Snp value = t4_read_reg(padap, 714322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L) + 715322014Snp (i * T5_PORT_STRIDE))); 716322014Snp err += value; 717322014Snp value = t4_read_reg(padap, 718322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L) + 719322014Snp (i * T5_PORT_STRIDE) + 4)); 720322014Snp 721322014Snp value = t4_read_reg(padap, 722322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L) + 723322014Snp (i * T5_PORT_STRIDE))); 724322014Snp err += value; 725322014Snp value = t4_read_reg(padap, 726322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L) + 727322014Snp (i * T5_PORT_STRIDE) + 4)); 728322014Snp 729322014Snp value = t4_read_reg(padap, 730322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L) + 731322014Snp (i * T5_PORT_STRIDE))); 732322014Snp err += value; 733322014Snp value = t4_read_reg(padap, 734322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L) + 735322014Snp (i * T5_PORT_STRIDE) + 4)); 736322014Snp 737322014Snp value = t4_read_reg(padap, 738322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LESS_64B_L) + 739322014Snp (i * T5_PORT_STRIDE))); 740322014Snp err += value; 741322014Snp value = t4_read_reg(padap, 742322014Snp (T5_PORT0_REG((A_MPS_PORT_STAT_RX_PORT_LESS_64B_L) + 743322014Snp (i * T5_PORT_STRIDE) + 4))); 744322014Snp } 745322014Snp wtp->xgm_mps.err = (err & 0xFF); 746322014Snp 747322014Snp drop = 0; 748322014Snp for (i = 0; i < 2; i++) { 749322014Snp value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_OUT01 + (i << 2))); 750322014Snp 751322014Snp wtp->mps_tp.sop[(i*2)] = ((value >> 8) & 0xFF); /*bit 8:15*/ 752322014Snp wtp->mps_tp.eop[(i*2)] = ((value >> 0) & 0xFF); /*bit 0:7*/ 753322014Snp wtp->mps_tp.sop[(i*2) + 1] = ((value >> 24) & 0xFF);/*bit 24:31 754322014Snp */ 755322014Snp wtp->mps_tp.eop[(i*2) + 1] = ((value >> 16) & 0xFF);/*bit 16:23 756322014Snp */ 757322014Snp } 758322014Snp drop = ptp_mib->TP_MIB_TNL_CNG_DROP_0.value; 759322014Snp drop += ptp_mib->TP_MIB_TNL_CNG_DROP_1.value; 760322014Snp drop += ptp_mib->TP_MIB_TNL_CNG_DROP_2.value; 761322014Snp drop += ptp_mib->TP_MIB_TNL_CNG_DROP_3.value; 762322014Snp drop += ptp_mib->TP_MIB_OFD_CHN_DROP_0.value; 763322014Snp drop += ptp_mib->TP_MIB_OFD_CHN_DROP_1.value; 764322014Snp drop += ptp_mib->TP_MIB_OFD_CHN_DROP_2.value; 765322014Snp drop += ptp_mib->TP_MIB_OFD_CHN_DROP_3.value; 766322014Snp drop += ptp_mib->TP_MIB_FCOE_DROP_0.value; 767322014Snp drop += ptp_mib->TP_MIB_FCOE_DROP_1.value; 768322014Snp drop += ptp_mib->TP_MIB_FCOE_DROP_2.value; 769322014Snp drop += ptp_mib->TP_MIB_FCOE_DROP_3.value; 770322014Snp drop += ptp_mib->TP_MIB_OFD_VLN_DROP_0.value; 771322014Snp drop += ptp_mib->TP_MIB_OFD_VLN_DROP_1.value; 772322014Snp drop += ptp_mib->TP_MIB_OFD_VLN_DROP_2.value; 773322014Snp drop += ptp_mib->TP_MIB_OFD_VLN_DROP_3.value; 774322014Snp drop += ptp_mib->TP_MIB_USM_DROP.value; 775322014Snp 776322014Snp wtp->mps_tp.drops = drop; 777322014Snp 778322014Snp /* Get TP_DBG_CSIDE_TX registers*/ 779322014Snp for (i = 0; i < 4; i++) { 780322014Snp t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_RX0 + i), 781322014Snp true); 782322014Snp 783322014Snp wtp->tpcside_csw.sop[i] = ((value >> 28) & 0xF);/*bits 28:31*/ 784322014Snp wtp->tpcside_csw.eop[i] = ((value >> 24) & 0xF);/*bits 24:27*/ 785322014Snp wtp->tpcside_pm.sop[i] = ((value >> 20) & 0xF);/*bits 20:23*/ 786322014Snp wtp->tpcside_pm.eop[i] = ((value >> 16) & 0xF);/*bits 16:19*/ 787322014Snp wtp->tpcside_uturn.sop[i] = ((value >> 12) & 0xF);/*bits 12:15*/ 788322014Snp wtp->tpcside_uturn.eop[i] = ((value >> 8) & 0xF); /*bits 8:11*/ 789322014Snp wtp->tpcside_txcpl.sop[i] = ((value >> 4) & 0xF); /*bits 4:7*/ 790322014Snp wtp->tpcside_txcpl.eop[i] = ((value >> 0) & 0xF); /*bits 0:3*/ 791322014Snp } 792322014Snp 793322014Snp /* TP to CPL_SWITCH*/ 794322014Snp wtp->tp_csw.sop[0] = sge_dbg_reg->debug_CPLSW_TP_Rx_SOP0_cnt; 795322014Snp wtp->tp_csw.sop[1] = sge_dbg_reg->debug_CPLSW_TP_Rx_SOP1_cnt; 796322014Snp 797322014Snp wtp->tp_csw.eop[0] = sge_dbg_reg->debug_CPLSW_TP_Rx_EOP0_cnt; 798322014Snp wtp->tp_csw.eop[1] = sge_dbg_reg->debug_CPLSW_TP_Rx_EOP1_cnt; 799322014Snp 800322014Snp /* TP/CPL_SWITCH to SGE*/ 801322014Snp wtp->csw_sge.sop[0] = sge_dbg_reg->debug_T_Rx_SOP0_cnt; 802322014Snp wtp->csw_sge.sop[1] = sge_dbg_reg->debug_T_Rx_SOP1_cnt; 803322014Snp 804322014Snp wtp->csw_sge.eop[0] = sge_dbg_reg->debug_T_Rx_EOP0_cnt; 805322014Snp wtp->csw_sge.eop[1] = sge_dbg_reg->debug_T_Rx_EOP1_cnt; 806322014Snp 807322014Snp wtp->sge_pcie.sop[0] = sge_dbg_reg->debug_PD_Req_SOP0_cnt; 808322014Snp wtp->sge_pcie.sop[1] = sge_dbg_reg->debug_PD_Req_SOP1_cnt; 809322014Snp wtp->sge_pcie.sop[2] = sge_dbg_reg->debug_PD_Req_SOP2_cnt; 810322014Snp wtp->sge_pcie.sop[3] = sge_dbg_reg->debug_PD_Req_SOP3_cnt; 811322014Snp 812322014Snp wtp->sge_pcie.eop[0] = sge_dbg_reg->debug_PD_Req_EOP0_cnt; 813322014Snp wtp->sge_pcie.eop[1] = sge_dbg_reg->debug_PD_Req_EOP1_cnt; 814322014Snp wtp->sge_pcie.eop[2] = sge_dbg_reg->debug_PD_Req_EOP2_cnt; 815322014Snp wtp->sge_pcie.eop[3] = sge_dbg_reg->debug_PD_Req_EOP3_cnt; 816322014Snp 817322014Snp wtp->sge_pcie_ints.sop[0] = sge_dbg_reg->debug_PD_Req_Int0_cnt; 818322014Snp wtp->sge_pcie_ints.sop[1] = sge_dbg_reg->debug_PD_Req_Int1_cnt; 819322014Snp wtp->sge_pcie_ints.sop[2] = sge_dbg_reg->debug_PD_Req_Int2_cnt; 820322014Snp wtp->sge_pcie_ints.sop[3] = sge_dbg_reg->debug_PD_Req_Int3_cnt; 821322014Snp /* NO EOP, so fake it.*/ 822322014Snp wtp->sge_pcie_ints.eop[0] = sge_dbg_reg->debug_PD_Req_Int0_cnt; 823322014Snp wtp->sge_pcie_ints.eop[1] = sge_dbg_reg->debug_PD_Req_Int1_cnt; 824322014Snp wtp->sge_pcie_ints.eop[2] = sge_dbg_reg->debug_PD_Req_Int2_cnt; 825322014Snp wtp->sge_pcie_ints.eop[3] = sge_dbg_reg->debug_PD_Req_Int3_cnt; 826322014Snp 827322014Snp /*Get PCIE DMA1 STAT2*/ 828322014Snp for (i = 0; i < 4; i++) { 829322014Snp value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT2 + (i * 0x10)); 830322014Snp wtp->pcie_dma1_stat2.sop[i] = ((value >> 8) & 0x0F); 831322014Snp wtp->pcie_dma1_stat2.eop[i] = ((value >> 8) & 0x0F); 832322014Snp wtp->pcie_dma1_stat2_core.sop[i] += value & 0x0F; 833322014Snp wtp->pcie_dma1_stat2_core.eop[i] += value & 0x0F; 834322014Snp } 835322014Snp 836322014Snp /* Get mac porrx aFramesTransmittedok*/ 837322014Snp for (i = 0; i < 4; i++) { 838322014Snp value = t4_read_reg(padap, 0x30a88 + ((i * 4) << 12)); 839322014Snp wtp->mac_porrx_aframestra_ok.sop[i] = (value & 0xFF); 840322014Snp wtp->mac_porrx_aframestra_ok.eop[i] = (value & 0xFF); 841322014Snp } 842322014Snp 843322014Snp /*Get SGE debug data high index 7*/ 844322014Snp value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_7); 845322014Snp wtp->sge_debug_data_high_indx7.sop[0] = ((value >> 4) & 0x0F); 846322014Snp wtp->sge_debug_data_high_indx7.eop[0] = ((value >> 0) & 0x0F); 847322014Snp wtp->sge_debug_data_high_indx7.sop[1] = ((value >> 12) & 0x0F); 848322014Snp wtp->sge_debug_data_high_indx7.eop[1] = ((value >> 8) & 0x0F); 849322014Snp wtp->sge_debug_data_high_indx7.sop[2] = ((value >> 20) & 0x0F); 850322014Snp wtp->sge_debug_data_high_indx7.eop[2] = ((value >> 16) & 0x0F); 851322014Snp wtp->sge_debug_data_high_indx7.sop[3] = ((value >> 28) & 0x0F); 852322014Snp wtp->sge_debug_data_high_indx7.eop[3] = ((value >> 24) & 0x0F); 853322014Snp 854322014Snp /*Get SGE debug data high index 1*/ 855322014Snp value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_1); 856322014Snp wtp->sge_debug_data_high_indx1.sop[0] = ((value >> 20) & 0x0F); 857322014Snp wtp->sge_debug_data_high_indx1.eop[0] = ((value >> 16) & 0x0F); 858322014Snp wtp->sge_debug_data_high_indx1.sop[1] = ((value >> 28) & 0x0F); 859322014Snp wtp->sge_debug_data_high_indx1.eop[1] = ((value >> 24) & 0x0F); 860322014Snp 861322014Snp /*Get TP debug CSIDE Tx registers*/ 862322014Snp for (i = 0; i < 2; i++) { 863322014Snp t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_TX0 + i), 864322014Snp true); 865322014Snp 866322014Snp wtp->utx_tpcside_tx.sop[i] = ((value >> 28) & 0xF);/*bits 28:31 867322014Snp */ 868322014Snp wtp->utx_tpcside_tx.eop[i] = ((value >> 24) & 0xF); 869322014Snp } 870322014Snp 871322014Snp /*Get SGE debug data high index 9*/ 872322014Snp value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_9); 873322014Snp wtp->sge_debug_data_high_indx9.sop[0] = ((value >> 20) & 0x0F); 874322014Snp wtp->sge_debug_data_high_indx9.sop[1] = ((value >> 28) & 0x0F); 875322014Snp wtp->sge_debug_data_high_indx9.eop[0] = ((value >> 16) & 0x0F); 876322014Snp wtp->sge_debug_data_high_indx9.eop[1] = ((value >> 24) & 0x0F); 877322014Snp wtp->sge_work_req_pkt.sop[0] = ((value >> 4) & 0x0F); 878322014Snp wtp->sge_work_req_pkt.sop[1] = ((value >> 12) & 0x0F); 879322014Snp 880322014Snp /*Get LE DB response count*/ 881322014Snp value = t4_read_reg(padap, A_LE_DB_REQ_RSP_CNT); 882322014Snp wtp->le_db_rsp_cnt.sop = value & 0xF; 883322014Snp wtp->le_db_rsp_cnt.eop = (value >> 16) & 0xF; 884322014Snp 885322014Snp /*Get TP debug Eside PKTx*/ 886322014Snp for (i = 0; i < 4; i++) { 887322014Snp t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i), 888322014Snp true); 889322014Snp 890322014Snp wtp->tp_dbg_eside_pktx.sop[i] = ((value >> 12) & 0xF); 891322014Snp wtp->tp_dbg_eside_pktx.eop[i] = ((value >> 8) & 0xF); 892322014Snp } 893322014Snp 894322014Snp /* Get data responses from core to PCIE*/ 895322014Snp value = t4_read_reg(padap, A_PCIE_DMAW_SOP_CNT); 896322014Snp 897322014Snp wtp->pcie_core_dmaw.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/ 898322014Snp wtp->pcie_core_dmaw.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/ 899322014Snp wtp->pcie_core_dmaw.sop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/ 900322014Snp wtp->pcie_core_dmaw.sop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/ 901322014Snp 902322014Snp value = t4_read_reg(padap, A_PCIE_DMAW_EOP_CNT); 903322014Snp 904322014Snp wtp->pcie_core_dmaw.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/ 905322014Snp wtp->pcie_core_dmaw.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/ 906322014Snp wtp->pcie_core_dmaw.eop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/ 907322014Snp wtp->pcie_core_dmaw.eop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/ 908322014Snp 909322014Snp value = t4_read_reg(padap, A_PCIE_DMAI_CNT); 910322014Snp 911322014Snp wtp->pcie_core_dmai.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/ 912322014Snp wtp->pcie_core_dmai.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/ 913322014Snp wtp->pcie_core_dmai.sop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/ 914322014Snp wtp->pcie_core_dmai.sop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/ 915322014Snp /* no eop for interrups, just fake it.*/ 916322014Snp wtp->pcie_core_dmai.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/ 917322014Snp wtp->pcie_core_dmai.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/ 918322014Snp wtp->pcie_core_dmai.eop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/ 919322014Snp wtp->pcie_core_dmai.eop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/ 920322014Snp 921322014Snp rc = write_compression_hdr(&scratch_buff, dbg_buff); 922322014Snp 923322014Snp if (rc) 924322014Snp goto err1; 925322014Snp 926322014Snp rc = compress_buff(&scratch_buff, dbg_buff); 927322014Snp 928322014Snperr1: 929322014Snp release_scratch_buff(&scratch_buff, dbg_buff); 930322014Snperr: 931322014Snp return rc; 932322014Snp} 933322014Snp 934322014Snpstatic int t6_wtp_data(struct cudbg_init *pdbg_init, 935322014Snp struct cudbg_buffer *dbg_buff, 936322014Snp struct cudbg_error *cudbg_err) 937322014Snp{ 938322014Snp struct adapter *padap = pdbg_init->adap; 939322014Snp struct sge_debug_reg_data *sge_dbg_reg = NULL; 940322014Snp struct cudbg_buffer scratch_buff; 941322014Snp struct tp_mib_data *ptp_mib = NULL; 942322014Snp struct wtp_data *wtp; 943322014Snp u32 Sge_Dbg[32] = {0}; 944322014Snp u32 value = 0; 945322014Snp u32 i = 0; 946322014Snp u32 drop = 0; 947322014Snp u32 err = 0; 948322014Snp u32 offset; 949322014Snp int rc = 0; 950322014Snp 951322014Snp rc = get_scratch_buff(dbg_buff, sizeof(struct wtp_data), &scratch_buff); 952322014Snp 953322014Snp if (rc) 954322014Snp goto err; 955322014Snp 956322014Snp offset = scratch_buff.offset; 957322014Snp wtp = (struct wtp_data *)((char *)scratch_buff.data + offset); 958322014Snp 959322014Snp read_sge_debug_data(pdbg_init, Sge_Dbg); 960322014Snp read_tp_mib_data(pdbg_init, &ptp_mib); 961322014Snp 962322014Snp sge_dbg_reg = (struct sge_debug_reg_data *) &Sge_Dbg[0]; 963322014Snp 964322014Snp /*# TX PATH*/ 965322014Snp 966322014Snp /*PCIE CMD STAT2*/ 967322014Snp value = t4_read_reg(padap, A_PCIE_T5_CMD_STAT2); 968322014Snp wtp->pcie_cmd_stat2.sop[0] = value & 0xFF; 969322014Snp wtp->pcie_cmd_stat2.eop[0] = value & 0xFF; 970322014Snp 971322014Snp value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_7); 972322014Snp wtp->sge_pcie_cmd_req.sop[0] = ((value >> 20) & 0x0F); 973322014Snp wtp->sge_pcie_cmd_req.eop[0] = ((value >> 16) & 0x0F); 974322014Snp wtp->sge_pcie_cmd_req.sop[1] = ((value >> 28) & 0x0F); 975322014Snp wtp->sge_pcie_cmd_req.eop[1] = ((value >> 24) & 0x0F); 976322014Snp 977322014Snp value = t4_read_reg(padap, A_PCIE_T5_CMD_STAT3); 978322014Snp wtp->pcie_cmd_stat3.sop[0] = value & 0xFF; 979322014Snp wtp->pcie_cmd_stat3.eop[0] = value & 0xFF; 980322014Snp 981322014Snp /*Get command Resposes from PCIE to SGE*/ 982322014Snp wtp->pcie_sge_cmd_rsp.sop[0] = sge_dbg_reg->debug_PC_Rsp_SOP0_cnt; 983322014Snp wtp->pcie_sge_cmd_rsp.eop[0] = sge_dbg_reg->debug_PC_Rsp_EOP0_cnt; 984322014Snp wtp->pcie_sge_cmd_rsp.sop[1] = sge_dbg_reg->debug_PC_Rsp_SOP1_cnt; 985322014Snp wtp->pcie_sge_cmd_rsp.eop[1] = sge_dbg_reg->debug_PC_Rsp_EOP0_cnt; 986322014Snp 987322014Snp /* Get commands sent from SGE to CIM/uP*/ 988322014Snp wtp->sge_cim.sop[0] = sge_dbg_reg->debug_CIM_SOP0_cnt; 989322014Snp wtp->sge_cim.sop[1] = sge_dbg_reg->debug_CIM_SOP1_cnt; 990322014Snp 991322014Snp wtp->sge_cim.eop[0] = sge_dbg_reg->debug_CIM_EOP0_cnt; 992322014Snp wtp->sge_cim.eop[1] = sge_dbg_reg->debug_CIM_EOP1_cnt; 993322014Snp 994322014Snp /*Get SGE debug data high index 9*/ 995322014Snp value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_9); 996322014Snp wtp->sge_work_req_pkt.sop[0] = ((value >> 4) & 0x0F); 997322014Snp wtp->sge_work_req_pkt.eop[0] = ((value >> 0) & 0x0F); 998322014Snp 999322014Snp for (i = 0; i < 2; i++) { 1000322014Snp value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT2 + (i * 0x10)); 1001322014Snp wtp->pcie_dma1_stat2.sop[i] = ((value >> 8) & 0x0F); 1002322014Snp wtp->pcie_dma1_stat2.eop[i] = ((value >> 8) & 0x0F); 1003322014Snp wtp->pcie_dma1_stat2_core.sop[i] = value & 0x0F; 1004322014Snp wtp->pcie_dma1_stat2_core.eop[i] = value & 0x0F; 1005322014Snp } 1006322014Snp 1007322014Snp /* Get DMA0 stats3*/ 1008322014Snp for (i = 0; i < 2; i++) { 1009322014Snp value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT3 + (i * 0x10)); 1010322014Snp wtp->pcie_t5_dma_stat3.sop[i] = value & 0xFF; 1011322014Snp wtp->pcie_t5_dma_stat3.eop[i] = ((value >> 16) & 0xFF); 1012322014Snp } 1013322014Snp 1014322014Snp /* Get ULP SE CNT CHx*/ 1015322014Snp for (i = 0; i < 4; i++) { 1016322014Snp value = t4_read_reg(padap, A_ULP_TX_SE_CNT_CH0 + (i * 4)); 1017322014Snp wtp->ulp_se_cnt_chx.sop[i] = ((value >> 28) & 0x0F); 1018322014Snp wtp->ulp_se_cnt_chx.eop[i] = ((value >> 24) & 0x0F); 1019322014Snp } 1020322014Snp 1021322014Snp /* Get TP_DBG_CSIDE registers*/ 1022322014Snp for (i = 0; i < 4; i++) { 1023322014Snp t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_RX0 + i), 1024322014Snp true); 1025322014Snp 1026322014Snp wtp->utx_tpcside.sop[i] = ((value >> 28) & 0xF);/*bits 28:31*/ 1027322014Snp wtp->utx_tpcside.eop[i] = ((value >> 24) & 0xF);/*bits 24:27*/ 1028322014Snp wtp->tpcside_rxarb.sop[i] = ((value >> 12) & 0xF);/*bits 12:15*/ 1029322014Snp wtp->tpcside_rxarb.eop[i] = ((value >> 8) & 0xF); /*bits 8:11*/ 1030322014Snp } 1031322014Snp 1032322014Snp for (i = 0; i < 4; i++) { 1033322014Snp t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i), 1034322014Snp true); 1035322014Snp 1036322014Snp 1037322014Snp wtp->tpeside_mps.sop[i] = ((value >> 28) & 0xF); /*bits 28:31*/ 1038322014Snp wtp->tpeside_mps.eop[i] = ((value >> 24) & 0xF); /*bits 24:27*/ 1039322014Snp } 1040322014Snp 1041322014Snp for (i = 0; i < 2; i++) { 1042322014Snp value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_TP01 + (i << 2))); 1043322014Snp wtp->tp_mps.sop[(i*2)] = ((value >> 8) & 0xFF); /*bit 8:15*/ 1044322014Snp wtp->tp_mps.eop[(i*2)] = ((value >> 0) & 0xFF); /*bit 0:7*/ 1045322014Snp wtp->tp_mps.sop[(i*2) + 1] = ((value >> 24) & 0xFF);/*bit 24:31 1046322014Snp */ 1047322014Snp wtp->tp_mps.eop[(i*2) + 1] = ((value >> 16) & 0xFF);/*bit 16:23 1048322014Snp */ 1049322014Snp } 1050322014Snp 1051322014Snp for (i = 0; i < 2; i++) { 1052322014Snp value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_MAC01 + (i << 2))); 1053322014Snp wtp->mps_xgm.sop[(i*2)] = ((value >> 8) & 0xFF);/*bit 8:15*/ 1054322014Snp wtp->mps_xgm.eop[(i*2)] = ((value >> 0) & 0xFF); /*bit 0:7*/ 1055322014Snp wtp->mps_xgm.sop[(i*2) + 1] = ((value >> 24) & 0xFF);/*bit 24:31 1056322014Snp */ 1057322014Snp wtp->mps_xgm.eop[(i*2) + 1] = ((value >> 16) & 0xFF);/*bit 16:23 1058322014Snp */ 1059322014Snp } 1060322014Snp 1061322014Snp /* Get MAC PORTx PKT COUNT*/ 1062322014Snp for (i = 0; i < 2; i++) { 1063322014Snp value = t4_read_reg(padap, 0x3081c + ((i * 4) << 12)); 1064322014Snp wtp->mac_portx_pkt_count.sop[i] = ((value >> 24) & 0xFF); 1065322014Snp wtp->mac_portx_pkt_count.eop[i] = ((value >> 16) & 0xFF); 1066322014Snp wtp->mac_porrx_pkt_count.sop[i] = ((value >> 8) & 0xFF); 1067322014Snp wtp->mac_porrx_pkt_count.eop[i] = ((value >> 0) & 0xFF); 1068322014Snp } 1069322014Snp 1070322014Snp for (i = 0; i < 2; i++) { 1071322014Snp value = t4_read_reg(padap, 0x30f20 + ((i * 4) << 12)); 1072322014Snp wtp->mac_portx_aframestra_ok.sop[i] = value & 0xff; 1073322014Snp wtp->mac_portx_aframestra_ok.eop[i] = value & 0xff; 1074322014Snp } 1075322014Snp 1076322014Snp /*MAC_PORT_MTIP_1G10G_TX_etherStatsPkts*/ 1077322014Snp 1078322014Snp for (i = 0; i < 2; i++) { 1079322014Snp value = t4_read_reg(padap, 0x30f60 + ((i * 4) << 12)); 1080322014Snp wtp->mac_portx_etherstatspkts.sop[i] = value & 0xff; 1081322014Snp wtp->mac_portx_etherstatspkts.eop[i] = value & 0xff; 1082322014Snp } 1083322014Snp 1084322014Snp /*RX path*/ 1085322014Snp 1086322014Snp value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_7); 1087322014Snp wtp->sge_debug_data_high_indx7.sop[0] = ((value >> 4) & 0x0F); 1088322014Snp wtp->sge_debug_data_high_indx7.eop[0] = ((value >> 0) & 0x0F); 1089322014Snp wtp->sge_debug_data_high_indx7.sop[1] = ((value >> 12) & 0x0F); 1090322014Snp wtp->sge_debug_data_high_indx7.eop[1] = ((value >> 8) & 0x0F); 1091322014Snp 1092322014Snp /*Get SGE debug data high index 1*/ 1093322014Snp value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_1); 1094322014Snp wtp->sge_debug_data_high_indx1.sop[0] = ((value >> 20) & 0x0F); 1095322014Snp wtp->sge_debug_data_high_indx1.eop[0] = ((value >> 16) & 0x0F); 1096322014Snp wtp->sge_debug_data_high_indx1.sop[1] = ((value >> 28) & 0x0F); 1097322014Snp wtp->sge_debug_data_high_indx1.eop[1] = ((value >> 24) & 0x0F); 1098322014Snp 1099322014Snp value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_9); 1100322014Snp wtp->sge_debug_data_high_indx9.sop[0] = ((value >> 20) & 0x0F); 1101322014Snp wtp->sge_debug_data_high_indx9.sop[1] = ((value >> 28) & 0x0F); 1102322014Snp 1103322014Snp wtp->sge_debug_data_high_indx9.eop[0] = ((value >> 16) & 0x0F); 1104322014Snp wtp->sge_debug_data_high_indx9.eop[1] = ((value >> 24) & 0x0F); 1105322014Snp 1106322014Snp for (i = 0; i < 2; i++) { 1107322014Snp t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_TX0 + i), 1108322014Snp true); 1109322014Snp 1110322014Snp wtp->utx_tpcside_tx.sop[i] = ((value >> 28) & 0xF);/*bits 28:31 1111322014Snp */ 1112322014Snp wtp->utx_tpcside_tx.eop[i] = ((value >> 24) & 0xF); 1113322014Snp } 1114322014Snp 1115322014Snp /*ULP_RX input/output*/ 1116322014Snp for (i = 0; i < 2; i++) { 1117322014Snp value = t4_read_reg(padap, (A_ULP_RX_SE_CNT_CH0 + (i*4))); 1118322014Snp 1119322014Snp wtp->pmrx_ulprx.sop[i] = ((value >> 4) & 0xF); /*bits 4:7*/ 1120322014Snp wtp->pmrx_ulprx.eop[i] = ((value >> 0) & 0xF); /*bits 0:3*/ 1121322014Snp wtp->ulprx_tpcside.sop[i] = ((value >> 28) & 0xF);/*bits 28:31*/ 1122322014Snp wtp->ulprx_tpcside.eop[i] = ((value >> 24) & 0xF);/*bits 24:27*/ 1123322014Snp } 1124322014Snp 1125322014Snp /*Get LE DB response count*/ 1126322014Snp value = t4_read_reg(padap, A_LE_DB_REQ_RSP_CNT); 1127322014Snp wtp->le_db_rsp_cnt.sop = value & 0xF; 1128322014Snp wtp->le_db_rsp_cnt.eop = (value >> 16) & 0xF; 1129322014Snp 1130322014Snp /*Get TP debug Eside PKTx*/ 1131322014Snp for (i = 0; i < 4; i++) { 1132322014Snp t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i), 1133322014Snp true); 1134322014Snp 1135322014Snp wtp->tp_dbg_eside_pktx.sop[i] = ((value >> 12) & 0xF); 1136322014Snp wtp->tp_dbg_eside_pktx.eop[i] = ((value >> 8) & 0xF); 1137322014Snp } 1138322014Snp 1139322014Snp drop = 0; 1140322014Snp /*MPS_RX_SE_CNT_OUT01*/ 1141322014Snp value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_OUT01 + (i << 2))); 1142322014Snp wtp->mps_tp.sop[0] = ((value >> 8) & 0xFF); /*bit 8:15*/ 1143322014Snp wtp->mps_tp.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/ 1144322014Snp wtp->mps_tp.sop[1] = ((value >> 24) & 0xFF); /*bit 24:31*/ 1145322014Snp wtp->mps_tp.eop[1] = ((value >> 16) & 0xFF); /*bit 16:23*/ 1146322014Snp 1147322014Snp drop = ptp_mib->TP_MIB_TNL_CNG_DROP_0.value; 1148322014Snp drop += ptp_mib->TP_MIB_TNL_CNG_DROP_1.value; 1149322014Snp drop += ptp_mib->TP_MIB_OFD_CHN_DROP_0.value; 1150322014Snp drop += ptp_mib->TP_MIB_OFD_CHN_DROP_1.value; 1151322014Snp drop += ptp_mib->TP_MIB_FCOE_DROP_0.value; 1152322014Snp drop += ptp_mib->TP_MIB_FCOE_DROP_1.value; 1153322014Snp drop += ptp_mib->TP_MIB_OFD_VLN_DROP_0.value; 1154322014Snp drop += ptp_mib->TP_MIB_OFD_VLN_DROP_1.value; 1155322014Snp drop += ptp_mib->TP_MIB_USM_DROP.value; 1156322014Snp 1157322014Snp wtp->mps_tp.drops = drop; 1158322014Snp 1159322014Snp drop = 0; 1160322014Snp for (i = 0; i < 8; i++) { 1161322014Snp value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_IN0 + (i << 2))); 1162322014Snp 1163322014Snp wtp->xgm_mps.sop[i] = ((value >> 8) & 0xFF); /*bits 8:15*/ 1164322014Snp wtp->xgm_mps.eop[i] = ((value >> 0) & 0xFF); /*bits 0:7*/ 1165322014Snp } 1166322014Snp for (i = 0; i < 2; i++) { 1167322014Snp value = t4_read_reg(padap, (A_MPS_RX_CLS_DROP_CNT0 + (i << 2))); 1168322014Snp drop += (value & 0xFFFF) + ((value >> 16) & 0xFFFF); 1169322014Snp } 1170322014Snp wtp->xgm_mps.cls_drop = drop & 0xFF; 1171322014Snp 1172322014Snp for (i = 0; i < 2; i++) { 1173322014Snp value = t4_read_reg(padap, 0x30e20 + ((i * 4) << 12)); 1174322014Snp wtp->mac_porrx_aframestra_ok.sop[i] = value & 0xff; 1175322014Snp wtp->mac_porrx_aframestra_ok.eop[i] = value & 0xff; 1176322014Snp } 1177322014Snp 1178322014Snp /*MAC_PORT_MTIP_1G10G_RX_etherStatsPkts*/ 1179322014Snp for (i = 0; i < 2; i++) { 1180322014Snp value = t4_read_reg(padap, 0x30e60 + ((i * 4) << 12)); 1181322014Snp wtp->mac_porrx_etherstatspkts.sop[i] = value & 0xff; 1182322014Snp wtp->mac_porrx_etherstatspkts.eop[i] = value & 0xff; 1183322014Snp } 1184322014Snp 1185322014Snp wtp->sge_pcie_ints.sop[0] = sge_dbg_reg->debug_PD_Req_Int0_cnt; 1186322014Snp wtp->sge_pcie_ints.sop[1] = sge_dbg_reg->debug_PD_Req_Int1_cnt; 1187322014Snp wtp->sge_pcie_ints.sop[2] = sge_dbg_reg->debug_PD_Req_Int2_cnt; 1188322014Snp wtp->sge_pcie_ints.sop[3] = sge_dbg_reg->debug_PD_Req_Int3_cnt; 1189322014Snp 1190322014Snp /* Add up the overflow drops on all 4 ports.*/ 1191322014Snp drop = 0; 1192322014Snp for (i = 0; i < 2; i++) { 1193322014Snp value = t4_read_reg(padap, 1194322014Snp (A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + 1195322014Snp (i << 3))); 1196322014Snp drop += value; 1197322014Snp value = t4_read_reg(padap, 1198322014Snp (A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + 1199322014Snp (i << 2))); 1200322014Snp value = t4_read_reg(padap, 1201322014Snp (A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L + 1202322014Snp (i << 3))); 1203322014Snp drop += value; 1204322014Snp value = t4_read_reg(padap, 1205322014Snp (A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + 1206322014Snp (i << 2))); 1207322014Snp 1208322014Snp value = t4_read_reg(padap, 1209322014Snp (A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + 1210322014Snp (i << 3))); 1211322014Snp drop += value; 1212322014Snp value = t4_read_reg(padap, 1213322014Snp (A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + 1214322014Snp (i << 3))); 1215322014Snp value = t4_read_reg(padap, 1216322014Snp (A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L + 1217322014Snp (i << 3))); 1218322014Snp drop += value; 1219322014Snp value = t4_read_reg(padap, 1220322014Snp (A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + 1221322014Snp (i << 3))); 1222322014Snp 1223322014Snp value = t4_read_reg(padap, 1224322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES) + 1225322014Snp (i * T5_PORT_STRIDE))); 1226322014Snp drop += value; 1227322014Snp } 1228322014Snp wtp->xgm_mps.drop = (drop & 0xFF); 1229322014Snp 1230322014Snp /* Add up the MPS errors that should result in dropped packets*/ 1231322014Snp err = 0; 1232322014Snp for (i = 0; i < 2; i++) { 1233322014Snp 1234322014Snp value = t4_read_reg(padap, 1235322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L) + 1236322014Snp (i * T5_PORT_STRIDE))); 1237322014Snp err += value; 1238322014Snp value = t4_read_reg(padap, 1239322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L) + 1240322014Snp (i * T5_PORT_STRIDE) + 4)); 1241322014Snp 1242322014Snp value = t4_read_reg(padap, 1243322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L) + 1244322014Snp (i * T5_PORT_STRIDE))); 1245322014Snp err += value; 1246322014Snp value = t4_read_reg(padap, 1247322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L) + 1248322014Snp (i * T5_PORT_STRIDE) + 4)); 1249322014Snp 1250322014Snp value = t4_read_reg(padap, 1251322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L) + 1252322014Snp (i * T5_PORT_STRIDE))); 1253322014Snp err += value; 1254322014Snp value = t4_read_reg(padap, 1255322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L) + 1256322014Snp (i * T5_PORT_STRIDE) + 4)); 1257322014Snp 1258322014Snp value = t4_read_reg(padap, 1259322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L) + 1260322014Snp (i * T5_PORT_STRIDE))); 1261322014Snp err += value; 1262322014Snp value = t4_read_reg(padap, 1263322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L) + 1264322014Snp (i * T5_PORT_STRIDE) + 4)); 1265322014Snp 1266322014Snp value = t4_read_reg(padap, 1267322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L) + 1268322014Snp (i * T5_PORT_STRIDE))); 1269322014Snp err += value; 1270322014Snp value = t4_read_reg(padap, 1271322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L) + 1272322014Snp (i * T5_PORT_STRIDE) + 4)); 1273322014Snp 1274322014Snp value = t4_read_reg(padap, 1275322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LESS_64B_L) + 1276322014Snp (i * T5_PORT_STRIDE))); 1277322014Snp err += value; 1278322014Snp value = t4_read_reg(padap, 1279322014Snp (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LESS_64B_L) + 1280322014Snp (i * T5_PORT_STRIDE) + 4)); 1281322014Snp } 1282322014Snp wtp->xgm_mps.err = (err & 0xFF); 1283322014Snp 1284322014Snp rc = write_compression_hdr(&scratch_buff, dbg_buff); 1285322014Snp 1286322014Snp if (rc) 1287322014Snp goto err1; 1288322014Snp 1289322014Snp rc = compress_buff(&scratch_buff, dbg_buff); 1290322014Snp 1291322014Snperr1: 1292322014Snp release_scratch_buff(&scratch_buff, dbg_buff); 1293322014Snperr: 1294322014Snp return rc; 1295322014Snp} 1296322014Snp 1297322014Snpint collect_wtp_data(struct cudbg_init *pdbg_init, 1298322014Snp struct cudbg_buffer *dbg_buff, 1299322014Snp struct cudbg_error *cudbg_err) 1300322014Snp{ 1301322014Snp struct adapter *padap = pdbg_init->adap; 1302322014Snp int rc = -1; 1303322014Snp 1304322014Snp if (is_t5(padap)) 1305322014Snp rc = t5_wtp_data(pdbg_init, dbg_buff, cudbg_err); 1306322014Snp else if (is_t6(padap)) 1307322014Snp rc = t6_wtp_data(pdbg_init, dbg_buff, cudbg_err); 1308322014Snp 1309322014Snp return rc; 1310322014Snp} 1311