1218792Snp/*- 2295778Snp * Copyright (c) 2011, 2016 Chelsio Communications, Inc. 3218792Snp * All rights reserved. 4218792Snp * 5218792Snp * Redistribution and use in source and binary forms, with or without 6218792Snp * modification, are permitted provided that the following conditions 7218792Snp * are met: 8218792Snp * 1. Redistributions of source code must retain the above copyright 9218792Snp * notice, this list of conditions and the following disclaimer. 10218792Snp * 2. Redistributions in binary form must reproduce the above copyright 11218792Snp * notice, this list of conditions and the following disclaimer in the 12218792Snp * documentation and/or other materials provided with the distribution. 13218792Snp * 14218792Snp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15218792Snp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16218792Snp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17218792Snp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18218792Snp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19218792Snp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20218792Snp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21218792Snp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22218792Snp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23218792Snp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24218792Snp * SUCH DAMAGE. 25218792Snp * 26218792Snp * $FreeBSD: stable/11/sys/dev/cxgbe/common/t4_regs_values.h 355250 2019-11-30 20:42:18Z np $ 27218792Snp * 28218792Snp */ 29218792Snp 30218792Snp#ifndef __T4_REGS_VALUES_H__ 31218792Snp#define __T4_REGS_VALUES_H__ 32218792Snp 33218792Snp/* 34218792Snp * This file contains definitions for various T4 register value hardware 35218792Snp * constants. The types of values encoded here are predominantly those for 36218792Snp * register fields which control "modal" behavior. For the most part, we do 37218792Snp * not include definitions for register fields which are simple numeric 38218792Snp * metrics, etc. 39218792Snp * 40218792Snp * These new "modal values" use a naming convention which matches the 41218792Snp * currently existing macros in t4_reg.h. For register field FOO which would 42218792Snp * have S_FOO, M_FOO, V_FOO() and G_FOO() macros, we introduce X_FOO_{MODE} 43218792Snp * definitions. These can be used as V_FOO(X_FOO_MODE) or as (G_FOO(x) == 44218792Snp * X_FOO_MODE). 45218792Snp * 46218792Snp * Note that this should all be part of t4_regs.h but the toolset used to 47218792Snp * generate that file doesn't [yet] have the capability of collecting these 48218792Snp * constants. 49218792Snp */ 50218792Snp 51218792Snp/* 52218792Snp * SGE definitions. 53218792Snp * ================ 54218792Snp */ 55218792Snp 56218792Snp/* 57218792Snp * SGE register field values. 58218792Snp */ 59218792Snp 60218792Snp/* CONTROL register */ 61218792Snp#define X_FLSPLITMODE_FLSPLITMIN 0 62218792Snp#define X_FLSPLITMODE_ETHHDR 1 63218792Snp#define X_FLSPLITMODE_IPHDR 2 64218792Snp#define X_FLSPLITMODE_TCPHDR 3 65218792Snp 66218792Snp#define X_DCASYSTYPE_FSB 0 67218792Snp#define X_DCASYSTYPE_CSI 1 68218792Snp 69218792Snp#define X_EGSTATPAGESIZE_64B 0 70218792Snp#define X_EGSTATPAGESIZE_128B 1 71218792Snp 72218792Snp#define X_RXPKTCPLMODE_DATA 0 73218792Snp#define X_RXPKTCPLMODE_SPLIT 1 74218792Snp 75218792Snp#define X_INGPCIEBOUNDARY_SHIFT 5 76218792Snp#define X_INGPCIEBOUNDARY_32B 0 77218792Snp#define X_INGPCIEBOUNDARY_64B 1 78218792Snp#define X_INGPCIEBOUNDARY_128B 2 79218792Snp#define X_INGPCIEBOUNDARY_256B 3 80218792Snp#define X_INGPCIEBOUNDARY_512B 4 81218792Snp#define X_INGPCIEBOUNDARY_1024B 5 82218792Snp#define X_INGPCIEBOUNDARY_2048B 6 83218792Snp#define X_INGPCIEBOUNDARY_4096B 7 84218792Snp 85295778Snp#define X_T6_INGPADBOUNDARY_SHIFT 3 86295778Snp#define X_T6_INGPADBOUNDARY_8B 0 87295778Snp#define X_T6_INGPADBOUNDARY_16B 1 88295778Snp#define X_T6_INGPADBOUNDARY_32B 2 89295778Snp#define X_T6_INGPADBOUNDARY_64B 3 90295778Snp#define X_T6_INGPADBOUNDARY_128B 4 91295778Snp#define X_T6_INGPADBOUNDARY_256B 5 92295778Snp#define X_T6_INGPADBOUNDARY_512B 6 93295778Snp#define X_T6_INGPADBOUNDARY_1024B 7 94295778Snp 95218792Snp#define X_INGPADBOUNDARY_SHIFT 5 96218792Snp#define X_INGPADBOUNDARY_32B 0 97218792Snp#define X_INGPADBOUNDARY_64B 1 98218792Snp#define X_INGPADBOUNDARY_128B 2 99218792Snp#define X_INGPADBOUNDARY_256B 3 100218792Snp#define X_INGPADBOUNDARY_512B 4 101218792Snp#define X_INGPADBOUNDARY_1024B 5 102218792Snp#define X_INGPADBOUNDARY_2048B 6 103218792Snp#define X_INGPADBOUNDARY_4096B 7 104218792Snp 105218792Snp#define X_EGRPCIEBOUNDARY_SHIFT 5 106218792Snp#define X_EGRPCIEBOUNDARY_32B 0 107218792Snp#define X_EGRPCIEBOUNDARY_64B 1 108218792Snp#define X_EGRPCIEBOUNDARY_128B 2 109218792Snp#define X_EGRPCIEBOUNDARY_256B 3 110218792Snp#define X_EGRPCIEBOUNDARY_512B 4 111218792Snp#define X_EGRPCIEBOUNDARY_1024B 5 112218792Snp#define X_EGRPCIEBOUNDARY_2048B 6 113218792Snp#define X_EGRPCIEBOUNDARY_4096B 7 114218792Snp 115295778Snp/* CONTROL2 register */ 116295778Snp#define X_INGPACKBOUNDARY_SHIFT 5 // *most* of the values ... 117295778Snp#define X_INGPACKBOUNDARY_16B 0 // Note weird value! 118295778Snp#define X_INGPACKBOUNDARY_64B 1 119295778Snp#define X_INGPACKBOUNDARY_128B 2 120295778Snp#define X_INGPACKBOUNDARY_256B 3 121295778Snp#define X_INGPACKBOUNDARY_512B 4 122295778Snp#define X_INGPACKBOUNDARY_1024B 5 123295778Snp#define X_INGPACKBOUNDARY_2048B 6 124295778Snp#define X_INGPACKBOUNDARY_4096B 7 125295778Snp 126218792Snp/* GTS register */ 127218792Snp#define SGE_TIMERREGS 6 128218792Snp#define X_TIMERREG_COUNTER0 0 129218792Snp#define X_TIMERREG_COUNTER1 1 130218792Snp#define X_TIMERREG_COUNTER2 2 131218792Snp#define X_TIMERREG_COUNTER3 3 132218792Snp#define X_TIMERREG_COUNTER4 4 133218792Snp#define X_TIMERREG_COUNTER5 5 134218792Snp#define X_TIMERREG_RESTART_COUNTER 6 135218792Snp#define X_TIMERREG_UPDATE_CIDX 7 136218792Snp 137218792Snp/* 138218792Snp * Egress Context field values 139218792Snp */ 140218792Snp#define EC_WR_UNITS 16 141218792Snp 142218792Snp#define X_FETCHBURSTMIN_SHIFT 4 143218792Snp#define X_FETCHBURSTMIN_16B 0 144218792Snp#define X_FETCHBURSTMIN_32B 1 145218792Snp#define X_FETCHBURSTMIN_64B 2 146218792Snp#define X_FETCHBURSTMIN_128B 3 147218792Snp 148355250Snp/* T6 and later use a single-bit encoding for FetchBurstMin */ 149355250Snp#define X_FETCHBURSTMIN_SHIFT_T6 6 150355250Snp#define X_FETCHBURSTMIN_64B_T6 0 151355250Snp#define X_FETCHBURSTMIN_128B_T6 1 152355250Snp 153218792Snp#define X_FETCHBURSTMAX_SHIFT 6 154218792Snp#define X_FETCHBURSTMAX_64B 0 155218792Snp#define X_FETCHBURSTMAX_128B 1 156218792Snp#define X_FETCHBURSTMAX_256B 2 157218792Snp#define X_FETCHBURSTMAX_512B 3 158218792Snp 159218792Snp#define X_HOSTFCMODE_NONE 0 160218792Snp#define X_HOSTFCMODE_INGRESS_QUEUE 1 161218792Snp#define X_HOSTFCMODE_STATUS_PAGE 2 162218792Snp#define X_HOSTFCMODE_BOTH 3 163218792Snp 164218792Snp#define X_HOSTFCOWNER_UP 0 165218792Snp#define X_HOSTFCOWNER_SGE 1 166218792Snp 167218792Snp#define X_CIDXFLUSHTHRESH_1 0 168218792Snp#define X_CIDXFLUSHTHRESH_2 1 169218792Snp#define X_CIDXFLUSHTHRESH_4 2 170218792Snp#define X_CIDXFLUSHTHRESH_8 3 171218792Snp#define X_CIDXFLUSHTHRESH_16 4 172218792Snp#define X_CIDXFLUSHTHRESH_32 5 173218792Snp#define X_CIDXFLUSHTHRESH_64 6 174218792Snp#define X_CIDXFLUSHTHRESH_128 7 175218792Snp 176218792Snp#define X_IDXSIZE_UNIT 64 177218792Snp 178218792Snp#define X_BASEADDRESS_ALIGN 512 179218792Snp 180218792Snp/* 181218792Snp * Ingress Context field values 182218792Snp */ 183218792Snp#define X_UPDATESCHEDULING_TIMER 0 184218792Snp#define X_UPDATESCHEDULING_COUNTER_OPTTIMER 1 185218792Snp 186218792Snp#define X_UPDATEDELIVERY_NONE 0 187218792Snp#define X_UPDATEDELIVERY_INTERRUPT 1 188218792Snp#define X_UPDATEDELIVERY_STATUS_PAGE 2 189218792Snp#define X_UPDATEDELIVERY_BOTH 3 190218792Snp 191218792Snp#define X_INTERRUPTDESTINATION_PCIE 0 192218792Snp#define X_INTERRUPTDESTINATION_IQ 1 193218792Snp 194218792Snp#define X_QUEUEENTRYSIZE_16B 0 195218792Snp#define X_QUEUEENTRYSIZE_32B 1 196218792Snp#define X_QUEUEENTRYSIZE_64B 2 197218792Snp#define X_QUEUEENTRYSIZE_128B 3 198218792Snp 199218792Snp#define IC_SIZE_UNIT 16 200218792Snp#define IC_BASEADDRESS_ALIGN 512 201218792Snp 202218792Snp#define X_RSPD_TYPE_FLBUF 0 203218792Snp#define X_RSPD_TYPE_CPL 1 204218792Snp#define X_RSPD_TYPE_INTR 2 205218792Snp 206218792Snp/* 207295778Snp * Context field definitions. This is by no means a complete list of SGE 208295778Snp * Context fields. In the vast majority of cases the firmware initializes 209295778Snp * things the way they need to be set up. But in a few small cases, we need 210295778Snp * to compute new values and ship them off to the firmware to be applied to 211295778Snp * the SGE Conexts ... 212295778Snp */ 213295778Snp 214295778Snp/* 215295778Snp * Congestion Manager Definitions. 216295778Snp */ 217295778Snp#define S_CONMCTXT_CNGTPMODE 19 218295778Snp#define M_CONMCTXT_CNGTPMODE 0x3 219295778Snp#define V_CONMCTXT_CNGTPMODE(x) ((x) << S_CONMCTXT_CNGTPMODE) 220295778Snp#define G_CONMCTXT_CNGTPMODE(x) \ 221295778Snp (((x) >> S_CONMCTXT_CNGTPMODE) & M_CONMCTXT_CNGTPMODE) 222295778Snp#define S_CONMCTXT_CNGCHMAP 0 223295778Snp#define M_CONMCTXT_CNGCHMAP 0xffff 224295778Snp#define V_CONMCTXT_CNGCHMAP(x) ((x) << S_CONMCTXT_CNGCHMAP) 225295778Snp#define G_CONMCTXT_CNGCHMAP(x) \ 226295778Snp (((x) >> S_CONMCTXT_CNGCHMAP) & M_CONMCTXT_CNGCHMAP) 227295778Snp 228295778Snp#define X_CONMCTXT_CNGTPMODE_DISABLE 0 229295778Snp#define X_CONMCTXT_CNGTPMODE_QUEUE 1 230295778Snp#define X_CONMCTXT_CNGTPMODE_CHANNEL 2 231295778Snp#define X_CONMCTXT_CNGTPMODE_BOTH 3 232295778Snp 233295778Snp/* 234295778Snp * T5 and later support a new BAR2-based doorbell mechanism for Egress Queues. 235295778Snp * The User Doorbells are each 128 bytes in length with a Simple Doorbell at 236295778Snp * offsets 8x and a Write Combining single 64-byte Egress Queue Unit 237295778Snp * (X_IDXSIZE_UNIT) Gather Buffer interface at offset 64. For Ingress Queues, 238295778Snp * we have a Going To Sleep register at offsets 8x+4. 239295778Snp * 240295778Snp * As noted above, we have many instances of the Simple Doorbell and Going To 241295778Snp * Sleep registers at offsets 8x and 8x+4, respectively. We want to use a 242295778Snp * non-64-byte aligned offset for the Simple Doorbell in order to attempt to 243295778Snp * avoid buffering of the writes to the Simple Doorbell and we want to use a 244295778Snp * non-contiguous offset for the Going To Sleep writes in order to avoid 245295778Snp * possible combining between them. 246295778Snp */ 247295778Snp#define SGE_UDB_SIZE 128 248295778Snp#define SGE_UDB_KDOORBELL 8 249295778Snp#define SGE_UDB_GTS 20 250295778Snp#define SGE_UDB_WCDOORBELL 64 251295778Snp 252295778Snp/* 253218792Snp * CIM definitions. 254218792Snp * ================ 255218792Snp */ 256218792Snp 257218792Snp/* 258218792Snp * CIM register field values. 259218792Snp */ 260218792Snp#define X_MBOWNER_NONE 0 261218792Snp#define X_MBOWNER_FW 1 262218792Snp#define X_MBOWNER_PL 2 263295778Snp#define X_MBOWNER_FW_DEFERRED 3 264218792Snp 265252705Snp/* 266252705Snp * PCI-E definitions. 267252705Snp * ================== 268252705Snp */ 269252705Snp 270252705Snp#define X_WINDOW_SHIFT 10 271252705Snp#define X_PCIEOFST_SHIFT 10 272252705Snp 273252705Snp/* 274252705Snp * TP definitions. 275252705Snp * =============== 276252705Snp */ 277252705Snp 278252705Snp/* 279252705Snp * TP_VLAN_PRI_MAP controls which subset of fields will be present in the 280252705Snp * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP 281252705Snp * selects for a particular field being present. These fields, when present 282252705Snp * in the Compressed Filter Tuple, have the following widths in bits. 283252705Snp */ 284295778Snp#define S_FT_FIRST S_FCOE 285295778Snp#define S_FT_LAST S_FRAGMENTATION 286295778Snp 287252705Snp#define W_FT_FCOE 1 288252705Snp#define W_FT_PORT 3 289252705Snp#define W_FT_VNIC_ID 17 290252705Snp#define W_FT_VLAN 17 291252705Snp#define W_FT_TOS 8 292252705Snp#define W_FT_PROTOCOL 8 293252705Snp#define W_FT_ETHERTYPE 16 294252705Snp#define W_FT_MACMATCH 9 295252705Snp#define W_FT_MPSHITTYPE 3 296252705Snp#define W_FT_FRAGMENTATION 1 297252705Snp 298346855Snp#define M_FT_FCOE ((1ULL << W_FT_FCOE) - 1) 299346855Snp#define M_FT_PORT ((1ULL << W_FT_PORT) - 1) 300346855Snp#define M_FT_VNIC_ID ((1ULL << W_FT_VNIC_ID) - 1) 301346855Snp#define M_FT_VLAN ((1ULL << W_FT_VLAN) - 1) 302346855Snp#define M_FT_TOS ((1ULL << W_FT_TOS) - 1) 303346855Snp#define M_FT_PROTOCOL ((1ULL << W_FT_PROTOCOL) - 1) 304346855Snp#define M_FT_ETHERTYPE ((1ULL << W_FT_ETHERTYPE) - 1) 305346855Snp#define M_FT_MACMATCH ((1ULL << W_FT_MACMATCH) - 1) 306346855Snp#define M_FT_MPSHITTYPE ((1ULL << W_FT_MPSHITTYPE) - 1) 307346855Snp#define M_FT_FRAGMENTATION ((1ULL << W_FT_FRAGMENTATION) - 1) 308346855Snp 309252705Snp/* 310252705Snp * Some of the Compressed Filter Tuple fields have internal structure. These 311252705Snp * bit shifts/masks describe those structures. All shifts are relative to the 312252705Snp * base position of the fields within the Compressed Filter Tuple 313252705Snp */ 314252705Snp#define S_FT_VLAN_VLD 16 315252705Snp#define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD) 316252705Snp#define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U) 317252705Snp 318252705Snp#define S_FT_VNID_ID_VF 0 319252705Snp#define M_FT_VNID_ID_VF 0x7fU 320252705Snp#define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF) 321252705Snp#define G_FT_VNID_ID_VF(x) (((x) >> S_FT_VNID_ID_VF) & M_FT_VNID_ID_VF) 322252705Snp 323252705Snp#define S_FT_VNID_ID_PF 7 324252705Snp#define M_FT_VNID_ID_PF 0x7U 325252705Snp#define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF) 326252705Snp#define G_FT_VNID_ID_PF(x) (((x) >> S_FT_VNID_ID_PF) & M_FT_VNID_ID_PF) 327252705Snp 328252705Snp#define S_FT_VNID_ID_VLD 16 329252705Snp#define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD) 330252705Snp#define F_FT_VNID_ID_VLD(x) V_FT_VNID_ID_VLD(1U) 331252705Snp 332218792Snp#endif /* __T4_REGS_VALUES_H__ */ 333