1/*- 2 * Copyright (c) 2011, 2016 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/11/sys/dev/cxgbe/common/t4_msg.h 346863 2019-04-29 00:40:02Z np $ 27 * 28 */ 29 30#ifndef T4_MSG_H 31#define T4_MSG_H 32 33enum { 34 CPL_PASS_OPEN_REQ = 0x1, 35 CPL_PASS_ACCEPT_RPL = 0x2, 36 CPL_ACT_OPEN_REQ = 0x3, 37 CPL_SET_TCB = 0x4, 38 CPL_SET_TCB_FIELD = 0x5, 39 CPL_GET_TCB = 0x6, 40 CPL_CLOSE_CON_REQ = 0x8, 41 CPL_CLOSE_LISTSRV_REQ = 0x9, 42 CPL_ABORT_REQ = 0xA, 43 CPL_ABORT_RPL = 0xB, 44 CPL_TX_DATA = 0xC, 45 CPL_RX_DATA_ACK = 0xD, 46 CPL_TX_PKT = 0xE, 47 CPL_RTE_DELETE_REQ = 0xF, 48 CPL_RTE_WRITE_REQ = 0x10, 49 CPL_RTE_READ_REQ = 0x11, 50 CPL_L2T_WRITE_REQ = 0x12, 51 CPL_L2T_READ_REQ = 0x13, 52 CPL_SMT_WRITE_REQ = 0x14, 53 CPL_SMT_READ_REQ = 0x15, 54 CPL_TAG_WRITE_REQ = 0x16, 55 CPL_BARRIER = 0x18, 56 CPL_TID_RELEASE = 0x1A, 57 CPL_TAG_READ_REQ = 0x1B, 58 CPL_SRQ_TABLE_REQ = 0x1C, 59 CPL_TX_PKT_FSO = 0x1E, 60 CPL_TX_DATA_ISO = 0x1F, 61 62 CPL_CLOSE_LISTSRV_RPL = 0x20, 63 CPL_ERROR = 0x21, 64 CPL_GET_TCB_RPL = 0x22, 65 CPL_L2T_WRITE_RPL = 0x23, 66 CPL_PASS_OPEN_RPL = 0x24, 67 CPL_ACT_OPEN_RPL = 0x25, 68 CPL_PEER_CLOSE = 0x26, 69 CPL_RTE_DELETE_RPL = 0x27, 70 CPL_RTE_WRITE_RPL = 0x28, 71 CPL_RX_URG_PKT = 0x29, 72 CPL_TAG_WRITE_RPL = 0x2A, 73 CPL_ABORT_REQ_RSS = 0x2B, 74 CPL_RX_URG_NOTIFY = 0x2C, 75 CPL_ABORT_RPL_RSS = 0x2D, 76 CPL_SMT_WRITE_RPL = 0x2E, 77 CPL_TX_DATA_ACK = 0x2F, 78 79 CPL_RX_PHYS_ADDR = 0x30, 80 CPL_PCMD_READ_RPL = 0x31, 81 CPL_CLOSE_CON_RPL = 0x32, 82 CPL_ISCSI_HDR = 0x33, 83 CPL_L2T_READ_RPL = 0x34, 84 CPL_RDMA_CQE = 0x35, 85 CPL_RDMA_CQE_READ_RSP = 0x36, 86 CPL_RDMA_CQE_ERR = 0x37, 87 CPL_RTE_READ_RPL = 0x38, 88 CPL_RX_DATA = 0x39, 89 CPL_SET_TCB_RPL = 0x3A, 90 CPL_RX_PKT = 0x3B, 91 CPL_TAG_READ_RPL = 0x3C, 92 CPL_HIT_NOTIFY = 0x3D, 93 CPL_PKT_NOTIFY = 0x3E, 94 CPL_RX_DDP_COMPLETE = 0x3F, 95 96 CPL_ACT_ESTABLISH = 0x40, 97 CPL_PASS_ESTABLISH = 0x41, 98 CPL_RX_DATA_DDP = 0x42, 99 CPL_SMT_READ_RPL = 0x43, 100 CPL_PASS_ACCEPT_REQ = 0x44, 101 CPL_RX_ISCSI_CMP = 0x45, 102 CPL_RX_FCOE_DDP = 0x46, 103 CPL_FCOE_HDR = 0x47, 104 CPL_T5_TRACE_PKT = 0x48, 105 CPL_RX_ISCSI_DDP = 0x49, 106 CPL_RX_FCOE_DIF = 0x4A, 107 CPL_RX_DATA_DIF = 0x4B, 108 CPL_ERR_NOTIFY = 0x4D, 109 CPL_RX_TLS_CMP = 0x4E, 110 111 CPL_RDMA_READ_REQ = 0x60, 112 CPL_RX_ISCSI_DIF = 0x60, 113 114 CPL_SET_LE_REQ = 0x80, 115 CPL_PASS_OPEN_REQ6 = 0x81, 116 CPL_ACT_OPEN_REQ6 = 0x83, 117 CPL_TX_TLS_PDU = 0x88, 118 CPL_TX_TLS_SFO = 0x89, 119 120 CPL_TX_SEC_PDU = 0x8A, 121 CPL_TX_TLS_ACK = 0x8B, 122 123 CPL_RDMA_TERMINATE = 0xA2, 124 CPL_RDMA_WRITE = 0xA4, 125 CPL_SGE_EGR_UPDATE = 0xA5, 126 CPL_SET_LE_RPL = 0xA6, 127 CPL_FW2_MSG = 0xA7, 128 CPL_FW2_PLD = 0xA8, 129 CPL_T5_RDMA_READ_REQ = 0xA9, 130 CPL_RDMA_ATOMIC_REQ = 0xAA, 131 CPL_RDMA_ATOMIC_RPL = 0xAB, 132 CPL_RDMA_IMM_DATA = 0xAC, 133 CPL_RDMA_IMM_DATA_SE = 0xAD, 134 CPL_RX_MPS_PKT = 0xAF, 135 136 CPL_TRACE_PKT = 0xB0, 137 CPL_RX2TX_DATA = 0xB1, 138 CPL_TLS_DATA = 0xB1, 139 CPL_ISCSI_DATA = 0xB2, 140 CPL_FCOE_DATA = 0xB3, 141 142 CPL_FW4_MSG = 0xC0, 143 CPL_FW4_PLD = 0xC1, 144 CPL_FW4_ACK = 0xC3, 145 CPL_SRQ_TABLE_RPL = 0xCC, 146 CPL_RX_PHYS_DSGL = 0xD0, 147 148 CPL_FW6_MSG = 0xE0, 149 CPL_FW6_PLD = 0xE1, 150 CPL_TX_TNL_LSO = 0xEC, 151 CPL_TX_PKT_LSO = 0xED, 152 CPL_TX_PKT_XT = 0xEE, 153 154 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 155}; 156 157enum CPL_error { 158 CPL_ERR_NONE = 0, 159 CPL_ERR_TCAM_PARITY = 1, 160 CPL_ERR_TCAM_MISS = 2, 161 CPL_ERR_TCAM_FULL = 3, 162 CPL_ERR_BAD_LENGTH = 15, 163 CPL_ERR_BAD_ROUTE = 18, 164 CPL_ERR_CONN_RESET = 20, 165 CPL_ERR_CONN_EXIST_SYNRECV = 21, 166 CPL_ERR_CONN_EXIST = 22, 167 CPL_ERR_ARP_MISS = 23, 168 CPL_ERR_BAD_SYN = 24, 169 CPL_ERR_CONN_TIMEDOUT = 30, 170 CPL_ERR_XMIT_TIMEDOUT = 31, 171 CPL_ERR_PERSIST_TIMEDOUT = 32, 172 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 173 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 174 CPL_ERR_RTX_NEG_ADVICE = 35, 175 CPL_ERR_PERSIST_NEG_ADVICE = 36, 176 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 177 CPL_ERR_WAIT_ARP_RPL = 41, 178 CPL_ERR_ABORT_FAILED = 42, 179 CPL_ERR_IWARP_FLM = 50, 180 CPL_CONTAINS_READ_RPL = 60, 181 CPL_CONTAINS_WRITE_RPL = 61, 182}; 183 184/* 185 * Some of the error codes above implicitly indicate that there is no TID 186 * allocated with the result of an ACT_OPEN. We use this predicate to make 187 * that explicit. 188 */ 189static inline int act_open_has_tid(int status) 190{ 191 return (status != CPL_ERR_TCAM_PARITY && 192 status != CPL_ERR_TCAM_MISS && 193 status != CPL_ERR_TCAM_FULL && 194 status != CPL_ERR_CONN_EXIST_SYNRECV && 195 status != CPL_ERR_CONN_EXIST); 196} 197 198/* 199 * Convert an ACT_OPEN_RPL status to an errno. 200 */ 201static inline int 202act_open_rpl_status_to_errno(int status) 203{ 204 205 switch (status) { 206 case CPL_ERR_CONN_RESET: 207 return (ECONNREFUSED); 208 case CPL_ERR_ARP_MISS: 209 return (EHOSTUNREACH); 210 case CPL_ERR_CONN_TIMEDOUT: 211 return (ETIMEDOUT); 212 case CPL_ERR_TCAM_FULL: 213 return (EAGAIN); 214 case CPL_ERR_CONN_EXIST: 215 return (EAGAIN); 216 default: 217 return (EIO); 218 } 219} 220 221 222enum { 223 CPL_CONN_POLICY_AUTO = 0, 224 CPL_CONN_POLICY_ASK = 1, 225 CPL_CONN_POLICY_FILTER = 2, 226 CPL_CONN_POLICY_DENY = 3 227}; 228 229enum { 230 ULP_MODE_NONE = 0, 231 ULP_MODE_ISCSI = 2, 232 ULP_MODE_RDMA = 4, 233 ULP_MODE_TCPDDP = 5, 234 ULP_MODE_FCOE = 6, 235 ULP_MODE_TLS = 8, 236}; 237 238enum { 239 ULP_CRC_HEADER = 1 << 0, 240 ULP_CRC_DATA = 1 << 1 241}; 242 243enum { 244 CPL_PASS_OPEN_ACCEPT, 245 CPL_PASS_OPEN_REJECT, 246 CPL_PASS_OPEN_ACCEPT_TNL 247}; 248 249enum { 250 CPL_ABORT_SEND_RST = 0, 251 CPL_ABORT_NO_RST, 252}; 253 254enum { /* TX_PKT_XT checksum types */ 255 TX_CSUM_TCP = 0, 256 TX_CSUM_UDP = 1, 257 TX_CSUM_CRC16 = 4, 258 TX_CSUM_CRC32 = 5, 259 TX_CSUM_CRC32C = 6, 260 TX_CSUM_FCOE = 7, 261 TX_CSUM_TCPIP = 8, 262 TX_CSUM_UDPIP = 9, 263 TX_CSUM_TCPIP6 = 10, 264 TX_CSUM_UDPIP6 = 11, 265 TX_CSUM_IP = 12, 266}; 267 268enum { /* packet type in CPL_RX_PKT */ 269 PKTYPE_XACT_UCAST = 0, 270 PKTYPE_HASH_UCAST = 1, 271 PKTYPE_XACT_MCAST = 2, 272 PKTYPE_HASH_MCAST = 3, 273 PKTYPE_PROMISC = 4, 274 PKTYPE_HPROMISC = 5, 275 PKTYPE_BCAST = 6 276}; 277 278enum { /* DMAC type in CPL_RX_PKT */ 279 DATYPE_UCAST, 280 DATYPE_MCAST, 281 DATYPE_BCAST 282}; 283 284enum { /* TCP congestion control algorithms */ 285 CONG_ALG_RENO, 286 CONG_ALG_TAHOE, 287 CONG_ALG_NEWRENO, 288 CONG_ALG_HIGHSPEED 289}; 290 291enum { /* RSS hash type */ 292 RSS_HASH_NONE = 0, /* no hash computed */ 293 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 294 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 295 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 296}; 297 298enum { /* LE commands */ 299 LE_CMD_READ = 0x4, 300 LE_CMD_WRITE = 0xb 301}; 302 303enum { /* LE request size */ 304 LE_SZ_NONE = 0, 305 LE_SZ_33 = 1, 306 LE_SZ_66 = 2, 307 LE_SZ_132 = 3, 308 LE_SZ_264 = 4, 309 LE_SZ_528 = 5 310}; 311 312union opcode_tid { 313 __be32 opcode_tid; 314 __u8 opcode; 315}; 316 317#define S_CPL_OPCODE 24 318#define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 319#define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 320#define G_TID(x) ((x) & 0xFFFFFF) 321 322/* tid is assumed to be 24-bits */ 323#define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 324 325#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 326 327/* extract the TID from a CPL command */ 328#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 329#define GET_OPCODE(cmd) ((cmd)->ot.opcode) 330 331/* partitioning of TID fields that also carry a queue id */ 332#define S_TID_TID 0 333#define M_TID_TID 0x7ff 334#define V_TID_TID(x) ((x) << S_TID_TID) 335#define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 336 337#define S_TID_COOKIE 11 338#define M_TID_COOKIE 0x7 339#define V_TID_COOKIE(x) ((x) << S_TID_COOKIE) 340#define G_TID_COOKIE(x) (((x) >> S_TID_COOKIE) & M_TID_COOKIE) 341 342#define S_TID_QID 14 343#define M_TID_QID 0x3ff 344#define V_TID_QID(x) ((x) << S_TID_QID) 345#define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 346 347union opcode_info { 348 __be64 opcode_info; 349 __u8 opcode; 350}; 351 352struct tcp_options { 353 __be16 mss; 354 __u8 wsf; 355#if defined(__LITTLE_ENDIAN_BITFIELD) 356 __u8 :4; 357 __u8 unknown:1; 358 __u8 ecn:1; 359 __u8 sack:1; 360 __u8 tstamp:1; 361#else 362 __u8 tstamp:1; 363 __u8 sack:1; 364 __u8 ecn:1; 365 __u8 unknown:1; 366 __u8 :4; 367#endif 368}; 369 370struct rss_header { 371 __u8 opcode; 372#if defined(__LITTLE_ENDIAN_BITFIELD) 373 __u8 channel:2; 374 __u8 filter_hit:1; 375 __u8 filter_tid:1; 376 __u8 hash_type:2; 377 __u8 ipv6:1; 378 __u8 send2fw:1; 379#else 380 __u8 send2fw:1; 381 __u8 ipv6:1; 382 __u8 hash_type:2; 383 __u8 filter_tid:1; 384 __u8 filter_hit:1; 385 __u8 channel:2; 386#endif 387 __be16 qid; 388 __be32 hash_val; 389}; 390 391#define S_HASHTYPE 20 392#define M_HASHTYPE 0x3 393#define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 394 395#define S_QNUM 0 396#define M_QNUM 0xFFFF 397#define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 398 399#if defined(RSS_HDR_VLD) || defined(CHELSIO_FW) 400# define RSS_HDR struct rss_header rss_hdr; 401#else 402# define RSS_HDR 403#endif 404 405#ifndef CHELSIO_FW 406struct work_request_hdr { 407 __be32 wr_hi; 408 __be32 wr_mid; 409 __be64 wr_lo; 410}; 411 412/* wr_mid fields */ 413#define S_WR_LEN16 0 414#define M_WR_LEN16 0xFF 415#define V_WR_LEN16(x) ((x) << S_WR_LEN16) 416#define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 417 418/* wr_hi fields */ 419#define S_WR_OP 24 420#define M_WR_OP 0xFF 421#define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 422#define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 423 424# define WR_HDR struct work_request_hdr wr 425# define WR_HDR_SIZE sizeof(struct work_request_hdr) 426#else 427# define WR_HDR 428# define WR_HDR_SIZE 0 429#endif 430 431/* option 0 fields */ 432#define S_ACCEPT_MODE 0 433#define M_ACCEPT_MODE 0x3 434#define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 435#define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 436 437#define S_TX_CHAN 2 438#define M_TX_CHAN 0x3 439#define V_TX_CHAN(x) ((x) << S_TX_CHAN) 440#define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 441 442#define S_NO_CONG 4 443#define V_NO_CONG(x) ((x) << S_NO_CONG) 444#define F_NO_CONG V_NO_CONG(1U) 445 446#define S_DELACK 5 447#define V_DELACK(x) ((x) << S_DELACK) 448#define F_DELACK V_DELACK(1U) 449 450#define S_INJECT_TIMER 6 451#define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 452#define F_INJECT_TIMER V_INJECT_TIMER(1U) 453 454#define S_NON_OFFLOAD 7 455#define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 456#define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 457 458#define S_ULP_MODE 8 459#define M_ULP_MODE 0xF 460#define V_ULP_MODE(x) ((x) << S_ULP_MODE) 461#define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 462 463#define S_RCV_BUFSIZ 12 464#define M_RCV_BUFSIZ 0x3FFU 465#define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 466#define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 467 468#define S_DSCP 22 469#define M_DSCP 0x3F 470#define V_DSCP(x) ((x) << S_DSCP) 471#define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 472 473#define S_SMAC_SEL 28 474#define M_SMAC_SEL 0xFF 475#define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 476#define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 477 478#define S_L2T_IDX 36 479#define M_L2T_IDX 0xFFF 480#define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 481#define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 482 483#define S_TCAM_BYPASS 48 484#define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 485#define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 486 487#define S_NAGLE 49 488#define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 489#define F_NAGLE V_NAGLE(1ULL) 490 491#define S_WND_SCALE 50 492#define M_WND_SCALE 0xF 493#define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 494#define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 495 496#define S_KEEP_ALIVE 54 497#define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 498#define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 499 500#define S_MAX_RT 55 501#define M_MAX_RT 0xF 502#define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 503#define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 504 505#define S_MAX_RT_OVERRIDE 59 506#define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 507#define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 508 509#define S_MSS_IDX 60 510#define M_MSS_IDX 0xF 511#define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 512#define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 513 514/* option 1 fields */ 515#define S_SYN_RSS_ENABLE 0 516#define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 517#define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 518 519#define S_SYN_RSS_USE_HASH 1 520#define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 521#define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 522 523#define S_SYN_RSS_QUEUE 2 524#define M_SYN_RSS_QUEUE 0x3FF 525#define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 526#define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 527 528#define S_LISTEN_INTF 12 529#define M_LISTEN_INTF 0xFF 530#define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 531#define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 532 533#define S_LISTEN_FILTER 20 534#define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 535#define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 536 537#define S_SYN_DEFENSE 21 538#define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 539#define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 540 541#define S_CONN_POLICY 22 542#define M_CONN_POLICY 0x3 543#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 544#define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 545 546#define S_T5_FILT_INFO 24 547#define M_T5_FILT_INFO 0xffffffffffULL 548#define V_T5_FILT_INFO(x) ((x) << S_T5_FILT_INFO) 549#define G_T5_FILT_INFO(x) (((x) >> S_T5_FILT_INFO) & M_T5_FILT_INFO) 550 551#define S_FILT_INFO 28 552#define M_FILT_INFO 0xfffffffffULL 553#define V_FILT_INFO(x) ((x) << S_FILT_INFO) 554#define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) 555 556/* option 2 fields */ 557#define S_RSS_QUEUE 0 558#define M_RSS_QUEUE 0x3FF 559#define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 560#define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 561 562#define S_RSS_QUEUE_VALID 10 563#define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 564#define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 565 566#define S_RX_COALESCE_VALID 11 567#define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 568#define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 569 570#define S_RX_COALESCE 12 571#define M_RX_COALESCE 0x3 572#define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 573#define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 574 575#define S_CONG_CNTRL 14 576#define M_CONG_CNTRL 0x3 577#define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 578#define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 579 580#define S_PACE 16 581#define M_PACE 0x3 582#define V_PACE(x) ((x) << S_PACE) 583#define G_PACE(x) (((x) >> S_PACE) & M_PACE) 584 585#define S_CONG_CNTRL_VALID 18 586#define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 587#define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 588 589#define S_T5_ISS 18 590#define V_T5_ISS(x) ((x) << S_T5_ISS) 591#define F_T5_ISS V_T5_ISS(1U) 592 593#define S_PACE_VALID 19 594#define V_PACE_VALID(x) ((x) << S_PACE_VALID) 595#define F_PACE_VALID V_PACE_VALID(1U) 596 597#define S_RX_FC_DISABLE 20 598#define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 599#define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 600 601#define S_RX_FC_DDP 21 602#define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 603#define F_RX_FC_DDP V_RX_FC_DDP(1U) 604 605#define S_RX_FC_VALID 22 606#define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 607#define F_RX_FC_VALID V_RX_FC_VALID(1U) 608 609#define S_TX_QUEUE 23 610#define M_TX_QUEUE 0x7 611#define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 612#define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 613 614#define S_RX_CHANNEL 26 615#define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 616#define F_RX_CHANNEL V_RX_CHANNEL(1U) 617 618#define S_CCTRL_ECN 27 619#define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 620#define F_CCTRL_ECN V_CCTRL_ECN(1U) 621 622#define S_WND_SCALE_EN 28 623#define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 624#define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 625 626#define S_TSTAMPS_EN 29 627#define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 628#define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 629 630#define S_SACK_EN 30 631#define V_SACK_EN(x) ((x) << S_SACK_EN) 632#define F_SACK_EN V_SACK_EN(1U) 633 634#define S_T5_OPT_2_VALID 31 635#define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID) 636#define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U) 637 638struct cpl_pass_open_req { 639 WR_HDR; 640 union opcode_tid ot; 641 __be16 local_port; 642 __be16 peer_port; 643 __be32 local_ip; 644 __be32 peer_ip; 645 __be64 opt0; 646 __be64 opt1; 647}; 648 649struct cpl_pass_open_req6 { 650 WR_HDR; 651 union opcode_tid ot; 652 __be16 local_port; 653 __be16 peer_port; 654 __be64 local_ip_hi; 655 __be64 local_ip_lo; 656 __be64 peer_ip_hi; 657 __be64 peer_ip_lo; 658 __be64 opt0; 659 __be64 opt1; 660}; 661 662struct cpl_pass_open_rpl { 663 RSS_HDR 664 union opcode_tid ot; 665 __u8 rsvd[3]; 666 __u8 status; 667}; 668 669struct cpl_pass_establish { 670 RSS_HDR 671 union opcode_tid ot; 672 __be32 rsvd; 673 __be32 tos_stid; 674 __be16 mac_idx; 675 __be16 tcp_opt; 676 __be32 snd_isn; 677 __be32 rcv_isn; 678}; 679 680/* cpl_pass_establish.tos_stid fields */ 681#define S_PASS_OPEN_TID 0 682#define M_PASS_OPEN_TID 0xFFFFFF 683#define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 684#define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 685 686#define S_PASS_OPEN_TOS 24 687#define M_PASS_OPEN_TOS 0xFF 688#define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 689#define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 690 691/* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 692#define S_TCPOPT_WSCALE_OK 5 693#define M_TCPOPT_WSCALE_OK 0x1 694#define V_TCPOPT_WSCALE_OK(x) ((x) << S_TCPOPT_WSCALE_OK) 695#define G_TCPOPT_WSCALE_OK(x) (((x) >> S_TCPOPT_WSCALE_OK) & M_TCPOPT_WSCALE_OK) 696 697#define S_TCPOPT_SACK 6 698#define M_TCPOPT_SACK 0x1 699#define V_TCPOPT_SACK(x) ((x) << S_TCPOPT_SACK) 700#define G_TCPOPT_SACK(x) (((x) >> S_TCPOPT_SACK) & M_TCPOPT_SACK) 701 702#define S_TCPOPT_TSTAMP 7 703#define M_TCPOPT_TSTAMP 0x1 704#define V_TCPOPT_TSTAMP(x) ((x) << S_TCPOPT_TSTAMP) 705#define G_TCPOPT_TSTAMP(x) (((x) >> S_TCPOPT_TSTAMP) & M_TCPOPT_TSTAMP) 706 707#define S_TCPOPT_SND_WSCALE 8 708#define M_TCPOPT_SND_WSCALE 0xF 709#define V_TCPOPT_SND_WSCALE(x) ((x) << S_TCPOPT_SND_WSCALE) 710#define G_TCPOPT_SND_WSCALE(x) (((x) >> S_TCPOPT_SND_WSCALE) & M_TCPOPT_SND_WSCALE) 711 712#define S_TCPOPT_MSS 12 713#define M_TCPOPT_MSS 0xF 714#define V_TCPOPT_MSS(x) ((x) << S_TCPOPT_MSS) 715#define G_TCPOPT_MSS(x) (((x) >> S_TCPOPT_MSS) & M_TCPOPT_MSS) 716 717struct cpl_pass_accept_req { 718 RSS_HDR 719 union opcode_tid ot; 720 __be16 rsvd; 721 __be16 len; 722 __be32 hdr_len; 723 __be16 vlan; 724 __be16 l2info; 725 __be32 tos_stid; 726 struct tcp_options tcpopt; 727}; 728 729/* cpl_pass_accept_req.hdr_len fields */ 730#define S_SYN_RX_CHAN 0 731#define M_SYN_RX_CHAN 0xF 732#define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 733#define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 734 735#define S_TCP_HDR_LEN 10 736#define M_TCP_HDR_LEN 0x3F 737#define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 738#define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 739 740#define S_T6_TCP_HDR_LEN 8 741#define V_T6_TCP_HDR_LEN(x) ((x) << S_T6_TCP_HDR_LEN) 742#define G_T6_TCP_HDR_LEN(x) (((x) >> S_T6_TCP_HDR_LEN) & M_TCP_HDR_LEN) 743 744#define S_IP_HDR_LEN 16 745#define M_IP_HDR_LEN 0x3FF 746#define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 747#define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 748 749#define S_T6_IP_HDR_LEN 14 750#define V_T6_IP_HDR_LEN(x) ((x) << S_T6_IP_HDR_LEN) 751#define G_T6_IP_HDR_LEN(x) (((x) >> S_T6_IP_HDR_LEN) & M_IP_HDR_LEN) 752 753#define S_ETH_HDR_LEN 26 754#define M_ETH_HDR_LEN 0x3F 755#define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 756#define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 757 758#define S_T6_ETH_HDR_LEN 24 759#define M_T6_ETH_HDR_LEN 0xFF 760#define V_T6_ETH_HDR_LEN(x) ((x) << S_T6_ETH_HDR_LEN) 761#define G_T6_ETH_HDR_LEN(x) (((x) >> S_T6_ETH_HDR_LEN) & M_T6_ETH_HDR_LEN) 762 763/* cpl_pass_accept_req.l2info fields */ 764#define S_SYN_MAC_IDX 0 765#define M_SYN_MAC_IDX 0x1FF 766#define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 767#define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 768 769#define S_SYN_XACT_MATCH 9 770#define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 771#define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 772 773#define S_SYN_INTF 12 774#define M_SYN_INTF 0xF 775#define V_SYN_INTF(x) ((x) << S_SYN_INTF) 776#define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 777 778struct cpl_pass_accept_rpl { 779 WR_HDR; 780 union opcode_tid ot; 781 __be32 opt2; 782 __be64 opt0; 783}; 784 785struct cpl_t5_pass_accept_rpl { 786 WR_HDR; 787 union opcode_tid ot; 788 __be32 opt2; 789 __be64 opt0; 790 __be32 iss; 791 union { 792 __be32 rsvd; /* T5 */ 793 __be32 opt3; /* T6 */ 794 } u; 795}; 796 797struct cpl_act_open_req { 798 WR_HDR; 799 union opcode_tid ot; 800 __be16 local_port; 801 __be16 peer_port; 802 __be32 local_ip; 803 __be32 peer_ip; 804 __be64 opt0; 805 __be32 params; 806 __be32 opt2; 807}; 808 809#define S_FILTER_TUPLE 24 810#define M_FILTER_TUPLE 0xFFFFFFFFFF 811#define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 812#define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 813struct cpl_t5_act_open_req { 814 WR_HDR; 815 union opcode_tid ot; 816 __be16 local_port; 817 __be16 peer_port; 818 __be32 local_ip; 819 __be32 peer_ip; 820 __be64 opt0; 821 __be32 iss; 822 __be32 opt2; 823 __be64 params; 824}; 825 826struct cpl_t6_act_open_req { 827 WR_HDR; 828 union opcode_tid ot; 829 __be16 local_port; 830 __be16 peer_port; 831 __be32 local_ip; 832 __be32 peer_ip; 833 __be64 opt0; 834 __be32 iss; 835 __be32 opt2; 836 __be64 params; 837 __be32 rsvd2; 838 __be32 opt3; 839}; 840 841/* cpl_{t5,t6}_act_open_req.params field */ 842#define S_AOPEN_FCOEMASK 0 843#define V_AOPEN_FCOEMASK(x) ((x) << S_AOPEN_FCOEMASK) 844#define F_AOPEN_FCOEMASK V_AOPEN_FCOEMASK(1U) 845 846struct cpl_act_open_req6 { 847 WR_HDR; 848 union opcode_tid ot; 849 __be16 local_port; 850 __be16 peer_port; 851 __be64 local_ip_hi; 852 __be64 local_ip_lo; 853 __be64 peer_ip_hi; 854 __be64 peer_ip_lo; 855 __be64 opt0; 856 __be32 params; 857 __be32 opt2; 858}; 859 860struct cpl_t5_act_open_req6 { 861 WR_HDR; 862 union opcode_tid ot; 863 __be16 local_port; 864 __be16 peer_port; 865 __be64 local_ip_hi; 866 __be64 local_ip_lo; 867 __be64 peer_ip_hi; 868 __be64 peer_ip_lo; 869 __be64 opt0; 870 __be32 iss; 871 __be32 opt2; 872 __be64 params; 873}; 874 875struct cpl_t6_act_open_req6 { 876 WR_HDR; 877 union opcode_tid ot; 878 __be16 local_port; 879 __be16 peer_port; 880 __be64 local_ip_hi; 881 __be64 local_ip_lo; 882 __be64 peer_ip_hi; 883 __be64 peer_ip_lo; 884 __be64 opt0; 885 __be32 iss; 886 __be32 opt2; 887 __be64 params; 888 __be32 rsvd2; 889 __be32 opt3; 890}; 891 892struct cpl_act_open_rpl { 893 RSS_HDR 894 union opcode_tid ot; 895 __be32 atid_status; 896}; 897 898/* cpl_act_open_rpl.atid_status fields */ 899#define S_AOPEN_STATUS 0 900#define M_AOPEN_STATUS 0xFF 901#define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 902#define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 903 904#define S_AOPEN_ATID 8 905#define M_AOPEN_ATID 0xFFFFFF 906#define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 907#define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 908 909struct cpl_act_establish { 910 RSS_HDR 911 union opcode_tid ot; 912 __be32 rsvd; 913 __be32 tos_atid; 914 __be16 mac_idx; 915 __be16 tcp_opt; 916 __be32 snd_isn; 917 __be32 rcv_isn; 918}; 919 920struct cpl_get_tcb { 921 WR_HDR; 922 union opcode_tid ot; 923 __be16 reply_ctrl; 924 __be16 cookie; 925}; 926 927/* cpl_get_tcb.reply_ctrl fields */ 928#define S_QUEUENO 0 929#define M_QUEUENO 0x3FF 930#define V_QUEUENO(x) ((x) << S_QUEUENO) 931#define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 932 933#define S_REPLY_CHAN 14 934#define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 935#define F_REPLY_CHAN V_REPLY_CHAN(1U) 936 937#define S_NO_REPLY 15 938#define V_NO_REPLY(x) ((x) << S_NO_REPLY) 939#define F_NO_REPLY V_NO_REPLY(1U) 940 941struct cpl_get_tcb_rpl { 942 RSS_HDR 943 union opcode_tid ot; 944 __u8 cookie; 945 __u8 status; 946 __be16 len; 947}; 948 949struct cpl_set_tcb { 950 WR_HDR; 951 union opcode_tid ot; 952 __be16 reply_ctrl; 953 __be16 cookie; 954}; 955 956struct cpl_set_tcb_field { 957 WR_HDR; 958 union opcode_tid ot; 959 __be16 reply_ctrl; 960 __be16 word_cookie; 961 __be64 mask; 962 __be64 val; 963}; 964 965struct cpl_set_tcb_field_core { 966 union opcode_tid ot; 967 __be16 reply_ctrl; 968 __be16 word_cookie; 969 __be64 mask; 970 __be64 val; 971}; 972 973/* cpl_set_tcb_field.word_cookie fields */ 974#define S_WORD 0 975#define M_WORD 0x1F 976#define V_WORD(x) ((x) << S_WORD) 977#define G_WORD(x) (((x) >> S_WORD) & M_WORD) 978 979#define S_COOKIE 5 980#define M_COOKIE 0x7 981#define V_COOKIE(x) ((x) << S_COOKIE) 982#define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 983 984struct cpl_set_tcb_rpl { 985 RSS_HDR 986 union opcode_tid ot; 987 __be16 rsvd; 988 __u8 cookie; 989 __u8 status; 990 __be64 oldval; 991}; 992 993struct cpl_close_con_req { 994 WR_HDR; 995 union opcode_tid ot; 996 __be32 rsvd; 997}; 998 999struct cpl_close_con_rpl { 1000 RSS_HDR 1001 union opcode_tid ot; 1002 __u8 rsvd[3]; 1003 __u8 status; 1004 __be32 snd_nxt; 1005 __be32 rcv_nxt; 1006}; 1007 1008struct cpl_close_listsvr_req { 1009 WR_HDR; 1010 union opcode_tid ot; 1011 __be16 reply_ctrl; 1012 __be16 rsvd; 1013}; 1014 1015/* additional cpl_close_listsvr_req.reply_ctrl field */ 1016#define S_LISTSVR_IPV6 14 1017#define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 1018#define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 1019 1020struct cpl_close_listsvr_rpl { 1021 RSS_HDR 1022 union opcode_tid ot; 1023 __u8 rsvd[3]; 1024 __u8 status; 1025}; 1026 1027struct cpl_abort_req_rss { 1028 RSS_HDR 1029 union opcode_tid ot; 1030 __u8 rsvd[3]; 1031 __u8 status; 1032}; 1033 1034struct cpl_abort_req_rss6 { 1035 RSS_HDR 1036 union opcode_tid ot; 1037 __u32 srqidx_status; 1038}; 1039 1040#define S_ABORT_RSS_STATUS 0 1041#define M_ABORT_RSS_STATUS 0xff 1042#define V_ABORT_RSS_STATUS(x) ((x) << S_ABORT_RSS_STATUS) 1043#define G_ABORT_RSS_STATUS(x) (((x) >> S_ABORT_RSS_STATUS) & M_ABORT_RSS_STATUS) 1044 1045#define S_ABORT_RSS_SRQIDX 8 1046#define M_ABORT_RSS_SRQIDX 0xffffff 1047#define V_ABORT_RSS_SRQIDX(x) ((x) << S_ABORT_RSS_SRQIDX) 1048#define G_ABORT_RSS_SRQIDX(x) (((x) >> S_ABORT_RSS_SRQIDX) & M_ABORT_RSS_SRQIDX) 1049 1050 1051/* cpl_abort_req status command code in case of T6, 1052 * bit[0] specifies whether to send RST (0) to remote peer or suppress it (1) 1053 * bit[1] indicates ABORT_REQ was sent after a CLOSE_CON_REQ 1054 * bit[2] specifies whether to disable the mmgr (1) or not (0) 1055 */ 1056struct cpl_abort_req { 1057 WR_HDR; 1058 union opcode_tid ot; 1059 __be32 rsvd0; 1060 __u8 rsvd1; 1061 __u8 cmd; 1062 __u8 rsvd2[6]; 1063}; 1064 1065struct cpl_abort_req_core { 1066 union opcode_tid ot; 1067 __be32 rsvd0; 1068 __u8 rsvd1; 1069 __u8 cmd; 1070 __u8 rsvd2[6]; 1071}; 1072 1073struct cpl_abort_rpl_rss { 1074 RSS_HDR 1075 union opcode_tid ot; 1076 __u8 rsvd[3]; 1077 __u8 status; 1078}; 1079 1080struct cpl_abort_rpl_rss6 { 1081 RSS_HDR 1082 union opcode_tid ot; 1083 __u32 srqidx_status; 1084}; 1085 1086struct cpl_abort_rpl { 1087 WR_HDR; 1088 union opcode_tid ot; 1089 __be32 rsvd0; 1090 __u8 rsvd1; 1091 __u8 cmd; 1092 __u8 rsvd2[6]; 1093}; 1094 1095struct cpl_abort_rpl_core { 1096 union opcode_tid ot; 1097 __be32 rsvd0; 1098 __u8 rsvd1; 1099 __u8 cmd; 1100 __u8 rsvd2[6]; 1101}; 1102 1103struct cpl_peer_close { 1104 RSS_HDR 1105 union opcode_tid ot; 1106 __be32 rcv_nxt; 1107}; 1108 1109struct cpl_tid_release { 1110 WR_HDR; 1111 union opcode_tid ot; 1112 __be32 rsvd; 1113}; 1114 1115struct tx_data_wr { 1116 __be32 wr_hi; 1117 __be32 wr_lo; 1118 __be32 len; 1119 __be32 flags; 1120 __be32 sndseq; 1121 __be32 param; 1122}; 1123 1124/* tx_data_wr.flags fields */ 1125#define S_TX_ACK_PAGES 21 1126#define M_TX_ACK_PAGES 0x7 1127#define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 1128#define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 1129 1130/* tx_data_wr.param fields */ 1131#define S_TX_PORT 0 1132#define M_TX_PORT 0x7 1133#define V_TX_PORT(x) ((x) << S_TX_PORT) 1134#define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 1135 1136#define S_TX_MSS 4 1137#define M_TX_MSS 0xF 1138#define V_TX_MSS(x) ((x) << S_TX_MSS) 1139#define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 1140 1141#define S_TX_QOS 8 1142#define M_TX_QOS 0xFF 1143#define V_TX_QOS(x) ((x) << S_TX_QOS) 1144#define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 1145 1146#define S_TX_SNDBUF 16 1147#define M_TX_SNDBUF 0xFFFF 1148#define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 1149#define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 1150 1151struct cpl_tx_data { 1152 union opcode_tid ot; 1153 __be32 len; 1154 __be32 rsvd; 1155 __be32 flags; 1156}; 1157 1158/* cpl_tx_data.flags fields */ 1159#define S_TX_PROXY 5 1160#define V_TX_PROXY(x) ((x) << S_TX_PROXY) 1161#define F_TX_PROXY V_TX_PROXY(1U) 1162 1163#define S_TX_ULP_SUBMODE 6 1164#define M_TX_ULP_SUBMODE 0xF 1165#define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 1166#define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 1167 1168#define S_TX_ULP_MODE 10 1169#define M_TX_ULP_MODE 0x7 1170#define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 1171#define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 1172 1173#define S_TX_FORCE 13 1174#define V_TX_FORCE(x) ((x) << S_TX_FORCE) 1175#define F_TX_FORCE V_TX_FORCE(1U) 1176 1177#define S_TX_SHOVE 14 1178#define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 1179#define F_TX_SHOVE V_TX_SHOVE(1U) 1180 1181#define S_TX_MORE 15 1182#define V_TX_MORE(x) ((x) << S_TX_MORE) 1183#define F_TX_MORE V_TX_MORE(1U) 1184 1185#define S_TX_URG 16 1186#define V_TX_URG(x) ((x) << S_TX_URG) 1187#define F_TX_URG V_TX_URG(1U) 1188 1189#define S_TX_FLUSH 17 1190#define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 1191#define F_TX_FLUSH V_TX_FLUSH(1U) 1192 1193#define S_TX_SAVE 18 1194#define V_TX_SAVE(x) ((x) << S_TX_SAVE) 1195#define F_TX_SAVE V_TX_SAVE(1U) 1196 1197#define S_TX_TNL 19 1198#define V_TX_TNL(x) ((x) << S_TX_TNL) 1199#define F_TX_TNL V_TX_TNL(1U) 1200 1201#define S_T6_TX_FORCE 20 1202#define V_T6_TX_FORCE(x) ((x) << S_T6_TX_FORCE) 1203#define F_T6_TX_FORCE V_T6_TX_FORCE(1U) 1204 1205/* additional tx_data_wr.flags fields */ 1206#define S_TX_CPU_IDX 0 1207#define M_TX_CPU_IDX 0x3F 1208#define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 1209#define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 1210 1211#define S_TX_CLOSE 17 1212#define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 1213#define F_TX_CLOSE V_TX_CLOSE(1U) 1214 1215#define S_TX_INIT 18 1216#define V_TX_INIT(x) ((x) << S_TX_INIT) 1217#define F_TX_INIT V_TX_INIT(1U) 1218 1219#define S_TX_IMM_ACK 19 1220#define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 1221#define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 1222 1223#define S_TX_IMM_DMA 20 1224#define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 1225#define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 1226 1227struct cpl_tx_data_ack { 1228 RSS_HDR 1229 union opcode_tid ot; 1230 __be32 snd_una; 1231}; 1232 1233struct cpl_wr_ack { /* XXX */ 1234 RSS_HDR 1235 union opcode_tid ot; 1236 __be16 credits; 1237 __be16 rsvd; 1238 __be32 snd_nxt; 1239 __be32 snd_una; 1240}; 1241 1242struct cpl_tx_pkt_core { 1243 __be32 ctrl0; 1244 __be16 pack; 1245 __be16 len; 1246 __be64 ctrl1; 1247}; 1248 1249struct cpl_tx_pkt { 1250 WR_HDR; 1251 struct cpl_tx_pkt_core c; 1252}; 1253 1254#define cpl_tx_pkt_xt cpl_tx_pkt 1255 1256/* cpl_tx_pkt_core.ctrl0 fields */ 1257#define S_TXPKT_VF 0 1258#define M_TXPKT_VF 0xFF 1259#define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1260#define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1261 1262#define S_TXPKT_PF 8 1263#define M_TXPKT_PF 0x7 1264#define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1265#define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1266 1267#define S_TXPKT_VF_VLD 11 1268#define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1269#define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1270 1271#define S_TXPKT_OVLAN_IDX 12 1272#define M_TXPKT_OVLAN_IDX 0xF 1273#define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1274#define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1275 1276#define S_TXPKT_T5_OVLAN_IDX 12 1277#define M_TXPKT_T5_OVLAN_IDX 0x7 1278#define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX) 1279#define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \ 1280 M_TXPKT_T5_OVLAN_IDX) 1281 1282#define S_TXPKT_INTF 16 1283#define M_TXPKT_INTF 0xF 1284#define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1285#define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1286 1287#define S_TXPKT_SPECIAL_STAT 20 1288#define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1289#define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1290 1291#define S_TXPKT_T5_FCS_DIS 21 1292#define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS) 1293#define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U) 1294 1295#define S_TXPKT_INS_OVLAN 21 1296#define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1297#define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1298 1299#define S_TXPKT_T5_INS_OVLAN 15 1300#define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN) 1301#define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U) 1302 1303#define S_TXPKT_STAT_DIS 22 1304#define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1305#define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1306 1307#define S_TXPKT_LOOPBACK 23 1308#define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1309#define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1310 1311#define S_TXPKT_TSTAMP 23 1312#define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1313#define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1314 1315#define S_TXPKT_OPCODE 24 1316#define M_TXPKT_OPCODE 0xFF 1317#define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1318#define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1319 1320/* cpl_tx_pkt_core.ctrl1 fields */ 1321#define S_TXPKT_SA_IDX 0 1322#define M_TXPKT_SA_IDX 0xFFF 1323#define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1324#define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1325 1326#define S_TXPKT_CSUM_END 12 1327#define M_TXPKT_CSUM_END 0xFF 1328#define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1329#define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1330 1331#define S_TXPKT_CSUM_START 20 1332#define M_TXPKT_CSUM_START 0x3FF 1333#define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1334#define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1335 1336#define S_TXPKT_IPHDR_LEN 20 1337#define M_TXPKT_IPHDR_LEN 0x3FFF 1338#define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1339#define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1340 1341#define M_T6_TXPKT_IPHDR_LEN 0xFFF 1342#define G_T6_TXPKT_IPHDR_LEN(x) \ 1343 (((x) >> S_TXPKT_IPHDR_LEN) & M_T6_TXPKT_IPHDR_LEN) 1344 1345#define S_TXPKT_CSUM_LOC 30 1346#define M_TXPKT_CSUM_LOC 0x3FF 1347#define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1348#define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1349 1350#define S_TXPKT_ETHHDR_LEN 34 1351#define M_TXPKT_ETHHDR_LEN 0x3F 1352#define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1353#define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1354 1355#define S_T6_TXPKT_ETHHDR_LEN 32 1356#define M_T6_TXPKT_ETHHDR_LEN 0xFF 1357#define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN) 1358#define G_T6_TXPKT_ETHHDR_LEN(x) \ 1359 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN) 1360 1361#define S_TXPKT_CSUM_TYPE 40 1362#define M_TXPKT_CSUM_TYPE 0xF 1363#define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1364#define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1365 1366#define S_TXPKT_VLAN 44 1367#define M_TXPKT_VLAN 0xFFFF 1368#define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1369#define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1370 1371#define S_TXPKT_VLAN_VLD 60 1372#define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1373#define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1374 1375#define S_TXPKT_IPSEC 61 1376#define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1377#define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1378 1379#define S_TXPKT_IPCSUM_DIS 62 1380#define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1381#define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1382 1383#define S_TXPKT_L4CSUM_DIS 63 1384#define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1385#define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1386 1387struct cpl_tx_pkt_lso_core { 1388 __be32 lso_ctrl; 1389 __be16 ipid_ofst; 1390 __be16 mss; 1391 __be32 seqno_offset; 1392 __be32 len; 1393 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1394}; 1395 1396struct cpl_tx_pkt_lso { 1397 WR_HDR; 1398 struct cpl_tx_pkt_lso_core c; 1399 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1400}; 1401 1402struct cpl_tx_pkt_ufo_core { 1403 __be16 ethlen; 1404 __be16 iplen; 1405 __be16 udplen; 1406 __be16 mss; 1407 __be32 len; 1408 __be32 r1; 1409 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1410}; 1411 1412struct cpl_tx_pkt_ufo { 1413 WR_HDR; 1414 struct cpl_tx_pkt_ufo_core c; 1415 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1416}; 1417 1418/* cpl_tx_pkt_lso_core.lso_ctrl fields */ 1419#define S_LSO_TCPHDR_LEN 0 1420#define M_LSO_TCPHDR_LEN 0xF 1421#define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1422#define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1423 1424#define S_LSO_IPHDR_LEN 4 1425#define M_LSO_IPHDR_LEN 0xFFF 1426#define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1427#define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1428 1429#define S_LSO_ETHHDR_LEN 16 1430#define M_LSO_ETHHDR_LEN 0xF 1431#define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1432#define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1433 1434#define S_LSO_IPV6 20 1435#define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1436#define F_LSO_IPV6 V_LSO_IPV6(1U) 1437 1438#define S_LSO_OFLD_ENCAP 21 1439#define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1440#define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1441 1442#define S_LSO_LAST_SLICE 22 1443#define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1444#define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1445 1446#define S_LSO_FIRST_SLICE 23 1447#define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1448#define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1449 1450#define S_LSO_OPCODE 24 1451#define M_LSO_OPCODE 0xFF 1452#define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1453#define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1454 1455#define S_LSO_T5_XFER_SIZE 0 1456#define M_LSO_T5_XFER_SIZE 0xFFFFFFF 1457#define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) 1458#define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) 1459 1460/* cpl_tx_pkt_lso_core.mss fields */ 1461#define S_LSO_MSS 0 1462#define M_LSO_MSS 0x3FFF 1463#define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1464#define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1465 1466#define S_LSO_IPID_SPLIT 15 1467#define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1468#define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1469 1470struct cpl_tx_pkt_fso { 1471 WR_HDR; 1472 __be32 fso_ctrl; 1473 __be16 seqcnt_ofst; 1474 __be16 mtu; 1475 __be32 param_offset; 1476 __be32 len; 1477 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 1478}; 1479 1480/* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1481#define S_FSO_XCHG_CLASS 21 1482#define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 1483#define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 1484 1485#define S_FSO_INITIATOR 20 1486#define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 1487#define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 1488 1489#define S_FSO_FCHDR_LEN 12 1490#define M_FSO_FCHDR_LEN 0xF 1491#define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 1492#define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 1493 1494struct cpl_iscsi_hdr_no_rss { 1495 union opcode_tid ot; 1496 __be16 pdu_len_ddp; 1497 __be16 len; 1498 __be32 seq; 1499 __be16 urg; 1500 __u8 rsvd; 1501 __u8 status; 1502}; 1503 1504struct cpl_tx_data_iso { 1505 __be32 op_to_scsi; 1506 __u8 reserved1; 1507 __u8 ahs_len; 1508 __be16 mpdu; 1509 __be32 burst_size; 1510 __be32 len; 1511 __be32 reserved2_seglen_offset; 1512 __be32 datasn_offset; 1513 __be32 buffer_offset; 1514 __be32 reserved3; 1515 1516 /* encapsulated CPL_TX_DATA follows here */ 1517}; 1518 1519/* cpl_tx_data_iso.op_to_scsi fields */ 1520#define S_CPL_TX_DATA_ISO_OP 24 1521#define M_CPL_TX_DATA_ISO_OP 0xff 1522#define V_CPL_TX_DATA_ISO_OP(x) ((x) << S_CPL_TX_DATA_ISO_OP) 1523#define G_CPL_TX_DATA_ISO_OP(x) \ 1524 (((x) >> S_CPL_TX_DATA_ISO_OP) & M_CPL_TX_DATA_ISO_OP) 1525 1526#define S_CPL_TX_DATA_ISO_FIRST 23 1527#define M_CPL_TX_DATA_ISO_FIRST 0x1 1528#define V_CPL_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_TX_DATA_ISO_FIRST) 1529#define G_CPL_TX_DATA_ISO_FIRST(x) \ 1530 (((x) >> S_CPL_TX_DATA_ISO_FIRST) & M_CPL_TX_DATA_ISO_FIRST) 1531#define F_CPL_TX_DATA_ISO_FIRST V_CPL_TX_DATA_ISO_FIRST(1U) 1532 1533#define S_CPL_TX_DATA_ISO_LAST 22 1534#define M_CPL_TX_DATA_ISO_LAST 0x1 1535#define V_CPL_TX_DATA_ISO_LAST(x) ((x) << S_CPL_TX_DATA_ISO_LAST) 1536#define G_CPL_TX_DATA_ISO_LAST(x) \ 1537 (((x) >> S_CPL_TX_DATA_ISO_LAST) & M_CPL_TX_DATA_ISO_LAST) 1538#define F_CPL_TX_DATA_ISO_LAST V_CPL_TX_DATA_ISO_LAST(1U) 1539 1540#define S_CPL_TX_DATA_ISO_CPLHDRLEN 21 1541#define M_CPL_TX_DATA_ISO_CPLHDRLEN 0x1 1542#define V_CPL_TX_DATA_ISO_CPLHDRLEN(x) ((x) << S_CPL_TX_DATA_ISO_CPLHDRLEN) 1543#define G_CPL_TX_DATA_ISO_CPLHDRLEN(x) \ 1544 (((x) >> S_CPL_TX_DATA_ISO_CPLHDRLEN) & M_CPL_TX_DATA_ISO_CPLHDRLEN) 1545#define F_CPL_TX_DATA_ISO_CPLHDRLEN V_CPL_TX_DATA_ISO_CPLHDRLEN(1U) 1546 1547#define S_CPL_TX_DATA_ISO_HDRCRC 20 1548#define M_CPL_TX_DATA_ISO_HDRCRC 0x1 1549#define V_CPL_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_TX_DATA_ISO_HDRCRC) 1550#define G_CPL_TX_DATA_ISO_HDRCRC(x) \ 1551 (((x) >> S_CPL_TX_DATA_ISO_HDRCRC) & M_CPL_TX_DATA_ISO_HDRCRC) 1552#define F_CPL_TX_DATA_ISO_HDRCRC V_CPL_TX_DATA_ISO_HDRCRC(1U) 1553 1554#define S_CPL_TX_DATA_ISO_PLDCRC 19 1555#define M_CPL_TX_DATA_ISO_PLDCRC 0x1 1556#define V_CPL_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_TX_DATA_ISO_PLDCRC) 1557#define G_CPL_TX_DATA_ISO_PLDCRC(x) \ 1558 (((x) >> S_CPL_TX_DATA_ISO_PLDCRC) & M_CPL_TX_DATA_ISO_PLDCRC) 1559#define F_CPL_TX_DATA_ISO_PLDCRC V_CPL_TX_DATA_ISO_PLDCRC(1U) 1560 1561#define S_CPL_TX_DATA_ISO_IMMEDIATE 18 1562#define M_CPL_TX_DATA_ISO_IMMEDIATE 0x1 1563#define V_CPL_TX_DATA_ISO_IMMEDIATE(x) ((x) << S_CPL_TX_DATA_ISO_IMMEDIATE) 1564#define G_CPL_TX_DATA_ISO_IMMEDIATE(x) \ 1565 (((x) >> S_CPL_TX_DATA_ISO_IMMEDIATE) & M_CPL_TX_DATA_ISO_IMMEDIATE) 1566#define F_CPL_TX_DATA_ISO_IMMEDIATE V_CPL_TX_DATA_ISO_IMMEDIATE(1U) 1567 1568#define S_CPL_TX_DATA_ISO_SCSI 16 1569#define M_CPL_TX_DATA_ISO_SCSI 0x3 1570#define V_CPL_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_TX_DATA_ISO_SCSI) 1571#define G_CPL_TX_DATA_ISO_SCSI(x) \ 1572 (((x) >> S_CPL_TX_DATA_ISO_SCSI) & M_CPL_TX_DATA_ISO_SCSI) 1573 1574/* cpl_tx_data_iso.reserved2_seglen_offset fields */ 1575#define S_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0 1576#define M_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0xffffff 1577#define V_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 1578 ((x) << S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 1579#define G_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 1580 (((x) >> S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) & \ 1581 M_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 1582 1583struct cpl_iscsi_hdr { 1584 RSS_HDR 1585 union opcode_tid ot; 1586 __be16 pdu_len_ddp; 1587 __be16 len; 1588 __be32 seq; 1589 __be16 urg; 1590 __u8 rsvd; 1591 __u8 status; 1592}; 1593 1594/* cpl_iscsi_hdr.pdu_len_ddp fields */ 1595#define S_ISCSI_PDU_LEN 0 1596#define M_ISCSI_PDU_LEN 0x7FFF 1597#define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1598#define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1599 1600#define S_ISCSI_DDP 15 1601#define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1602#define F_ISCSI_DDP V_ISCSI_DDP(1U) 1603 1604struct cpl_iscsi_data { 1605 RSS_HDR 1606 union opcode_tid ot; 1607 __u8 rsvd0[2]; 1608 __be16 len; 1609 __be32 seq; 1610 __be16 urg; 1611 __u8 rsvd1; 1612 __u8 status; 1613}; 1614 1615struct cpl_rx_data { 1616 RSS_HDR 1617 union opcode_tid ot; 1618 __be16 rsvd; 1619 __be16 len; 1620 __be32 seq; 1621 __be16 urg; 1622#if defined(__LITTLE_ENDIAN_BITFIELD) 1623 __u8 dack_mode:2; 1624 __u8 psh:1; 1625 __u8 heartbeat:1; 1626 __u8 ddp_off:1; 1627 __u8 :3; 1628#else 1629 __u8 :3; 1630 __u8 ddp_off:1; 1631 __u8 heartbeat:1; 1632 __u8 psh:1; 1633 __u8 dack_mode:2; 1634#endif 1635 __u8 status; 1636}; 1637 1638struct cpl_fcoe_hdr { 1639 RSS_HDR 1640 union opcode_tid ot; 1641 __be16 oxid; 1642 __be16 len; 1643 __be32 rctl_fctl; 1644 __u8 cs_ctl; 1645 __u8 df_ctl; 1646 __u8 sof; 1647 __u8 eof; 1648 __be16 seq_cnt; 1649 __u8 seq_id; 1650 __u8 type; 1651 __be32 param; 1652}; 1653 1654/* cpl_fcoe_hdr.rctl_fctl fields */ 1655#define S_FCOE_FCHDR_RCTL 24 1656#define M_FCOE_FCHDR_RCTL 0xff 1657#define V_FCOE_FCHDR_RCTL(x) ((x) << S_FCOE_FCHDR_RCTL) 1658#define G_FCOE_FCHDR_RCTL(x) \ 1659 (((x) >> S_FCOE_FCHDR_RCTL) & M_FCOE_FCHDR_RCTL) 1660 1661#define S_FCOE_FCHDR_FCTL 0 1662#define M_FCOE_FCHDR_FCTL 0xffffff 1663#define V_FCOE_FCHDR_FCTL(x) ((x) << S_FCOE_FCHDR_FCTL) 1664#define G_FCOE_FCHDR_FCTL(x) \ 1665 (((x) >> S_FCOE_FCHDR_FCTL) & M_FCOE_FCHDR_FCTL) 1666 1667struct cpl_fcoe_data { 1668 RSS_HDR 1669 union opcode_tid ot; 1670 __u8 rsvd0[2]; 1671 __be16 len; 1672 __be32 seq; 1673 __u8 rsvd1[3]; 1674 __u8 status; 1675}; 1676 1677struct cpl_rx_urg_notify { 1678 RSS_HDR 1679 union opcode_tid ot; 1680 __be32 seq; 1681}; 1682 1683struct cpl_rx_urg_pkt { 1684 RSS_HDR 1685 union opcode_tid ot; 1686 __be16 rsvd; 1687 __be16 len; 1688}; 1689 1690struct cpl_rx_data_ack { 1691 WR_HDR; 1692 union opcode_tid ot; 1693 __be32 credit_dack; 1694}; 1695 1696struct cpl_rx_data_ack_core { 1697 union opcode_tid ot; 1698 __be32 credit_dack; 1699}; 1700 1701/* cpl_rx_data_ack.ack_seq fields */ 1702#define S_RX_CREDITS 0 1703#define M_RX_CREDITS 0x3FFFFFF 1704#define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1705#define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1706 1707#define S_RX_MODULATE_TX 26 1708#define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1709#define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1710 1711#define S_RX_MODULATE_RX 27 1712#define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1713#define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1714 1715#define S_RX_FORCE_ACK 28 1716#define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1717#define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1718 1719#define S_RX_DACK_MODE 29 1720#define M_RX_DACK_MODE 0x3 1721#define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1722#define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1723 1724#define S_RX_DACK_CHANGE 31 1725#define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1726#define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1727 1728struct cpl_rx_ddp_complete { 1729 RSS_HDR 1730 union opcode_tid ot; 1731 __be32 ddp_report; 1732 __be32 rcv_nxt; 1733 __be32 rsvd; 1734}; 1735 1736struct cpl_rx_data_ddp { 1737 RSS_HDR 1738 union opcode_tid ot; 1739 __be16 urg; 1740 __be16 len; 1741 __be32 seq; 1742 union { 1743 __be32 nxt_seq; 1744 __be32 ddp_report; 1745 } u; 1746 __be32 ulp_crc; 1747 __be32 ddpvld; 1748}; 1749 1750#define cpl_rx_iscsi_ddp cpl_rx_data_ddp 1751 1752struct cpl_rx_fcoe_ddp { 1753 RSS_HDR 1754 union opcode_tid ot; 1755 __be16 rsvd; 1756 __be16 len; 1757 __be32 seq; 1758 __be32 ddp_report; 1759 __be32 ulp_crc; 1760 __be32 ddpvld; 1761}; 1762 1763struct cpl_rx_data_dif { 1764 RSS_HDR 1765 union opcode_tid ot; 1766 __be16 ddp_len; 1767 __be16 msg_len; 1768 __be32 seq; 1769 union { 1770 __be32 nxt_seq; 1771 __be32 ddp_report; 1772 } u; 1773 __be32 err_vec; 1774 __be32 ddpvld; 1775}; 1776 1777struct cpl_rx_iscsi_dif { 1778 RSS_HDR 1779 union opcode_tid ot; 1780 __be16 ddp_len; 1781 __be16 msg_len; 1782 __be32 seq; 1783 union { 1784 __be32 nxt_seq; 1785 __be32 ddp_report; 1786 } u; 1787 __be32 ulp_crc; 1788 __be32 ddpvld; 1789 __u8 rsvd0[8]; 1790 __be32 err_vec; 1791 __u8 rsvd1[4]; 1792}; 1793 1794struct cpl_rx_iscsi_cmp { 1795 RSS_HDR 1796 union opcode_tid ot; 1797 __be16 pdu_len_ddp; 1798 __be16 len; 1799 __be32 seq; 1800 __be16 urg; 1801 __u8 rsvd; 1802 __u8 status; 1803 __be32 ulp_crc; 1804 __be32 ddpvld; 1805}; 1806 1807struct cpl_rx_fcoe_dif { 1808 RSS_HDR 1809 union opcode_tid ot; 1810 __be16 ddp_len; 1811 __be16 msg_len; 1812 __be32 seq; 1813 __be32 ddp_report; 1814 __be32 err_vec; 1815 __be32 ddpvld; 1816}; 1817 1818/* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 1819#define S_DDP_VALID 15 1820#define M_DDP_VALID 0x1FFFF 1821#define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1822#define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1823 1824#define S_DDP_PPOD_MISMATCH 15 1825#define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1826#define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1827 1828#define S_DDP_PDU 16 1829#define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1830#define F_DDP_PDU V_DDP_PDU(1U) 1831 1832#define S_DDP_LLIMIT_ERR 17 1833#define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1834#define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1835 1836#define S_DDP_PPOD_PARITY_ERR 18 1837#define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1838#define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1839 1840#define S_DDP_PADDING_ERR 19 1841#define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1842#define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1843 1844#define S_DDP_HDRCRC_ERR 20 1845#define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1846#define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1847 1848#define S_DDP_DATACRC_ERR 21 1849#define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1850#define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1851 1852#define S_DDP_INVALID_TAG 22 1853#define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1854#define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1855 1856#define S_DDP_ULIMIT_ERR 23 1857#define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1858#define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1859 1860#define S_DDP_OFFSET_ERR 24 1861#define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1862#define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1863 1864#define S_DDP_COLOR_ERR 25 1865#define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1866#define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1867 1868#define S_DDP_TID_MISMATCH 26 1869#define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1870#define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1871 1872#define S_DDP_INVALID_PPOD 27 1873#define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1874#define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1875 1876#define S_DDP_ULP_MODE 28 1877#define M_DDP_ULP_MODE 0xF 1878#define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1879#define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1880 1881/* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 1882#define S_DDP_OFFSET 0 1883#define M_DDP_OFFSET 0xFFFFFF 1884#define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1885#define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1886 1887#define S_DDP_DACK_MODE 24 1888#define M_DDP_DACK_MODE 0x3 1889#define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1890#define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1891 1892#define S_DDP_BUF_IDX 26 1893#define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1894#define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1895 1896#define S_DDP_URG 27 1897#define V_DDP_URG(x) ((x) << S_DDP_URG) 1898#define F_DDP_URG V_DDP_URG(1U) 1899 1900#define S_DDP_PSH 28 1901#define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1902#define F_DDP_PSH V_DDP_PSH(1U) 1903 1904#define S_DDP_BUF_COMPLETE 29 1905#define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1906#define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1907 1908#define S_DDP_BUF_TIMED_OUT 30 1909#define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1910#define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1911 1912#define S_DDP_INV 31 1913#define V_DDP_INV(x) ((x) << S_DDP_INV) 1914#define F_DDP_INV V_DDP_INV(1U) 1915 1916struct cpl_rx_pkt { 1917 RSS_HDR 1918 __u8 opcode; 1919#if defined(__LITTLE_ENDIAN_BITFIELD) 1920 __u8 iff:4; 1921 __u8 csum_calc:1; 1922 __u8 ipmi_pkt:1; 1923 __u8 vlan_ex:1; 1924 __u8 ip_frag:1; 1925#else 1926 __u8 ip_frag:1; 1927 __u8 vlan_ex:1; 1928 __u8 ipmi_pkt:1; 1929 __u8 csum_calc:1; 1930 __u8 iff:4; 1931#endif 1932 __be16 csum; 1933 __be16 vlan; 1934 __be16 len; 1935 __be32 l2info; 1936 __be16 hdr_len; 1937 __be16 err_vec; 1938}; 1939 1940/* rx_pkt.l2info fields */ 1941#define S_RX_ETHHDR_LEN 0 1942#define M_RX_ETHHDR_LEN 0x1F 1943#define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1944#define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1945 1946#define S_RX_T5_ETHHDR_LEN 0 1947#define M_RX_T5_ETHHDR_LEN 0x3F 1948#define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 1949#define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 1950 1951#define M_RX_T6_ETHHDR_LEN 0xFF 1952#define G_RX_T6_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_T6_ETHHDR_LEN) 1953 1954#define S_RX_PKTYPE 5 1955#define M_RX_PKTYPE 0x7 1956#define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1957#define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1958 1959#define S_RX_T5_DATYPE 6 1960#define M_RX_T5_DATYPE 0x3 1961#define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 1962#define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 1963 1964#define S_RX_MACIDX 8 1965#define M_RX_MACIDX 0x1FF 1966#define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1967#define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1968 1969#define S_RX_T5_PKTYPE 17 1970#define M_RX_T5_PKTYPE 0x7 1971#define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 1972#define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 1973 1974#define S_RX_DATYPE 18 1975#define M_RX_DATYPE 0x3 1976#define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1977#define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1978 1979#define S_RXF_PSH 20 1980#define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1981#define F_RXF_PSH V_RXF_PSH(1U) 1982 1983#define S_RXF_SYN 21 1984#define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1985#define F_RXF_SYN V_RXF_SYN(1U) 1986 1987#define S_RXF_UDP 22 1988#define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1989#define F_RXF_UDP V_RXF_UDP(1U) 1990 1991#define S_RXF_TCP 23 1992#define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1993#define F_RXF_TCP V_RXF_TCP(1U) 1994 1995#define S_RXF_IP 24 1996#define V_RXF_IP(x) ((x) << S_RXF_IP) 1997#define F_RXF_IP V_RXF_IP(1U) 1998 1999#define S_RXF_IP6 25 2000#define V_RXF_IP6(x) ((x) << S_RXF_IP6) 2001#define F_RXF_IP6 V_RXF_IP6(1U) 2002 2003#define S_RXF_SYN_COOKIE 26 2004#define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 2005#define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 2006 2007#define S_RXF_FCOE 26 2008#define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 2009#define F_RXF_FCOE V_RXF_FCOE(1U) 2010 2011#define S_RXF_LRO 27 2012#define V_RXF_LRO(x) ((x) << S_RXF_LRO) 2013#define F_RXF_LRO V_RXF_LRO(1U) 2014 2015#define S_RX_CHAN 28 2016#define M_RX_CHAN 0xF 2017#define V_RX_CHAN(x) ((x) << S_RX_CHAN) 2018#define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 2019 2020/* rx_pkt.hdr_len fields */ 2021#define S_RX_TCPHDR_LEN 0 2022#define M_RX_TCPHDR_LEN 0x3F 2023#define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 2024#define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 2025 2026#define S_RX_IPHDR_LEN 6 2027#define M_RX_IPHDR_LEN 0x3FF 2028#define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 2029#define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 2030 2031/* rx_pkt.err_vec fields */ 2032#define S_RXERR_OR 0 2033#define V_RXERR_OR(x) ((x) << S_RXERR_OR) 2034#define F_RXERR_OR V_RXERR_OR(1U) 2035 2036#define S_RXERR_MAC 1 2037#define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 2038#define F_RXERR_MAC V_RXERR_MAC(1U) 2039 2040#define S_RXERR_IPVERS 2 2041#define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 2042#define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 2043 2044#define S_RXERR_FRAG 3 2045#define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 2046#define F_RXERR_FRAG V_RXERR_FRAG(1U) 2047 2048#define S_RXERR_ATTACK 4 2049#define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 2050#define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 2051 2052#define S_RXERR_ETHHDR_LEN 5 2053#define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 2054#define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 2055 2056#define S_RXERR_IPHDR_LEN 6 2057#define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 2058#define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 2059 2060#define S_RXERR_TCPHDR_LEN 7 2061#define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 2062#define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 2063 2064#define S_RXERR_PKT_LEN 8 2065#define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 2066#define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 2067 2068#define S_RXERR_TCP_OPT 9 2069#define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 2070#define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 2071 2072#define S_RXERR_IPCSUM 12 2073#define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 2074#define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 2075 2076#define S_RXERR_CSUM 13 2077#define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 2078#define F_RXERR_CSUM V_RXERR_CSUM(1U) 2079 2080#define S_RXERR_PING 14 2081#define V_RXERR_PING(x) ((x) << S_RXERR_PING) 2082#define F_RXERR_PING V_RXERR_PING(1U) 2083 2084/* In T6, rx_pkt.err_vec indicates 2085 * RxError Error vector (16b) or 2086 * Encapsulating header length (8b), 2087 * Outer encapsulation type (2b) and 2088 * compressed error vector (6b) if CRxPktEnc is 2089 * enabled in TP_OUT_CONFIG 2090 */ 2091 2092#define S_T6_COMPR_RXERR_VEC 0 2093#define M_T6_COMPR_RXERR_VEC 0x3F 2094#define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC) 2095#define G_T6_COMPR_RXERR_VEC(x) \ 2096 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC) 2097 2098#define S_T6_COMPR_RXERR_MAC 0 2099#define V_T6_COMPR_RXERR_MAC(x) ((x) << S_T6_COMPR_RXERR_MAC) 2100#define F_T6_COMPR_RXERR_MAC V_T6_COMPR_RXERR_MAC(1U) 2101 2102/* Logical OR of RX_ERROR_PKT_LEN, RX_ERROR_TCP_HDR_LEN 2103 * RX_ERROR_IP_HDR_LEN, RX_ERROR_ETH_HDR_LEN 2104 */ 2105#define S_T6_COMPR_RXERR_LEN 1 2106#define V_T6_COMPR_RXERR_LEN(x) ((x) << S_T6_COMPR_RXERR_LEN) 2107#define F_T6_COMPR_RXERR_LEN V_COMPR_T6_RXERR_LEN(1U) 2108 2109#define S_T6_COMPR_RXERR_TCP_OPT 2 2110#define V_T6_COMPR_RXERR_TCP_OPT(x) ((x) << S_T6_COMPR_RXERR_TCP_OPT) 2111#define F_T6_COMPR_RXERR_TCP_OPT V_T6_COMPR_RXERR_TCP_OPT(1U) 2112 2113#define S_T6_COMPR_RXERR_IPV6_EXT 3 2114#define V_T6_COMPR_RXERR_IPV6_EXT(x) ((x) << S_T6_COMPR_RXERR_IPV6_EXT) 2115#define F_T6_COMPR_RXERR_IPV6_EXT V_T6_COMPR_RXERR_IPV6_EXT(1U) 2116 2117/* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */ 2118#define S_T6_COMPR_RXERR_SUM 4 2119#define V_T6_COMPR_RXERR_SUM(x) ((x) << S_T6_COMPR_RXERR_SUM) 2120#define F_T6_COMPR_RXERR_SUM V_T6_COMPR_RXERR_SUM(1U) 2121 2122/* Logical OR of RX_ERROR_FPMA, RX_ERROR_PING_DROP, 2123 * RX_ERROR_ATTACK, RX_ERROR_FRAG,RX_ERROR_IPVERSION 2124 */ 2125#define S_T6_COMPR_RXERR_MISC 5 2126#define V_T6_COMPR_RXERR_MISC(x) ((x) << S_T6_COMPR_RXERR_MISC) 2127#define F_T6_COMPR_RXERR_MISC V_T6_COMPR_RXERR_MISC(1U) 2128 2129#define S_T6_RX_TNL_TYPE 6 2130#define M_T6_RX_TNL_TYPE 0x3 2131#define V_T6_RX_TNL_TYPE(x) ((x) << S_T6_RX_TNL_TYPE) 2132#define G_T6_RX_TNL_TYPE(x) (((x) >> S_T6_RX_TNL_TYPE) & M_T6_RX_TNL_TYPE) 2133 2134#define RX_PKT_TNL_TYPE_NVGRE 1 2135#define RX_PKT_TNL_TYPE_VXLAN 2 2136#define RX_PKT_TNL_TYPE_GENEVE 3 2137 2138#define S_T6_RX_TNLHDR_LEN 8 2139#define M_T6_RX_TNLHDR_LEN 0xFF 2140#define V_T6_RX_TNLHDR_LEN(x) ((x) << S_T6_RX_TNLHDR_LEN) 2141#define G_T6_RX_TNLHDR_LEN(x) (((x) >> S_T6_RX_TNLHDR_LEN) & M_T6_RX_TNLHDR_LEN) 2142 2143struct cpl_trace_pkt { 2144 RSS_HDR 2145 __u8 opcode; 2146 __u8 intf; 2147#if defined(__LITTLE_ENDIAN_BITFIELD) 2148 __u8 runt:4; 2149 __u8 filter_hit:4; 2150 __u8 :6; 2151 __u8 err:1; 2152 __u8 trunc:1; 2153#else 2154 __u8 filter_hit:4; 2155 __u8 runt:4; 2156 __u8 trunc:1; 2157 __u8 err:1; 2158 __u8 :6; 2159#endif 2160 __be16 rsvd; 2161 __be16 len; 2162 __be64 tstamp; 2163}; 2164 2165struct cpl_t5_trace_pkt { 2166 RSS_HDR 2167 __u8 opcode; 2168 __u8 intf; 2169#if defined(__LITTLE_ENDIAN_BITFIELD) 2170 __u8 runt:4; 2171 __u8 filter_hit:4; 2172 __u8 :6; 2173 __u8 err:1; 2174 __u8 trunc:1; 2175#else 2176 __u8 filter_hit:4; 2177 __u8 runt:4; 2178 __u8 trunc:1; 2179 __u8 err:1; 2180 __u8 :6; 2181#endif 2182 __be16 rsvd; 2183 __be16 len; 2184 __be64 tstamp; 2185 __be64 rsvd1; 2186}; 2187 2188struct cpl_rte_delete_req { 2189 WR_HDR; 2190 union opcode_tid ot; 2191 __be32 params; 2192}; 2193 2194/* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 2195#define S_RTE_REQ_LUT_IX 8 2196#define M_RTE_REQ_LUT_IX 0x7FF 2197#define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 2198#define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 2199 2200#define S_RTE_REQ_LUT_BASE 19 2201#define M_RTE_REQ_LUT_BASE 0x7FF 2202#define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 2203#define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 2204 2205#define S_RTE_READ_REQ_SELECT 31 2206#define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 2207#define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 2208 2209struct cpl_rte_delete_rpl { 2210 RSS_HDR 2211 union opcode_tid ot; 2212 __u8 status; 2213 __u8 rsvd[3]; 2214}; 2215 2216struct cpl_rte_write_req { 2217 WR_HDR; 2218 union opcode_tid ot; 2219 __u32 write_sel; 2220 __be32 lut_params; 2221 __be32 l2t_idx; 2222 __be32 netmask; 2223 __be32 faddr; 2224}; 2225 2226/* cpl_rte_write_req.write_sel fields */ 2227#define S_RTE_WR_L2TIDX 31 2228#define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 2229#define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 2230 2231#define S_RTE_WR_FADDR 30 2232#define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 2233#define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 2234 2235/* cpl_rte_write_req.lut_params fields */ 2236#define S_RTE_WR_LUT_IX 10 2237#define M_RTE_WR_LUT_IX 0x7FF 2238#define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 2239#define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 2240 2241#define S_RTE_WR_LUT_BASE 21 2242#define M_RTE_WR_LUT_BASE 0x7FF 2243#define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 2244#define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 2245 2246struct cpl_rte_write_rpl { 2247 RSS_HDR 2248 union opcode_tid ot; 2249 __u8 status; 2250 __u8 rsvd[3]; 2251}; 2252 2253struct cpl_rte_read_req { 2254 WR_HDR; 2255 union opcode_tid ot; 2256 __be32 params; 2257}; 2258 2259struct cpl_rte_read_rpl { 2260 RSS_HDR 2261 union opcode_tid ot; 2262 __u8 status; 2263 __u8 rsvd; 2264 __be16 l2t_idx; 2265#if defined(__LITTLE_ENDIAN_BITFIELD) 2266 __u32 :30; 2267 __u32 select:1; 2268#else 2269 __u32 select:1; 2270 __u32 :30; 2271#endif 2272 __be32 addr; 2273}; 2274 2275struct cpl_l2t_write_req { 2276 WR_HDR; 2277 union opcode_tid ot; 2278 __be16 params; 2279 __be16 l2t_idx; 2280 __be16 vlan; 2281 __u8 dst_mac[6]; 2282}; 2283 2284/* cpl_l2t_write_req.params fields */ 2285#define S_L2T_W_INFO 2 2286#define M_L2T_W_INFO 0x3F 2287#define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 2288#define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 2289 2290#define S_L2T_W_PORT 8 2291#define M_L2T_W_PORT 0x3 2292#define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 2293#define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 2294 2295#define S_L2T_W_LPBK 10 2296#define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) 2297#define F_L2T_W_PKBK V_L2T_W_LPBK(1U) 2298 2299#define S_L2T_W_ARPMISS 11 2300#define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) 2301#define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U) 2302 2303#define S_L2T_W_NOREPLY 15 2304#define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 2305#define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 2306 2307#define CPL_L2T_VLAN_NONE 0xfff 2308 2309struct cpl_l2t_write_rpl { 2310 RSS_HDR 2311 union opcode_tid ot; 2312 __u8 status; 2313 __u8 rsvd[3]; 2314}; 2315 2316struct cpl_l2t_read_req { 2317 WR_HDR; 2318 union opcode_tid ot; 2319 __be32 l2t_idx; 2320}; 2321 2322struct cpl_l2t_read_rpl { 2323 RSS_HDR 2324 union opcode_tid ot; 2325 __u8 status; 2326#if defined(__LITTLE_ENDIAN_BITFIELD) 2327 __u8 :4; 2328 __u8 iff:4; 2329#else 2330 __u8 iff:4; 2331 __u8 :4; 2332#endif 2333 __be16 vlan; 2334 __be16 info; 2335 __u8 dst_mac[6]; 2336}; 2337 2338struct cpl_srq_table_req { 2339 WR_HDR; 2340 union opcode_tid ot; 2341 __u8 status; 2342 __u8 rsvd[2]; 2343 __u8 idx; 2344 __be64 rsvd_pdid; 2345 __be32 qlen_qbase; 2346 __be16 cur_msn; 2347 __be16 max_msn; 2348}; 2349 2350struct cpl_srq_table_rpl { 2351 RSS_HDR 2352 union opcode_tid ot; 2353 __u8 status; 2354 __u8 rsvd[2]; 2355 __u8 idx; 2356 __be64 rsvd_pdid; 2357 __be32 qlen_qbase; 2358 __be16 cur_msn; 2359 __be16 max_msn; 2360}; 2361 2362/* cpl_srq_table_{req,rpl}.params fields */ 2363#define S_SRQT_QLEN 28 2364#define M_SRQT_QLEN 0xF 2365#define V_SRQT_QLEN(x) ((x) << S_SRQT_QLEN) 2366#define G_SRQT_QLEN(x) (((x) >> S_SRQT_QLEN) & M_SRQT_QLEN) 2367 2368#define S_SRQT_QBASE 0 2369#define M_SRQT_QBASE 0x3FFFFFF 2370#define V_SRQT_QBASE(x) ((x) << S_SRQT_QBASE) 2371#define G_SRQT_QBASE(x) (((x) >> S_SRQT_QBASE) & M_SRQT_QBASE) 2372 2373#define S_SRQT_PDID 0 2374#define M_SRQT_PDID 0xFF 2375#define V_SRQT_PDID(x) ((x) << S_SRQT_PDID) 2376#define G_SRQT_PDID(x) (((x) >> S_SRQT_PDID) & M_SRQT_PDID) 2377 2378#define S_SRQT_IDX 0 2379#define M_SRQT_IDX 0xF 2380#define V_SRQT_IDX(x) ((x) << S_SRQT_IDX) 2381#define G_SRQT_IDX(x) (((x) >> S_SRQT_IDX) & M_SRQT_IDX) 2382 2383struct cpl_smt_write_req { 2384 WR_HDR; 2385 union opcode_tid ot; 2386 __be32 params; 2387 __be16 pfvf1; 2388 __u8 src_mac1[6]; 2389 __be16 pfvf0; 2390 __u8 src_mac0[6]; 2391}; 2392 2393struct cpl_t6_smt_write_req { 2394 WR_HDR; 2395 union opcode_tid ot; 2396 __be32 params; 2397 __be64 tag; 2398 __be16 pfvf0; 2399 __u8 src_mac0[6]; 2400 __be32 local_ip; 2401 __be32 rsvd; 2402}; 2403 2404struct cpl_smt_write_rpl { 2405 RSS_HDR 2406 union opcode_tid ot; 2407 __u8 status; 2408 __u8 rsvd[3]; 2409}; 2410 2411struct cpl_smt_read_req { 2412 WR_HDR; 2413 union opcode_tid ot; 2414 __be32 params; 2415}; 2416 2417struct cpl_smt_read_rpl { 2418 RSS_HDR 2419 union opcode_tid ot; 2420 __u8 status; 2421 __u8 ovlan_idx; 2422 __be16 rsvd; 2423 __be16 pfvf1; 2424 __u8 src_mac1[6]; 2425 __be16 pfvf0; 2426 __u8 src_mac0[6]; 2427}; 2428 2429/* cpl_smt_{read,write}_req.params fields */ 2430#define S_SMTW_OVLAN_IDX 16 2431#define M_SMTW_OVLAN_IDX 0xF 2432#define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 2433#define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 2434 2435#define S_SMTW_IDX 20 2436#define M_SMTW_IDX 0x7F 2437#define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 2438#define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 2439 2440#define M_T6_SMTW_IDX 0xFF 2441#define G_T6_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_T6_SMTW_IDX) 2442 2443#define S_SMTW_NORPL 31 2444#define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 2445#define F_SMTW_NORPL V_SMTW_NORPL(1U) 2446 2447/* cpl_smt_{read,write}_req.pfvf? fields */ 2448#define S_SMTW_VF 0 2449#define M_SMTW_VF 0xFF 2450#define V_SMTW_VF(x) ((x) << S_SMTW_VF) 2451#define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 2452 2453#define S_SMTW_PF 8 2454#define M_SMTW_PF 0x7 2455#define V_SMTW_PF(x) ((x) << S_SMTW_PF) 2456#define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 2457 2458#define S_SMTW_VF_VLD 11 2459#define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 2460#define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 2461 2462struct cpl_tag_write_req { 2463 WR_HDR; 2464 union opcode_tid ot; 2465 __be32 params; 2466 __be64 tag_val; 2467}; 2468 2469struct cpl_tag_write_rpl { 2470 RSS_HDR 2471 union opcode_tid ot; 2472 __u8 status; 2473 __u8 rsvd[2]; 2474 __u8 idx; 2475}; 2476 2477struct cpl_tag_read_req { 2478 WR_HDR; 2479 union opcode_tid ot; 2480 __be32 params; 2481}; 2482 2483struct cpl_tag_read_rpl { 2484 RSS_HDR 2485 union opcode_tid ot; 2486 __u8 status; 2487#if defined(__LITTLE_ENDIAN_BITFIELD) 2488 __u8 :4; 2489 __u8 tag_len:1; 2490 __u8 :2; 2491 __u8 ins_enable:1; 2492#else 2493 __u8 ins_enable:1; 2494 __u8 :2; 2495 __u8 tag_len:1; 2496 __u8 :4; 2497#endif 2498 __u8 rsvd; 2499 __u8 tag_idx; 2500 __be64 tag_val; 2501}; 2502 2503/* cpl_tag{read,write}_req.params fields */ 2504#define S_TAGW_IDX 0 2505#define M_TAGW_IDX 0x7F 2506#define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 2507#define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 2508 2509#define S_TAGW_LEN 20 2510#define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 2511#define F_TAGW_LEN V_TAGW_LEN(1U) 2512 2513#define S_TAGW_INS_ENABLE 23 2514#define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 2515#define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 2516 2517#define S_TAGW_NORPL 31 2518#define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 2519#define F_TAGW_NORPL V_TAGW_NORPL(1U) 2520 2521struct cpl_barrier { 2522 WR_HDR; 2523 __u8 opcode; 2524 __u8 chan_map; 2525 __be16 rsvd0; 2526 __be32 rsvd1; 2527}; 2528 2529/* cpl_barrier.chan_map fields */ 2530#define S_CHAN_MAP 4 2531#define M_CHAN_MAP 0xF 2532#define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 2533#define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 2534 2535struct cpl_error { 2536 RSS_HDR 2537 union opcode_tid ot; 2538 __be32 error; 2539}; 2540 2541struct cpl_hit_notify { 2542 RSS_HDR 2543 union opcode_tid ot; 2544 __be32 rsvd; 2545 __be32 info; 2546 __be32 reason; 2547}; 2548 2549struct cpl_pkt_notify { 2550 RSS_HDR 2551 union opcode_tid ot; 2552 __be16 rsvd; 2553 __be16 len; 2554 __be32 info; 2555 __be32 reason; 2556}; 2557 2558/* cpl_{hit,pkt}_notify.info fields */ 2559#define S_NTFY_MAC_IDX 0 2560#define M_NTFY_MAC_IDX 0x1FF 2561#define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 2562#define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 2563 2564#define S_NTFY_INTF 10 2565#define M_NTFY_INTF 0xF 2566#define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 2567#define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 2568 2569#define S_NTFY_TCPHDR_LEN 14 2570#define M_NTFY_TCPHDR_LEN 0xF 2571#define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 2572#define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 2573 2574#define S_NTFY_IPHDR_LEN 18 2575#define M_NTFY_IPHDR_LEN 0x1FF 2576#define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 2577#define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 2578 2579#define S_NTFY_ETHHDR_LEN 27 2580#define M_NTFY_ETHHDR_LEN 0x1F 2581#define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 2582#define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 2583 2584#define S_NTFY_T5_IPHDR_LEN 18 2585#define M_NTFY_T5_IPHDR_LEN 0xFF 2586#define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 2587#define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 2588 2589#define S_NTFY_T5_ETHHDR_LEN 26 2590#define M_NTFY_T5_ETHHDR_LEN 0x3F 2591#define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 2592#define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 2593 2594struct cpl_rdma_terminate { 2595 RSS_HDR 2596 union opcode_tid ot; 2597 __be16 rsvd; 2598 __be16 len; 2599}; 2600 2601struct cpl_set_le_req { 2602 WR_HDR; 2603 union opcode_tid ot; 2604 __be16 reply_ctrl; 2605 __be16 params; 2606 __be64 mask_hi; 2607 __be64 mask_lo; 2608 __be64 val_hi; 2609 __be64 val_lo; 2610}; 2611 2612/* cpl_set_le_req.reply_ctrl additional fields */ 2613#define S_LE_REQ_IP6 13 2614#define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 2615#define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 2616 2617/* cpl_set_le_req.params fields */ 2618#define S_LE_CHAN 0 2619#define M_LE_CHAN 0x3 2620#define V_LE_CHAN(x) ((x) << S_LE_CHAN) 2621#define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 2622 2623#define S_LE_OFFSET 5 2624#define M_LE_OFFSET 0x7 2625#define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 2626#define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 2627 2628#define S_LE_MORE 8 2629#define V_LE_MORE(x) ((x) << S_LE_MORE) 2630#define F_LE_MORE V_LE_MORE(1U) 2631 2632#define S_LE_REQSIZE 9 2633#define M_LE_REQSIZE 0x7 2634#define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 2635#define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 2636 2637#define S_LE_REQCMD 12 2638#define M_LE_REQCMD 0xF 2639#define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 2640#define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 2641 2642struct cpl_set_le_rpl { 2643 RSS_HDR 2644 union opcode_tid ot; 2645 __u8 chan; 2646 __u8 info; 2647 __be16 len; 2648}; 2649 2650/* cpl_set_le_rpl.info fields */ 2651#define S_LE_RSPCMD 0 2652#define M_LE_RSPCMD 0xF 2653#define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 2654#define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 2655 2656#define S_LE_RSPSIZE 4 2657#define M_LE_RSPSIZE 0x7 2658#define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 2659#define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 2660 2661#define S_LE_RSPTYPE 7 2662#define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 2663#define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 2664 2665struct cpl_sge_egr_update { 2666 RSS_HDR 2667 __be32 opcode_qid; 2668 __be16 cidx; 2669 __be16 pidx; 2670}; 2671 2672/* cpl_sge_egr_update.ot fields */ 2673#define S_AUTOEQU 22 2674#define M_AUTOEQU 0x1 2675#define V_AUTOEQU(x) ((x) << S_AUTOEQU) 2676#define G_AUTOEQU(x) (((x) >> S_AUTOEQU) & M_AUTOEQU) 2677 2678#define S_EGR_QID 0 2679#define M_EGR_QID 0x1FFFF 2680#define V_EGR_QID(x) ((x) << S_EGR_QID) 2681#define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 2682 2683/* cpl_fw*.type values */ 2684enum { 2685 FW_TYPE_CMD_RPL = 0, 2686 FW_TYPE_WR_RPL = 1, 2687 FW_TYPE_CQE = 2, 2688 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 2689 FW_TYPE_RSSCPL = 4, 2690 FW_TYPE_WRERR_RPL = 5, 2691 FW_TYPE_PI_ERR = 6, 2692 FW_TYPE_TLS_KEY = 7, 2693}; 2694 2695struct cpl_fw2_pld { 2696 RSS_HDR 2697 u8 opcode; 2698 u8 rsvd[5]; 2699 __be16 len; 2700}; 2701 2702struct cpl_fw4_pld { 2703 RSS_HDR 2704 u8 opcode; 2705 u8 rsvd0[3]; 2706 u8 type; 2707 u8 rsvd1; 2708 __be16 len; 2709 __be64 data; 2710 __be64 rsvd2; 2711}; 2712 2713struct cpl_fw6_pld { 2714 RSS_HDR 2715 u8 opcode; 2716 u8 rsvd[5]; 2717 __be16 len; 2718 __be64 data[4]; 2719}; 2720 2721struct cpl_fw2_msg { 2722 RSS_HDR 2723 union opcode_info oi; 2724}; 2725 2726struct cpl_fw4_msg { 2727 RSS_HDR 2728 u8 opcode; 2729 u8 type; 2730 __be16 rsvd0; 2731 __be32 rsvd1; 2732 __be64 data[2]; 2733}; 2734 2735struct cpl_fw4_ack { 2736 RSS_HDR 2737 union opcode_tid ot; 2738 u8 credits; 2739 u8 rsvd0[2]; 2740 u8 flags; 2741 __be32 snd_nxt; 2742 __be32 snd_una; 2743 __be64 rsvd1; 2744}; 2745 2746enum { 2747 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 2748 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 2749 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 2750}; 2751 2752#define S_CPL_FW4_ACK_OPCODE 24 2753#define M_CPL_FW4_ACK_OPCODE 0xff 2754#define V_CPL_FW4_ACK_OPCODE(x) ((x) << S_CPL_FW4_ACK_OPCODE) 2755#define G_CPL_FW4_ACK_OPCODE(x) \ 2756 (((x) >> S_CPL_FW4_ACK_OPCODE) & M_CPL_FW4_ACK_OPCODE) 2757 2758#define S_CPL_FW4_ACK_FLOWID 0 2759#define M_CPL_FW4_ACK_FLOWID 0xffffff 2760#define V_CPL_FW4_ACK_FLOWID(x) ((x) << S_CPL_FW4_ACK_FLOWID) 2761#define G_CPL_FW4_ACK_FLOWID(x) \ 2762 (((x) >> S_CPL_FW4_ACK_FLOWID) & M_CPL_FW4_ACK_FLOWID) 2763 2764#define S_CPL_FW4_ACK_CR 24 2765#define M_CPL_FW4_ACK_CR 0xff 2766#define V_CPL_FW4_ACK_CR(x) ((x) << S_CPL_FW4_ACK_CR) 2767#define G_CPL_FW4_ACK_CR(x) (((x) >> S_CPL_FW4_ACK_CR) & M_CPL_FW4_ACK_CR) 2768 2769#define S_CPL_FW4_ACK_SEQVAL 0 2770#define M_CPL_FW4_ACK_SEQVAL 0x1 2771#define V_CPL_FW4_ACK_SEQVAL(x) ((x) << S_CPL_FW4_ACK_SEQVAL) 2772#define G_CPL_FW4_ACK_SEQVAL(x) \ 2773 (((x) >> S_CPL_FW4_ACK_SEQVAL) & M_CPL_FW4_ACK_SEQVAL) 2774#define F_CPL_FW4_ACK_SEQVAL V_CPL_FW4_ACK_SEQVAL(1U) 2775 2776struct cpl_fw6_msg { 2777 RSS_HDR 2778 u8 opcode; 2779 u8 type; 2780 __be16 rsvd0; 2781 __be32 rsvd1; 2782 __be64 data[4]; 2783}; 2784 2785/* cpl_fw6_msg.type values */ 2786enum { 2787 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL, 2788 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL, 2789 FW6_TYPE_CQE = FW_TYPE_CQE, 2790 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL, 2791 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 2792 FW6_TYPE_WRERR_RPL = FW_TYPE_WRERR_RPL, 2793 FW6_TYPE_PI_ERR = FW_TYPE_PI_ERR, 2794 NUM_FW6_TYPES 2795}; 2796 2797struct cpl_fw6_msg_ofld_connection_wr_rpl { 2798 __u64 cookie; 2799 __be32 tid; /* or atid in case of active failure */ 2800 __u8 t_state; 2801 __u8 retval; 2802 __u8 rsvd[2]; 2803}; 2804 2805/* ULP_TX opcodes */ 2806enum { 2807 ULP_TX_MEM_READ = 2, 2808 ULP_TX_MEM_WRITE = 3, 2809 ULP_TX_PKT = 4 2810}; 2811 2812enum { 2813 ULP_TX_SC_NOOP = 0x80, 2814 ULP_TX_SC_IMM = 0x81, 2815 ULP_TX_SC_DSGL = 0x82, 2816 ULP_TX_SC_ISGL = 0x83, 2817 ULP_TX_SC_PICTRL = 0x84, 2818 ULP_TX_SC_MEMRD = 0x86 2819}; 2820 2821#define S_ULPTX_CMD 24 2822#define M_ULPTX_CMD 0xFF 2823#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2824 2825#define S_ULPTX_LEN16 0 2826#define M_ULPTX_LEN16 0xFF 2827#define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2828 2829#define S_ULP_TX_SC_MORE 23 2830#define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2831#define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2832 2833struct ulptx_sge_pair { 2834 __be32 len[2]; 2835 __be64 addr[2]; 2836}; 2837 2838struct ulptx_sgl { 2839 __be32 cmd_nsge; 2840 __be32 len0; 2841 __be64 addr0; 2842#if !(defined C99_NOT_SUPPORTED) 2843 struct ulptx_sge_pair sge[0]; 2844#endif 2845}; 2846 2847struct ulptx_isge { 2848 __be32 stag; 2849 __be32 len; 2850 __be64 target_ofst; 2851}; 2852 2853struct ulptx_isgl { 2854 __be32 cmd_nisge; 2855 __be32 rsvd; 2856#if !(defined C99_NOT_SUPPORTED) 2857 struct ulptx_isge sge[0]; 2858#endif 2859}; 2860 2861struct ulptx_idata { 2862 __be32 cmd_more; 2863 __be32 len; 2864}; 2865 2866#define S_ULPTX_NSGE 0 2867#define M_ULPTX_NSGE 0xFFFF 2868#define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2869#define G_ULPTX_NSGE(x) (((x) >> S_ULPTX_NSGE) & M_ULPTX_NSGE) 2870 2871struct ulptx_sc_memrd { 2872 __be32 cmd_to_len; 2873 __be32 addr; 2874}; 2875 2876struct ulp_mem_io { 2877 WR_HDR; 2878 __be32 cmd; 2879 __be32 len16; /* command length */ 2880 __be32 dlen; /* data length in 32-byte units */ 2881 __be32 lock_addr; 2882}; 2883 2884/* additional ulp_mem_io.cmd fields */ 2885#define S_ULP_MEMIO_ORDER 23 2886#define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2887#define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2888 2889#define S_T5_ULP_MEMIO_IMM 23 2890#define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 2891#define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 2892 2893#define S_T5_ULP_MEMIO_ORDER 22 2894#define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 2895#define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 2896 2897#define S_T5_ULP_MEMIO_FID 4 2898#define M_T5_ULP_MEMIO_FID 0x7ff 2899#define V_T5_ULP_MEMIO_FID(x) ((x) << S_T5_ULP_MEMIO_FID) 2900 2901/* ulp_mem_io.lock_addr fields */ 2902#define S_ULP_MEMIO_ADDR 0 2903#define M_ULP_MEMIO_ADDR 0x7FFFFFF 2904#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2905 2906#define S_ULP_MEMIO_LOCK 31 2907#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2908#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2909 2910/* ulp_mem_io.dlen fields */ 2911#define S_ULP_MEMIO_DATA_LEN 0 2912#define M_ULP_MEMIO_DATA_LEN 0x1F 2913#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2914 2915/* ULP_TXPKT field values */ 2916enum { 2917 ULP_TXPKT_DEST_TP = 0, 2918 ULP_TXPKT_DEST_SGE, 2919 ULP_TXPKT_DEST_UP, 2920 ULP_TXPKT_DEST_DEVNULL, 2921}; 2922 2923struct ulp_txpkt { 2924 __be32 cmd_dest; 2925 __be32 len; 2926}; 2927 2928/* ulp_txpkt.cmd_dest fields */ 2929#define S_ULP_TXPKT_DATAMODIFY 23 2930#define M_ULP_TXPKT_DATAMODIFY 0x1 2931#define V_ULP_TXPKT_DATAMODIFY(x) ((x) << S_ULP_TXPKT_DATAMODIFY) 2932#define G_ULP_TXPKT_DATAMODIFY(x) \ 2933 (((x) >> S_ULP_TXPKT_DATAMODIFY) & M_ULP_TXPKT_DATAMODIFY_) 2934#define F_ULP_TXPKT_DATAMODIFY V_ULP_TXPKT_DATAMODIFY(1U) 2935 2936#define S_ULP_TXPKT_CHANNELID 22 2937#define M_ULP_TXPKT_CHANNELID 0x1 2938#define V_ULP_TXPKT_CHANNELID(x) ((x) << S_ULP_TXPKT_CHANNELID) 2939#define G_ULP_TXPKT_CHANNELID(x) \ 2940 (((x) >> S_ULP_TXPKT_CHANNELID) & M_ULP_TXPKT_CHANNELID) 2941#define F_ULP_TXPKT_CHANNELID V_ULP_TXPKT_CHANNELID(1U) 2942 2943/* ulp_txpkt.cmd_dest fields */ 2944#define S_ULP_TXPKT_DEST 16 2945#define M_ULP_TXPKT_DEST 0x3 2946#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2947 2948#define S_ULP_TXPKT_FID 4 2949#define M_ULP_TXPKT_FID 0x7ff 2950#define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2951 2952#define S_ULP_TXPKT_RO 3 2953#define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 2954#define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 2955 2956enum cpl_tx_tnl_lso_type { 2957 TX_TNL_TYPE_OPAQUE, 2958 TX_TNL_TYPE_NVGRE, 2959 TX_TNL_TYPE_VXLAN, 2960 TX_TNL_TYPE_GENEVE, 2961}; 2962 2963struct cpl_tx_tnl_lso { 2964 __be32 op_to_IpIdSplitOut; 2965 __be16 IpIdOffsetOut; 2966 __be16 UdpLenSetOut_to_TnlHdrLen; 2967 __be64 r1; 2968 __be32 Flow_to_TcpHdrLen; 2969 __be16 IpIdOffset; 2970 __be16 IpIdSplit_to_Mss; 2971 __be32 TCPSeqOffset; 2972 __be32 EthLenOffset_Size; 2973 /* encapsulated CPL (TX_PKT_XT) follows here */ 2974}; 2975 2976#define S_CPL_TX_TNL_LSO_OPCODE 24 2977#define M_CPL_TX_TNL_LSO_OPCODE 0xff 2978#define V_CPL_TX_TNL_LSO_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_OPCODE) 2979#define G_CPL_TX_TNL_LSO_OPCODE(x) \ 2980 (((x) >> S_CPL_TX_TNL_LSO_OPCODE) & M_CPL_TX_TNL_LSO_OPCODE) 2981 2982#define S_CPL_TX_TNL_LSO_FIRST 23 2983#define M_CPL_TX_TNL_LSO_FIRST 0x1 2984#define V_CPL_TX_TNL_LSO_FIRST(x) ((x) << S_CPL_TX_TNL_LSO_FIRST) 2985#define G_CPL_TX_TNL_LSO_FIRST(x) \ 2986 (((x) >> S_CPL_TX_TNL_LSO_FIRST) & M_CPL_TX_TNL_LSO_FIRST) 2987#define F_CPL_TX_TNL_LSO_FIRST V_CPL_TX_TNL_LSO_FIRST(1U) 2988 2989#define S_CPL_TX_TNL_LSO_LAST 22 2990#define M_CPL_TX_TNL_LSO_LAST 0x1 2991#define V_CPL_TX_TNL_LSO_LAST(x) ((x) << S_CPL_TX_TNL_LSO_LAST) 2992#define G_CPL_TX_TNL_LSO_LAST(x) \ 2993 (((x) >> S_CPL_TX_TNL_LSO_LAST) & M_CPL_TX_TNL_LSO_LAST) 2994#define F_CPL_TX_TNL_LSO_LAST V_CPL_TX_TNL_LSO_LAST(1U) 2995 2996#define S_CPL_TX_TNL_LSO_ETHHDRLENXOUT 21 2997#define M_CPL_TX_TNL_LSO_ETHHDRLENXOUT 0x1 2998#define V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 2999 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 3000#define G_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 3001 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 3002#define F_CPL_TX_TNL_LSO_ETHHDRLENXOUT V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(1U) 3003 3004#define S_CPL_TX_TNL_LSO_IPV6OUT 20 3005#define M_CPL_TX_TNL_LSO_IPV6OUT 0x1 3006#define V_CPL_TX_TNL_LSO_IPV6OUT(x) ((x) << S_CPL_TX_TNL_LSO_IPV6OUT) 3007#define G_CPL_TX_TNL_LSO_IPV6OUT(x) \ 3008 (((x) >> S_CPL_TX_TNL_LSO_IPV6OUT) & M_CPL_TX_TNL_LSO_IPV6OUT) 3009#define F_CPL_TX_TNL_LSO_IPV6OUT V_CPL_TX_TNL_LSO_IPV6OUT(1U) 3010 3011#define S_CPL_TX_TNL_LSO_ETHHDRLENOUT 16 3012#define M_CPL_TX_TNL_LSO_ETHHDRLENOUT 0xf 3013#define V_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 3014 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENOUT) 3015#define G_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 3016 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENOUT) 3017 3018#define S_CPL_TX_TNL_LSO_IPHDRLENOUT 4 3019#define M_CPL_TX_TNL_LSO_IPHDRLENOUT 0xfff 3020#define V_CPL_TX_TNL_LSO_IPHDRLENOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLENOUT) 3021#define G_CPL_TX_TNL_LSO_IPHDRLENOUT(x) \ 3022 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLENOUT) & M_CPL_TX_TNL_LSO_IPHDRLENOUT) 3023 3024#define S_CPL_TX_TNL_LSO_IPHDRCHKOUT 3 3025#define M_CPL_TX_TNL_LSO_IPHDRCHKOUT 0x1 3026#define V_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRCHKOUT) 3027#define G_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) \ 3028 (((x) >> S_CPL_TX_TNL_LSO_IPHDRCHKOUT) & M_CPL_TX_TNL_LSO_IPHDRCHKOUT) 3029#define F_CPL_TX_TNL_LSO_IPHDRCHKOUT V_CPL_TX_TNL_LSO_IPHDRCHKOUT(1U) 3030 3031#define S_CPL_TX_TNL_LSO_IPLENSETOUT 2 3032#define M_CPL_TX_TNL_LSO_IPLENSETOUT 0x1 3033#define V_CPL_TX_TNL_LSO_IPLENSETOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPLENSETOUT) 3034#define G_CPL_TX_TNL_LSO_IPLENSETOUT(x) \ 3035 (((x) >> S_CPL_TX_TNL_LSO_IPLENSETOUT) & M_CPL_TX_TNL_LSO_IPLENSETOUT) 3036#define F_CPL_TX_TNL_LSO_IPLENSETOUT V_CPL_TX_TNL_LSO_IPLENSETOUT(1U) 3037 3038#define S_CPL_TX_TNL_LSO_IPIDINCOUT 1 3039#define M_CPL_TX_TNL_LSO_IPIDINCOUT 0x1 3040#define V_CPL_TX_TNL_LSO_IPIDINCOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDINCOUT) 3041#define G_CPL_TX_TNL_LSO_IPIDINCOUT(x) \ 3042 (((x) >> S_CPL_TX_TNL_LSO_IPIDINCOUT) & M_CPL_TX_TNL_LSO_IPIDINCOUT) 3043#define F_CPL_TX_TNL_LSO_IPIDINCOUT V_CPL_TX_TNL_LSO_IPIDINCOUT(1U) 3044 3045#define S_CPL_TX_TNL_LSO_IPIDSPLITOUT 0 3046#define M_CPL_TX_TNL_LSO_IPIDSPLITOUT 0x1 3047#define V_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 3048 ((x) << S_CPL_TX_TNL_LSO_IPIDSPLITOUT) 3049#define G_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 3050 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLITOUT) & M_CPL_TX_TNL_LSO_IPIDSPLITOUT) 3051#define F_CPL_TX_TNL_LSO_IPIDSPLITOUT V_CPL_TX_TNL_LSO_IPIDSPLITOUT(1U) 3052 3053#define S_CPL_TX_TNL_LSO_UDPLENSETOUT 15 3054#define M_CPL_TX_TNL_LSO_UDPLENSETOUT 0x1 3055#define V_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 3056 ((x) << S_CPL_TX_TNL_LSO_UDPLENSETOUT) 3057#define G_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 3058 (((x) >> S_CPL_TX_TNL_LSO_UDPLENSETOUT) & M_CPL_TX_TNL_LSO_UDPLENSETOUT) 3059#define F_CPL_TX_TNL_LSO_UDPLENSETOUT V_CPL_TX_TNL_LSO_UDPLENSETOUT(1U) 3060 3061#define S_CPL_TX_TNL_LSO_UDPCHKCLROUT 14 3062#define M_CPL_TX_TNL_LSO_UDPCHKCLROUT 0x1 3063#define V_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 3064 ((x) << S_CPL_TX_TNL_LSO_UDPCHKCLROUT) 3065#define G_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 3066 (((x) >> S_CPL_TX_TNL_LSO_UDPCHKCLROUT) & M_CPL_TX_TNL_LSO_UDPCHKCLROUT) 3067#define F_CPL_TX_TNL_LSO_UDPCHKCLROUT V_CPL_TX_TNL_LSO_UDPCHKCLROUT(1U) 3068 3069#define S_CPL_TX_TNL_LSO_TNLTYPE 12 3070#define M_CPL_TX_TNL_LSO_TNLTYPE 0x3 3071#define V_CPL_TX_TNL_LSO_TNLTYPE(x) ((x) << S_CPL_TX_TNL_LSO_TNLTYPE) 3072#define G_CPL_TX_TNL_LSO_TNLTYPE(x) \ 3073 (((x) >> S_CPL_TX_TNL_LSO_TNLTYPE) & M_CPL_TX_TNL_LSO_TNLTYPE) 3074 3075#define S_CPL_TX_TNL_LSO_TNLHDRLEN 0 3076#define M_CPL_TX_TNL_LSO_TNLHDRLEN 0xfff 3077#define V_CPL_TX_TNL_LSO_TNLHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TNLHDRLEN) 3078#define G_CPL_TX_TNL_LSO_TNLHDRLEN(x) \ 3079 (((x) >> S_CPL_TX_TNL_LSO_TNLHDRLEN) & M_CPL_TX_TNL_LSO_TNLHDRLEN) 3080 3081#define S_CPL_TX_TNL_LSO_FLOW 21 3082#define M_CPL_TX_TNL_LSO_FLOW 0x1 3083#define V_CPL_TX_TNL_LSO_FLOW(x) ((x) << S_CPL_TX_TNL_LSO_FLOW) 3084#define G_CPL_TX_TNL_LSO_FLOW(x) \ 3085 (((x) >> S_CPL_TX_TNL_LSO_FLOW) & M_CPL_TX_TNL_LSO_FLOW) 3086#define F_CPL_TX_TNL_LSO_FLOW V_CPL_TX_TNL_LSO_FLOW(1U) 3087 3088#define S_CPL_TX_TNL_LSO_IPV6 20 3089#define M_CPL_TX_TNL_LSO_IPV6 0x1 3090#define V_CPL_TX_TNL_LSO_IPV6(x) ((x) << S_CPL_TX_TNL_LSO_IPV6) 3091#define G_CPL_TX_TNL_LSO_IPV6(x) \ 3092 (((x) >> S_CPL_TX_TNL_LSO_IPV6) & M_CPL_TX_TNL_LSO_IPV6) 3093#define F_CPL_TX_TNL_LSO_IPV6 V_CPL_TX_TNL_LSO_IPV6(1U) 3094 3095#define S_CPL_TX_TNL_LSO_ETHHDRLEN 16 3096#define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf 3097#define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN) 3098#define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \ 3099 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN) 3100 3101#define S_CPL_TX_TNL_LSO_IPHDRLEN 4 3102#define M_CPL_TX_TNL_LSO_IPHDRLEN 0xfff 3103#define V_CPL_TX_TNL_LSO_IPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLEN) 3104#define G_CPL_TX_TNL_LSO_IPHDRLEN(x) \ 3105 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLEN) & M_CPL_TX_TNL_LSO_IPHDRLEN) 3106 3107#define S_CPL_TX_TNL_LSO_TCPHDRLEN 0 3108#define M_CPL_TX_TNL_LSO_TCPHDRLEN 0xf 3109#define V_CPL_TX_TNL_LSO_TCPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TCPHDRLEN) 3110#define G_CPL_TX_TNL_LSO_TCPHDRLEN(x) \ 3111 (((x) >> S_CPL_TX_TNL_LSO_TCPHDRLEN) & M_CPL_TX_TNL_LSO_TCPHDRLEN) 3112 3113#define S_CPL_TX_TNL_LSO_IPIDSPLIT 15 3114#define M_CPL_TX_TNL_LSO_IPIDSPLIT 0x1 3115#define V_CPL_TX_TNL_LSO_IPIDSPLIT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDSPLIT) 3116#define G_CPL_TX_TNL_LSO_IPIDSPLIT(x) \ 3117 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLIT) & M_CPL_TX_TNL_LSO_IPIDSPLIT) 3118#define F_CPL_TX_TNL_LSO_IPIDSPLIT V_CPL_TX_TNL_LSO_IPIDSPLIT(1U) 3119 3120#define S_CPL_TX_TNL_LSO_ETHHDRLENX 14 3121#define M_CPL_TX_TNL_LSO_ETHHDRLENX 0x1 3122#define V_CPL_TX_TNL_LSO_ETHHDRLENX(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENX) 3123#define G_CPL_TX_TNL_LSO_ETHHDRLENX(x) \ 3124 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENX) & M_CPL_TX_TNL_LSO_ETHHDRLENX) 3125#define F_CPL_TX_TNL_LSO_ETHHDRLENX V_CPL_TX_TNL_LSO_ETHHDRLENX(1U) 3126 3127#define S_CPL_TX_TNL_LSO_MSS 0 3128#define M_CPL_TX_TNL_LSO_MSS 0x3fff 3129#define V_CPL_TX_TNL_LSO_MSS(x) ((x) << S_CPL_TX_TNL_LSO_MSS) 3130#define G_CPL_TX_TNL_LSO_MSS(x) \ 3131 (((x) >> S_CPL_TX_TNL_LSO_MSS) & M_CPL_TX_TNL_LSO_MSS) 3132 3133#define S_CPL_TX_TNL_LSO_ETHLENOFFSET 28 3134#define M_CPL_TX_TNL_LSO_ETHLENOFFSET 0xf 3135#define V_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 3136 ((x) << S_CPL_TX_TNL_LSO_ETHLENOFFSET) 3137#define G_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 3138 (((x) >> S_CPL_TX_TNL_LSO_ETHLENOFFSET) & M_CPL_TX_TNL_LSO_ETHLENOFFSET) 3139 3140#define S_CPL_TX_TNL_LSO_SIZE 0 3141#define M_CPL_TX_TNL_LSO_SIZE 0xfffffff 3142#define V_CPL_TX_TNL_LSO_SIZE(x) ((x) << S_CPL_TX_TNL_LSO_SIZE) 3143#define G_CPL_TX_TNL_LSO_SIZE(x) \ 3144 (((x) >> S_CPL_TX_TNL_LSO_SIZE) & M_CPL_TX_TNL_LSO_SIZE) 3145 3146struct cpl_rx_mps_pkt { 3147 __be32 op_to_r1_hi; 3148 __be32 r1_lo_length; 3149}; 3150 3151#define S_CPL_RX_MPS_PKT_OP 24 3152#define M_CPL_RX_MPS_PKT_OP 0xff 3153#define V_CPL_RX_MPS_PKT_OP(x) ((x) << S_CPL_RX_MPS_PKT_OP) 3154#define G_CPL_RX_MPS_PKT_OP(x) \ 3155 (((x) >> S_CPL_RX_MPS_PKT_OP) & M_CPL_RX_MPS_PKT_OP) 3156 3157#define S_CPL_RX_MPS_PKT_TYPE 20 3158#define M_CPL_RX_MPS_PKT_TYPE 0xf 3159#define V_CPL_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_RX_MPS_PKT_TYPE) 3160#define G_CPL_RX_MPS_PKT_TYPE(x) \ 3161 (((x) >> S_CPL_RX_MPS_PKT_TYPE) & M_CPL_RX_MPS_PKT_TYPE) 3162 3163/* 3164 * Values for CPL_RX_MPS_PKT_TYPE, a bit-wise orthogonal field. 3165 */ 3166#define X_CPL_RX_MPS_PKT_TYPE_PAUSE (1 << 0) 3167#define X_CPL_RX_MPS_PKT_TYPE_PPP (1 << 1) 3168#define X_CPL_RX_MPS_PKT_TYPE_QFC (1 << 2) 3169#define X_CPL_RX_MPS_PKT_TYPE_PTP (1 << 3) 3170 3171struct cpl_tx_tls_sfo { 3172 __be32 op_to_seg_len; 3173 __be32 pld_len; 3174 __be32 type_protover; 3175 __be32 r1_lo; 3176 __be32 seqno_numivs; 3177 __be32 ivgen_hdrlen; 3178 __be64 scmd1; 3179}; 3180 3181/* cpl_tx_tls_sfo macros */ 3182#define S_CPL_TX_TLS_SFO_OPCODE 24 3183#define M_CPL_TX_TLS_SFO_OPCODE 0xff 3184#define V_CPL_TX_TLS_SFO_OPCODE(x) ((x) << S_CPL_TX_TLS_SFO_OPCODE) 3185#define G_CPL_TX_TLS_SFO_OPCODE(x) \ 3186 (((x) >> S_CPL_TX_TLS_SFO_OPCODE) & M_CPL_TX_TLS_SFO_OPCODE) 3187 3188#define S_CPL_TX_TLS_SFO_DATA_TYPE 20 3189#define M_CPL_TX_TLS_SFO_DATA_TYPE 0xf 3190#define V_CPL_TX_TLS_SFO_DATA_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_DATA_TYPE) 3191#define G_CPL_TX_TLS_SFO_DATA_TYPE(x) \ 3192 (((x) >> S_CPL_TX_TLS_SFO_DATA_TYPE) & M_CPL_TX_TLS_SFO_DATA_TYPE) 3193 3194#define S_CPL_TX_TLS_SFO_CPL_LEN 16 3195#define M_CPL_TX_TLS_SFO_CPL_LEN 0xf 3196#define V_CPL_TX_TLS_SFO_CPL_LEN(x) ((x) << S_CPL_TX_TLS_SFO_CPL_LEN) 3197#define G_CPL_TX_TLS_SFO_CPL_LEN(x) \ 3198 (((x) >> S_CPL_TX_TLS_SFO_CPL_LEN) & M_CPL_TX_TLS_SFO_CPL_LEN) 3199 3200#define S_CPL_TX_TLS_SFO_SEG_LEN 0 3201#define M_CPL_TX_TLS_SFO_SEG_LEN 0xffff 3202#define V_CPL_TX_TLS_SFO_SEG_LEN(x) ((x) << S_CPL_TX_TLS_SFO_SEG_LEN) 3203#define G_CPL_TX_TLS_SFO_SEG_LEN(x) \ 3204 (((x) >> S_CPL_TX_TLS_SFO_SEG_LEN) & M_CPL_TX_TLS_SFO_SEG_LEN) 3205 3206#define S_CPL_TX_TLS_SFO_TYPE 24 3207#define M_CPL_TX_TLS_SFO_TYPE 0xff 3208#define V_CPL_TX_TLS_SFO_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_TYPE) 3209#define G_CPL_TX_TLS_SFO_TYPE(x) \ 3210 (((x) >> S_CPL_TX_TLS_SFO_TYPE) & M_CPL_TX_TLS_SFO_TYPE) 3211 3212#define S_CPL_TX_TLS_SFO_PROTOVER 8 3213#define M_CPL_TX_TLS_SFO_PROTOVER 0xffff 3214#define V_CPL_TX_TLS_SFO_PROTOVER(x) ((x) << S_CPL_TX_TLS_SFO_PROTOVER) 3215#define G_CPL_TX_TLS_SFO_PROTOVER(x) \ 3216 (((x) >> S_CPL_TX_TLS_SFO_PROTOVER) & M_CPL_TX_TLS_SFO_PROTOVER) 3217 3218struct cpl_tls_data { 3219 RSS_HDR 3220 union opcode_tid ot; 3221 __be32 length_pkd; 3222 __be32 seq; 3223 __be32 r1; 3224}; 3225 3226#define S_CPL_TLS_DATA_OPCODE 24 3227#define M_CPL_TLS_DATA_OPCODE 0xff 3228#define V_CPL_TLS_DATA_OPCODE(x) ((x) << S_CPL_TLS_DATA_OPCODE) 3229#define G_CPL_TLS_DATA_OPCODE(x) \ 3230 (((x) >> S_CPL_TLS_DATA_OPCODE) & M_CPL_TLS_DATA_OPCODE) 3231 3232#define S_CPL_TLS_DATA_TID 0 3233#define M_CPL_TLS_DATA_TID 0xffffff 3234#define V_CPL_TLS_DATA_TID(x) ((x) << S_CPL_TLS_DATA_TID) 3235#define G_CPL_TLS_DATA_TID(x) \ 3236 (((x) >> S_CPL_TLS_DATA_TID) & M_CPL_TLS_DATA_TID) 3237 3238#define S_CPL_TLS_DATA_LENGTH 0 3239#define M_CPL_TLS_DATA_LENGTH 0xffff 3240#define V_CPL_TLS_DATA_LENGTH(x) ((x) << S_CPL_TLS_DATA_LENGTH) 3241#define G_CPL_TLS_DATA_LENGTH(x) \ 3242 (((x) >> S_CPL_TLS_DATA_LENGTH) & M_CPL_TLS_DATA_LENGTH) 3243 3244struct cpl_rx_tls_cmp { 3245 RSS_HDR 3246 union opcode_tid ot; 3247 __be32 pdulength_length; 3248 __be32 seq; 3249 __be32 ddp_report; 3250 __be32 r; 3251 __be32 ddp_valid; 3252}; 3253 3254#define S_CPL_RX_TLS_CMP_OPCODE 24 3255#define M_CPL_RX_TLS_CMP_OPCODE 0xff 3256#define V_CPL_RX_TLS_CMP_OPCODE(x) ((x) << S_CPL_RX_TLS_CMP_OPCODE) 3257#define G_CPL_RX_TLS_CMP_OPCODE(x) \ 3258 (((x) >> S_CPL_RX_TLS_CMP_OPCODE) & M_CPL_RX_TLS_CMP_OPCODE) 3259 3260#define S_CPL_RX_TLS_CMP_TID 0 3261#define M_CPL_RX_TLS_CMP_TID 0xffffff 3262#define V_CPL_RX_TLS_CMP_TID(x) ((x) << S_CPL_RX_TLS_CMP_TID) 3263#define G_CPL_RX_TLS_CMP_TID(x) \ 3264 (((x) >> S_CPL_RX_TLS_CMP_TID) & M_CPL_RX_TLS_CMP_TID) 3265 3266#define S_CPL_RX_TLS_CMP_PDULENGTH 16 3267#define M_CPL_RX_TLS_CMP_PDULENGTH 0xffff 3268#define V_CPL_RX_TLS_CMP_PDULENGTH(x) ((x) << S_CPL_RX_TLS_CMP_PDULENGTH) 3269#define G_CPL_RX_TLS_CMP_PDULENGTH(x) \ 3270 (((x) >> S_CPL_RX_TLS_CMP_PDULENGTH) & M_CPL_RX_TLS_CMP_PDULENGTH) 3271 3272#define S_CPL_RX_TLS_CMP_LENGTH 0 3273#define M_CPL_RX_TLS_CMP_LENGTH 0xffff 3274#define V_CPL_RX_TLS_CMP_LENGTH(x) ((x) << S_CPL_RX_TLS_CMP_LENGTH) 3275#define G_CPL_RX_TLS_CMP_LENGTH(x) \ 3276 (((x) >> S_CPL_RX_TLS_CMP_LENGTH) & M_CPL_RX_TLS_CMP_LENGTH) 3277 3278#define S_SCMD_SEQ_NO_CTRL 29 3279#define M_SCMD_SEQ_NO_CTRL 0x3 3280#define V_SCMD_SEQ_NO_CTRL(x) ((x) << S_SCMD_SEQ_NO_CTRL) 3281#define G_SCMD_SEQ_NO_CTRL(x) \ 3282 (((x) >> S_SCMD_SEQ_NO_CTRL) & M_SCMD_SEQ_NO_CTRL) 3283 3284/* StsFieldPrsnt- Status field at the end of the TLS PDU */ 3285#define S_SCMD_STATUS_PRESENT 28 3286#define M_SCMD_STATUS_PRESENT 0x1 3287#define V_SCMD_STATUS_PRESENT(x) ((x) << S_SCMD_STATUS_PRESENT) 3288#define G_SCMD_STATUS_PRESENT(x) \ 3289 (((x) >> S_SCMD_STATUS_PRESENT) & M_SCMD_STATUS_PRESENT) 3290#define F_SCMD_STATUS_PRESENT V_SCMD_STATUS_PRESENT(1U) 3291 3292/* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic, 3293 * 3-15: Reserved. */ 3294#define S_SCMD_PROTO_VERSION 24 3295#define M_SCMD_PROTO_VERSION 0xf 3296#define V_SCMD_PROTO_VERSION(x) ((x) << S_SCMD_PROTO_VERSION) 3297#define G_SCMD_PROTO_VERSION(x) \ 3298 (((x) >> S_SCMD_PROTO_VERSION) & M_SCMD_PROTO_VERSION) 3299 3300/* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */ 3301#define S_SCMD_ENC_DEC_CTRL 23 3302#define M_SCMD_ENC_DEC_CTRL 0x1 3303#define V_SCMD_ENC_DEC_CTRL(x) ((x) << S_SCMD_ENC_DEC_CTRL) 3304#define G_SCMD_ENC_DEC_CTRL(x) \ 3305 (((x) >> S_SCMD_ENC_DEC_CTRL) & M_SCMD_ENC_DEC_CTRL) 3306#define F_SCMD_ENC_DEC_CTRL V_SCMD_ENC_DEC_CTRL(1U) 3307 3308/* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */ 3309#define S_SCMD_CIPH_AUTH_SEQ_CTRL 22 3310#define M_SCMD_CIPH_AUTH_SEQ_CTRL 0x1 3311#define V_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 3312 ((x) << S_SCMD_CIPH_AUTH_SEQ_CTRL) 3313#define G_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 3314 (((x) >> S_SCMD_CIPH_AUTH_SEQ_CTRL) & M_SCMD_CIPH_AUTH_SEQ_CTRL) 3315#define F_SCMD_CIPH_AUTH_SEQ_CTRL V_SCMD_CIPH_AUTH_SEQ_CTRL(1U) 3316 3317/* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR, 3318 * 4:Generic-AES, 5-15: Reserved. */ 3319#define S_SCMD_CIPH_MODE 18 3320#define M_SCMD_CIPH_MODE 0xf 3321#define V_SCMD_CIPH_MODE(x) ((x) << S_SCMD_CIPH_MODE) 3322#define G_SCMD_CIPH_MODE(x) \ 3323 (((x) >> S_SCMD_CIPH_MODE) & M_SCMD_CIPH_MODE) 3324 3325/* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256 3326 * 4-15: Reserved */ 3327#define S_SCMD_AUTH_MODE 14 3328#define M_SCMD_AUTH_MODE 0xf 3329#define V_SCMD_AUTH_MODE(x) ((x) << S_SCMD_AUTH_MODE) 3330#define G_SCMD_AUTH_MODE(x) \ 3331 (((x) >> S_SCMD_AUTH_MODE) & M_SCMD_AUTH_MODE) 3332 3333/* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation 3334 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved 3335 */ 3336#define S_SCMD_HMAC_CTRL 11 3337#define M_SCMD_HMAC_CTRL 0x7 3338#define V_SCMD_HMAC_CTRL(x) ((x) << S_SCMD_HMAC_CTRL) 3339#define G_SCMD_HMAC_CTRL(x) \ 3340 (((x) >> S_SCMD_HMAC_CTRL) & M_SCMD_HMAC_CTRL) 3341 3342/* IvSize - IV size in units of 2 bytes */ 3343#define S_SCMD_IV_SIZE 7 3344#define M_SCMD_IV_SIZE 0xf 3345#define V_SCMD_IV_SIZE(x) ((x) << S_SCMD_IV_SIZE) 3346#define G_SCMD_IV_SIZE(x) \ 3347 (((x) >> S_SCMD_IV_SIZE) & M_SCMD_IV_SIZE) 3348 3349/* NumIVs - Number of IVs */ 3350#define S_SCMD_NUM_IVS 0 3351#define M_SCMD_NUM_IVS 0x7f 3352#define V_SCMD_NUM_IVS(x) ((x) << S_SCMD_NUM_IVS) 3353#define G_SCMD_NUM_IVS(x) \ 3354 (((x) >> S_SCMD_NUM_IVS) & M_SCMD_NUM_IVS) 3355 3356/* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber 3357 * (below) are used as Cid (connection id for debug status), these 3358 * bits are padded to zero for forming the 64 bit 3359 * sequence number for TLS 3360 */ 3361#define S_SCMD_ENB_DBGID 31 3362#define M_SCMD_ENB_DBGID 0x1 3363#define V_SCMD_ENB_DBGID(x) ((x) << S_SCMD_ENB_DBGID) 3364#define G_SCMD_ENB_DBGID(x) \ 3365 (((x) >> S_SCMD_ENB_DBGID) & M_SCMD_ENB_DBGID) 3366 3367/* IV generation in SW. */ 3368#define S_SCMD_IV_GEN_CTRL 30 3369#define M_SCMD_IV_GEN_CTRL 0x1 3370#define V_SCMD_IV_GEN_CTRL(x) ((x) << S_SCMD_IV_GEN_CTRL) 3371#define G_SCMD_IV_GEN_CTRL(x) \ 3372 (((x) >> S_SCMD_IV_GEN_CTRL) & M_SCMD_IV_GEN_CTRL) 3373#define F_SCMD_IV_GEN_CTRL V_SCMD_IV_GEN_CTRL(1U) 3374 3375/* More frags */ 3376#define S_SCMD_MORE_FRAGS 20 3377#define M_SCMD_MORE_FRAGS 0x1 3378#define V_SCMD_MORE_FRAGS(x) ((x) << S_SCMD_MORE_FRAGS) 3379#define G_SCMD_MORE_FRAGS(x) (((x) >> S_SCMD_MORE_FRAGS) & M_SCMD_MORE_FRAGS) 3380 3381/*last frag */ 3382#define S_SCMD_LAST_FRAG 19 3383#define M_SCMD_LAST_FRAG 0x1 3384#define V_SCMD_LAST_FRAG(x) ((x) << S_SCMD_LAST_FRAG) 3385#define G_SCMD_LAST_FRAG(x) (((x) >> S_SCMD_LAST_FRAG) & M_SCMD_LAST_FRAG) 3386 3387/* TlsCompPdu */ 3388#define S_SCMD_TLS_COMPPDU 18 3389#define M_SCMD_TLS_COMPPDU 0x1 3390#define V_SCMD_TLS_COMPPDU(x) ((x) << S_SCMD_TLS_COMPPDU) 3391#define G_SCMD_TLS_COMPPDU(x) (((x) >> S_SCMD_TLS_COMPPDU) & M_SCMD_TLS_COMPPDU) 3392 3393/* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/ 3394#define S_SCMD_KEY_CTX_INLINE 17 3395#define M_SCMD_KEY_CTX_INLINE 0x1 3396#define V_SCMD_KEY_CTX_INLINE(x) ((x) << S_SCMD_KEY_CTX_INLINE) 3397#define G_SCMD_KEY_CTX_INLINE(x) \ 3398 (((x) >> S_SCMD_KEY_CTX_INLINE) & M_SCMD_KEY_CTX_INLINE) 3399#define F_SCMD_KEY_CTX_INLINE V_SCMD_KEY_CTX_INLINE(1U) 3400 3401/* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */ 3402#define S_SCMD_TLS_FRAG_ENABLE 16 3403#define M_SCMD_TLS_FRAG_ENABLE 0x1 3404#define V_SCMD_TLS_FRAG_ENABLE(x) ((x) << S_SCMD_TLS_FRAG_ENABLE) 3405#define G_SCMD_TLS_FRAG_ENABLE(x) \ 3406 (((x) >> S_SCMD_TLS_FRAG_ENABLE) & M_SCMD_TLS_FRAG_ENABLE) 3407#define F_SCMD_TLS_FRAG_ENABLE V_SCMD_TLS_FRAG_ENABLE(1U) 3408 3409/* MacOnly - Only send the MAC and discard PDU. This is valid for hash only 3410 * modes, in this case TLS_TX will drop the PDU and only 3411 * send back the MAC bytes. */ 3412#define S_SCMD_MAC_ONLY 15 3413#define M_SCMD_MAC_ONLY 0x1 3414#define V_SCMD_MAC_ONLY(x) ((x) << S_SCMD_MAC_ONLY) 3415#define G_SCMD_MAC_ONLY(x) \ 3416 (((x) >> S_SCMD_MAC_ONLY) & M_SCMD_MAC_ONLY) 3417#define F_SCMD_MAC_ONLY V_SCMD_MAC_ONLY(1U) 3418 3419/* AadIVDrop - Drop the AAD and IV fields. Useful in protocols 3420 * which have complex AAD and IV formations Eg:AES-CCM 3421 */ 3422#define S_SCMD_AADIVDROP 14 3423#define M_SCMD_AADIVDROP 0x1 3424#define V_SCMD_AADIVDROP(x) ((x) << S_SCMD_AADIVDROP) 3425#define G_SCMD_AADIVDROP(x) \ 3426 (((x) >> S_SCMD_AADIVDROP) & M_SCMD_AADIVDROP) 3427#define F_SCMD_AADIVDROP V_SCMD_AADIVDROP(1U) 3428 3429/* HdrLength - Length of all headers excluding TLS header 3430 * present before start of crypto PDU/payload. */ 3431#define S_SCMD_HDR_LEN 0 3432#define M_SCMD_HDR_LEN 0x3fff 3433#define V_SCMD_HDR_LEN(x) ((x) << S_SCMD_HDR_LEN) 3434#define G_SCMD_HDR_LEN(x) \ 3435 (((x) >> S_SCMD_HDR_LEN) & M_SCMD_HDR_LEN) 3436 3437struct cpl_tx_sec_pdu { 3438 __be32 op_ivinsrtofst; 3439 __be32 pldlen; 3440 __be32 aadstart_cipherstop_hi; 3441 __be32 cipherstop_lo_authinsert; 3442 __be32 seqno_numivs; 3443 __be32 ivgen_hdrlen; 3444 __be64 scmd1; 3445}; 3446 3447#define S_CPL_TX_SEC_PDU_OPCODE 24 3448#define M_CPL_TX_SEC_PDU_OPCODE 0xff 3449#define V_CPL_TX_SEC_PDU_OPCODE(x) ((x) << S_CPL_TX_SEC_PDU_OPCODE) 3450#define G_CPL_TX_SEC_PDU_OPCODE(x) \ 3451 (((x) >> S_CPL_TX_SEC_PDU_OPCODE) & M_CPL_TX_SEC_PDU_OPCODE) 3452 3453/* RX Channel Id */ 3454#define S_CPL_TX_SEC_PDU_RXCHID 22 3455#define M_CPL_TX_SEC_PDU_RXCHID 0x1 3456#define V_CPL_TX_SEC_PDU_RXCHID(x) ((x) << S_CPL_TX_SEC_PDU_RXCHID) 3457#define G_CPL_TX_SEC_PDU_RXCHID(x) \ 3458(((x) >> S_CPL_TX_SEC_PDU_RXCHID) & M_CPL_TX_SEC_PDU_RXCHID) 3459#define F_CPL_TX_SEC_PDU_RXCHID V_CPL_TX_SEC_PDU_RXCHID(1U) 3460 3461/* Ack Follows */ 3462#define S_CPL_TX_SEC_PDU_ACKFOLLOWS 21 3463#define M_CPL_TX_SEC_PDU_ACKFOLLOWS 0x1 3464#define V_CPL_TX_SEC_PDU_ACKFOLLOWS(x) ((x) << S_CPL_TX_SEC_PDU_ACKFOLLOWS) 3465#define G_CPL_TX_SEC_PDU_ACKFOLLOWS(x) \ 3466(((x) >> S_CPL_TX_SEC_PDU_ACKFOLLOWS) & M_CPL_TX_SEC_PDU_ACKFOLLOWS) 3467#define F_CPL_TX_SEC_PDU_ACKFOLLOWS V_CPL_TX_SEC_PDU_ACKFOLLOWS(1U) 3468 3469/* Loopback bit in cpl_tx_sec_pdu */ 3470#define S_CPL_TX_SEC_PDU_ULPTXLPBK 20 3471#define M_CPL_TX_SEC_PDU_ULPTXLPBK 0x1 3472#define V_CPL_TX_SEC_PDU_ULPTXLPBK(x) ((x) << S_CPL_TX_SEC_PDU_ULPTXLPBK) 3473#define G_CPL_TX_SEC_PDU_ULPTXLPBK(x) \ 3474(((x) >> S_CPL_TX_SEC_PDU_ULPTXLPBK) & M_CPL_TX_SEC_PDU_ULPTXLPBK) 3475#define F_CPL_TX_SEC_PDU_ULPTXLPBK V_CPL_TX_SEC_PDU_ULPTXLPBK(1U) 3476 3477/* Length of cpl header encapsulated */ 3478#define S_CPL_TX_SEC_PDU_CPLLEN 16 3479#define M_CPL_TX_SEC_PDU_CPLLEN 0xf 3480#define V_CPL_TX_SEC_PDU_CPLLEN(x) ((x) << S_CPL_TX_SEC_PDU_CPLLEN) 3481#define G_CPL_TX_SEC_PDU_CPLLEN(x) \ 3482 (((x) >> S_CPL_TX_SEC_PDU_CPLLEN) & M_CPL_TX_SEC_PDU_CPLLEN) 3483 3484/* PlaceHolder */ 3485#define S_CPL_TX_SEC_PDU_PLACEHOLDER 10 3486#define M_CPL_TX_SEC_PDU_PLACEHOLDER 0x1 3487#define V_CPL_TX_SEC_PDU_PLACEHOLDER(x) ((x) << S_CPL_TX_SEC_PDU_PLACEHOLDER) 3488#define G_CPL_TX_SEC_PDU_PLACEHOLDER(x) \ 3489 (((x) >> S_CPL_TX_SEC_PDU_PLACEHOLDER) & \ 3490 M_CPL_TX_SEC_PDU_PLACEHOLDER) 3491 3492/* IvInsrtOffset: Insertion location for IV */ 3493#define S_CPL_TX_SEC_PDU_IVINSRTOFST 0 3494#define M_CPL_TX_SEC_PDU_IVINSRTOFST 0x3ff 3495#define V_CPL_TX_SEC_PDU_IVINSRTOFST(x) ((x) << S_CPL_TX_SEC_PDU_IVINSRTOFST) 3496#define G_CPL_TX_SEC_PDU_IVINSRTOFST(x) \ 3497 (((x) >> S_CPL_TX_SEC_PDU_IVINSRTOFST) & \ 3498 M_CPL_TX_SEC_PDU_IVINSRTOFST) 3499 3500/* AadStartOffset: Offset in bytes for AAD start from 3501 * the first byte following 3502 * the pkt headers (0-255 3503 * bytes) */ 3504#define S_CPL_TX_SEC_PDU_AADSTART 24 3505#define M_CPL_TX_SEC_PDU_AADSTART 0xff 3506#define V_CPL_TX_SEC_PDU_AADSTART(x) ((x) << S_CPL_TX_SEC_PDU_AADSTART) 3507#define G_CPL_TX_SEC_PDU_AADSTART(x) \ 3508 (((x) >> S_CPL_TX_SEC_PDU_AADSTART) & \ 3509 M_CPL_TX_SEC_PDU_AADSTART) 3510 3511/* AadStopOffset: offset in bytes for AAD stop/end from the first byte following 3512 * the pkt headers (0-511 bytes) */ 3513#define S_CPL_TX_SEC_PDU_AADSTOP 15 3514#define M_CPL_TX_SEC_PDU_AADSTOP 0x1ff 3515#define V_CPL_TX_SEC_PDU_AADSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AADSTOP) 3516#define G_CPL_TX_SEC_PDU_AADSTOP(x) \ 3517 (((x) >> S_CPL_TX_SEC_PDU_AADSTOP) & M_CPL_TX_SEC_PDU_AADSTOP) 3518 3519/* CipherStartOffset: offset in bytes for encryption/decryption start from the 3520 * first byte following the pkt headers (0-1023 3521 * bytes) */ 3522#define S_CPL_TX_SEC_PDU_CIPHERSTART 5 3523#define M_CPL_TX_SEC_PDU_CIPHERSTART 0x3ff 3524#define V_CPL_TX_SEC_PDU_CIPHERSTART(x) ((x) << S_CPL_TX_SEC_PDU_CIPHERSTART) 3525#define G_CPL_TX_SEC_PDU_CIPHERSTART(x) \ 3526 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTART) & \ 3527 M_CPL_TX_SEC_PDU_CIPHERSTART) 3528 3529/* CipherStopOffset: offset in bytes for encryption/decryption end 3530 * from end of the payload of this command (0-511 bytes) */ 3531#define S_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0 3532#define M_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0x1f 3533#define V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 3534 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 3535#define G_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 3536 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) & \ 3537 M_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 3538 3539#define S_CPL_TX_SEC_PDU_CIPHERSTOP_LO 28 3540#define M_CPL_TX_SEC_PDU_CIPHERSTOP_LO 0xf 3541#define V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 3542 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 3543#define G_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 3544 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) & \ 3545 M_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 3546 3547/* AuthStartOffset: offset in bytes for authentication start from 3548 * the first byte following the pkt headers (0-1023) 3549 * */ 3550#define S_CPL_TX_SEC_PDU_AUTHSTART 18 3551#define M_CPL_TX_SEC_PDU_AUTHSTART 0x3ff 3552#define V_CPL_TX_SEC_PDU_AUTHSTART(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTART) 3553#define G_CPL_TX_SEC_PDU_AUTHSTART(x) \ 3554 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTART) & \ 3555 M_CPL_TX_SEC_PDU_AUTHSTART) 3556 3557/* AuthStopOffset: offset in bytes for authentication 3558 * end from end of the payload of this command (0-511 Bytes) */ 3559#define S_CPL_TX_SEC_PDU_AUTHSTOP 9 3560#define M_CPL_TX_SEC_PDU_AUTHSTOP 0x1ff 3561#define V_CPL_TX_SEC_PDU_AUTHSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTOP) 3562#define G_CPL_TX_SEC_PDU_AUTHSTOP(x) \ 3563 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTOP) & \ 3564 M_CPL_TX_SEC_PDU_AUTHSTOP) 3565 3566/* AuthInsrtOffset: offset in bytes for authentication insertion 3567 * from end of the payload of this command (0-511 bytes) */ 3568#define S_CPL_TX_SEC_PDU_AUTHINSERT 0 3569#define M_CPL_TX_SEC_PDU_AUTHINSERT 0x1ff 3570#define V_CPL_TX_SEC_PDU_AUTHINSERT(x) ((x) << S_CPL_TX_SEC_PDU_AUTHINSERT) 3571#define G_CPL_TX_SEC_PDU_AUTHINSERT(x) \ 3572 (((x) >> S_CPL_TX_SEC_PDU_AUTHINSERT) & \ 3573 M_CPL_TX_SEC_PDU_AUTHINSERT) 3574 3575struct cpl_rx_phys_dsgl { 3576 __be32 op_to_tid; 3577 __be32 pcirlxorder_to_noofsgentr; 3578 struct rss_header rss_hdr_int; 3579}; 3580 3581#define S_CPL_RX_PHYS_DSGL_OPCODE 24 3582#define M_CPL_RX_PHYS_DSGL_OPCODE 0xff 3583#define V_CPL_RX_PHYS_DSGL_OPCODE(x) ((x) << S_CPL_RX_PHYS_DSGL_OPCODE) 3584#define G_CPL_RX_PHYS_DSGL_OPCODE(x) \ 3585 (((x) >> S_CPL_RX_PHYS_DSGL_OPCODE) & M_CPL_RX_PHYS_DSGL_OPCODE) 3586 3587#define S_CPL_RX_PHYS_DSGL_ISRDMA 23 3588#define M_CPL_RX_PHYS_DSGL_ISRDMA 0x1 3589#define V_CPL_RX_PHYS_DSGL_ISRDMA(x) ((x) << S_CPL_RX_PHYS_DSGL_ISRDMA) 3590#define G_CPL_RX_PHYS_DSGL_ISRDMA(x) \ 3591 (((x) >> S_CPL_RX_PHYS_DSGL_ISRDMA) & M_CPL_RX_PHYS_DSGL_ISRDMA) 3592#define F_CPL_RX_PHYS_DSGL_ISRDMA V_CPL_RX_PHYS_DSGL_ISRDMA(1U) 3593 3594#define S_CPL_RX_PHYS_DSGL_RSVD1 20 3595#define M_CPL_RX_PHYS_DSGL_RSVD1 0x7 3596#define V_CPL_RX_PHYS_DSGL_RSVD1(x) ((x) << S_CPL_RX_PHYS_DSGL_RSVD1) 3597#define G_CPL_RX_PHYS_DSGL_RSVD1(x) \ 3598 (((x) >> S_CPL_RX_PHYS_DSGL_RSVD1) & M_CPL_RX_PHYS_DSGL_RSVD1) 3599 3600#define S_CPL_RX_PHYS_DSGL_PCIRLXORDER 31 3601#define M_CPL_RX_PHYS_DSGL_PCIRLXORDER 0x1 3602#define V_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 3603 ((x) << S_CPL_RX_PHYS_DSGL_PCIRLXORDER) 3604#define G_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 3605 (((x) >> S_CPL_RX_PHYS_DSGL_PCIRLXORDER) & \ 3606 M_CPL_RX_PHYS_DSGL_PCIRLXORDER) 3607#define F_CPL_RX_PHYS_DSGL_PCIRLXORDER V_CPL_RX_PHYS_DSGL_PCIRLXORDER(1U) 3608 3609#define S_CPL_RX_PHYS_DSGL_PCINOSNOOP 30 3610#define M_CPL_RX_PHYS_DSGL_PCINOSNOOP 0x1 3611#define V_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 3612 ((x) << S_CPL_RX_PHYS_DSGL_PCINOSNOOP) 3613#define G_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 3614 (((x) >> S_CPL_RX_PHYS_DSGL_PCINOSNOOP) & \ 3615 M_CPL_RX_PHYS_DSGL_PCINOSNOOP) 3616#define F_CPL_RX_PHYS_DSGL_PCINOSNOOP V_CPL_RX_PHYS_DSGL_PCINOSNOOP(1U) 3617 3618#define S_CPL_RX_PHYS_DSGL_PCITPHNTENB 29 3619#define M_CPL_RX_PHYS_DSGL_PCITPHNTENB 0x1 3620#define V_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 3621 ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNTENB) 3622#define G_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 3623 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNTENB) & \ 3624 M_CPL_RX_PHYS_DSGL_PCITPHNTENB) 3625#define F_CPL_RX_PHYS_DSGL_PCITPHNTENB V_CPL_RX_PHYS_DSGL_PCITPHNTENB(1U) 3626 3627#define S_CPL_RX_PHYS_DSGL_PCITPHNT 27 3628#define M_CPL_RX_PHYS_DSGL_PCITPHNT 0x3 3629#define V_CPL_RX_PHYS_DSGL_PCITPHNT(x) ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNT) 3630#define G_CPL_RX_PHYS_DSGL_PCITPHNT(x) \ 3631 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNT) & \ 3632 M_CPL_RX_PHYS_DSGL_PCITPHNT) 3633 3634#define S_CPL_RX_PHYS_DSGL_DCAID 16 3635#define M_CPL_RX_PHYS_DSGL_DCAID 0x7ff 3636#define V_CPL_RX_PHYS_DSGL_DCAID(x) ((x) << S_CPL_RX_PHYS_DSGL_DCAID) 3637#define G_CPL_RX_PHYS_DSGL_DCAID(x) \ 3638 (((x) >> S_CPL_RX_PHYS_DSGL_DCAID) & \ 3639 M_CPL_RX_PHYS_DSGL_DCAID) 3640 3641#define S_CPL_RX_PHYS_DSGL_NOOFSGENTR 0 3642#define M_CPL_RX_PHYS_DSGL_NOOFSGENTR 0xffff 3643#define V_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 3644 ((x) << S_CPL_RX_PHYS_DSGL_NOOFSGENTR) 3645#define G_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 3646 (((x) >> S_CPL_RX_PHYS_DSGL_NOOFSGENTR) & \ 3647 M_CPL_RX_PHYS_DSGL_NOOFSGENTR) 3648 3649/* CPL_TX_TLS_ACK */ 3650struct cpl_tx_tls_ack { 3651 __be32 op_to_Rsvd2; 3652 __be32 PldLen; 3653 __be64 Rsvd3; 3654}; 3655 3656#define S_CPL_TX_TLS_ACK_OPCODE 24 3657#define M_CPL_TX_TLS_ACK_OPCODE 0xff 3658#define V_CPL_TX_TLS_ACK_OPCODE(x) ((x) << S_CPL_TX_TLS_ACK_OPCODE) 3659#define G_CPL_TX_TLS_ACK_OPCODE(x) \ 3660 (((x) >> S_CPL_TX_TLS_ACK_OPCODE) & M_CPL_TX_TLS_ACK_OPCODE) 3661 3662#define S_CPL_TX_TLS_ACK_RSVD1 23 3663#define M_CPL_TX_TLS_ACK_RSVD1 0x1 3664#define V_CPL_TX_TLS_ACK_RSVD1(x) ((x) << S_CPL_TX_TLS_ACK_RSVD1) 3665#define G_CPL_TX_TLS_ACK_RSVD1(x) \ 3666 (((x) >> S_CPL_TX_TLS_ACK_RSVD1) & M_CPL_TX_TLS_ACK_RSVD1) 3667#define F_CPL_TX_TLS_ACK_RSVD1 V_CPL_TX_TLS_ACK_RSVD1(1U) 3668 3669#define S_CPL_TX_TLS_ACK_RXCHID 22 3670#define M_CPL_TX_TLS_ACK_RXCHID 0x1 3671#define V_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_CPL_TX_TLS_ACK_RXCHID) 3672#define G_CPL_TX_TLS_ACK_RXCHID(x) \ 3673 (((x) >> S_CPL_TX_TLS_ACK_RXCHID) & M_CPL_TX_TLS_ACK_RXCHID) 3674#define F_CPL_TX_TLS_ACK_RXCHID V_CPL_TX_TLS_ACK_RXCHID(1U) 3675 3676#define S_CPL_TX_TLS_ACK_FWMSG 21 3677#define M_CPL_TX_TLS_ACK_FWMSG 0x1 3678#define V_CPL_TX_TLS_ACK_FWMSG(x) ((x) << S_CPL_TX_TLS_ACK_FWMSG) 3679#define G_CPL_TX_TLS_ACK_FWMSG(x) \ 3680 (((x) >> S_CPL_TX_TLS_ACK_FWMSG) & M_CPL_TX_TLS_ACK_FWMSG) 3681#define F_CPL_TX_TLS_ACK_FWMSG V_CPL_TX_TLS_ACK_FWMSG(1U) 3682 3683#define S_CPL_TX_TLS_ACK_ULPTXLPBK 20 3684#define M_CPL_TX_TLS_ACK_ULPTXLPBK 0x1 3685#define V_CPL_TX_TLS_ACK_ULPTXLPBK(x) ((x) << S_CPL_TX_TLS_ACK_ULPTXLPBK) 3686#define G_CPL_TX_TLS_ACK_ULPTXLPBK(x) \ 3687 (((x) >> S_CPL_TX_TLS_ACK_ULPTXLPBK) & M_CPL_TX_TLS_ACK_ULPTXLPBK) 3688#define F_CPL_TX_TLS_ACK_ULPTXLPBK V_CPL_TX_TLS_ACK_ULPTXLPBK(1U) 3689 3690#define S_CPL_TX_TLS_ACK_CPLLEN 16 3691#define M_CPL_TX_TLS_ACK_CPLLEN 0xf 3692#define V_CPL_TX_TLS_ACK_CPLLEN(x) ((x) << S_CPL_TX_TLS_ACK_CPLLEN) 3693#define G_CPL_TX_TLS_ACK_CPLLEN(x) \ 3694 (((x) >> S_CPL_TX_TLS_ACK_CPLLEN) & M_CPL_TX_TLS_ACK_CPLLEN) 3695 3696#define S_CPL_TX_TLS_ACK_COMPLONERR 15 3697#define M_CPL_TX_TLS_ACK_COMPLONERR 0x1 3698#define V_CPL_TX_TLS_ACK_COMPLONERR(x) ((x) << S_CPL_TX_TLS_ACK_COMPLONERR) 3699#define G_CPL_TX_TLS_ACK_COMPLONERR(x) \ 3700 (((x) >> S_CPL_TX_TLS_ACK_COMPLONERR) & M_CPL_TX_TLS_ACK_COMPLONERR) 3701#define F_CPL_TX_TLS_ACK_COMPLONERR V_CPL_TX_TLS_ACK_COMPLONERR(1U) 3702 3703#define S_CPL_TX_TLS_ACK_LCB 14 3704#define M_CPL_TX_TLS_ACK_LCB 0x1 3705#define V_CPL_TX_TLS_ACK_LCB(x) ((x) << S_CPL_TX_TLS_ACK_LCB) 3706#define G_CPL_TX_TLS_ACK_LCB(x) \ 3707 (((x) >> S_CPL_TX_TLS_ACK_LCB) & M_CPL_TX_TLS_ACK_LCB) 3708#define F_CPL_TX_TLS_ACK_LCB V_CPL_TX_TLS_ACK_LCB(1U) 3709 3710#define S_CPL_TX_TLS_ACK_PHASH 13 3711#define M_CPL_TX_TLS_ACK_PHASH 0x1 3712#define V_CPL_TX_TLS_ACK_PHASH(x) ((x) << S_CPL_TX_TLS_ACK_PHASH) 3713#define G_CPL_TX_TLS_ACK_PHASH(x) \ 3714 (((x) >> S_CPL_TX_TLS_ACK_PHASH) & M_CPL_TX_TLS_ACK_PHASH) 3715#define F_CPL_TX_TLS_ACK_PHASH V_CPL_TX_TLS_ACK_PHASH(1U) 3716 3717#define S_CPL_TX_TLS_ACK_RSVD2 0 3718#define M_CPL_TX_TLS_ACK_RSVD2 0x1fff 3719#define V_CPL_TX_TLS_ACK_RSVD2(x) ((x) << S_CPL_TX_TLS_ACK_RSVD2) 3720#define G_CPL_TX_TLS_ACK_RSVD2(x) \ 3721 (((x) >> S_CPL_TX_TLS_ACK_RSVD2) & M_CPL_TX_TLS_ACK_RSVD2) 3722 3723#endif /* T4_MSG_H */ 3724