common.h revision 346967
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/11/sys/dev/cxgbe/common/common.h 346967 2019-04-30 17:30:37Z np $ 27 * 28 */ 29 30#ifndef __CHELSIO_COMMON_H 31#define __CHELSIO_COMMON_H 32 33#include "t4_hw.h" 34 35enum { 36 MAX_NPORTS = 4, /* max # of ports */ 37 SERNUM_LEN = 24, /* Serial # length */ 38 EC_LEN = 16, /* E/C length */ 39 ID_LEN = 16, /* ID length */ 40 PN_LEN = 16, /* Part Number length */ 41 MD_LEN = 16, /* MFG diags version length */ 42 MACADDR_LEN = 12, /* MAC Address length */ 43}; 44 45enum { 46 T4_REGMAP_SIZE = (160 * 1024), 47 T5_REGMAP_SIZE = (332 * 1024), 48}; 49 50enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 51 52enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 53 54enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 55 56enum { 57 PAUSE_RX = 1 << 0, 58 PAUSE_TX = 1 << 1, 59 PAUSE_AUTONEG = 1 << 2 60}; 61 62enum { 63 FEC_NONE = 0, 64 FEC_RS = 1 << 0, 65 FEC_BASER_RS = 1 << 1, 66 FEC_AUTO = 1 << 5, /* M_FW_PORT_CAP32_FEC + 1 */ 67}; 68 69enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 70 71struct port_stats { 72 u64 tx_octets; /* total # of octets in good frames */ 73 u64 tx_frames; /* all good frames */ 74 u64 tx_bcast_frames; /* all broadcast frames */ 75 u64 tx_mcast_frames; /* all multicast frames */ 76 u64 tx_ucast_frames; /* all unicast frames */ 77 u64 tx_error_frames; /* all error frames */ 78 79 u64 tx_frames_64; /* # of Tx frames in a particular range */ 80 u64 tx_frames_65_127; 81 u64 tx_frames_128_255; 82 u64 tx_frames_256_511; 83 u64 tx_frames_512_1023; 84 u64 tx_frames_1024_1518; 85 u64 tx_frames_1519_max; 86 87 u64 tx_drop; /* # of dropped Tx frames */ 88 u64 tx_pause; /* # of transmitted pause frames */ 89 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 90 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 91 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 92 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 93 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 94 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 95 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 96 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 97 98 u64 rx_octets; /* total # of octets in good frames */ 99 u64 rx_frames; /* all good frames */ 100 u64 rx_bcast_frames; /* all broadcast frames */ 101 u64 rx_mcast_frames; /* all multicast frames */ 102 u64 rx_ucast_frames; /* all unicast frames */ 103 u64 rx_too_long; /* # of frames exceeding MTU */ 104 u64 rx_jabber; /* # of jabber frames */ 105 u64 rx_fcs_err; /* # of received frames with bad FCS */ 106 u64 rx_len_err; /* # of received frames with length error */ 107 u64 rx_symbol_err; /* symbol errors */ 108 u64 rx_runt; /* # of short frames */ 109 110 u64 rx_frames_64; /* # of Rx frames in a particular range */ 111 u64 rx_frames_65_127; 112 u64 rx_frames_128_255; 113 u64 rx_frames_256_511; 114 u64 rx_frames_512_1023; 115 u64 rx_frames_1024_1518; 116 u64 rx_frames_1519_max; 117 118 u64 rx_pause; /* # of received pause frames */ 119 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 120 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 121 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 122 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 123 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 124 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 125 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 126 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 127 128 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 129 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 130 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 131 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 132 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 133 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 134 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 135 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 136}; 137 138struct lb_port_stats { 139 u64 octets; 140 u64 frames; 141 u64 bcast_frames; 142 u64 mcast_frames; 143 u64 ucast_frames; 144 u64 error_frames; 145 146 u64 frames_64; 147 u64 frames_65_127; 148 u64 frames_128_255; 149 u64 frames_256_511; 150 u64 frames_512_1023; 151 u64 frames_1024_1518; 152 u64 frames_1519_max; 153 154 u64 drop; 155 156 u64 ovflow0; 157 u64 ovflow1; 158 u64 ovflow2; 159 u64 ovflow3; 160 u64 trunc0; 161 u64 trunc1; 162 u64 trunc2; 163 u64 trunc3; 164}; 165 166struct tp_tcp_stats { 167 u32 tcp_out_rsts; 168 u64 tcp_in_segs; 169 u64 tcp_out_segs; 170 u64 tcp_retrans_segs; 171}; 172 173struct tp_usm_stats { 174 u32 frames; 175 u32 drops; 176 u64 octets; 177}; 178 179struct tp_fcoe_stats { 180 u32 frames_ddp; 181 u32 frames_drop; 182 u64 octets_ddp; 183}; 184 185struct tp_err_stats { 186 u32 mac_in_errs[MAX_NCHAN]; 187 u32 hdr_in_errs[MAX_NCHAN]; 188 u32 tcp_in_errs[MAX_NCHAN]; 189 u32 tnl_cong_drops[MAX_NCHAN]; 190 u32 ofld_chan_drops[MAX_NCHAN]; 191 u32 tnl_tx_drops[MAX_NCHAN]; 192 u32 ofld_vlan_drops[MAX_NCHAN]; 193 u32 tcp6_in_errs[MAX_NCHAN]; 194 u32 ofld_no_neigh; 195 u32 ofld_cong_defer; 196}; 197 198struct tp_proxy_stats { 199 u32 proxy[MAX_NCHAN]; 200}; 201 202struct tp_cpl_stats { 203 u32 req[MAX_NCHAN]; 204 u32 rsp[MAX_NCHAN]; 205}; 206 207struct tp_rdma_stats { 208 u32 rqe_dfr_pkt; 209 u32 rqe_dfr_mod; 210}; 211 212struct sge_params { 213 int timer_val[SGE_NTIMERS]; /* final, scaled values */ 214 int counter_val[SGE_NCOUNTERS]; 215 int fl_starve_threshold; 216 int fl_starve_threshold2; 217 int page_shift; 218 int eq_s_qpp; 219 int iq_s_qpp; 220 int spg_len; 221 int pad_boundary; 222 int pack_boundary; 223 int fl_pktshift; 224 u32 sge_control; 225 u32 sge_fl_buffer_size[SGE_FLBUF_SIZES]; 226}; 227 228struct tp_params { 229 unsigned int tre; /* log2 of core clocks per TP tick */ 230 unsigned int dack_re; /* DACK timer resolution */ 231 unsigned int la_mask; /* what events are recorded by TP LA */ 232 unsigned short tx_modq[MAX_NCHAN]; /* channel to modulation queue map */ 233 234 uint32_t vlan_pri_map; 235 uint32_t ingress_config; 236 uint64_t hash_filter_mask; 237 __be16 err_vec_mask; 238 239 int8_t fcoe_shift; 240 int8_t port_shift; 241 int8_t vnic_shift; 242 int8_t vlan_shift; 243 int8_t tos_shift; 244 int8_t protocol_shift; 245 int8_t ethertype_shift; 246 int8_t macmatch_shift; 247 int8_t matchtype_shift; 248 int8_t frag_shift; 249}; 250 251struct vpd_params { 252 unsigned int cclk; 253 u8 ec[EC_LEN + 1]; 254 u8 sn[SERNUM_LEN + 1]; 255 u8 id[ID_LEN + 1]; 256 u8 pn[PN_LEN + 1]; 257 u8 na[MACADDR_LEN + 1]; 258 u8 md[MD_LEN + 1]; 259}; 260 261struct pci_params { 262 unsigned int vpd_cap_addr; 263 unsigned int mps; 264 unsigned short speed; 265 unsigned short width; 266}; 267 268/* 269 * Firmware device log. 270 */ 271struct devlog_params { 272 u32 memtype; /* which memory (FW_MEMTYPE_* ) */ 273 u32 start; /* start of log in firmware memory */ 274 u32 size; /* size of log */ 275 u32 addr; /* start address in flat addr space */ 276}; 277 278/* Stores chip specific parameters */ 279struct chip_params { 280 u8 nchan; 281 u8 pm_stats_cnt; 282 u8 cng_ch_bits_log; /* congestion channel map bits width */ 283 u8 nsched_cls; 284 u8 cim_num_obq; 285 u16 mps_rplc_size; 286 u16 vfcount; 287 u32 sge_fl_db; 288 u16 mps_tcam_size; 289}; 290 291/* VF-only parameters. */ 292 293/* 294 * Global Receive Side Scaling (RSS) parameters in host-native format. 295 */ 296struct rss_params { 297 unsigned int mode; /* RSS mode */ 298 union { 299 struct { 300 u_int synmapen:1; /* SYN Map Enable */ 301 u_int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */ 302 u_int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */ 303 u_int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */ 304 u_int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */ 305 u_int ofdmapen:1; /* Offload Map Enable */ 306 u_int tnlmapen:1; /* Tunnel Map Enable */ 307 u_int tnlalllookup:1; /* Tunnel All Lookup */ 308 u_int hashtoeplitz:1; /* use Toeplitz hash */ 309 } basicvirtual; 310 } u; 311}; 312 313/* 314 * Maximum resources provisioned for a PCI VF. 315 */ 316struct vf_resources { 317 unsigned int nvi; /* N virtual interfaces */ 318 unsigned int neq; /* N egress Qs */ 319 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 320 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 321 unsigned int niq; /* N ingress Qs */ 322 unsigned int tc; /* PCI-E traffic class */ 323 unsigned int pmask; /* port access rights mask */ 324 unsigned int nexactf; /* N exact MPS filters */ 325 unsigned int r_caps; /* read capabilities */ 326 unsigned int wx_caps; /* write/execute capabilities */ 327}; 328 329struct adapter_params { 330 struct sge_params sge; 331 struct tp_params tp; /* PF-only */ 332 struct vpd_params vpd; 333 struct pci_params pci; 334 struct devlog_params devlog; /* PF-only */ 335 struct rss_params rss; /* VF-only */ 336 struct vf_resources vfres; /* VF-only */ 337 unsigned int core_vdd; 338 339 unsigned int sf_size; /* serial flash size in bytes */ 340 unsigned int sf_nsec; /* # of flash sectors */ 341 342 unsigned int fw_vers; /* firmware version */ 343 unsigned int bs_vers; /* bootstrap version */ 344 unsigned int tp_vers; /* TP microcode version */ 345 unsigned int er_vers; /* expansion ROM version */ 346 unsigned int scfg_vers; /* Serial Configuration version */ 347 unsigned int vpd_vers; /* VPD version */ 348 349 unsigned short mtus[NMTUS]; 350 unsigned short a_wnd[NCCTRL_WIN]; 351 unsigned short b_wnd[NCCTRL_WIN]; 352 353 unsigned int cim_la_size; 354 355 uint8_t nports; /* # of ethernet ports */ 356 uint8_t portvec; 357 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */ 358 unsigned int rev:4; /* chip revision */ 359 unsigned int fpga:1; /* this is an FPGA */ 360 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card 361 resources for TOE operation. */ 362 unsigned int bypass:1; /* this is a bypass card */ 363 unsigned int ethoffload:1; 364 unsigned int port_caps32:1; 365 unsigned int hash_filter:1; 366 unsigned int filter2_wr_support:1; 367 368 unsigned int ofldq_wr_cred; 369 unsigned int eo_wr_cred; 370 371 unsigned int max_ordird_qp; 372 unsigned int max_ird_adapter; 373 374 uint32_t mps_bg_map; /* rx buffer group map for all ports (upto 4) */ 375 376 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 377 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 378 bool viid_smt_extn_support; /* FW returns vin, vfvld & smt index? */ 379}; 380 381#define CHELSIO_T4 0x4 382#define CHELSIO_T5 0x5 383#define CHELSIO_T6 0x6 384 385/* 386 * State needed to monitor the forward progress of SGE Ingress DMA activities 387 * and possible hangs. 388 */ 389struct sge_idma_monitor_state { 390 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 391 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 392 unsigned int idma_state[2]; /* IDMA Hang detect state */ 393 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 394 unsigned int idma_warn[2]; /* time to warning in HZ */ 395}; 396 397struct trace_params { 398 u32 data[TRACE_LEN / 4]; 399 u32 mask[TRACE_LEN / 4]; 400 unsigned short snap_len; 401 unsigned short min_len; 402 unsigned char skip_ofst; 403 unsigned char skip_len; 404 unsigned char invert; 405 unsigned char port; 406}; 407 408struct link_config { 409 /* OS-specific code owns all the requested_* fields. */ 410 int8_t requested_aneg; /* link autonegotiation */ 411 int8_t requested_fc; /* flow control */ 412 int8_t requested_fec; /* FEC */ 413 u_int requested_speed; /* speed (Mbps) */ 414 415 uint32_t supported; /* link capabilities */ 416 uint32_t advertising; /* advertised capabilities */ 417 uint32_t lp_advertising; /* peer advertised capabilities */ 418 uint32_t fec_hint; /* use this fec */ 419 u_int speed; /* actual link speed (Mbps) */ 420 int8_t fc; /* actual link flow control */ 421 int8_t fec; /* actual FEC */ 422 bool link_ok; /* link up? */ 423 uint8_t link_down_rc; /* link down reason */ 424}; 425 426#include "adapter.h" 427 428#ifndef PCI_VENDOR_ID_CHELSIO 429# define PCI_VENDOR_ID_CHELSIO 0x1425 430#endif 431 432#define for_each_port(adapter, iter) \ 433 for (iter = 0; iter < (adapter)->params.nports; ++iter) 434 435static inline int is_ftid(const struct adapter *sc, u_int tid) 436{ 437 438 return (sc->tids.nftids > 0 && tid >= sc->tids.ftid_base && 439 tid <= sc->tids.ftid_end); 440} 441 442static inline int is_hpftid(const struct adapter *sc, u_int tid) 443{ 444 445 return (sc->tids.nhpftids > 0 && tid >= sc->tids.hpftid_base && 446 tid <= sc->tids.hpftid_end); 447} 448 449static inline int is_etid(const struct adapter *sc, u_int tid) 450{ 451 452 return (sc->tids.netids > 0 && tid >= sc->tids.etid_base && 453 tid <= sc->tids.etid_end); 454} 455 456static inline int is_offload(const struct adapter *adap) 457{ 458 return adap->params.offload; 459} 460 461static inline int is_ethoffload(const struct adapter *adap) 462{ 463 return adap->params.ethoffload; 464} 465 466static inline int is_hashfilter(const struct adapter *adap) 467{ 468 return adap->params.hash_filter; 469} 470 471static inline int chip_id(struct adapter *adap) 472{ 473 return adap->params.chipid; 474} 475 476static inline int chip_rev(struct adapter *adap) 477{ 478 return adap->params.rev; 479} 480 481static inline int is_t4(struct adapter *adap) 482{ 483 return adap->params.chipid == CHELSIO_T4; 484} 485 486static inline int is_t5(struct adapter *adap) 487{ 488 return adap->params.chipid == CHELSIO_T5; 489} 490 491static inline int is_t6(struct adapter *adap) 492{ 493 return adap->params.chipid == CHELSIO_T6; 494} 495 496static inline int is_fpga(struct adapter *adap) 497{ 498 return adap->params.fpga; 499} 500 501static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 502{ 503 return adap->params.vpd.cclk / 1000; 504} 505 506static inline unsigned int us_to_core_ticks(const struct adapter *adap, 507 unsigned int us) 508{ 509 return (us * adap->params.vpd.cclk) / 1000; 510} 511 512static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 513 unsigned int ticks) 514{ 515 /* add Core Clock / 2 to round ticks to nearest uS */ 516 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 517 adapter->params.vpd.cclk); 518} 519 520static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 521 unsigned int ticks) 522{ 523 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 524} 525 526static inline u_int us_to_tcp_ticks(const struct adapter *adap, u_long us) 527{ 528 529 return (us * adap->params.vpd.cclk / 1000 >> adap->params.tp.tre); 530} 531 532static inline u_int tcp_ticks_to_us(const struct adapter *adap, u_int ticks) 533{ 534 return ((uint64_t)ticks << adap->params.tp.tre) / 535 core_ticks_per_usec(adap); 536} 537 538void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val); 539 540int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 541 int size, void *rpl, bool sleep_ok, int timeout); 542int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 543 void *rpl, bool sleep_ok); 544 545static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 546 const void *cmd, int size, void *rpl, 547 int timeout) 548{ 549 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 550 timeout); 551} 552 553static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 554 int size, void *rpl) 555{ 556 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 557} 558 559static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 560 int size, void *rpl) 561{ 562 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 563} 564 565void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 566 unsigned int data_reg, u32 *vals, unsigned int nregs, 567 unsigned int start_idx); 568void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 569 unsigned int data_reg, const u32 *vals, 570 unsigned int nregs, unsigned int start_idx); 571 572u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg); 573 574struct fw_filter_wr; 575 576void t4_intr_enable(struct adapter *adapter); 577void t4_intr_disable(struct adapter *adapter); 578void t4_intr_clear(struct adapter *adapter); 579int t4_slow_intr_handler(struct adapter *adapter, bool verbose); 580 581int t4_hash_mac_addr(const u8 *addr); 582int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 583 struct link_config *lc); 584int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 585int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 586int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 587int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 588int t4_seeprom_wp(struct adapter *adapter, int enable); 589int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, 590 u32 *data, int byte_oriented); 591int t4_write_flash(struct adapter *adapter, unsigned int addr, 592 unsigned int n, const u8 *data, int byte_oriented); 593int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 594int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 595int t5_fw_init_extern_mem(struct adapter *adap); 596int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 597int t4_load_boot(struct adapter *adap, u8 *boot_data, 598 unsigned int boot_addr, unsigned int size); 599int t4_flash_erase_sectors(struct adapter *adapter, int start, int end); 600int t4_flash_cfg_addr(struct adapter *adapter); 601int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 602int t4_get_fw_version(struct adapter *adapter, u32 *vers); 603int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr); 604int t4_get_bs_version(struct adapter *adapter, u32 *vers); 605int t4_get_tp_version(struct adapter *adapter, u32 *vers); 606int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 607int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 608int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 609int t4_get_version_info(struct adapter *adapter); 610int t4_init_hw(struct adapter *adapter, u32 fw_params); 611const struct chip_params *t4_get_chip_params(int chipid); 612int t4_prep_adapter(struct adapter *adapter, u32 *buf); 613int t4_shutdown_adapter(struct adapter *adapter); 614int t4_init_devlog_params(struct adapter *adapter, int fw_attach); 615int t4_init_sge_params(struct adapter *adapter); 616int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 617int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 618int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id); 619void t4_fatal_err(struct adapter *adapter, bool fw_error); 620int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 621 int filter_index, int enable); 622void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 623 int filter_index, int *enabled); 624int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 625 int start, int n, const u16 *rspq, unsigned int nrspq); 626int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 627 unsigned int flags); 628int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 629 unsigned int flags, unsigned int defq, unsigned int skeyidx, 630 unsigned int skey); 631int t4_read_rss(struct adapter *adapter, u16 *entries); 632void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 633void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 634 bool sleep_ok); 635void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 636 u32 *valp, bool sleep_ok); 637void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 638 u32 val, bool sleep_ok); 639void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 640 u32 *vfl, u32 *vfh, bool sleep_ok); 641void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 642 u32 vfl, u32 vfh, bool sleep_ok); 643u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 644void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok); 645u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 646void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok); 647int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 648void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 649void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 650void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 651int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 652int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 653int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 654 unsigned int *valp); 655int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 656 const unsigned int *valp); 657int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 658 unsigned int *valp); 659int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 660void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 661 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); 662void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 663int t4_get_flash_params(struct adapter *adapter); 664 665u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach); 666int t4_mc_read(struct adapter *adap, int idx, u32 addr, 667 __be32 *data, u64 *parity); 668int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); 669int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, 670 __be32 *data); 671void t4_idma_monitor_init(struct adapter *adapter, 672 struct sge_idma_monitor_state *idma); 673void t4_idma_monitor(struct adapter *adapter, 674 struct sge_idma_monitor_state *idma, 675 int hz, int ticks); 676 677unsigned int t4_get_regs_len(struct adapter *adapter); 678void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size); 679 680const char *t4_get_port_type_description(enum fw_port_type port_type); 681void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 682void t4_get_port_stats_offset(struct adapter *adap, int idx, 683 struct port_stats *stats, 684 struct port_stats *offset); 685void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 686void t4_clr_port_stats(struct adapter *adap, int idx); 687 688void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 689void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 690void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 691void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 692 unsigned int *ipg, bool sleep_ok); 693void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 694 unsigned int mask, unsigned int val); 695void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 696void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 697 bool sleep_ok); 698void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 699 bool sleep_ok); 700void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 701 bool sleep_ok); 702void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 703 bool sleep_ok); 704void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 705 bool sleep_ok); 706void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 707 struct tp_tcp_stats *v6, bool sleep_ok); 708void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 709 struct tp_fcoe_stats *st, bool sleep_ok); 710void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 711 const unsigned short *alpha, const unsigned short *beta); 712 713void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 714 715int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps); 716int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg); 717int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 718 unsigned int start, unsigned int n); 719void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 720int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map, 721 bool sleep_ok); 722void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 723 724void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr); 725int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 726 u64 mask0, u64 mask1, unsigned int crc, bool enable); 727 728int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 729 enum dev_master master, enum dev_state *state); 730int t4_fw_bye(struct adapter *adap, unsigned int mbox); 731int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 732int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force); 733int t4_fw_restart(struct adapter *adap, unsigned int mbox); 734int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 735 const u8 *fw_data, unsigned int size, int force); 736int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 737int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 738 unsigned int vf, unsigned int nparams, const u32 *params, 739 u32 *val); 740int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 741 unsigned int vf, unsigned int nparams, const u32 *params, 742 u32 *val, int rw); 743int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 744 unsigned int pf, unsigned int vf, 745 unsigned int nparams, const u32 *params, 746 const u32 *val, int timeout); 747int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 748 unsigned int vf, unsigned int nparams, const u32 *params, 749 const u32 *val); 750int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 751 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 752 unsigned int rxqi, unsigned int rxq, unsigned int tc, 753 unsigned int vi, unsigned int cmask, unsigned int pmask, 754 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); 755int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 756 unsigned int port, unsigned int pf, unsigned int vf, 757 unsigned int nmac, u8 *mac, u16 *rss_size, 758 uint8_t *vfvld, uint16_t *vin, 759 unsigned int portfunc, unsigned int idstype); 760int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 761 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 762 u16 *rss_size, uint8_t *vfvld, uint16_t *vin); 763int t4_free_vi(struct adapter *adap, unsigned int mbox, 764 unsigned int pf, unsigned int vf, 765 unsigned int viid); 766int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 767 int mtu, int promisc, int all_multi, int bcast, int vlanex, 768 bool sleep_ok); 769int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, 770 bool free, unsigned int naddr, const u8 **addr, u16 *idx, 771 u64 *hash, bool sleep_ok); 772int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 773 int idx, const u8 *addr, bool persist, uint16_t *smt_idx); 774int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 775 bool ucast, u64 vec, bool sleep_ok); 776int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 777 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 778int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 779 bool rx_en, bool tx_en); 780int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 781 unsigned int nblinks); 782int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 783 unsigned int mmd, unsigned int reg, unsigned int *valp); 784int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 785 unsigned int mmd, unsigned int reg, unsigned int val); 786int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 787 int port, unsigned int devid, 788 unsigned int offset, unsigned int len, 789 u8 *buf); 790int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 791 int port, unsigned int devid, 792 unsigned int offset, unsigned int len, 793 u8 *buf); 794int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 795 unsigned int vf, unsigned int iqtype, unsigned int iqid, 796 unsigned int fl0id, unsigned int fl1id); 797int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 798 unsigned int vf, unsigned int iqtype, unsigned int iqid, 799 unsigned int fl0id, unsigned int fl1id); 800int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 801 unsigned int vf, unsigned int eqid); 802int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 803 unsigned int vf, unsigned int eqid); 804int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 805 unsigned int vf, unsigned int eqid); 806int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 807 enum ctxt_type ctype, u32 *data); 808int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 809 u32 *data); 810int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 811const char *t4_link_down_rc_str(unsigned char link_down_rc); 812int t4_update_port_info(struct port_info *pi); 813int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 814int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val); 815int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 816 int sleep_ok); 817int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 818 int rateunit, int ratemode, int channel, int cl, 819 int minrate, int maxrate, int weight, int pktsize, 820 int burstsize, int sleep_ok); 821int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 822 unsigned int maxrate, int sleep_ok); 823int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 824 int weight, int sleep_ok); 825int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 826 int mode, unsigned int maxrate, int pktsize, 827 int sleep_ok); 828int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 829 unsigned int pf, unsigned int vf, 830 unsigned int timeout, unsigned int action); 831int t4_get_devlog_level(struct adapter *adapter, unsigned int *level); 832int t4_set_devlog_level(struct adapter *adapter, unsigned int level); 833void t4_sge_decode_idma_state(struct adapter *adapter, int state); 834 835void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 836 u32 start_index, bool sleep_ok); 837void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 838 u32 start_index, bool sleep_ok); 839void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 840 u32 start_index, bool sleep_ok); 841void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 842 u32 start_index, bool sleep_ok); 843 844static inline int t4vf_query_params(struct adapter *adapter, 845 unsigned int nparams, const u32 *params, 846 u32 *vals) 847{ 848 return t4_query_params(adapter, 0, 0, 0, nparams, params, vals); 849} 850 851static inline int t4vf_set_params(struct adapter *adapter, 852 unsigned int nparams, const u32 *params, 853 const u32 *vals) 854{ 855 return t4_set_params(adapter, 0, 0, 0, nparams, params, vals); 856} 857 858static inline int t4vf_wr_mbox(struct adapter *adap, const void *cmd, 859 int size, void *rpl) 860{ 861 return t4_wr_mbox(adap, adap->mbox, cmd, size, rpl); 862} 863 864int t4vf_wait_dev_ready(struct adapter *adapter); 865int t4vf_fw_reset(struct adapter *adapter); 866int t4vf_get_sge_params(struct adapter *adapter); 867int t4vf_get_rss_glb_config(struct adapter *adapter); 868int t4vf_get_vfres(struct adapter *adapter); 869int t4vf_prep_adapter(struct adapter *adapter); 870int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid, 871 enum t4_bar2_qtype qtype, int user, u64 *pbar2_qoffset, 872 unsigned int *pbar2_qid); 873unsigned int fwcap_to_speed(uint32_t caps); 874uint32_t speed_to_fwcap(unsigned int speed); 875uint32_t fwcap_top_speed(uint32_t caps); 876 877static inline int 878port_top_speed(const struct port_info *pi) 879{ 880 881 /* Mbps -> Gbps */ 882 return (fwcap_to_speed(pi->link_cfg.supported) / 1000); 883} 884 885#endif /* __CHELSIO_COMMON_H */ 886