common.h revision 346872
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/11/sys/dev/cxgbe/common/common.h 346872 2019-04-29 03:31:20Z np $ 27 * 28 */ 29 30#ifndef __CHELSIO_COMMON_H 31#define __CHELSIO_COMMON_H 32 33#include "t4_hw.h" 34 35#define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \ 36 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \ 37 F_CPL_SWITCH | F_SGE | F_ULP_TX) 38 39enum { 40 MAX_NPORTS = 4, /* max # of ports */ 41 SERNUM_LEN = 24, /* Serial # length */ 42 EC_LEN = 16, /* E/C length */ 43 ID_LEN = 16, /* ID length */ 44 PN_LEN = 16, /* Part Number length */ 45 MD_LEN = 16, /* MFG diags version length */ 46 MACADDR_LEN = 12, /* MAC Address length */ 47}; 48 49enum { 50 T4_REGMAP_SIZE = (160 * 1024), 51 T5_REGMAP_SIZE = (332 * 1024), 52}; 53 54enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 55 56enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 57 58enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 59 60enum { 61 PAUSE_RX = 1 << 0, 62 PAUSE_TX = 1 << 1, 63 PAUSE_AUTONEG = 1 << 2 64}; 65 66enum { 67 FEC_NONE = 0, 68 FEC_RS = 1 << 0, 69 FEC_BASER_RS = 1 << 1, 70 FEC_AUTO = 1 << 5, /* M_FW_PORT_CAP32_FEC + 1 */ 71}; 72 73enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 74 75struct port_stats { 76 u64 tx_octets; /* total # of octets in good frames */ 77 u64 tx_frames; /* all good frames */ 78 u64 tx_bcast_frames; /* all broadcast frames */ 79 u64 tx_mcast_frames; /* all multicast frames */ 80 u64 tx_ucast_frames; /* all unicast frames */ 81 u64 tx_error_frames; /* all error frames */ 82 83 u64 tx_frames_64; /* # of Tx frames in a particular range */ 84 u64 tx_frames_65_127; 85 u64 tx_frames_128_255; 86 u64 tx_frames_256_511; 87 u64 tx_frames_512_1023; 88 u64 tx_frames_1024_1518; 89 u64 tx_frames_1519_max; 90 91 u64 tx_drop; /* # of dropped Tx frames */ 92 u64 tx_pause; /* # of transmitted pause frames */ 93 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 94 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 95 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 96 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 97 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 98 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 99 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 100 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 101 102 u64 rx_octets; /* total # of octets in good frames */ 103 u64 rx_frames; /* all good frames */ 104 u64 rx_bcast_frames; /* all broadcast frames */ 105 u64 rx_mcast_frames; /* all multicast frames */ 106 u64 rx_ucast_frames; /* all unicast frames */ 107 u64 rx_too_long; /* # of frames exceeding MTU */ 108 u64 rx_jabber; /* # of jabber frames */ 109 u64 rx_fcs_err; /* # of received frames with bad FCS */ 110 u64 rx_len_err; /* # of received frames with length error */ 111 u64 rx_symbol_err; /* symbol errors */ 112 u64 rx_runt; /* # of short frames */ 113 114 u64 rx_frames_64; /* # of Rx frames in a particular range */ 115 u64 rx_frames_65_127; 116 u64 rx_frames_128_255; 117 u64 rx_frames_256_511; 118 u64 rx_frames_512_1023; 119 u64 rx_frames_1024_1518; 120 u64 rx_frames_1519_max; 121 122 u64 rx_pause; /* # of received pause frames */ 123 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 124 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 125 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 126 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 127 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 128 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 129 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 130 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 131 132 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 133 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 134 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 135 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 136 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 137 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 138 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 139 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 140}; 141 142struct lb_port_stats { 143 u64 octets; 144 u64 frames; 145 u64 bcast_frames; 146 u64 mcast_frames; 147 u64 ucast_frames; 148 u64 error_frames; 149 150 u64 frames_64; 151 u64 frames_65_127; 152 u64 frames_128_255; 153 u64 frames_256_511; 154 u64 frames_512_1023; 155 u64 frames_1024_1518; 156 u64 frames_1519_max; 157 158 u64 drop; 159 160 u64 ovflow0; 161 u64 ovflow1; 162 u64 ovflow2; 163 u64 ovflow3; 164 u64 trunc0; 165 u64 trunc1; 166 u64 trunc2; 167 u64 trunc3; 168}; 169 170struct tp_tcp_stats { 171 u32 tcp_out_rsts; 172 u64 tcp_in_segs; 173 u64 tcp_out_segs; 174 u64 tcp_retrans_segs; 175}; 176 177struct tp_usm_stats { 178 u32 frames; 179 u32 drops; 180 u64 octets; 181}; 182 183struct tp_fcoe_stats { 184 u32 frames_ddp; 185 u32 frames_drop; 186 u64 octets_ddp; 187}; 188 189struct tp_err_stats { 190 u32 mac_in_errs[MAX_NCHAN]; 191 u32 hdr_in_errs[MAX_NCHAN]; 192 u32 tcp_in_errs[MAX_NCHAN]; 193 u32 tnl_cong_drops[MAX_NCHAN]; 194 u32 ofld_chan_drops[MAX_NCHAN]; 195 u32 tnl_tx_drops[MAX_NCHAN]; 196 u32 ofld_vlan_drops[MAX_NCHAN]; 197 u32 tcp6_in_errs[MAX_NCHAN]; 198 u32 ofld_no_neigh; 199 u32 ofld_cong_defer; 200}; 201 202struct tp_proxy_stats { 203 u32 proxy[MAX_NCHAN]; 204}; 205 206struct tp_cpl_stats { 207 u32 req[MAX_NCHAN]; 208 u32 rsp[MAX_NCHAN]; 209}; 210 211struct tp_rdma_stats { 212 u32 rqe_dfr_pkt; 213 u32 rqe_dfr_mod; 214}; 215 216struct sge_params { 217 int timer_val[SGE_NTIMERS]; /* final, scaled values */ 218 int counter_val[SGE_NCOUNTERS]; 219 int fl_starve_threshold; 220 int fl_starve_threshold2; 221 int page_shift; 222 int eq_s_qpp; 223 int iq_s_qpp; 224 int spg_len; 225 int pad_boundary; 226 int pack_boundary; 227 int fl_pktshift; 228 u32 sge_control; 229 u32 sge_fl_buffer_size[SGE_FLBUF_SIZES]; 230}; 231 232struct tp_params { 233 unsigned int tre; /* log2 of core clocks per TP tick */ 234 unsigned int dack_re; /* DACK timer resolution */ 235 unsigned int la_mask; /* what events are recorded by TP LA */ 236 unsigned short tx_modq[MAX_NCHAN]; /* channel to modulation queue map */ 237 238 uint32_t vlan_pri_map; 239 uint32_t ingress_config; 240 uint64_t hash_filter_mask; 241 __be16 err_vec_mask; 242 243 int8_t fcoe_shift; 244 int8_t port_shift; 245 int8_t vnic_shift; 246 int8_t vlan_shift; 247 int8_t tos_shift; 248 int8_t protocol_shift; 249 int8_t ethertype_shift; 250 int8_t macmatch_shift; 251 int8_t matchtype_shift; 252 int8_t frag_shift; 253}; 254 255struct vpd_params { 256 unsigned int cclk; 257 u8 ec[EC_LEN + 1]; 258 u8 sn[SERNUM_LEN + 1]; 259 u8 id[ID_LEN + 1]; 260 u8 pn[PN_LEN + 1]; 261 u8 na[MACADDR_LEN + 1]; 262 u8 md[MD_LEN + 1]; 263}; 264 265struct pci_params { 266 unsigned int vpd_cap_addr; 267 unsigned int mps; 268 unsigned short speed; 269 unsigned short width; 270}; 271 272/* 273 * Firmware device log. 274 */ 275struct devlog_params { 276 u32 memtype; /* which memory (FW_MEMTYPE_* ) */ 277 u32 start; /* start of log in firmware memory */ 278 u32 size; /* size of log */ 279 u32 addr; /* start address in flat addr space */ 280}; 281 282/* Stores chip specific parameters */ 283struct chip_params { 284 u8 nchan; 285 u8 pm_stats_cnt; 286 u8 cng_ch_bits_log; /* congestion channel map bits width */ 287 u8 nsched_cls; 288 u8 cim_num_obq; 289 u16 mps_rplc_size; 290 u16 vfcount; 291 u32 sge_fl_db; 292 u16 mps_tcam_size; 293}; 294 295/* VF-only parameters. */ 296 297/* 298 * Global Receive Side Scaling (RSS) parameters in host-native format. 299 */ 300struct rss_params { 301 unsigned int mode; /* RSS mode */ 302 union { 303 struct { 304 u_int synmapen:1; /* SYN Map Enable */ 305 u_int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */ 306 u_int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */ 307 u_int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */ 308 u_int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */ 309 u_int ofdmapen:1; /* Offload Map Enable */ 310 u_int tnlmapen:1; /* Tunnel Map Enable */ 311 u_int tnlalllookup:1; /* Tunnel All Lookup */ 312 u_int hashtoeplitz:1; /* use Toeplitz hash */ 313 } basicvirtual; 314 } u; 315}; 316 317/* 318 * Maximum resources provisioned for a PCI VF. 319 */ 320struct vf_resources { 321 unsigned int nvi; /* N virtual interfaces */ 322 unsigned int neq; /* N egress Qs */ 323 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 324 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 325 unsigned int niq; /* N ingress Qs */ 326 unsigned int tc; /* PCI-E traffic class */ 327 unsigned int pmask; /* port access rights mask */ 328 unsigned int nexactf; /* N exact MPS filters */ 329 unsigned int r_caps; /* read capabilities */ 330 unsigned int wx_caps; /* write/execute capabilities */ 331}; 332 333struct adapter_params { 334 struct sge_params sge; 335 struct tp_params tp; /* PF-only */ 336 struct vpd_params vpd; 337 struct pci_params pci; 338 struct devlog_params devlog; /* PF-only */ 339 struct rss_params rss; /* VF-only */ 340 struct vf_resources vfres; /* VF-only */ 341 unsigned int core_vdd; 342 343 unsigned int sf_size; /* serial flash size in bytes */ 344 unsigned int sf_nsec; /* # of flash sectors */ 345 346 unsigned int fw_vers; /* firmware version */ 347 unsigned int bs_vers; /* bootstrap version */ 348 unsigned int tp_vers; /* TP microcode version */ 349 unsigned int er_vers; /* expansion ROM version */ 350 unsigned int scfg_vers; /* Serial Configuration version */ 351 unsigned int vpd_vers; /* VPD version */ 352 353 unsigned short mtus[NMTUS]; 354 unsigned short a_wnd[NCCTRL_WIN]; 355 unsigned short b_wnd[NCCTRL_WIN]; 356 357 unsigned int cim_la_size; 358 359 uint8_t nports; /* # of ethernet ports */ 360 uint8_t portvec; 361 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */ 362 unsigned int rev:4; /* chip revision */ 363 unsigned int fpga:1; /* this is an FPGA */ 364 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card 365 resources for TOE operation. */ 366 unsigned int bypass:1; /* this is a bypass card */ 367 unsigned int ethoffload:1; 368 unsigned int port_caps32:1; 369 unsigned int hash_filter:1; 370 unsigned int filter2_wr_support:1; 371 372 unsigned int ofldq_wr_cred; 373 unsigned int eo_wr_cred; 374 375 unsigned int max_ordird_qp; 376 unsigned int max_ird_adapter; 377 378 uint32_t mps_bg_map; /* rx buffer group map for all ports (upto 4) */ 379 380 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 381 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 382}; 383 384#define CHELSIO_T4 0x4 385#define CHELSIO_T5 0x5 386#define CHELSIO_T6 0x6 387 388/* 389 * State needed to monitor the forward progress of SGE Ingress DMA activities 390 * and possible hangs. 391 */ 392struct sge_idma_monitor_state { 393 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 394 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 395 unsigned int idma_state[2]; /* IDMA Hang detect state */ 396 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 397 unsigned int idma_warn[2]; /* time to warning in HZ */ 398}; 399 400struct trace_params { 401 u32 data[TRACE_LEN / 4]; 402 u32 mask[TRACE_LEN / 4]; 403 unsigned short snap_len; 404 unsigned short min_len; 405 unsigned char skip_ofst; 406 unsigned char skip_len; 407 unsigned char invert; 408 unsigned char port; 409}; 410 411struct link_config { 412 /* OS-specific code owns all the requested_* fields. */ 413 int8_t requested_aneg; /* link autonegotiation */ 414 int8_t requested_fc; /* flow control */ 415 int8_t requested_fec; /* FEC */ 416 u_int requested_speed; /* speed (Mbps) */ 417 418 uint32_t supported; /* link capabilities */ 419 uint32_t advertising; /* advertised capabilities */ 420 uint32_t lp_advertising; /* peer advertised capabilities */ 421 uint32_t fec_hint; /* use this fec */ 422 u_int speed; /* actual link speed (Mbps) */ 423 int8_t fc; /* actual link flow control */ 424 int8_t fec; /* actual FEC */ 425 bool link_ok; /* link up? */ 426 uint8_t link_down_rc; /* link down reason */ 427}; 428 429#include "adapter.h" 430 431#ifndef PCI_VENDOR_ID_CHELSIO 432# define PCI_VENDOR_ID_CHELSIO 0x1425 433#endif 434 435#define for_each_port(adapter, iter) \ 436 for (iter = 0; iter < (adapter)->params.nports; ++iter) 437 438static inline int is_ftid(const struct adapter *sc, u_int tid) 439{ 440 441 return (sc->tids.nftids > 0 && tid >= sc->tids.ftid_base && 442 tid <= sc->tids.ftid_end); 443} 444 445static inline int is_etid(const struct adapter *sc, u_int tid) 446{ 447 448 return (sc->tids.netids > 0 && tid >= sc->tids.etid_base && 449 tid <= sc->tids.etid_end); 450} 451 452static inline int is_offload(const struct adapter *adap) 453{ 454 return adap->params.offload; 455} 456 457static inline int is_ethoffload(const struct adapter *adap) 458{ 459 return adap->params.ethoffload; 460} 461 462static inline int is_hashfilter(const struct adapter *adap) 463{ 464 return adap->params.hash_filter; 465} 466 467static inline int chip_id(struct adapter *adap) 468{ 469 return adap->params.chipid; 470} 471 472static inline int chip_rev(struct adapter *adap) 473{ 474 return adap->params.rev; 475} 476 477static inline int is_t4(struct adapter *adap) 478{ 479 return adap->params.chipid == CHELSIO_T4; 480} 481 482static inline int is_t5(struct adapter *adap) 483{ 484 return adap->params.chipid == CHELSIO_T5; 485} 486 487static inline int is_t6(struct adapter *adap) 488{ 489 return adap->params.chipid == CHELSIO_T6; 490} 491 492static inline int is_fpga(struct adapter *adap) 493{ 494 return adap->params.fpga; 495} 496 497static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 498{ 499 return adap->params.vpd.cclk / 1000; 500} 501 502static inline unsigned int us_to_core_ticks(const struct adapter *adap, 503 unsigned int us) 504{ 505 return (us * adap->params.vpd.cclk) / 1000; 506} 507 508static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 509 unsigned int ticks) 510{ 511 /* add Core Clock / 2 to round ticks to nearest uS */ 512 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 513 adapter->params.vpd.cclk); 514} 515 516static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 517 unsigned int ticks) 518{ 519 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 520} 521 522static inline u_int us_to_tcp_ticks(const struct adapter *adap, u_long us) 523{ 524 525 return (us * adap->params.vpd.cclk / 1000 >> adap->params.tp.tre); 526} 527 528static inline u_int tcp_ticks_to_us(const struct adapter *adap, u_int ticks) 529{ 530 return ((uint64_t)ticks << adap->params.tp.tre) / 531 core_ticks_per_usec(adap); 532} 533 534void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val); 535 536int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 537 int size, void *rpl, bool sleep_ok, int timeout); 538int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 539 void *rpl, bool sleep_ok); 540 541static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 542 const void *cmd, int size, void *rpl, 543 int timeout) 544{ 545 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 546 timeout); 547} 548 549static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 550 int size, void *rpl) 551{ 552 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 553} 554 555static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 556 int size, void *rpl) 557{ 558 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 559} 560 561void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 562 unsigned int data_reg, u32 *vals, unsigned int nregs, 563 unsigned int start_idx); 564void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 565 unsigned int data_reg, const u32 *vals, 566 unsigned int nregs, unsigned int start_idx); 567 568u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg); 569 570struct fw_filter_wr; 571 572void t4_intr_enable(struct adapter *adapter); 573void t4_intr_disable(struct adapter *adapter); 574void t4_intr_clear(struct adapter *adapter); 575int t4_slow_intr_handler(struct adapter *adapter); 576 577int t4_hash_mac_addr(const u8 *addr); 578int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 579 struct link_config *lc); 580int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 581int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 582int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 583int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 584int t4_seeprom_wp(struct adapter *adapter, int enable); 585int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, 586 u32 *data, int byte_oriented); 587int t4_write_flash(struct adapter *adapter, unsigned int addr, 588 unsigned int n, const u8 *data, int byte_oriented); 589int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 590int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 591int t5_fw_init_extern_mem(struct adapter *adap); 592int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 593int t4_load_boot(struct adapter *adap, u8 *boot_data, 594 unsigned int boot_addr, unsigned int size); 595int t4_flash_erase_sectors(struct adapter *adapter, int start, int end); 596int t4_flash_cfg_addr(struct adapter *adapter); 597int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 598int t4_get_fw_version(struct adapter *adapter, u32 *vers); 599int t4_get_bs_version(struct adapter *adapter, u32 *vers); 600int t4_get_tp_version(struct adapter *adapter, u32 *vers); 601int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 602int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 603int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 604int t4_get_version_info(struct adapter *adapter); 605int t4_init_hw(struct adapter *adapter, u32 fw_params); 606const struct chip_params *t4_get_chip_params(int chipid); 607int t4_prep_adapter(struct adapter *adapter, u32 *buf); 608int t4_shutdown_adapter(struct adapter *adapter); 609int t4_init_devlog_params(struct adapter *adapter, int fw_attach); 610int t4_init_sge_params(struct adapter *adapter); 611int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 612int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 613int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id); 614void t4_fatal_err(struct adapter *adapter); 615void t4_db_full(struct adapter *adapter); 616void t4_db_dropped(struct adapter *adapter); 617int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 618 int filter_index, int enable); 619void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 620 int filter_index, int *enabled); 621int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 622 int start, int n, const u16 *rspq, unsigned int nrspq); 623int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 624 unsigned int flags); 625int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 626 unsigned int flags, unsigned int defq, unsigned int skeyidx, 627 unsigned int skey); 628int t4_read_rss(struct adapter *adapter, u16 *entries); 629void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 630void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 631 bool sleep_ok); 632void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 633 u32 *valp, bool sleep_ok); 634void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 635 u32 val, bool sleep_ok); 636void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 637 u32 *vfl, u32 *vfh, bool sleep_ok); 638void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 639 u32 vfl, u32 vfh, bool sleep_ok); 640u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 641void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok); 642u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 643void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok); 644int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 645void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 646void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 647void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 648int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 649int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 650int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 651 unsigned int *valp); 652int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 653 const unsigned int *valp); 654int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 655 unsigned int *valp); 656int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 657void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 658 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); 659void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 660int t4_get_flash_params(struct adapter *adapter); 661 662u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach); 663int t4_mc_read(struct adapter *adap, int idx, u32 addr, 664 __be32 *data, u64 *parity); 665int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); 666int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, 667 __be32 *data); 668void t4_idma_monitor_init(struct adapter *adapter, 669 struct sge_idma_monitor_state *idma); 670void t4_idma_monitor(struct adapter *adapter, 671 struct sge_idma_monitor_state *idma, 672 int hz, int ticks); 673 674unsigned int t4_get_regs_len(struct adapter *adapter); 675void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size); 676 677const char *t4_get_port_type_description(enum fw_port_type port_type); 678void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 679void t4_get_port_stats_offset(struct adapter *adap, int idx, 680 struct port_stats *stats, 681 struct port_stats *offset); 682void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 683void t4_clr_port_stats(struct adapter *adap, int idx); 684 685void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 686void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 687void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 688void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 689 unsigned int *ipg, bool sleep_ok); 690void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 691 unsigned int mask, unsigned int val); 692void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 693void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 694 bool sleep_ok); 695void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 696 bool sleep_ok); 697void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 698 bool sleep_ok); 699void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 700 bool sleep_ok); 701void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 702 bool sleep_ok); 703void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 704 struct tp_tcp_stats *v6, bool sleep_ok); 705void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 706 struct tp_fcoe_stats *st, bool sleep_ok); 707void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 708 const unsigned short *alpha, const unsigned short *beta); 709 710void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 711 712int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps); 713int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg); 714int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 715 unsigned int start, unsigned int n); 716void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 717int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map, 718 bool sleep_ok); 719void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 720 721void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr); 722int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 723 u64 mask0, u64 mask1, unsigned int crc, bool enable); 724 725int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 726 enum dev_master master, enum dev_state *state); 727int t4_fw_bye(struct adapter *adap, unsigned int mbox); 728int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 729int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force); 730int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 731int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 732 const u8 *fw_data, unsigned int size, int force); 733int t4_fw_forceinstall(struct adapter *adap, const u8 *fw_data, 734 unsigned int size); 735int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 736int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 737 unsigned int vf, unsigned int nparams, const u32 *params, 738 u32 *val); 739int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 740 unsigned int vf, unsigned int nparams, const u32 *params, 741 u32 *val, int rw); 742int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 743 unsigned int pf, unsigned int vf, 744 unsigned int nparams, const u32 *params, 745 const u32 *val, int timeout); 746int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 747 unsigned int vf, unsigned int nparams, const u32 *params, 748 const u32 *val); 749int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 750 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 751 unsigned int rxqi, unsigned int rxq, unsigned int tc, 752 unsigned int vi, unsigned int cmask, unsigned int pmask, 753 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); 754int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 755 unsigned int port, unsigned int pf, unsigned int vf, 756 unsigned int nmac, u8 *mac, u16 *rss_size, 757 unsigned int portfunc, unsigned int idstype); 758int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 759 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 760 u16 *rss_size); 761int t4_free_vi(struct adapter *adap, unsigned int mbox, 762 unsigned int pf, unsigned int vf, 763 unsigned int viid); 764int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 765 int mtu, int promisc, int all_multi, int bcast, int vlanex, 766 bool sleep_ok); 767int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, 768 bool free, unsigned int naddr, const u8 **addr, u16 *idx, 769 u64 *hash, bool sleep_ok); 770int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 771 int idx, const u8 *addr, bool persist, bool add_smt); 772int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 773 bool ucast, u64 vec, bool sleep_ok); 774int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 775 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 776int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 777 bool rx_en, bool tx_en); 778int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 779 unsigned int nblinks); 780int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 781 unsigned int mmd, unsigned int reg, unsigned int *valp); 782int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 783 unsigned int mmd, unsigned int reg, unsigned int val); 784int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 785 int port, unsigned int devid, 786 unsigned int offset, unsigned int len, 787 u8 *buf); 788int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 789 int port, unsigned int devid, 790 unsigned int offset, unsigned int len, 791 u8 *buf); 792int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 793 unsigned int vf, unsigned int iqtype, unsigned int iqid, 794 unsigned int fl0id, unsigned int fl1id); 795int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 796 unsigned int vf, unsigned int iqtype, unsigned int iqid, 797 unsigned int fl0id, unsigned int fl1id); 798int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 799 unsigned int vf, unsigned int eqid); 800int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 801 unsigned int vf, unsigned int eqid); 802int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 803 unsigned int vf, unsigned int eqid); 804int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 805 enum ctxt_type ctype, u32 *data); 806int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 807 u32 *data); 808int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 809const char *t4_link_down_rc_str(unsigned char link_down_rc); 810int t4_update_port_info(struct port_info *pi); 811int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 812int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val); 813int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 814 int sleep_ok); 815int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 816 int rateunit, int ratemode, int channel, int cl, 817 int minrate, int maxrate, int weight, int pktsize, 818 int burstsize, int sleep_ok); 819int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 820 unsigned int maxrate, int sleep_ok); 821int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 822 int weight, int sleep_ok); 823int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 824 int mode, unsigned int maxrate, int pktsize, 825 int sleep_ok); 826int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 827 unsigned int pf, unsigned int vf, 828 unsigned int timeout, unsigned int action); 829int t4_get_devlog_level(struct adapter *adapter, unsigned int *level); 830int t4_set_devlog_level(struct adapter *adapter, unsigned int level); 831void t4_sge_decode_idma_state(struct adapter *adapter, int state); 832 833void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 834 u32 start_index, bool sleep_ok); 835void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 836 u32 start_index, bool sleep_ok); 837void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 838 u32 start_index, bool sleep_ok); 839void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 840 u32 start_index, bool sleep_ok); 841 842static inline int t4vf_query_params(struct adapter *adapter, 843 unsigned int nparams, const u32 *params, 844 u32 *vals) 845{ 846 return t4_query_params(adapter, 0, 0, 0, nparams, params, vals); 847} 848 849static inline int t4vf_set_params(struct adapter *adapter, 850 unsigned int nparams, const u32 *params, 851 const u32 *vals) 852{ 853 return t4_set_params(adapter, 0, 0, 0, nparams, params, vals); 854} 855 856static inline int t4vf_wr_mbox(struct adapter *adap, const void *cmd, 857 int size, void *rpl) 858{ 859 return t4_wr_mbox(adap, adap->mbox, cmd, size, rpl); 860} 861 862int t4vf_wait_dev_ready(struct adapter *adapter); 863int t4vf_fw_reset(struct adapter *adapter); 864int t4vf_get_sge_params(struct adapter *adapter); 865int t4vf_get_rss_glb_config(struct adapter *adapter); 866int t4vf_get_vfres(struct adapter *adapter); 867int t4vf_prep_adapter(struct adapter *adapter); 868int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid, 869 enum t4_bar2_qtype qtype, int user, u64 *pbar2_qoffset, 870 unsigned int *pbar2_qid); 871unsigned int fwcap_to_speed(uint32_t caps); 872uint32_t speed_to_fwcap(unsigned int speed); 873uint32_t fwcap_top_speed(uint32_t caps); 874 875static inline int 876port_top_speed(const struct port_info *pi) 877{ 878 879 /* Mbps -> Gbps */ 880 return (fwcap_to_speed(pi->link_cfg.supported) / 1000); 881} 882 883#endif /* __CHELSIO_COMMON_H */ 884