adapter.h revision 346883
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/11/sys/dev/cxgbe/adapter.h 346883 2019-04-29 05:35:52Z np $ 28 * 29 */ 30 31#ifndef __T4_ADAPTER_H__ 32#define __T4_ADAPTER_H__ 33 34#include <sys/kernel.h> 35#include <sys/bus.h> 36#include <sys/rman.h> 37#include <sys/types.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/rwlock.h> 41#include <sys/sx.h> 42#include <sys/vmem.h> 43#include <vm/uma.h> 44 45#include <dev/pci/pcivar.h> 46#include <dev/pci/pcireg.h> 47#include <machine/bus.h> 48#include <sys/socket.h> 49#include <sys/sysctl.h> 50#include <net/ethernet.h> 51#include <net/if.h> 52#include <net/if_var.h> 53#include <net/if_media.h> 54#include <netinet/in.h> 55#include <netinet/tcp_lro.h> 56 57#include "offload.h" 58#include "t4_ioctl.h" 59#include "common/t4_msg.h" 60#include "firmware/t4fw_interface.h" 61 62#define KTR_CXGBE KTR_SPARE3 63MALLOC_DECLARE(M_CXGBE); 64#define CXGBE_UNIMPLEMENTED(s) \ 65 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 66 67#if defined(__i386__) || defined(__amd64__) 68static __inline void 69prefetch(void *x) 70{ 71 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 72} 73#else 74#define prefetch(x) __builtin_prefetch(x) 75#endif 76 77#ifndef SYSCTL_ADD_UQUAD 78#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 79#define sysctl_handle_64 sysctl_handle_quad 80#define CTLTYPE_U64 CTLTYPE_QUAD 81#endif 82 83SYSCTL_DECL(_hw_cxgbe); 84 85struct adapter; 86typedef struct adapter adapter_t; 87 88enum { 89 /* 90 * All ingress queues use this entry size. Note that the firmware event 91 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 92 * be at least 64. 93 */ 94 IQ_ESIZE = 64, 95 96 /* Default queue sizes for all kinds of ingress queues */ 97 FW_IQ_QSIZE = 256, 98 RX_IQ_QSIZE = 1024, 99 100 /* All egress queues use this entry size */ 101 EQ_ESIZE = 64, 102 103 /* Default queue sizes for all kinds of egress queues */ 104 CTRL_EQ_QSIZE = 1024, 105 TX_EQ_QSIZE = 1024, 106 107#if MJUMPAGESIZE != MCLBYTES 108 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 109#else 110 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 111#endif 112 CL_METADATA_SIZE = CACHE_LINE_SIZE, 113 114 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 115 TX_SGL_SEGS = 39, 116 TX_SGL_SEGS_TSO = 38, 117 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 118}; 119 120enum { 121 /* adapter intr_type */ 122 INTR_INTX = (1 << 0), 123 INTR_MSI = (1 << 1), 124 INTR_MSIX = (1 << 2) 125}; 126 127enum { 128 XGMAC_MTU = (1 << 0), 129 XGMAC_PROMISC = (1 << 1), 130 XGMAC_ALLMULTI = (1 << 2), 131 XGMAC_VLANEX = (1 << 3), 132 XGMAC_UCADDR = (1 << 4), 133 XGMAC_MCADDRS = (1 << 5), 134 135 XGMAC_ALL = 0xffff 136}; 137 138enum { 139 /* flags understood by begin_synchronized_op */ 140 HOLD_LOCK = (1 << 0), 141 SLEEP_OK = (1 << 1), 142 INTR_OK = (1 << 2), 143 144 /* flags understood by end_synchronized_op */ 145 LOCK_HELD = HOLD_LOCK, 146}; 147 148enum { 149 /* adapter flags */ 150 FULL_INIT_DONE = (1 << 0), 151 FW_OK = (1 << 1), 152 CHK_MBOX_ACCESS = (1 << 2), 153 MASTER_PF = (1 << 3), 154 ADAP_SYSCTL_CTX = (1 << 4), 155 /* TOM_INIT_DONE= (1 << 5), No longer used */ 156 BUF_PACKING_OK = (1 << 6), 157 IS_VF = (1 << 7), 158 159 CXGBE_BUSY = (1 << 9), 160 161 /* port flags */ 162 HAS_TRACEQ = (1 << 3), 163 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 164 165 /* VI flags */ 166 DOOMED = (1 << 0), 167 VI_INIT_DONE = (1 << 1), 168 VI_SYSCTL_CTX = (1 << 2), 169 170 /* adapter debug_flags */ 171 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 172 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 173 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 174}; 175 176#define IS_DOOMED(vi) ((vi)->flags & DOOMED) 177#define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 178#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 179#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 180#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 181 182struct vi_info { 183 device_t dev; 184 struct port_info *pi; 185 186 struct ifnet *ifp; 187 188 unsigned long flags; 189 int if_flags; 190 191 uint16_t *rss, *nm_rss; 192 int smt_idx; /* for convenience */ 193 uint16_t viid; 194 int16_t xact_addr_filt;/* index of exact MAC address filter */ 195 uint16_t rss_size; /* size of VI's RSS table slice */ 196 uint16_t rss_base; /* start of VI's RSS table slice */ 197 198 int nintr; 199 int first_intr; 200 201 /* These need to be int as they are used in sysctl */ 202 int ntxq; /* # of tx queues */ 203 int first_txq; /* index of first tx queue */ 204 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 205 int nrxq; /* # of rx queues */ 206 int first_rxq; /* index of first rx queue */ 207 int nofldtxq; /* # of offload tx queues */ 208 int first_ofld_txq; /* index of first offload tx queue */ 209 int nofldrxq; /* # of offload rx queues */ 210 int first_ofld_rxq; /* index of first offload rx queue */ 211 int nnmtxq; 212 int first_nm_txq; 213 int nnmrxq; 214 int first_nm_rxq; 215 int tmr_idx; 216 int ofld_tmr_idx; 217 int pktc_idx; 218 int ofld_pktc_idx; 219 int qsize_rxq; 220 int qsize_txq; 221 222 struct timeval last_refreshed; 223 struct fw_vi_stats_vf stats; 224 225 struct callout tick; 226 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 227 228 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 229}; 230 231struct tx_ch_rl_params { 232 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 233 uint32_t maxrate; 234}; 235 236enum { 237 CLRL_USER = (1 << 0), /* allocated manually. */ 238 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 239 CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 240 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 241}; 242 243struct tx_cl_rl_params { 244 int refcount; 245 uint8_t flags; 246 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 247 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 248 enum fw_sched_params_mode mode; /* aggr or per-flow */ 249 uint32_t maxrate; 250 uint16_t pktsize; 251 uint16_t burstsize; 252}; 253 254/* Tx scheduler parameters for a channel/port */ 255struct tx_sched_params { 256 /* Channel Rate Limiter */ 257 struct tx_ch_rl_params ch_rl; 258 259 /* Class WRR */ 260 /* XXX */ 261 262 /* Class Rate Limiter (including the default pktsize and burstsize). */ 263 int pktsize; 264 int burstsize; 265 struct tx_cl_rl_params cl_rl[]; 266}; 267 268struct port_info { 269 device_t dev; 270 struct adapter *adapter; 271 272 struct vi_info *vi; 273 int nvi; 274 int up_vis; 275 int uld_vis; 276 277 struct tx_sched_params *sched_params; 278 279 struct mtx pi_lock; 280 char lockname[16]; 281 unsigned long flags; 282 283 uint8_t lport; /* associated offload logical port */ 284 int8_t mdio_addr; 285 uint8_t port_type; 286 uint8_t mod_type; 287 uint8_t port_id; 288 uint8_t tx_chan; 289 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 290 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 291 292 struct link_config link_cfg; 293 struct ifmedia media; 294 295 struct timeval last_refreshed; 296 struct port_stats stats; 297 u_int tnl_cong_drops; 298 u_int tx_parse_error; 299 u_long tx_tls_records; 300 u_long tx_tls_octets; 301 u_long rx_tls_records; 302 u_long rx_tls_octets; 303 304 struct callout tick; 305}; 306 307#define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 308 309/* Where the cluster came from, how it has been carved up. */ 310struct cluster_layout { 311 int8_t zidx; 312 int8_t hwidx; 313 uint16_t region1; /* mbufs laid out within this region */ 314 /* region2 is the DMA region */ 315 uint16_t region3; /* cluster_metadata within this region */ 316}; 317 318struct cluster_metadata { 319 u_int refcount; 320 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 321}; 322 323struct fl_sdesc { 324 caddr_t cl; 325 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 326 struct cluster_layout cll; 327}; 328 329struct tx_desc { 330 __be64 flit[8]; 331}; 332 333struct tx_sdesc { 334 struct mbuf *m; /* m_nextpkt linked chain of frames */ 335 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 336}; 337 338 339#define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 340struct iq_desc { 341 struct rss_header rss; 342 uint8_t cpl[IQ_PAD]; 343 struct rsp_ctrl rsp; 344}; 345#undef IQ_PAD 346CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 347 348enum { 349 /* iq flags */ 350 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 351 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 352 /* 1 << 2 Used to be IQ_INTR */ 353 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 354 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 355 356 /* iq state */ 357 IQS_DISABLED = 0, 358 IQS_BUSY = 1, 359 IQS_IDLE = 2, 360 361 /* netmap related flags */ 362 NM_OFF = 0, 363 NM_ON = 1, 364 NM_BUSY = 2, 365}; 366 367enum { 368 CPL_COOKIE_RESERVED = 0, 369 CPL_COOKIE_FILTER, 370 CPL_COOKIE_DDP0, 371 CPL_COOKIE_DDP1, 372 CPL_COOKIE_TOM, 373 CPL_COOKIE_HASHFILTER, 374 CPL_COOKIE_ETHOFLD, 375 CPL_COOKIE_AVAILABLE3, 376 377 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 378}; 379 380struct sge_iq; 381struct rss_header; 382typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 383 struct mbuf *); 384typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 385typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 386 387/* 388 * Ingress Queue: T4 is producer, driver is consumer. 389 */ 390struct sge_iq { 391 uint32_t flags; 392 volatile int state; 393 struct adapter *adapter; 394 struct iq_desc *desc; /* KVA of descriptor ring */ 395 int8_t intr_pktc_idx; /* packet count threshold index */ 396 uint8_t gen; /* generation bit */ 397 uint8_t intr_params; /* interrupt holdoff parameters */ 398 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 399 uint16_t qsize; /* size (# of entries) of the queue */ 400 uint16_t sidx; /* index of the entry with the status page */ 401 uint16_t cidx; /* consumer index */ 402 uint16_t cntxt_id; /* SGE context id for the iq */ 403 uint16_t abs_id; /* absolute SGE id for the iq */ 404 405 STAILQ_ENTRY(sge_iq) link; 406 407 bus_dma_tag_t desc_tag; 408 bus_dmamap_t desc_map; 409 bus_addr_t ba; /* bus address of descriptor ring */ 410}; 411 412enum { 413 EQ_CTRL = 1, 414 EQ_ETH = 2, 415 EQ_OFLD = 3, 416 417 /* eq flags */ 418 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 419 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 420 EQ_ENABLED = (1 << 3), /* open for business */ 421 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 422}; 423 424/* Listed in order of preference. Update t4_sysctls too if you change these */ 425enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 426 427/* 428 * Egress Queue: driver is producer, T4 is consumer. 429 * 430 * Note: A free list is an egress queue (driver produces the buffers and T4 431 * consumes them) but it's special enough to have its own struct (see sge_fl). 432 */ 433struct sge_eq { 434 unsigned int flags; /* MUST be first */ 435 unsigned int cntxt_id; /* SGE context id for the eq */ 436 unsigned int abs_id; /* absolute SGE id for the eq */ 437 struct mtx eq_lock; 438 439 struct tx_desc *desc; /* KVA of descriptor ring */ 440 uint8_t doorbells; 441 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 442 u_int udb_qid; /* relative qid within the doorbell page */ 443 uint16_t sidx; /* index of the entry with the status page */ 444 uint16_t cidx; /* consumer idx (desc idx) */ 445 uint16_t pidx; /* producer idx (desc idx) */ 446 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 447 uint16_t dbidx; /* pidx of the most recent doorbell */ 448 uint16_t iqid; /* iq that gets egr_update for the eq */ 449 uint8_t tx_chan; /* tx channel used by the eq */ 450 volatile u_int equiq; /* EQUIQ outstanding */ 451 452 bus_dma_tag_t desc_tag; 453 bus_dmamap_t desc_map; 454 bus_addr_t ba; /* bus address of descriptor ring */ 455 char lockname[16]; 456}; 457 458struct sw_zone_info { 459 uma_zone_t zone; /* zone that this cluster comes from */ 460 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 461 int type; /* EXT_xxx type of the cluster */ 462 int8_t head_hwidx; 463 int8_t tail_hwidx; 464}; 465 466struct hw_buf_info { 467 int8_t zidx; /* backpointer to zone; -ve means unused */ 468 int8_t next; /* next hwidx for this zone; -1 means no more */ 469 int size; 470}; 471 472enum { 473 NUM_MEMWIN = 3, 474 475 MEMWIN0_APERTURE = 2048, 476 MEMWIN0_BASE = 0x1b800, 477 478 MEMWIN1_APERTURE = 32768, 479 MEMWIN1_BASE = 0x28000, 480 481 MEMWIN2_APERTURE_T4 = 65536, 482 MEMWIN2_BASE_T4 = 0x30000, 483 484 MEMWIN2_APERTURE_T5 = 128 * 1024, 485 MEMWIN2_BASE_T5 = 0x60000, 486}; 487 488struct memwin { 489 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 490 uint32_t mw_base; /* constant after setup_memwin */ 491 uint32_t mw_aperture; /* ditto */ 492 uint32_t mw_curpos; /* protected by mw_lock */ 493}; 494 495enum { 496 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 497 FL_DOOMED = (1 << 1), /* about to be destroyed */ 498 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 499 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 500}; 501 502#define FL_RUNNING_LOW(fl) \ 503 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 504#define FL_NOT_RUNNING_LOW(fl) \ 505 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 506 507struct sge_fl { 508 struct mtx fl_lock; 509 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 510 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 511 struct cluster_layout cll_def; /* default refill zone, layout */ 512 uint16_t lowat; /* # of buffers <= this means fl needs help */ 513 int flags; 514 uint16_t buf_boundary; 515 516 /* The 16b idx all deal with hw descriptors */ 517 uint16_t dbidx; /* hw pidx after last doorbell */ 518 uint16_t sidx; /* index of status page */ 519 volatile uint16_t hw_cidx; 520 521 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 522 uint32_t cidx; /* consumer index */ 523 uint32_t pidx; /* producer index */ 524 525 uint32_t dbval; 526 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 527 volatile uint32_t *udb; 528 529 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 530 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 531 uint64_t cl_allocated; /* # of clusters allocated */ 532 uint64_t cl_recycled; /* # of clusters recycled */ 533 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 534 535 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 536 struct mbuf *m0; 537 struct mbuf **pnext; 538 u_int remaining; 539 540 uint16_t qsize; /* # of hw descriptors (status page included) */ 541 uint16_t cntxt_id; /* SGE context id for the freelist */ 542 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 543 bus_dma_tag_t desc_tag; 544 bus_dmamap_t desc_map; 545 char lockname[16]; 546 bus_addr_t ba; /* bus address of descriptor ring */ 547 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 548}; 549 550struct mp_ring; 551 552/* txq: SGE egress queue + what's needed for Ethernet NIC */ 553struct sge_txq { 554 struct sge_eq eq; /* MUST be first */ 555 556 struct ifnet *ifp; /* the interface this txq belongs to */ 557 struct mp_ring *r; /* tx software ring */ 558 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 559 struct sglist *gl; 560 __be32 cpl_ctrl0; /* for convenience */ 561 int tc_idx; /* traffic class */ 562 563 struct task tx_reclaim_task; 564 /* stats for common events first */ 565 566 uint64_t txcsum; /* # of times hardware assisted with checksum */ 567 uint64_t tso_wrs; /* # of TSO work requests */ 568 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 569 uint64_t imm_wrs; /* # of work requests with immediate data */ 570 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 571 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 572 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 573 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 574 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 575 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 576 577 /* stats for not-that-common events */ 578} __aligned(CACHE_LINE_SIZE); 579 580/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 581struct sge_rxq { 582 struct sge_iq iq; /* MUST be first */ 583 struct sge_fl fl; /* MUST follow iq */ 584 585 struct ifnet *ifp; /* the interface this rxq belongs to */ 586#if defined(INET) || defined(INET6) 587 struct lro_ctrl lro; /* LRO state */ 588#endif 589 590 /* stats for common events first */ 591 592 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 593 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 594 595 /* stats for not-that-common events */ 596 597} __aligned(CACHE_LINE_SIZE); 598 599static inline struct sge_rxq * 600iq_to_rxq(struct sge_iq *iq) 601{ 602 603 return (__containerof(iq, struct sge_rxq, iq)); 604} 605 606 607/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 608struct sge_ofld_rxq { 609 struct sge_iq iq; /* MUST be first */ 610 struct sge_fl fl; /* MUST follow iq */ 611} __aligned(CACHE_LINE_SIZE); 612 613static inline struct sge_ofld_rxq * 614iq_to_ofld_rxq(struct sge_iq *iq) 615{ 616 617 return (__containerof(iq, struct sge_ofld_rxq, iq)); 618} 619 620struct wrqe { 621 STAILQ_ENTRY(wrqe) link; 622 struct sge_wrq *wrq; 623 int wr_len; 624 char wr[] __aligned(16); 625}; 626 627struct wrq_cookie { 628 TAILQ_ENTRY(wrq_cookie) link; 629 int ndesc; 630 int pidx; 631}; 632 633/* 634 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 635 * and offload tx queues are of this type. 636 */ 637struct sge_wrq { 638 struct sge_eq eq; /* MUST be first */ 639 640 struct adapter *adapter; 641 struct task wrq_tx_task; 642 643 /* Tx desc reserved but WR not "committed" yet. */ 644 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 645 646 /* List of WRs ready to go out as soon as descriptors are available. */ 647 STAILQ_HEAD(, wrqe) wr_list; 648 u_int nwr_pending; 649 u_int ndesc_needed; 650 651 /* stats for common events first */ 652 653 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 654 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 655 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 656 657 /* stats for not-that-common events */ 658 659 /* 660 * Scratch space for work requests that wrap around after reaching the 661 * status page, and some information about the last WR that used it. 662 */ 663 uint16_t ss_pidx; 664 uint16_t ss_len; 665 uint8_t ss[SGE_MAX_WR_LEN]; 666 667} __aligned(CACHE_LINE_SIZE); 668 669 670struct sge_nm_rxq { 671 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 672 struct vi_info *vi; 673 674 struct iq_desc *iq_desc; 675 uint16_t iq_abs_id; 676 uint16_t iq_cntxt_id; 677 uint16_t iq_cidx; 678 uint16_t iq_sidx; 679 uint8_t iq_gen; 680 681 __be64 *fl_desc; 682 uint16_t fl_cntxt_id; 683 uint32_t fl_cidx; 684 uint32_t fl_pidx; 685 uint32_t fl_sidx; 686 uint32_t fl_db_val; 687 u_int fl_hwidx:4; 688 689 u_int nid; /* netmap ring # for this queue */ 690 691 /* infrequently used items after this */ 692 693 bus_dma_tag_t iq_desc_tag; 694 bus_dmamap_t iq_desc_map; 695 bus_addr_t iq_ba; 696 int intr_idx; 697 698 bus_dma_tag_t fl_desc_tag; 699 bus_dmamap_t fl_desc_map; 700 bus_addr_t fl_ba; 701} __aligned(CACHE_LINE_SIZE); 702 703struct sge_nm_txq { 704 struct tx_desc *desc; 705 uint16_t cidx; 706 uint16_t pidx; 707 uint16_t sidx; 708 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 709 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 710 uint16_t dbidx; /* pidx of the most recent doorbell */ 711 uint8_t doorbells; 712 volatile uint32_t *udb; 713 u_int udb_qid; 714 u_int cntxt_id; 715 __be32 cpl_ctrl0; /* for convenience */ 716 u_int nid; /* netmap ring # for this queue */ 717 718 /* infrequently used items after this */ 719 720 bus_dma_tag_t desc_tag; 721 bus_dmamap_t desc_map; 722 bus_addr_t ba; 723 int iqidx; 724} __aligned(CACHE_LINE_SIZE); 725 726struct sge { 727 int nrxq; /* total # of Ethernet rx queues */ 728 int ntxq; /* total # of Ethernet tx queues */ 729 int nofldrxq; /* total # of TOE rx queues */ 730 int nofldtxq; /* total # of TOE tx queues */ 731 int nnmrxq; /* total # of netmap rx queues */ 732 int nnmtxq; /* total # of netmap tx queues */ 733 int niq; /* total # of ingress queues */ 734 int neq; /* total # of egress queues */ 735 736 struct sge_iq fwq; /* Firmware event queue */ 737 struct sge_wrq *ctrlq; /* Control queues */ 738 struct sge_txq *txq; /* NIC tx queues */ 739 struct sge_rxq *rxq; /* NIC rx queues */ 740 struct sge_wrq *ofld_txq; /* TOE tx queues */ 741 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 742 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 743 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 744 745 uint16_t iq_start; /* first cntxt_id */ 746 uint16_t iq_base; /* first abs_id */ 747 int eq_start; /* first cntxt_id */ 748 int eq_base; /* first abs_id */ 749 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 750 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 751 752 int8_t safe_hwidx1; /* may not have room for metadata */ 753 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 754 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 755 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 756}; 757 758struct devnames { 759 const char *nexus_name; 760 const char *ifnet_name; 761 const char *vi_ifnet_name; 762 const char *pf03_drv_name; 763 const char *vf_nexus_name; 764 const char *vf_ifnet_name; 765}; 766 767struct adapter { 768 SLIST_ENTRY(adapter) link; 769 device_t dev; 770 struct cdev *cdev; 771 const struct devnames *names; 772 773 /* PCIe register resources */ 774 int regs_rid; 775 struct resource *regs_res; 776 int msix_rid; 777 struct resource *msix_res; 778 bus_space_handle_t bh; 779 bus_space_tag_t bt; 780 bus_size_t mmio_len; 781 int udbs_rid; 782 struct resource *udbs_res; 783 volatile uint8_t *udbs_base; 784 785 unsigned int pf; 786 unsigned int mbox; 787 unsigned int vpd_busy; 788 unsigned int vpd_flag; 789 790 /* Interrupt information */ 791 int intr_type; 792 int intr_count; 793 struct irq { 794 struct resource *res; 795 int rid; 796 void *tag; 797 struct sge_rxq *rxq; 798 struct sge_nm_rxq *nm_rxq; 799 } __aligned(CACHE_LINE_SIZE) *irq; 800 int sge_gts_reg; 801 int sge_kdoorbell_reg; 802 803 bus_dma_tag_t dmat; /* Parent DMA tag */ 804 805 struct sge sge; 806 int lro_timeout; 807 int sc_do_rxcopy; 808 809 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 810 struct port_info *port[MAX_NPORTS]; 811 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 812 813 void *tom_softc; /* (struct tom_data *) */ 814 struct tom_tunables tt; 815 struct t4_offload_policy *policy; 816 struct rwlock policy_lock; 817 818 void *iwarp_softc; /* (struct c4iw_dev *) */ 819 struct iw_tunables iwt; 820 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 821 void *ccr_softc; /* (struct ccr_softc *) */ 822 struct l2t_data *l2t; /* L2 table */ 823 struct smt_data *smt; /* Source MAC Table */ 824 struct tid_info tids; 825 vmem_t *key_map; 826 827 uint8_t doorbells; 828 int offload_map; /* ports with IFCAP_TOE enabled */ 829 int active_ulds; /* ULDs activated on this adapter */ 830 int flags; 831 int debug_flags; 832 833 char ifp_lockname[16]; 834 struct mtx ifp_lock; 835 struct ifnet *ifp; /* tracer ifp */ 836 struct ifmedia media; 837 int traceq; /* iq used by all tracers, -1 if none */ 838 int tracer_valid; /* bitmap of valid tracers */ 839 int tracer_enabled; /* bitmap of enabled tracers */ 840 841 char fw_version[16]; 842 char tp_version[16]; 843 char er_version[16]; 844 char bs_version[16]; 845 char cfg_file[32]; 846 u_int cfcsum; 847 struct adapter_params params; 848 const struct chip_params *chip_params; 849 struct t4_virt_res vres; 850 851 uint16_t nbmcaps; 852 uint16_t linkcaps; 853 uint16_t switchcaps; 854 uint16_t niccaps; 855 uint16_t toecaps; 856 uint16_t rdmacaps; 857 uint16_t cryptocaps; 858 uint16_t iscsicaps; 859 uint16_t fcoecaps; 860 861 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 862 863 struct mtx sc_lock; 864 char lockname[16]; 865 866 /* Starving free lists */ 867 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 868 TAILQ_HEAD(, sge_fl) sfl; 869 struct callout sfl_callout; 870 871 struct mtx reg_lock; /* for indirect register access */ 872 873 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 874 875 struct mtx tc_lock; 876 struct task tc_task; 877 878 const char *last_op; 879 const void *last_op_thr; 880 int last_op_flags; 881}; 882 883#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 884#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 885#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 886#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 887 888#define ASSERT_SYNCHRONIZED_OP(sc) \ 889 KASSERT(IS_BUSY(sc) && \ 890 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 891 ("%s: operation not synchronized.", __func__)) 892 893#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 894#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 895#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 896#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 897 898#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 899#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 900#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 901#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 902#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 903 904#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 905#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 906#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 907#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 908 909#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 910#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 911#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 912#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 913#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 914 915#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 916#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 917#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 918#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 919#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 920 921#define CH_DUMP_MBOX(sc, mbox, data_reg) \ 922 do { \ 923 if (sc->debug_flags & DF_DUMP_MBOX) { \ 924 log(LOG_NOTICE, \ 925 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 926 "%016llx %016llx %016llx %016llx\n", \ 927 device_get_nameunit(sc->dev), mbox, \ 928 (unsigned long long)t4_read_reg64(sc, data_reg), \ 929 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 930 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 931 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 932 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 933 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 934 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 935 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 936 } \ 937 } while (0) 938 939#define for_each_txq(vi, iter, q) \ 940 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 941 iter < vi->ntxq; ++iter, ++q) 942#define for_each_rxq(vi, iter, q) \ 943 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 944 iter < vi->nrxq; ++iter, ++q) 945#define for_each_ofld_txq(vi, iter, q) \ 946 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 947 iter < vi->nofldtxq; ++iter, ++q) 948#define for_each_ofld_rxq(vi, iter, q) \ 949 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 950 iter < vi->nofldrxq; ++iter, ++q) 951#define for_each_nm_txq(vi, iter, q) \ 952 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 953 iter < vi->nnmtxq; ++iter, ++q) 954#define for_each_nm_rxq(vi, iter, q) \ 955 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 956 iter < vi->nnmrxq; ++iter, ++q) 957#define for_each_vi(_pi, _iter, _vi) \ 958 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 959 ++(_iter), ++(_vi)) 960 961#define IDXINCR(idx, incr, wrap) do { \ 962 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 963} while (0) 964#define IDXDIFF(head, tail, wrap) \ 965 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 966 967/* One for errors, one for firmware events */ 968#define T4_EXTRA_INTR 2 969 970/* One for firmware events */ 971#define T4VF_EXTRA_INTR 1 972 973static inline int 974forwarding_intr_to_fwq(struct adapter *sc) 975{ 976 977 return (sc->intr_count == 1); 978} 979 980static inline uint32_t 981t4_read_reg(struct adapter *sc, uint32_t reg) 982{ 983 984 return bus_space_read_4(sc->bt, sc->bh, reg); 985} 986 987static inline void 988t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 989{ 990 991 bus_space_write_4(sc->bt, sc->bh, reg, val); 992} 993 994static inline uint64_t 995t4_read_reg64(struct adapter *sc, uint32_t reg) 996{ 997 998#ifdef __LP64__ 999 return bus_space_read_8(sc->bt, sc->bh, reg); 1000#else 1001 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1002 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1003 1004#endif 1005} 1006 1007static inline void 1008t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1009{ 1010 1011#ifdef __LP64__ 1012 bus_space_write_8(sc->bt, sc->bh, reg, val); 1013#else 1014 bus_space_write_4(sc->bt, sc->bh, reg, val); 1015 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1016#endif 1017} 1018 1019static inline void 1020t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1021{ 1022 1023 *val = pci_read_config(sc->dev, reg, 1); 1024} 1025 1026static inline void 1027t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1028{ 1029 1030 pci_write_config(sc->dev, reg, val, 1); 1031} 1032 1033static inline void 1034t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1035{ 1036 1037 *val = pci_read_config(sc->dev, reg, 2); 1038} 1039 1040static inline void 1041t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1042{ 1043 1044 pci_write_config(sc->dev, reg, val, 2); 1045} 1046 1047static inline void 1048t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1049{ 1050 1051 *val = pci_read_config(sc->dev, reg, 4); 1052} 1053 1054static inline void 1055t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1056{ 1057 1058 pci_write_config(sc->dev, reg, val, 4); 1059} 1060 1061static inline struct port_info * 1062adap2pinfo(struct adapter *sc, int idx) 1063{ 1064 1065 return (sc->port[idx]); 1066} 1067 1068static inline void 1069t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1070{ 1071 1072 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1073} 1074 1075static inline int 1076tx_resume_threshold(struct sge_eq *eq) 1077{ 1078 1079 /* not quite the same as qsize / 4, but this will do. */ 1080 return (eq->sidx / 4); 1081} 1082 1083static inline int 1084t4_use_ldst(struct adapter *sc) 1085{ 1086 1087#ifdef notyet 1088 return (sc->flags & FW_OK || !sc->use_bd); 1089#else 1090 return (0); 1091#endif 1092} 1093 1094/* t4_main.c */ 1095extern int t4_ntxq; 1096extern int t4_nrxq; 1097extern int t4_intr_types; 1098extern int t4_tmr_idx; 1099extern int t4_pktc_idx; 1100extern unsigned int t4_qsize_rxq; 1101extern unsigned int t4_qsize_txq; 1102extern device_method_t cxgbe_methods[]; 1103 1104int t4_os_find_pci_capability(struct adapter *, int); 1105int t4_os_pci_save_state(struct adapter *); 1106int t4_os_pci_restore_state(struct adapter *); 1107void t4_os_portmod_changed(struct port_info *); 1108void t4_os_link_changed(struct port_info *); 1109void t4_iterate(void (*)(struct adapter *, void *), void *); 1110void t4_init_devnames(struct adapter *); 1111void t4_add_adapter(struct adapter *); 1112void t4_aes_getdeckey(void *, const void *, unsigned int); 1113int t4_detach_common(device_t); 1114int t4_map_bars_0_and_4(struct adapter *); 1115int t4_map_bar_2(struct adapter *); 1116int t4_setup_intr_handlers(struct adapter *); 1117void t4_sysctls(struct adapter *); 1118int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1119void doom_vi(struct adapter *, struct vi_info *); 1120void end_synchronized_op(struct adapter *, int); 1121int update_mac_settings(struct ifnet *, int); 1122int adapter_full_init(struct adapter *); 1123int adapter_full_uninit(struct adapter *); 1124uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1125int vi_full_init(struct vi_info *); 1126int vi_full_uninit(struct vi_info *); 1127void vi_sysctls(struct vi_info *); 1128void vi_tick(void *); 1129int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1130int alloc_atid_tab(struct tid_info *, int); 1131void free_atid_tab(struct tid_info *); 1132int alloc_atid(struct adapter *, void *); 1133void *lookup_atid(struct adapter *, int); 1134void free_atid(struct adapter *, int); 1135void release_tid(struct adapter *, int, struct sge_wrq *); 1136int cxgbe_media_change(struct ifnet *); 1137void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1138 1139#ifdef DEV_NETMAP 1140/* t4_netmap.c */ 1141struct sge_nm_rxq; 1142void cxgbe_nm_attach(struct vi_info *); 1143void cxgbe_nm_detach(struct vi_info *); 1144void service_nm_rxq(struct sge_nm_rxq *); 1145#endif 1146 1147/* t4_sge.c */ 1148void t4_sge_modload(void); 1149void t4_sge_modunload(void); 1150uint64_t t4_sge_extfree_refs(void); 1151void t4_tweak_chip_settings(struct adapter *); 1152int t4_read_chip_settings(struct adapter *); 1153int t4_create_dma_tag(struct adapter *); 1154void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1155 struct sysctl_oid_list *); 1156int t4_destroy_dma_tag(struct adapter *); 1157int t4_setup_adapter_queues(struct adapter *); 1158int t4_teardown_adapter_queues(struct adapter *); 1159int t4_setup_vi_queues(struct vi_info *); 1160int t4_teardown_vi_queues(struct vi_info *); 1161void t4_intr_all(void *); 1162void t4_intr(void *); 1163#ifdef DEV_NETMAP 1164void t4_nm_intr(void *); 1165void t4_vi_intr(void *); 1166#endif 1167void t4_intr_err(void *); 1168void t4_intr_evt(void *); 1169void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1170void t4_update_fl_bufsize(struct ifnet *); 1171int parse_pkt(struct adapter *, struct mbuf **); 1172void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1173void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1174int tnl_cong(struct port_info *, int); 1175void t4_register_an_handler(an_handler_t); 1176void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1177void t4_register_cpl_handler(int, cpl_handler_t); 1178void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1179 1180/* t4_tracer.c */ 1181struct t4_tracer; 1182void t4_tracer_modload(void); 1183void t4_tracer_modunload(void); 1184void t4_tracer_port_detach(struct adapter *); 1185int t4_get_tracer(struct adapter *, struct t4_tracer *); 1186int t4_set_tracer(struct adapter *, struct t4_tracer *); 1187int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1188int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1189 1190/* t4_sched.c */ 1191int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1192int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1193int t4_init_tx_sched(struct adapter *); 1194int t4_free_tx_sched(struct adapter *); 1195void t4_update_tx_sched(struct adapter *); 1196int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1197void t4_release_cl_rl(struct adapter *, int, int); 1198int sysctl_tc(SYSCTL_HANDLER_ARGS); 1199int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1200 1201/* t4_filter.c */ 1202int get_filter_mode(struct adapter *, uint32_t *); 1203int set_filter_mode(struct adapter *, uint32_t); 1204int get_filter(struct adapter *, struct t4_filter *); 1205int set_filter(struct adapter *, struct t4_filter *); 1206int del_filter(struct adapter *, struct t4_filter *); 1207int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1208int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1209int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1210int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1211void free_hftid_hash(struct tid_info *); 1212 1213static inline struct wrqe * 1214alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1215{ 1216 int len = offsetof(struct wrqe, wr) + wr_len; 1217 struct wrqe *wr; 1218 1219 wr = malloc(len, M_CXGBE, M_NOWAIT); 1220 if (__predict_false(wr == NULL)) 1221 return (NULL); 1222 wr->wr_len = wr_len; 1223 wr->wrq = wrq; 1224 return (wr); 1225} 1226 1227static inline void * 1228wrtod(struct wrqe *wr) 1229{ 1230 return (&wr->wr[0]); 1231} 1232 1233static inline void 1234free_wrqe(struct wrqe *wr) 1235{ 1236 free(wr, M_CXGBE); 1237} 1238 1239static inline void 1240t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1241{ 1242 struct sge_wrq *wrq = wr->wrq; 1243 1244 TXQ_LOCK(wrq); 1245 t4_wrq_tx_locked(sc, wrq, wr); 1246 TXQ_UNLOCK(wrq); 1247} 1248 1249static inline int 1250read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1251 int len) 1252{ 1253 1254 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1255} 1256 1257static inline int 1258write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1259 const uint32_t *val, int len) 1260{ 1261 1262 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1263} 1264#endif 1265