adapter.h revision 346876
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/11/sys/dev/cxgbe/adapter.h 346876 2019-04-29 04:42:18Z np $ 28 * 29 */ 30 31#ifndef __T4_ADAPTER_H__ 32#define __T4_ADAPTER_H__ 33 34#include <sys/kernel.h> 35#include <sys/bus.h> 36#include <sys/rman.h> 37#include <sys/types.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/rwlock.h> 41#include <sys/sx.h> 42#include <sys/vmem.h> 43#include <vm/uma.h> 44 45#include <dev/pci/pcivar.h> 46#include <dev/pci/pcireg.h> 47#include <machine/bus.h> 48#include <sys/socket.h> 49#include <sys/sysctl.h> 50#include <net/ethernet.h> 51#include <net/if.h> 52#include <net/if_var.h> 53#include <net/if_media.h> 54#include <netinet/in.h> 55#include <netinet/tcp_lro.h> 56 57#include "offload.h" 58#include "t4_ioctl.h" 59#include "common/t4_msg.h" 60#include "firmware/t4fw_interface.h" 61 62#define KTR_CXGBE KTR_SPARE3 63MALLOC_DECLARE(M_CXGBE); 64#define CXGBE_UNIMPLEMENTED(s) \ 65 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 66 67#if defined(__i386__) || defined(__amd64__) 68static __inline void 69prefetch(void *x) 70{ 71 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 72} 73#else 74#define prefetch(x) __builtin_prefetch(x) 75#endif 76 77#ifndef SYSCTL_ADD_UQUAD 78#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 79#define sysctl_handle_64 sysctl_handle_quad 80#define CTLTYPE_U64 CTLTYPE_QUAD 81#endif 82 83SYSCTL_DECL(_hw_cxgbe); 84 85struct adapter; 86typedef struct adapter adapter_t; 87 88enum { 89 /* 90 * All ingress queues use this entry size. Note that the firmware event 91 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 92 * be at least 64. 93 */ 94 IQ_ESIZE = 64, 95 96 /* Default queue sizes for all kinds of ingress queues */ 97 FW_IQ_QSIZE = 256, 98 RX_IQ_QSIZE = 1024, 99 100 /* All egress queues use this entry size */ 101 EQ_ESIZE = 64, 102 103 /* Default queue sizes for all kinds of egress queues */ 104 CTRL_EQ_QSIZE = 1024, 105 TX_EQ_QSIZE = 1024, 106 107#if MJUMPAGESIZE != MCLBYTES 108 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 109#else 110 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 111#endif 112 CL_METADATA_SIZE = CACHE_LINE_SIZE, 113 114 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 115 TX_SGL_SEGS = 39, 116 TX_SGL_SEGS_TSO = 38, 117 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 118}; 119 120enum { 121 /* adapter intr_type */ 122 INTR_INTX = (1 << 0), 123 INTR_MSI = (1 << 1), 124 INTR_MSIX = (1 << 2) 125}; 126 127enum { 128 XGMAC_MTU = (1 << 0), 129 XGMAC_PROMISC = (1 << 1), 130 XGMAC_ALLMULTI = (1 << 2), 131 XGMAC_VLANEX = (1 << 3), 132 XGMAC_UCADDR = (1 << 4), 133 XGMAC_MCADDRS = (1 << 5), 134 135 XGMAC_ALL = 0xffff 136}; 137 138enum { 139 /* flags understood by begin_synchronized_op */ 140 HOLD_LOCK = (1 << 0), 141 SLEEP_OK = (1 << 1), 142 INTR_OK = (1 << 2), 143 144 /* flags understood by end_synchronized_op */ 145 LOCK_HELD = HOLD_LOCK, 146}; 147 148enum { 149 /* adapter flags */ 150 FULL_INIT_DONE = (1 << 0), 151 FW_OK = (1 << 1), 152 CHK_MBOX_ACCESS = (1 << 2), 153 MASTER_PF = (1 << 3), 154 ADAP_SYSCTL_CTX = (1 << 4), 155 /* TOM_INIT_DONE= (1 << 5), No longer used */ 156 BUF_PACKING_OK = (1 << 6), 157 IS_VF = (1 << 7), 158 159 CXGBE_BUSY = (1 << 9), 160 161 /* port flags */ 162 HAS_TRACEQ = (1 << 3), 163 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 164 165 /* VI flags */ 166 DOOMED = (1 << 0), 167 VI_INIT_DONE = (1 << 1), 168 VI_SYSCTL_CTX = (1 << 2), 169 170 /* adapter debug_flags */ 171 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 172 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 173 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 174}; 175 176#define IS_DOOMED(vi) ((vi)->flags & DOOMED) 177#define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 178#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 179#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 180#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 181 182struct vi_info { 183 device_t dev; 184 struct port_info *pi; 185 186 struct ifnet *ifp; 187 188 unsigned long flags; 189 int if_flags; 190 191 uint16_t *rss, *nm_rss; 192 int smt_idx; /* for convenience */ 193 uint16_t viid; 194 int16_t xact_addr_filt;/* index of exact MAC address filter */ 195 uint16_t rss_size; /* size of VI's RSS table slice */ 196 uint16_t rss_base; /* start of VI's RSS table slice */ 197 198 eventhandler_tag vlan_c; 199 200 int nintr; 201 int first_intr; 202 203 /* These need to be int as they are used in sysctl */ 204 int ntxq; /* # of tx queues */ 205 int first_txq; /* index of first tx queue */ 206 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 207 int nrxq; /* # of rx queues */ 208 int first_rxq; /* index of first rx queue */ 209 int nofldtxq; /* # of offload tx queues */ 210 int first_ofld_txq; /* index of first offload tx queue */ 211 int nofldrxq; /* # of offload rx queues */ 212 int first_ofld_rxq; /* index of first offload rx queue */ 213 int nnmtxq; 214 int first_nm_txq; 215 int nnmrxq; 216 int first_nm_rxq; 217 int tmr_idx; 218 int ofld_tmr_idx; 219 int pktc_idx; 220 int ofld_pktc_idx; 221 int qsize_rxq; 222 int qsize_txq; 223 224 struct timeval last_refreshed; 225 struct fw_vi_stats_vf stats; 226 227 struct callout tick; 228 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 229 230 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 231}; 232 233struct tx_ch_rl_params { 234 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 235 uint32_t maxrate; 236}; 237 238enum { 239 CLRL_USER = (1 << 0), /* allocated manually. */ 240 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */ 241 CLRL_ASYNC = (1 << 2), /* async hw update requested. */ 242 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */ 243}; 244 245struct tx_cl_rl_params { 246 int refcount; 247 uint8_t flags; 248 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 249 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 250 enum fw_sched_params_mode mode; /* aggr or per-flow */ 251 uint32_t maxrate; 252 uint16_t pktsize; 253 uint16_t burstsize; 254}; 255 256/* Tx scheduler parameters for a channel/port */ 257struct tx_sched_params { 258 /* Channel Rate Limiter */ 259 struct tx_ch_rl_params ch_rl; 260 261 /* Class WRR */ 262 /* XXX */ 263 264 /* Class Rate Limiter (including the default pktsize and burstsize). */ 265 int pktsize; 266 int burstsize; 267 struct tx_cl_rl_params cl_rl[]; 268}; 269 270struct port_info { 271 device_t dev; 272 struct adapter *adapter; 273 274 struct vi_info *vi; 275 int nvi; 276 int up_vis; 277 int uld_vis; 278 279 struct tx_sched_params *sched_params; 280 281 struct mtx pi_lock; 282 char lockname[16]; 283 unsigned long flags; 284 285 uint8_t lport; /* associated offload logical port */ 286 int8_t mdio_addr; 287 uint8_t port_type; 288 uint8_t mod_type; 289 uint8_t port_id; 290 uint8_t tx_chan; 291 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 292 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 293 294 struct link_config link_cfg; 295 struct ifmedia media; 296 297 struct timeval last_refreshed; 298 struct port_stats stats; 299 u_int tnl_cong_drops; 300 u_int tx_parse_error; 301 u_long tx_tls_records; 302 u_long tx_tls_octets; 303 u_long rx_tls_records; 304 u_long rx_tls_octets; 305 306 struct callout tick; 307}; 308 309#define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 310 311/* Where the cluster came from, how it has been carved up. */ 312struct cluster_layout { 313 int8_t zidx; 314 int8_t hwidx; 315 uint16_t region1; /* mbufs laid out within this region */ 316 /* region2 is the DMA region */ 317 uint16_t region3; /* cluster_metadata within this region */ 318}; 319 320struct cluster_metadata { 321 u_int refcount; 322 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 323}; 324 325struct fl_sdesc { 326 caddr_t cl; 327 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 328 struct cluster_layout cll; 329}; 330 331struct tx_desc { 332 __be64 flit[8]; 333}; 334 335struct tx_sdesc { 336 struct mbuf *m; /* m_nextpkt linked chain of frames */ 337 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 338}; 339 340 341#define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 342struct iq_desc { 343 struct rss_header rss; 344 uint8_t cpl[IQ_PAD]; 345 struct rsp_ctrl rsp; 346}; 347#undef IQ_PAD 348CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 349 350enum { 351 /* iq flags */ 352 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 353 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 354 /* 1 << 2 Used to be IQ_INTR */ 355 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 356 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 357 358 /* iq state */ 359 IQS_DISABLED = 0, 360 IQS_BUSY = 1, 361 IQS_IDLE = 2, 362 363 /* netmap related flags */ 364 NM_OFF = 0, 365 NM_ON = 1, 366 NM_BUSY = 2, 367}; 368 369enum { 370 CPL_COOKIE_RESERVED = 0, 371 CPL_COOKIE_FILTER, 372 CPL_COOKIE_DDP0, 373 CPL_COOKIE_DDP1, 374 CPL_COOKIE_TOM, 375 CPL_COOKIE_HASHFILTER, 376 CPL_COOKIE_ETHOFLD, 377 CPL_COOKIE_AVAILABLE3, 378 379 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 380}; 381 382struct sge_iq; 383struct rss_header; 384typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 385 struct mbuf *); 386typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 387typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 388 389/* 390 * Ingress Queue: T4 is producer, driver is consumer. 391 */ 392struct sge_iq { 393 uint32_t flags; 394 volatile int state; 395 struct adapter *adapter; 396 struct iq_desc *desc; /* KVA of descriptor ring */ 397 int8_t intr_pktc_idx; /* packet count threshold index */ 398 uint8_t gen; /* generation bit */ 399 uint8_t intr_params; /* interrupt holdoff parameters */ 400 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 401 uint16_t qsize; /* size (# of entries) of the queue */ 402 uint16_t sidx; /* index of the entry with the status page */ 403 uint16_t cidx; /* consumer index */ 404 uint16_t cntxt_id; /* SGE context id for the iq */ 405 uint16_t abs_id; /* absolute SGE id for the iq */ 406 407 STAILQ_ENTRY(sge_iq) link; 408 409 bus_dma_tag_t desc_tag; 410 bus_dmamap_t desc_map; 411 bus_addr_t ba; /* bus address of descriptor ring */ 412}; 413 414enum { 415 EQ_CTRL = 1, 416 EQ_ETH = 2, 417 EQ_OFLD = 3, 418 419 /* eq flags */ 420 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 421 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 422 EQ_ENABLED = (1 << 3), /* open for business */ 423 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 424}; 425 426/* Listed in order of preference. Update t4_sysctls too if you change these */ 427enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 428 429/* 430 * Egress Queue: driver is producer, T4 is consumer. 431 * 432 * Note: A free list is an egress queue (driver produces the buffers and T4 433 * consumes them) but it's special enough to have its own struct (see sge_fl). 434 */ 435struct sge_eq { 436 unsigned int flags; /* MUST be first */ 437 unsigned int cntxt_id; /* SGE context id for the eq */ 438 unsigned int abs_id; /* absolute SGE id for the eq */ 439 struct mtx eq_lock; 440 441 struct tx_desc *desc; /* KVA of descriptor ring */ 442 uint8_t doorbells; 443 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 444 u_int udb_qid; /* relative qid within the doorbell page */ 445 uint16_t sidx; /* index of the entry with the status page */ 446 uint16_t cidx; /* consumer idx (desc idx) */ 447 uint16_t pidx; /* producer idx (desc idx) */ 448 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 449 uint16_t dbidx; /* pidx of the most recent doorbell */ 450 uint16_t iqid; /* iq that gets egr_update for the eq */ 451 uint8_t tx_chan; /* tx channel used by the eq */ 452 volatile u_int equiq; /* EQUIQ outstanding */ 453 454 bus_dma_tag_t desc_tag; 455 bus_dmamap_t desc_map; 456 bus_addr_t ba; /* bus address of descriptor ring */ 457 char lockname[16]; 458}; 459 460struct sw_zone_info { 461 uma_zone_t zone; /* zone that this cluster comes from */ 462 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 463 int type; /* EXT_xxx type of the cluster */ 464 int8_t head_hwidx; 465 int8_t tail_hwidx; 466}; 467 468struct hw_buf_info { 469 int8_t zidx; /* backpointer to zone; -ve means unused */ 470 int8_t next; /* next hwidx for this zone; -1 means no more */ 471 int size; 472}; 473 474enum { 475 NUM_MEMWIN = 3, 476 477 MEMWIN0_APERTURE = 2048, 478 MEMWIN0_BASE = 0x1b800, 479 480 MEMWIN1_APERTURE = 32768, 481 MEMWIN1_BASE = 0x28000, 482 483 MEMWIN2_APERTURE_T4 = 65536, 484 MEMWIN2_BASE_T4 = 0x30000, 485 486 MEMWIN2_APERTURE_T5 = 128 * 1024, 487 MEMWIN2_BASE_T5 = 0x60000, 488}; 489 490struct memwin { 491 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 492 uint32_t mw_base; /* constant after setup_memwin */ 493 uint32_t mw_aperture; /* ditto */ 494 uint32_t mw_curpos; /* protected by mw_lock */ 495}; 496 497enum { 498 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 499 FL_DOOMED = (1 << 1), /* about to be destroyed */ 500 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 501 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 502}; 503 504#define FL_RUNNING_LOW(fl) \ 505 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 506#define FL_NOT_RUNNING_LOW(fl) \ 507 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 508 509struct sge_fl { 510 struct mtx fl_lock; 511 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 512 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 513 struct cluster_layout cll_def; /* default refill zone, layout */ 514 uint16_t lowat; /* # of buffers <= this means fl needs help */ 515 int flags; 516 uint16_t buf_boundary; 517 518 /* The 16b idx all deal with hw descriptors */ 519 uint16_t dbidx; /* hw pidx after last doorbell */ 520 uint16_t sidx; /* index of status page */ 521 volatile uint16_t hw_cidx; 522 523 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 524 uint32_t cidx; /* consumer index */ 525 uint32_t pidx; /* producer index */ 526 527 uint32_t dbval; 528 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 529 volatile uint32_t *udb; 530 531 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 532 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 533 uint64_t cl_allocated; /* # of clusters allocated */ 534 uint64_t cl_recycled; /* # of clusters recycled */ 535 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 536 537 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 538 struct mbuf *m0; 539 struct mbuf **pnext; 540 u_int remaining; 541 542 uint16_t qsize; /* # of hw descriptors (status page included) */ 543 uint16_t cntxt_id; /* SGE context id for the freelist */ 544 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 545 bus_dma_tag_t desc_tag; 546 bus_dmamap_t desc_map; 547 char lockname[16]; 548 bus_addr_t ba; /* bus address of descriptor ring */ 549 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 550}; 551 552struct mp_ring; 553 554/* txq: SGE egress queue + what's needed for Ethernet NIC */ 555struct sge_txq { 556 struct sge_eq eq; /* MUST be first */ 557 558 struct ifnet *ifp; /* the interface this txq belongs to */ 559 struct mp_ring *r; /* tx software ring */ 560 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 561 struct sglist *gl; 562 __be32 cpl_ctrl0; /* for convenience */ 563 int tc_idx; /* traffic class */ 564 565 struct task tx_reclaim_task; 566 /* stats for common events first */ 567 568 uint64_t txcsum; /* # of times hardware assisted with checksum */ 569 uint64_t tso_wrs; /* # of TSO work requests */ 570 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 571 uint64_t imm_wrs; /* # of work requests with immediate data */ 572 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 573 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 574 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 575 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 576 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 577 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 578 579 /* stats for not-that-common events */ 580} __aligned(CACHE_LINE_SIZE); 581 582/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 583struct sge_rxq { 584 struct sge_iq iq; /* MUST be first */ 585 struct sge_fl fl; /* MUST follow iq */ 586 587 struct ifnet *ifp; /* the interface this rxq belongs to */ 588#if defined(INET) || defined(INET6) 589 struct lro_ctrl lro; /* LRO state */ 590#endif 591 592 /* stats for common events first */ 593 594 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 595 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 596 597 /* stats for not-that-common events */ 598 599} __aligned(CACHE_LINE_SIZE); 600 601static inline struct sge_rxq * 602iq_to_rxq(struct sge_iq *iq) 603{ 604 605 return (__containerof(iq, struct sge_rxq, iq)); 606} 607 608 609/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 610struct sge_ofld_rxq { 611 struct sge_iq iq; /* MUST be first */ 612 struct sge_fl fl; /* MUST follow iq */ 613} __aligned(CACHE_LINE_SIZE); 614 615static inline struct sge_ofld_rxq * 616iq_to_ofld_rxq(struct sge_iq *iq) 617{ 618 619 return (__containerof(iq, struct sge_ofld_rxq, iq)); 620} 621 622struct wrqe { 623 STAILQ_ENTRY(wrqe) link; 624 struct sge_wrq *wrq; 625 int wr_len; 626 char wr[] __aligned(16); 627}; 628 629struct wrq_cookie { 630 TAILQ_ENTRY(wrq_cookie) link; 631 int ndesc; 632 int pidx; 633}; 634 635/* 636 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 637 * and offload tx queues are of this type. 638 */ 639struct sge_wrq { 640 struct sge_eq eq; /* MUST be first */ 641 642 struct adapter *adapter; 643 struct task wrq_tx_task; 644 645 /* Tx desc reserved but WR not "committed" yet. */ 646 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 647 648 /* List of WRs ready to go out as soon as descriptors are available. */ 649 STAILQ_HEAD(, wrqe) wr_list; 650 u_int nwr_pending; 651 u_int ndesc_needed; 652 653 /* stats for common events first */ 654 655 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 656 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 657 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 658 659 /* stats for not-that-common events */ 660 661 /* 662 * Scratch space for work requests that wrap around after reaching the 663 * status page, and some information about the last WR that used it. 664 */ 665 uint16_t ss_pidx; 666 uint16_t ss_len; 667 uint8_t ss[SGE_MAX_WR_LEN]; 668 669} __aligned(CACHE_LINE_SIZE); 670 671 672struct sge_nm_rxq { 673 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 674 struct vi_info *vi; 675 676 struct iq_desc *iq_desc; 677 uint16_t iq_abs_id; 678 uint16_t iq_cntxt_id; 679 uint16_t iq_cidx; 680 uint16_t iq_sidx; 681 uint8_t iq_gen; 682 683 __be64 *fl_desc; 684 uint16_t fl_cntxt_id; 685 uint32_t fl_cidx; 686 uint32_t fl_pidx; 687 uint32_t fl_sidx; 688 uint32_t fl_db_val; 689 u_int fl_hwidx:4; 690 691 u_int nid; /* netmap ring # for this queue */ 692 693 /* infrequently used items after this */ 694 695 bus_dma_tag_t iq_desc_tag; 696 bus_dmamap_t iq_desc_map; 697 bus_addr_t iq_ba; 698 int intr_idx; 699 700 bus_dma_tag_t fl_desc_tag; 701 bus_dmamap_t fl_desc_map; 702 bus_addr_t fl_ba; 703} __aligned(CACHE_LINE_SIZE); 704 705struct sge_nm_txq { 706 struct tx_desc *desc; 707 uint16_t cidx; 708 uint16_t pidx; 709 uint16_t sidx; 710 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 711 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 712 uint16_t dbidx; /* pidx of the most recent doorbell */ 713 uint8_t doorbells; 714 volatile uint32_t *udb; 715 u_int udb_qid; 716 u_int cntxt_id; 717 __be32 cpl_ctrl0; /* for convenience */ 718 u_int nid; /* netmap ring # for this queue */ 719 720 /* infrequently used items after this */ 721 722 bus_dma_tag_t desc_tag; 723 bus_dmamap_t desc_map; 724 bus_addr_t ba; 725 int iqidx; 726} __aligned(CACHE_LINE_SIZE); 727 728struct sge { 729 int nrxq; /* total # of Ethernet rx queues */ 730 int ntxq; /* total # of Ethernet tx queues */ 731 int nofldrxq; /* total # of TOE rx queues */ 732 int nofldtxq; /* total # of TOE tx queues */ 733 int nnmrxq; /* total # of netmap rx queues */ 734 int nnmtxq; /* total # of netmap tx queues */ 735 int niq; /* total # of ingress queues */ 736 int neq; /* total # of egress queues */ 737 738 struct sge_iq fwq; /* Firmware event queue */ 739 struct sge_wrq *ctrlq; /* Control queues */ 740 struct sge_txq *txq; /* NIC tx queues */ 741 struct sge_rxq *rxq; /* NIC rx queues */ 742 struct sge_wrq *ofld_txq; /* TOE tx queues */ 743 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 744 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 745 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 746 747 uint16_t iq_start; /* first cntxt_id */ 748 uint16_t iq_base; /* first abs_id */ 749 int eq_start; /* first cntxt_id */ 750 int eq_base; /* first abs_id */ 751 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 752 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 753 754 int8_t safe_hwidx1; /* may not have room for metadata */ 755 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 756 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 757 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 758}; 759 760struct devnames { 761 const char *nexus_name; 762 const char *ifnet_name; 763 const char *vi_ifnet_name; 764 const char *pf03_drv_name; 765 const char *vf_nexus_name; 766 const char *vf_ifnet_name; 767}; 768 769struct adapter { 770 SLIST_ENTRY(adapter) link; 771 device_t dev; 772 struct cdev *cdev; 773 const struct devnames *names; 774 775 /* PCIe register resources */ 776 int regs_rid; 777 struct resource *regs_res; 778 int msix_rid; 779 struct resource *msix_res; 780 bus_space_handle_t bh; 781 bus_space_tag_t bt; 782 bus_size_t mmio_len; 783 int udbs_rid; 784 struct resource *udbs_res; 785 volatile uint8_t *udbs_base; 786 787 unsigned int pf; 788 unsigned int mbox; 789 unsigned int vpd_busy; 790 unsigned int vpd_flag; 791 792 /* Interrupt information */ 793 int intr_type; 794 int intr_count; 795 struct irq { 796 struct resource *res; 797 int rid; 798 void *tag; 799 struct sge_rxq *rxq; 800 struct sge_nm_rxq *nm_rxq; 801 } __aligned(CACHE_LINE_SIZE) *irq; 802 int sge_gts_reg; 803 int sge_kdoorbell_reg; 804 805 bus_dma_tag_t dmat; /* Parent DMA tag */ 806 807 struct sge sge; 808 int lro_timeout; 809 int sc_do_rxcopy; 810 811 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 812 struct port_info *port[MAX_NPORTS]; 813 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 814 815 void *tom_softc; /* (struct tom_data *) */ 816 struct tom_tunables tt; 817 struct t4_offload_policy *policy; 818 struct rwlock policy_lock; 819 820 void *iwarp_softc; /* (struct c4iw_dev *) */ 821 struct iw_tunables iwt; 822 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 823 void *ccr_softc; /* (struct ccr_softc *) */ 824 struct l2t_data *l2t; /* L2 table */ 825 struct smt_data *smt; /* Source MAC Table */ 826 struct tid_info tids; 827 vmem_t *key_map; 828 829 uint8_t doorbells; 830 int offload_map; /* ports with IFCAP_TOE enabled */ 831 int active_ulds; /* ULDs activated on this adapter */ 832 int flags; 833 int debug_flags; 834 835 char ifp_lockname[16]; 836 struct mtx ifp_lock; 837 struct ifnet *ifp; /* tracer ifp */ 838 struct ifmedia media; 839 int traceq; /* iq used by all tracers, -1 if none */ 840 int tracer_valid; /* bitmap of valid tracers */ 841 int tracer_enabled; /* bitmap of enabled tracers */ 842 843 char fw_version[16]; 844 char tp_version[16]; 845 char er_version[16]; 846 char bs_version[16]; 847 char cfg_file[32]; 848 u_int cfcsum; 849 struct adapter_params params; 850 const struct chip_params *chip_params; 851 struct t4_virt_res vres; 852 853 uint16_t nbmcaps; 854 uint16_t linkcaps; 855 uint16_t switchcaps; 856 uint16_t niccaps; 857 uint16_t toecaps; 858 uint16_t rdmacaps; 859 uint16_t cryptocaps; 860 uint16_t iscsicaps; 861 uint16_t fcoecaps; 862 863 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 864 865 struct mtx sc_lock; 866 char lockname[16]; 867 868 /* Starving free lists */ 869 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 870 TAILQ_HEAD(, sge_fl) sfl; 871 struct callout sfl_callout; 872 873 struct mtx reg_lock; /* for indirect register access */ 874 875 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 876 877 struct mtx tc_lock; 878 struct task tc_task; 879 880 const char *last_op; 881 const void *last_op_thr; 882 int last_op_flags; 883}; 884 885#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 886#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 887#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 888#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 889 890#define ASSERT_SYNCHRONIZED_OP(sc) \ 891 KASSERT(IS_BUSY(sc) && \ 892 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 893 ("%s: operation not synchronized.", __func__)) 894 895#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 896#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 897#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 898#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 899 900#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 901#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 902#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 903#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 904#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 905 906#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 907#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 908#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 909#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 910 911#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 912#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 913#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 914#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 915#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 916 917#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 918#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 919#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 920#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 921#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 922 923#define CH_DUMP_MBOX(sc, mbox, data_reg) \ 924 do { \ 925 if (sc->debug_flags & DF_DUMP_MBOX) { \ 926 log(LOG_NOTICE, \ 927 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 928 "%016llx %016llx %016llx %016llx\n", \ 929 device_get_nameunit(sc->dev), mbox, \ 930 (unsigned long long)t4_read_reg64(sc, data_reg), \ 931 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 932 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 933 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 934 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 935 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 936 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 937 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 938 } \ 939 } while (0) 940 941#define for_each_txq(vi, iter, q) \ 942 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 943 iter < vi->ntxq; ++iter, ++q) 944#define for_each_rxq(vi, iter, q) \ 945 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 946 iter < vi->nrxq; ++iter, ++q) 947#define for_each_ofld_txq(vi, iter, q) \ 948 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 949 iter < vi->nofldtxq; ++iter, ++q) 950#define for_each_ofld_rxq(vi, iter, q) \ 951 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 952 iter < vi->nofldrxq; ++iter, ++q) 953#define for_each_nm_txq(vi, iter, q) \ 954 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 955 iter < vi->nnmtxq; ++iter, ++q) 956#define for_each_nm_rxq(vi, iter, q) \ 957 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 958 iter < vi->nnmrxq; ++iter, ++q) 959#define for_each_vi(_pi, _iter, _vi) \ 960 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 961 ++(_iter), ++(_vi)) 962 963#define IDXINCR(idx, incr, wrap) do { \ 964 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 965} while (0) 966#define IDXDIFF(head, tail, wrap) \ 967 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 968 969/* One for errors, one for firmware events */ 970#define T4_EXTRA_INTR 2 971 972/* One for firmware events */ 973#define T4VF_EXTRA_INTR 1 974 975static inline int 976forwarding_intr_to_fwq(struct adapter *sc) 977{ 978 979 return (sc->intr_count == 1); 980} 981 982static inline uint32_t 983t4_read_reg(struct adapter *sc, uint32_t reg) 984{ 985 986 return bus_space_read_4(sc->bt, sc->bh, reg); 987} 988 989static inline void 990t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 991{ 992 993 bus_space_write_4(sc->bt, sc->bh, reg, val); 994} 995 996static inline uint64_t 997t4_read_reg64(struct adapter *sc, uint32_t reg) 998{ 999 1000#ifdef __LP64__ 1001 return bus_space_read_8(sc->bt, sc->bh, reg); 1002#else 1003 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1004 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1005 1006#endif 1007} 1008 1009static inline void 1010t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1011{ 1012 1013#ifdef __LP64__ 1014 bus_space_write_8(sc->bt, sc->bh, reg, val); 1015#else 1016 bus_space_write_4(sc->bt, sc->bh, reg, val); 1017 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1018#endif 1019} 1020 1021static inline void 1022t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1023{ 1024 1025 *val = pci_read_config(sc->dev, reg, 1); 1026} 1027 1028static inline void 1029t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1030{ 1031 1032 pci_write_config(sc->dev, reg, val, 1); 1033} 1034 1035static inline void 1036t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1037{ 1038 1039 *val = pci_read_config(sc->dev, reg, 2); 1040} 1041 1042static inline void 1043t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1044{ 1045 1046 pci_write_config(sc->dev, reg, val, 2); 1047} 1048 1049static inline void 1050t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1051{ 1052 1053 *val = pci_read_config(sc->dev, reg, 4); 1054} 1055 1056static inline void 1057t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1058{ 1059 1060 pci_write_config(sc->dev, reg, val, 4); 1061} 1062 1063static inline struct port_info * 1064adap2pinfo(struct adapter *sc, int idx) 1065{ 1066 1067 return (sc->port[idx]); 1068} 1069 1070static inline void 1071t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1072{ 1073 1074 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1075} 1076 1077static inline int 1078tx_resume_threshold(struct sge_eq *eq) 1079{ 1080 1081 /* not quite the same as qsize / 4, but this will do. */ 1082 return (eq->sidx / 4); 1083} 1084 1085static inline int 1086t4_use_ldst(struct adapter *sc) 1087{ 1088 1089#ifdef notyet 1090 return (sc->flags & FW_OK || !sc->use_bd); 1091#else 1092 return (0); 1093#endif 1094} 1095 1096/* t4_main.c */ 1097extern int t4_ntxq; 1098extern int t4_nrxq; 1099extern int t4_intr_types; 1100extern int t4_tmr_idx; 1101extern int t4_pktc_idx; 1102extern unsigned int t4_qsize_rxq; 1103extern unsigned int t4_qsize_txq; 1104extern device_method_t cxgbe_methods[]; 1105 1106int t4_os_find_pci_capability(struct adapter *, int); 1107int t4_os_pci_save_state(struct adapter *); 1108int t4_os_pci_restore_state(struct adapter *); 1109void t4_os_portmod_changed(struct port_info *); 1110void t4_os_link_changed(struct port_info *); 1111void t4_iterate(void (*)(struct adapter *, void *), void *); 1112void t4_init_devnames(struct adapter *); 1113void t4_add_adapter(struct adapter *); 1114void t4_aes_getdeckey(void *, const void *, unsigned int); 1115int t4_detach_common(device_t); 1116int t4_map_bars_0_and_4(struct adapter *); 1117int t4_map_bar_2(struct adapter *); 1118int t4_setup_intr_handlers(struct adapter *); 1119void t4_sysctls(struct adapter *); 1120int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1121void doom_vi(struct adapter *, struct vi_info *); 1122void end_synchronized_op(struct adapter *, int); 1123int update_mac_settings(struct ifnet *, int); 1124int adapter_full_init(struct adapter *); 1125int adapter_full_uninit(struct adapter *); 1126uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1127int vi_full_init(struct vi_info *); 1128int vi_full_uninit(struct vi_info *); 1129void vi_sysctls(struct vi_info *); 1130void vi_tick(void *); 1131int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1132int alloc_atid_tab(struct tid_info *, int); 1133void free_atid_tab(struct tid_info *); 1134int alloc_atid(struct adapter *, void *); 1135void *lookup_atid(struct adapter *, int); 1136void free_atid(struct adapter *, int); 1137void release_tid(struct adapter *, int, struct sge_wrq *); 1138 1139#ifdef DEV_NETMAP 1140/* t4_netmap.c */ 1141struct sge_nm_rxq; 1142void cxgbe_nm_attach(struct vi_info *); 1143void cxgbe_nm_detach(struct vi_info *); 1144void service_nm_rxq(struct sge_nm_rxq *); 1145#endif 1146 1147/* t4_sge.c */ 1148void t4_sge_modload(void); 1149void t4_sge_modunload(void); 1150uint64_t t4_sge_extfree_refs(void); 1151void t4_tweak_chip_settings(struct adapter *); 1152int t4_read_chip_settings(struct adapter *); 1153int t4_create_dma_tag(struct adapter *); 1154void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1155 struct sysctl_oid_list *); 1156int t4_destroy_dma_tag(struct adapter *); 1157int t4_setup_adapter_queues(struct adapter *); 1158int t4_teardown_adapter_queues(struct adapter *); 1159int t4_setup_vi_queues(struct vi_info *); 1160int t4_teardown_vi_queues(struct vi_info *); 1161void t4_intr_all(void *); 1162void t4_intr(void *); 1163#ifdef DEV_NETMAP 1164void t4_nm_intr(void *); 1165void t4_vi_intr(void *); 1166#endif 1167void t4_intr_err(void *); 1168void t4_intr_evt(void *); 1169void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1170void t4_update_fl_bufsize(struct ifnet *); 1171int parse_pkt(struct adapter *, struct mbuf **); 1172void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1173void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1174int tnl_cong(struct port_info *, int); 1175void t4_register_an_handler(an_handler_t); 1176void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1177void t4_register_cpl_handler(int, cpl_handler_t); 1178void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1179 1180/* t4_tracer.c */ 1181struct t4_tracer; 1182void t4_tracer_modload(void); 1183void t4_tracer_modunload(void); 1184void t4_tracer_port_detach(struct adapter *); 1185int t4_get_tracer(struct adapter *, struct t4_tracer *); 1186int t4_set_tracer(struct adapter *, struct t4_tracer *); 1187int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1188int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1189 1190/* t4_sched.c */ 1191int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1192int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1193int t4_init_tx_sched(struct adapter *); 1194int t4_free_tx_sched(struct adapter *); 1195void t4_update_tx_sched(struct adapter *); 1196int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1197void t4_release_cl_rl(struct adapter *, int, int); 1198int sysctl_tc(SYSCTL_HANDLER_ARGS); 1199int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1200 1201/* t4_filter.c */ 1202int get_filter_mode(struct adapter *, uint32_t *); 1203int set_filter_mode(struct adapter *, uint32_t); 1204int get_filter(struct adapter *, struct t4_filter *); 1205int set_filter(struct adapter *, struct t4_filter *); 1206int del_filter(struct adapter *, struct t4_filter *); 1207int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1208int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1209int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1210int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1211void free_hftid_tab(struct tid_info *); 1212 1213static inline struct wrqe * 1214alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1215{ 1216 int len = offsetof(struct wrqe, wr) + wr_len; 1217 struct wrqe *wr; 1218 1219 wr = malloc(len, M_CXGBE, M_NOWAIT); 1220 if (__predict_false(wr == NULL)) 1221 return (NULL); 1222 wr->wr_len = wr_len; 1223 wr->wrq = wrq; 1224 return (wr); 1225} 1226 1227static inline void * 1228wrtod(struct wrqe *wr) 1229{ 1230 return (&wr->wr[0]); 1231} 1232 1233static inline void 1234free_wrqe(struct wrqe *wr) 1235{ 1236 free(wr, M_CXGBE); 1237} 1238 1239static inline void 1240t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1241{ 1242 struct sge_wrq *wrq = wr->wrq; 1243 1244 TXQ_LOCK(wrq); 1245 t4_wrq_tx_locked(sc, wrq, wr); 1246 TXQ_UNLOCK(wrq); 1247} 1248 1249static inline int 1250read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1251 int len) 1252{ 1253 1254 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1255} 1256 1257static inline int 1258write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1259 const uint32_t *val, int len) 1260{ 1261 1262 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1263} 1264#endif 1265