adapter.h revision 261537
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/dev/cxgbe/adapter.h 261537 2014-02-06 03:30:12Z np $ 28 * 29 */ 30 31#ifndef __T4_ADAPTER_H__ 32#define __T4_ADAPTER_H__ 33 34#include <sys/kernel.h> 35#include <sys/bus.h> 36#include <sys/rman.h> 37#include <sys/types.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/rwlock.h> 41#include <sys/sx.h> 42#include <vm/uma.h> 43 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcireg.h> 46#include <machine/bus.h> 47#include <sys/socket.h> 48#include <sys/sysctl.h> 49#include <net/ethernet.h> 50#include <net/if.h> 51#include <net/if_var.h> 52#include <net/if_media.h> 53#include <netinet/in.h> 54#include <netinet/tcp_lro.h> 55 56#include "offload.h" 57#include "firmware/t4fw_interface.h" 58 59MALLOC_DECLARE(M_CXGBE); 60#define CXGBE_UNIMPLEMENTED(s) \ 61 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 62 63#if defined(__i386__) || defined(__amd64__) 64static __inline void 65prefetch(void *x) 66{ 67 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 68} 69#else 70#define prefetch(x) 71#endif 72 73#ifndef SYSCTL_ADD_UQUAD 74#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 75#define sysctl_handle_64 sysctl_handle_quad 76#define CTLTYPE_U64 CTLTYPE_QUAD 77#endif 78 79#if (__FreeBSD_version >= 900030) || \ 80 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 81#define SBUF_DRAIN 1 82#endif 83 84#ifdef __amd64__ 85/* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 86static __inline uint64_t 87t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 88 bus_size_t offset) 89{ 90 KASSERT(tag == X86_BUS_SPACE_MEM, 91 ("%s: can only handle mem space", __func__)); 92 93 return (*(volatile uint64_t *)(handle + offset)); 94} 95 96static __inline void 97t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 98 bus_size_t offset, uint64_t value) 99{ 100 KASSERT(tag == X86_BUS_SPACE_MEM, 101 ("%s: can only handle mem space", __func__)); 102 103 *(volatile uint64_t *)(bsh + offset) = value; 104} 105#else 106static __inline uint64_t 107t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 108 bus_size_t offset) 109{ 110 return (uint64_t)bus_space_read_4(tag, handle, offset) + 111 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 112} 113 114static __inline void 115t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 116 bus_size_t offset, uint64_t value) 117{ 118 bus_space_write_4(tag, bsh, offset, value); 119 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 120} 121#endif 122 123struct adapter; 124typedef struct adapter adapter_t; 125 126enum { 127 FW_IQ_QSIZE = 256, 128 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 129 130 RX_IQ_QSIZE = 1024, 131 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 132 133 EQ_ESIZE = 64, /* All egress queues use this entry size */ 134 135 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */ 136#if MJUMPAGESIZE != MCLBYTES 137 FL_BUF_SIZES_MAX = 5, /* cluster, jumbop, jumbo9k, jumbo16k, extra */ 138#else 139 FL_BUF_SIZES_MAX = 4, /* cluster, jumbo9k, jumbo16k, extra */ 140#endif 141 142 CTRL_EQ_QSIZE = 128, 143 144 TX_EQ_QSIZE = 1024, 145 TX_SGL_SEGS = 36, 146 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 147}; 148 149enum { 150 /* adapter intr_type */ 151 INTR_INTX = (1 << 0), 152 INTR_MSI = (1 << 1), 153 INTR_MSIX = (1 << 2) 154}; 155 156enum { 157 /* flags understood by begin_synchronized_op */ 158 HOLD_LOCK = (1 << 0), 159 SLEEP_OK = (1 << 1), 160 INTR_OK = (1 << 2), 161 162 /* flags understood by end_synchronized_op */ 163 LOCK_HELD = HOLD_LOCK, 164}; 165 166enum { 167 /* adapter flags */ 168 FULL_INIT_DONE = (1 << 0), 169 FW_OK = (1 << 1), 170 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */ 171 MASTER_PF = (1 << 3), 172 ADAP_SYSCTL_CTX = (1 << 4), 173 TOM_INIT_DONE = (1 << 5), 174 BUF_PACKING_OK = (1 << 6), 175 176 CXGBE_BUSY = (1 << 9), 177 178 /* port flags */ 179 DOOMED = (1 << 0), 180 PORT_INIT_DONE = (1 << 1), 181 PORT_SYSCTL_CTX = (1 << 2), 182 HAS_TRACEQ = (1 << 3), 183}; 184 185#define IS_DOOMED(pi) ((pi)->flags & DOOMED) 186#define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0) 187#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 188#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 189#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 190 191struct port_info { 192 device_t dev; 193 struct adapter *adapter; 194 195 struct ifnet *ifp; 196 struct ifmedia media; 197 198 struct mtx pi_lock; 199 char lockname[16]; 200 unsigned long flags; 201 int if_flags; 202 203 uint16_t *rss; 204 uint16_t viid; 205 int16_t xact_addr_filt;/* index of exact MAC address filter */ 206 uint16_t rss_size; /* size of VI's RSS table slice */ 207 uint8_t lport; /* associated offload logical port */ 208 int8_t mdio_addr; 209 uint8_t port_type; 210 uint8_t mod_type; 211 uint8_t port_id; 212 uint8_t tx_chan; 213 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 214 215 /* These need to be int as they are used in sysctl */ 216 int ntxq; /* # of tx queues */ 217 int first_txq; /* index of first tx queue */ 218 int nrxq; /* # of rx queues */ 219 int first_rxq; /* index of first rx queue */ 220#ifdef TCP_OFFLOAD 221 int nofldtxq; /* # of offload tx queues */ 222 int first_ofld_txq; /* index of first offload tx queue */ 223 int nofldrxq; /* # of offload rx queues */ 224 int first_ofld_rxq; /* index of first offload rx queue */ 225#endif 226 int tmr_idx; 227 int pktc_idx; 228 int qsize_rxq; 229 int qsize_txq; 230 231 int linkdnrc; 232 struct link_config link_cfg; 233 struct port_stats stats; 234 235 eventhandler_tag vlan_c; 236 237 struct callout tick; 238 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 239 240 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 241}; 242 243struct fl_sdesc { 244 bus_dmamap_t map; 245 caddr_t cl; 246 uint8_t tag_idx; /* the fl->tag entry this map comes from */ 247#ifdef INVARIANTS 248 __be64 ba_hwtag; 249#endif 250}; 251 252struct tx_desc { 253 __be64 flit[8]; 254}; 255 256struct tx_map { 257 struct mbuf *m; 258 bus_dmamap_t map; 259}; 260 261/* DMA maps used for tx */ 262struct tx_maps { 263 struct tx_map *maps; 264 uint32_t map_total; /* # of DMA maps */ 265 uint32_t map_pidx; /* next map to be used */ 266 uint32_t map_cidx; /* reclaimed up to this index */ 267 uint32_t map_avail; /* # of available maps */ 268}; 269 270struct tx_sdesc { 271 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 272 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 273}; 274 275enum { 276 /* iq flags */ 277 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 278 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 279 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 280 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 281 282 /* iq state */ 283 IQS_DISABLED = 0, 284 IQS_BUSY = 1, 285 IQS_IDLE = 2, 286}; 287 288/* 289 * Ingress Queue: T4 is producer, driver is consumer. 290 */ 291struct sge_iq { 292 bus_dma_tag_t desc_tag; 293 bus_dmamap_t desc_map; 294 bus_addr_t ba; /* bus address of descriptor ring */ 295 uint32_t flags; 296 uint16_t abs_id; /* absolute SGE id for the iq */ 297 int8_t intr_pktc_idx; /* packet count threshold index */ 298 int8_t pad0; 299 __be64 *desc; /* KVA of descriptor ring */ 300 301 volatile int state; 302 struct adapter *adapter; 303 const __be64 *cdesc; /* current descriptor */ 304 uint8_t gen; /* generation bit */ 305 uint8_t intr_params; /* interrupt holdoff parameters */ 306 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 307 uint8_t esize; /* size (bytes) of each entry in the queue */ 308 uint16_t qsize; /* size (# of entries) of the queue */ 309 uint16_t cidx; /* consumer index */ 310 uint16_t cntxt_id; /* SGE context id for the iq */ 311 312 STAILQ_ENTRY(sge_iq) link; 313}; 314 315enum { 316 EQ_CTRL = 1, 317 EQ_ETH = 2, 318#ifdef TCP_OFFLOAD 319 EQ_OFLD = 3, 320#endif 321 322 /* eq flags */ 323 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 324 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 325 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 326 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 327 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 328}; 329 330/* Listed in order of preference. Update t4_sysctls too if you change these */ 331enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 332 333/* 334 * Egress Queue: driver is producer, T4 is consumer. 335 * 336 * Note: A free list is an egress queue (driver produces the buffers and T4 337 * consumes them) but it's special enough to have its own struct (see sge_fl). 338 */ 339struct sge_eq { 340 unsigned int flags; /* MUST be first */ 341 unsigned int cntxt_id; /* SGE context id for the eq */ 342 bus_dma_tag_t desc_tag; 343 bus_dmamap_t desc_map; 344 char lockname[16]; 345 struct mtx eq_lock; 346 347 struct tx_desc *desc; /* KVA of descriptor ring */ 348 bus_addr_t ba; /* bus address of descriptor ring */ 349 struct sge_qstat *spg; /* status page, for convenience */ 350 int doorbells; 351 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 352 u_int udb_qid; /* relative qid within the doorbell page */ 353 uint16_t cap; /* max # of desc, for convenience */ 354 uint16_t avail; /* available descriptors, for convenience */ 355 uint16_t qsize; /* size (# of entries) of the queue */ 356 uint16_t cidx; /* consumer idx (desc idx) */ 357 uint16_t pidx; /* producer idx (desc idx) */ 358 uint16_t pending; /* # of descriptors used since last doorbell */ 359 uint16_t iqid; /* iq that gets egr_update for the eq */ 360 uint8_t tx_chan; /* tx channel used by the eq */ 361 struct task tx_task; 362 struct callout tx_callout; 363 364 /* stats */ 365 366 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 367 uint32_t unstalled; /* recovered from stall */ 368}; 369 370struct fl_buf_info { 371 u_int size; 372 int type; 373 int hwtag:4; /* tag in low 4 bits of the pa. */ 374 uma_zone_t zone; 375}; 376#define FL_BUF_SIZES(sc) (sc->sge.fl_buf_sizes) 377#define FL_BUF_SIZE(sc, x) (sc->sge.fl_buf_info[x].size) 378#define FL_BUF_TYPE(sc, x) (sc->sge.fl_buf_info[x].type) 379#define FL_BUF_HWTAG(sc, x) (sc->sge.fl_buf_info[x].hwtag) 380#define FL_BUF_ZONE(sc, x) (sc->sge.fl_buf_info[x].zone) 381 382enum { 383 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 384 FL_DOOMED = (1 << 1), /* about to be destroyed */ 385 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 386}; 387 388#define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 389#define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 390 391struct sge_fl { 392 bus_dma_tag_t desc_tag; 393 bus_dmamap_t desc_map; 394 bus_dma_tag_t tag[FL_BUF_SIZES_MAX]; /* only first FL_BUF_SIZES(sc) are 395 valid */ 396 uint8_t tag_idx; 397 struct mtx fl_lock; 398 char lockname[16]; 399 int flags; 400 401 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 402 bus_addr_t ba; /* bus address of descriptor ring */ 403 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 404 uint32_t cap; /* max # of buffers, for convenience */ 405 uint16_t qsize; /* size (# of entries) of the queue */ 406 uint16_t cntxt_id; /* SGE context id for the freelist */ 407 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 408 uint32_t rx_offset; /* offset in fl buf (when buffer packing) */ 409 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 410 uint32_t needed; /* # of buffers needed to fill up fl. */ 411 uint32_t lowat; /* # of buffers <= this means fl needs help */ 412 uint32_t pending; /* # of bufs allocated since last doorbell */ 413 u_int dmamap_failed; 414 struct mbuf *mstash[8]; 415 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 416}; 417 418/* txq: SGE egress queue + what's needed for Ethernet NIC */ 419struct sge_txq { 420 struct sge_eq eq; /* MUST be first */ 421 422 struct ifnet *ifp; /* the interface this txq belongs to */ 423 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 424 struct buf_ring *br; /* tx buffer ring */ 425 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 426 struct mbuf *m; /* held up due to temporary resource shortage */ 427 428 struct tx_maps txmaps; 429 430 /* stats for common events first */ 431 432 uint64_t txcsum; /* # of times hardware assisted with checksum */ 433 uint64_t tso_wrs; /* # of TSO work requests */ 434 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 435 uint64_t imm_wrs; /* # of work requests with immediate data */ 436 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 437 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 438 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 439 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 440 441 /* stats for not-that-common events */ 442 443 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 444 uint32_t no_desc; /* out of hardware descriptors */ 445} __aligned(CACHE_LINE_SIZE); 446 447/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 448struct sge_rxq { 449 struct sge_iq iq; /* MUST be first */ 450 struct sge_fl fl; /* MUST follow iq */ 451 452 struct ifnet *ifp; /* the interface this rxq belongs to */ 453#if defined(INET) || defined(INET6) 454 struct lro_ctrl lro; /* LRO state */ 455#endif 456 457 /* stats for common events first */ 458 459 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 460 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 461 462 /* stats for not-that-common events */ 463 464} __aligned(CACHE_LINE_SIZE); 465 466static inline struct sge_rxq * 467iq_to_rxq(struct sge_iq *iq) 468{ 469 470 return (__containerof(iq, struct sge_rxq, iq)); 471} 472 473 474#ifdef TCP_OFFLOAD 475/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 476struct sge_ofld_rxq { 477 struct sge_iq iq; /* MUST be first */ 478 struct sge_fl fl; /* MUST follow iq */ 479} __aligned(CACHE_LINE_SIZE); 480 481static inline struct sge_ofld_rxq * 482iq_to_ofld_rxq(struct sge_iq *iq) 483{ 484 485 return (__containerof(iq, struct sge_ofld_rxq, iq)); 486} 487#endif 488 489struct wrqe { 490 STAILQ_ENTRY(wrqe) link; 491 struct sge_wrq *wrq; 492 int wr_len; 493 uint64_t wr[] __aligned(16); 494}; 495 496/* 497 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 498 * and offload tx queues are of this type. 499 */ 500struct sge_wrq { 501 struct sge_eq eq; /* MUST be first */ 502 503 struct adapter *adapter; 504 505 /* List of WRs held up due to lack of tx descriptors */ 506 STAILQ_HEAD(, wrqe) wr_list; 507 508 /* stats for common events first */ 509 510 uint64_t tx_wrs; /* # of tx work requests */ 511 512 /* stats for not-that-common events */ 513 514 uint32_t no_desc; /* out of hardware descriptors */ 515} __aligned(CACHE_LINE_SIZE); 516 517struct sge { 518 int timer_val[SGE_NTIMERS]; 519 int counter_val[SGE_NCOUNTERS]; 520 int fl_starve_threshold; 521 int fl_starve_threshold2; 522 int eq_s_qpp; 523 int iq_s_qpp; 524 525 int nrxq; /* total # of Ethernet rx queues */ 526 int ntxq; /* total # of Ethernet tx tx queues */ 527#ifdef TCP_OFFLOAD 528 int nofldrxq; /* total # of TOE rx queues */ 529 int nofldtxq; /* total # of TOE tx queues */ 530#endif 531 int niq; /* total # of ingress queues */ 532 int neq; /* total # of egress queues */ 533 534 struct sge_iq fwq; /* Firmware event queue */ 535 struct sge_wrq mgmtq; /* Management queue (control queue) */ 536 struct sge_wrq *ctrlq; /* Control queues */ 537 struct sge_txq *txq; /* NIC tx queues */ 538 struct sge_rxq *rxq; /* NIC rx queues */ 539#ifdef TCP_OFFLOAD 540 struct sge_wrq *ofld_txq; /* TOE tx queues */ 541 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 542#endif 543 544 uint16_t iq_start; 545 int eq_start; 546 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 547 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 548 549 u_int fl_buf_sizes __aligned(CACHE_LINE_SIZE); 550 struct fl_buf_info fl_buf_info[FL_BUF_SIZES_MAX]; 551}; 552 553struct rss_header; 554typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 555 struct mbuf *); 556typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 557typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 558 559struct adapter { 560 SLIST_ENTRY(adapter) link; 561 device_t dev; 562 struct cdev *cdev; 563 564 /* PCIe register resources */ 565 int regs_rid; 566 struct resource *regs_res; 567 int msix_rid; 568 struct resource *msix_res; 569 bus_space_handle_t bh; 570 bus_space_tag_t bt; 571 bus_size_t mmio_len; 572 int udbs_rid; 573 struct resource *udbs_res; 574 volatile uint8_t *udbs_base; 575 576 unsigned int pf; 577 unsigned int mbox; 578 579 /* Interrupt information */ 580 int intr_type; 581 int intr_count; 582 struct irq { 583 struct resource *res; 584 int rid; 585 void *tag; 586 } *irq; 587 588 bus_dma_tag_t dmat; /* Parent DMA tag */ 589 590 struct sge sge; 591 int lro_timeout; 592 593 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 594 struct port_info *port[MAX_NPORTS]; 595 uint8_t chan_map[NCHAN]; 596 597#ifdef TCP_OFFLOAD 598 void *tom_softc; /* (struct tom_data *) */ 599 struct tom_tunables tt; 600 void *iwarp_softc; /* (struct c4iw_dev *) */ 601#endif 602 struct l2t_data *l2t; /* L2 table */ 603 struct tid_info tids; 604 605 int doorbells; 606 int open_device_map; 607#ifdef TCP_OFFLOAD 608 int offload_map; 609#endif 610 int flags; 611 612 char ifp_lockname[16]; 613 struct mtx ifp_lock; 614 struct ifnet *ifp; /* tracer ifp */ 615 struct ifmedia media; 616 int traceq; /* iq used by all tracers, -1 if none */ 617 int tracer_valid; /* bitmap of valid tracers */ 618 int tracer_enabled; /* bitmap of enabled tracers */ 619 620 char fw_version[32]; 621 char cfg_file[32]; 622 u_int cfcsum; 623 struct adapter_params params; 624 struct t4_virt_res vres; 625 626 uint16_t linkcaps; 627 uint16_t niccaps; 628 uint16_t toecaps; 629 uint16_t rdmacaps; 630 uint16_t iscsicaps; 631 uint16_t fcoecaps; 632 633 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 634 635 struct mtx sc_lock; 636 char lockname[16]; 637 638 /* Starving free lists */ 639 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 640 TAILQ_HEAD(, sge_fl) sfl; 641 struct callout sfl_callout; 642 643 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 644 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 645 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 646 647#ifdef INVARIANTS 648 const char *last_op; 649 const void *last_op_thr; 650#endif 651 652 int sc_do_rxcopy; 653}; 654 655#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 656#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 657#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 658#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 659 660/* XXX: not bulletproof, but much better than nothing */ 661#define ASSERT_SYNCHRONIZED_OP(sc) \ 662 KASSERT(IS_BUSY(sc) && \ 663 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 664 ("%s: operation not synchronized.", __func__)) 665 666#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 667#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 668#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 669#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 670 671#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 672#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 673#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 674#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 675#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 676 677#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 678#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 679#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 680#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 681 682#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 683#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 684#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 685#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 686#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 687 688#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 689#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 690#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 691#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 692#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 693 694#define for_each_txq(pi, iter, q) \ 695 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \ 696 iter < pi->ntxq; ++iter, ++q) 697#define for_each_rxq(pi, iter, q) \ 698 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \ 699 iter < pi->nrxq; ++iter, ++q) 700#define for_each_ofld_txq(pi, iter, q) \ 701 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \ 702 iter < pi->nofldtxq; ++iter, ++q) 703#define for_each_ofld_rxq(pi, iter, q) \ 704 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \ 705 iter < pi->nofldrxq; ++iter, ++q) 706 707/* One for errors, one for firmware events */ 708#define T4_EXTRA_INTR 2 709 710static inline uint32_t 711t4_read_reg(struct adapter *sc, uint32_t reg) 712{ 713 714 return bus_space_read_4(sc->bt, sc->bh, reg); 715} 716 717static inline void 718t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 719{ 720 721 bus_space_write_4(sc->bt, sc->bh, reg, val); 722} 723 724static inline uint64_t 725t4_read_reg64(struct adapter *sc, uint32_t reg) 726{ 727 728 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 729} 730 731static inline void 732t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 733{ 734 735 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 736} 737 738static inline void 739t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 740{ 741 742 *val = pci_read_config(sc->dev, reg, 1); 743} 744 745static inline void 746t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 747{ 748 749 pci_write_config(sc->dev, reg, val, 1); 750} 751 752static inline void 753t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 754{ 755 756 *val = pci_read_config(sc->dev, reg, 2); 757} 758 759static inline void 760t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 761{ 762 763 pci_write_config(sc->dev, reg, val, 2); 764} 765 766static inline void 767t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 768{ 769 770 *val = pci_read_config(sc->dev, reg, 4); 771} 772 773static inline void 774t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 775{ 776 777 pci_write_config(sc->dev, reg, val, 4); 778} 779 780static inline struct port_info * 781adap2pinfo(struct adapter *sc, int idx) 782{ 783 784 return (sc->port[idx]); 785} 786 787static inline void 788t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 789{ 790 791 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 792} 793 794static inline bool 795is_10G_port(const struct port_info *pi) 796{ 797 798 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 799} 800 801static inline bool 802is_40G_port(const struct port_info *pi) 803{ 804 805 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 806} 807 808static inline int 809tx_resume_threshold(struct sge_eq *eq) 810{ 811 812 return (eq->qsize / 4); 813} 814 815/* t4_main.c */ 816void t4_tx_task(void *, int); 817void t4_tx_callout(void *); 818int t4_os_find_pci_capability(struct adapter *, int); 819int t4_os_pci_save_state(struct adapter *); 820int t4_os_pci_restore_state(struct adapter *); 821void t4_os_portmod_changed(const struct adapter *, int); 822void t4_os_link_changed(struct adapter *, int, int, int); 823void t4_iterate(void (*)(struct adapter *, void *), void *); 824int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 825int t4_register_an_handler(struct adapter *, an_handler_t); 826int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 827int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 828int begin_synchronized_op(struct adapter *, struct port_info *, int, char *); 829void end_synchronized_op(struct adapter *, int); 830 831/* t4_sge.c */ 832void t4_sge_modload(void); 833void t4_init_sge_cpl_handlers(struct adapter *); 834void t4_tweak_chip_settings(struct adapter *); 835int t4_read_chip_settings(struct adapter *); 836int t4_create_dma_tag(struct adapter *); 837void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 838 struct sysctl_oid_list *); 839int t4_destroy_dma_tag(struct adapter *); 840int t4_setup_adapter_queues(struct adapter *); 841int t4_teardown_adapter_queues(struct adapter *); 842int t4_setup_port_queues(struct port_info *); 843int t4_teardown_port_queues(struct port_info *); 844int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 845void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 846void t4_intr_all(void *); 847void t4_intr(void *); 848void t4_intr_err(void *); 849void t4_intr_evt(void *); 850void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 851int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 852void t4_update_fl_bufsize(struct ifnet *); 853int can_resume_tx(struct sge_eq *); 854 855/* t4_tracer.c */ 856struct t4_tracer; 857void t4_tracer_modload(void); 858void t4_tracer_modunload(void); 859void t4_tracer_port_detach(struct adapter *); 860int t4_get_tracer(struct adapter *, struct t4_tracer *); 861int t4_set_tracer(struct adapter *, struct t4_tracer *); 862int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 863int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 864 865static inline struct wrqe * 866alloc_wrqe(int wr_len, struct sge_wrq *wrq) 867{ 868 int len = offsetof(struct wrqe, wr) + wr_len; 869 struct wrqe *wr; 870 871 wr = malloc(len, M_CXGBE, M_NOWAIT); 872 if (__predict_false(wr == NULL)) 873 return (NULL); 874 wr->wr_len = wr_len; 875 wr->wrq = wrq; 876 return (wr); 877} 878 879static inline void * 880wrtod(struct wrqe *wr) 881{ 882 return (&wr->wr[0]); 883} 884 885static inline void 886free_wrqe(struct wrqe *wr) 887{ 888 free(wr, M_CXGBE); 889} 890 891static inline void 892t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 893{ 894 struct sge_wrq *wrq = wr->wrq; 895 896 TXQ_LOCK(wrq); 897 t4_wrq_tx_locked(sc, wrq, wr); 898 TXQ_UNLOCK(wrq); 899} 900 901#endif 902