adapter.h revision 255050
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/dev/cxgbe/adapter.h 255050 2013-08-30 01:45:36Z np $ 28 * 29 */ 30 31#ifndef __T4_ADAPTER_H__ 32#define __T4_ADAPTER_H__ 33 34#include <sys/kernel.h> 35#include <sys/bus.h> 36#include <sys/rman.h> 37#include <sys/types.h> 38#include <sys/malloc.h> 39#include <dev/pci/pcivar.h> 40#include <dev/pci/pcireg.h> 41#include <machine/bus.h> 42#include <sys/socket.h> 43#include <sys/sysctl.h> 44#include <net/ethernet.h> 45#include <net/if.h> 46#include <net/if_media.h> 47#include <netinet/in.h> 48#include <netinet/tcp_lro.h> 49 50#include "offload.h" 51#include "firmware/t4fw_interface.h" 52 53MALLOC_DECLARE(M_CXGBE); 54#define CXGBE_UNIMPLEMENTED(s) \ 55 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 56 57#if defined(__i386__) || defined(__amd64__) 58static __inline void 59prefetch(void *x) 60{ 61 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 62} 63#else 64#define prefetch(x) 65#endif 66 67#ifndef SYSCTL_ADD_UQUAD 68#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 69#define sysctl_handle_64 sysctl_handle_quad 70#define CTLTYPE_U64 CTLTYPE_QUAD 71#endif 72 73#if (__FreeBSD_version >= 900030) || \ 74 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 75#define SBUF_DRAIN 1 76#endif 77 78#ifdef __amd64__ 79/* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 80static __inline uint64_t 81t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 82 bus_size_t offset) 83{ 84 KASSERT(tag == X86_BUS_SPACE_MEM, 85 ("%s: can only handle mem space", __func__)); 86 87 return (*(volatile uint64_t *)(handle + offset)); 88} 89 90static __inline void 91t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 92 bus_size_t offset, uint64_t value) 93{ 94 KASSERT(tag == X86_BUS_SPACE_MEM, 95 ("%s: can only handle mem space", __func__)); 96 97 *(volatile uint64_t *)(bsh + offset) = value; 98} 99#else 100static __inline uint64_t 101t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 102 bus_size_t offset) 103{ 104 return (uint64_t)bus_space_read_4(tag, handle, offset) + 105 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 106} 107 108static __inline void 109t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 110 bus_size_t offset, uint64_t value) 111{ 112 bus_space_write_4(tag, bsh, offset, value); 113 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 114} 115#endif 116 117struct adapter; 118typedef struct adapter adapter_t; 119 120enum { 121 FW_IQ_QSIZE = 256, 122 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */ 123 124 RX_IQ_QSIZE = 1024, 125 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */ 126 127 EQ_ESIZE = 64, /* All egress queues use this entry size */ 128 129 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */ 130#if MJUMPAGESIZE != MCLBYTES 131 FL_BUF_SIZES_MAX = 5, /* cluster, jumbop, jumbo9k, jumbo16k, extra */ 132#else 133 FL_BUF_SIZES_MAX = 4, /* cluster, jumbo9k, jumbo16k, extra */ 134#endif 135 136 CTRL_EQ_QSIZE = 128, 137 138 TX_EQ_QSIZE = 1024, 139 TX_SGL_SEGS = 36, 140 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 141}; 142 143enum { 144 /* adapter intr_type */ 145 INTR_INTX = (1 << 0), 146 INTR_MSI = (1 << 1), 147 INTR_MSIX = (1 << 2) 148}; 149 150enum { 151 /* flags understood by begin_synchronized_op */ 152 HOLD_LOCK = (1 << 0), 153 SLEEP_OK = (1 << 1), 154 INTR_OK = (1 << 2), 155 156 /* flags understood by end_synchronized_op */ 157 LOCK_HELD = HOLD_LOCK, 158}; 159 160enum { 161 /* adapter flags */ 162 FULL_INIT_DONE = (1 << 0), 163 FW_OK = (1 << 1), 164 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */ 165 MASTER_PF = (1 << 3), 166 ADAP_SYSCTL_CTX = (1 << 4), 167 TOM_INIT_DONE = (1 << 5), 168 BUF_PACKING_OK = (1 << 6), 169 170 CXGBE_BUSY = (1 << 9), 171 172 /* port flags */ 173 DOOMED = (1 << 0), 174 PORT_INIT_DONE = (1 << 1), 175 PORT_SYSCTL_CTX = (1 << 2), 176 HAS_TRACEQ = (1 << 3), 177}; 178 179#define IS_DOOMED(pi) ((pi)->flags & DOOMED) 180#define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0) 181#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 182#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 183#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 184 185struct port_info { 186 device_t dev; 187 struct adapter *adapter; 188 189 struct ifnet *ifp; 190 struct ifmedia media; 191 192 struct mtx pi_lock; 193 char lockname[16]; 194 unsigned long flags; 195 int if_flags; 196 197 uint16_t viid; 198 int16_t xact_addr_filt;/* index of exact MAC address filter */ 199 uint16_t rss_size; /* size of VI's RSS table slice */ 200 uint8_t lport; /* associated offload logical port */ 201 int8_t mdio_addr; 202 uint8_t port_type; 203 uint8_t mod_type; 204 uint8_t port_id; 205 uint8_t tx_chan; 206 207 /* These need to be int as they are used in sysctl */ 208 int ntxq; /* # of tx queues */ 209 int first_txq; /* index of first tx queue */ 210 int nrxq; /* # of rx queues */ 211 int first_rxq; /* index of first rx queue */ 212#ifdef TCP_OFFLOAD 213 int nofldtxq; /* # of offload tx queues */ 214 int first_ofld_txq; /* index of first offload tx queue */ 215 int nofldrxq; /* # of offload rx queues */ 216 int first_ofld_rxq; /* index of first offload rx queue */ 217#endif 218 int tmr_idx; 219 int pktc_idx; 220 int qsize_rxq; 221 int qsize_txq; 222 223 int linkdnrc; 224 struct link_config link_cfg; 225 struct port_stats stats; 226 227 eventhandler_tag vlan_c; 228 229 struct callout tick; 230 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 231 232 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 233}; 234 235struct fl_sdesc { 236 bus_dmamap_t map; 237 caddr_t cl; 238 uint8_t tag_idx; /* the fl->tag entry this map comes from */ 239#ifdef INVARIANTS 240 __be64 ba_hwtag; 241#endif 242}; 243 244struct tx_desc { 245 __be64 flit[8]; 246}; 247 248struct tx_map { 249 struct mbuf *m; 250 bus_dmamap_t map; 251}; 252 253/* DMA maps used for tx */ 254struct tx_maps { 255 struct tx_map *maps; 256 uint32_t map_total; /* # of DMA maps */ 257 uint32_t map_pidx; /* next map to be used */ 258 uint32_t map_cidx; /* reclaimed up to this index */ 259 uint32_t map_avail; /* # of available maps */ 260}; 261 262struct tx_sdesc { 263 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 264 uint8_t credits; /* NIC txq: # of frames sent out in the WR */ 265}; 266 267enum { 268 /* iq flags */ 269 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 270 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 271 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 272 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 273 274 /* iq state */ 275 IQS_DISABLED = 0, 276 IQS_BUSY = 1, 277 IQS_IDLE = 2, 278}; 279 280/* 281 * Ingress Queue: T4 is producer, driver is consumer. 282 */ 283struct sge_iq { 284 bus_dma_tag_t desc_tag; 285 bus_dmamap_t desc_map; 286 bus_addr_t ba; /* bus address of descriptor ring */ 287 uint32_t flags; 288 uint16_t abs_id; /* absolute SGE id for the iq */ 289 int8_t intr_pktc_idx; /* packet count threshold index */ 290 int8_t pad0; 291 __be64 *desc; /* KVA of descriptor ring */ 292 293 volatile int state; 294 struct adapter *adapter; 295 const __be64 *cdesc; /* current descriptor */ 296 uint8_t gen; /* generation bit */ 297 uint8_t intr_params; /* interrupt holdoff parameters */ 298 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 299 uint8_t esize; /* size (bytes) of each entry in the queue */ 300 uint16_t qsize; /* size (# of entries) of the queue */ 301 uint16_t cidx; /* consumer index */ 302 uint16_t cntxt_id; /* SGE context id for the iq */ 303 304 STAILQ_ENTRY(sge_iq) link; 305}; 306 307enum { 308 EQ_CTRL = 1, 309 EQ_ETH = 2, 310#ifdef TCP_OFFLOAD 311 EQ_OFLD = 3, 312#endif 313 314 /* eq flags */ 315 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */ 316 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */ 317 EQ_DOOMED = (1 << 4), /* about to be destroyed */ 318 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */ 319 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */ 320}; 321 322/* Listed in order of preference. Update t4_sysctls too if you change these */ 323enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 324 325/* 326 * Egress Queue: driver is producer, T4 is consumer. 327 * 328 * Note: A free list is an egress queue (driver produces the buffers and T4 329 * consumes them) but it's special enough to have its own struct (see sge_fl). 330 */ 331struct sge_eq { 332 unsigned int flags; /* MUST be first */ 333 unsigned int cntxt_id; /* SGE context id for the eq */ 334 bus_dma_tag_t desc_tag; 335 bus_dmamap_t desc_map; 336 char lockname[16]; 337 struct mtx eq_lock; 338 339 struct tx_desc *desc; /* KVA of descriptor ring */ 340 bus_addr_t ba; /* bus address of descriptor ring */ 341 struct sge_qstat *spg; /* status page, for convenience */ 342 int doorbells; 343 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 344 u_int udb_qid; /* relative qid within the doorbell page */ 345 uint16_t cap; /* max # of desc, for convenience */ 346 uint16_t avail; /* available descriptors, for convenience */ 347 uint16_t qsize; /* size (# of entries) of the queue */ 348 uint16_t cidx; /* consumer idx (desc idx) */ 349 uint16_t pidx; /* producer idx (desc idx) */ 350 uint16_t pending; /* # of descriptors used since last doorbell */ 351 uint16_t iqid; /* iq that gets egr_update for the eq */ 352 uint8_t tx_chan; /* tx channel used by the eq */ 353 struct task tx_task; 354 struct callout tx_callout; 355 356 /* stats */ 357 358 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */ 359 uint32_t unstalled; /* recovered from stall */ 360}; 361 362struct fl_buf_info { 363 u_int size; 364 int type; 365 int hwtag:4; /* tag in low 4 bits of the pa. */ 366 uma_zone_t zone; 367}; 368#define FL_BUF_SIZES(sc) (sc->sge.fl_buf_sizes) 369#define FL_BUF_SIZE(sc, x) (sc->sge.fl_buf_info[x].size) 370#define FL_BUF_TYPE(sc, x) (sc->sge.fl_buf_info[x].type) 371#define FL_BUF_HWTAG(sc, x) (sc->sge.fl_buf_info[x].hwtag) 372#define FL_BUF_ZONE(sc, x) (sc->sge.fl_buf_info[x].zone) 373 374enum { 375 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 376 FL_DOOMED = (1 << 1), /* about to be destroyed */ 377 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 378}; 379 380#define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat) 381#define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat) 382 383struct sge_fl { 384 bus_dma_tag_t desc_tag; 385 bus_dmamap_t desc_map; 386 bus_dma_tag_t tag[FL_BUF_SIZES_MAX]; /* only first FL_BUF_SIZES(sc) are 387 valid */ 388 uint8_t tag_idx; 389 struct mtx fl_lock; 390 char lockname[16]; 391 int flags; 392 393 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 394 bus_addr_t ba; /* bus address of descriptor ring */ 395 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 396 uint32_t cap; /* max # of buffers, for convenience */ 397 uint16_t qsize; /* size (# of entries) of the queue */ 398 uint16_t cntxt_id; /* SGE context id for the freelist */ 399 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */ 400 uint32_t rx_offset; /* offset in fl buf (when buffer packing) */ 401 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */ 402 uint32_t needed; /* # of buffers needed to fill up fl. */ 403 uint32_t lowat; /* # of buffers <= this means fl needs help */ 404 uint32_t pending; /* # of bufs allocated since last doorbell */ 405 u_int dmamap_failed; 406 struct mbuf *mstash[8]; 407 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 408}; 409 410/* txq: SGE egress queue + what's needed for Ethernet NIC */ 411struct sge_txq { 412 struct sge_eq eq; /* MUST be first */ 413 414 struct ifnet *ifp; /* the interface this txq belongs to */ 415 bus_dma_tag_t tx_tag; /* tag for transmit buffers */ 416 struct buf_ring *br; /* tx buffer ring */ 417 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 418 struct mbuf *m; /* held up due to temporary resource shortage */ 419 420 struct tx_maps txmaps; 421 422 /* stats for common events first */ 423 424 uint64_t txcsum; /* # of times hardware assisted with checksum */ 425 uint64_t tso_wrs; /* # of TSO work requests */ 426 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 427 uint64_t imm_wrs; /* # of work requests with immediate data */ 428 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 429 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 430 uint64_t txpkts_wrs; /* # of coalesced tx work requests */ 431 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */ 432 433 /* stats for not-that-common events */ 434 435 uint32_t no_dmamap; /* no DMA map to load the mbuf */ 436 uint32_t no_desc; /* out of hardware descriptors */ 437} __aligned(CACHE_LINE_SIZE); 438 439/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 440struct sge_rxq { 441 struct sge_iq iq; /* MUST be first */ 442 struct sge_fl fl; /* MUST follow iq */ 443 444 struct ifnet *ifp; /* the interface this rxq belongs to */ 445#if defined(INET) || defined(INET6) 446 struct lro_ctrl lro; /* LRO state */ 447#endif 448 449 /* stats for common events first */ 450 451 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 452 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 453 454 /* stats for not-that-common events */ 455 456} __aligned(CACHE_LINE_SIZE); 457 458static inline struct sge_rxq * 459iq_to_rxq(struct sge_iq *iq) 460{ 461 462 return (__containerof(iq, struct sge_rxq, iq)); 463} 464 465 466#ifdef TCP_OFFLOAD 467/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 468struct sge_ofld_rxq { 469 struct sge_iq iq; /* MUST be first */ 470 struct sge_fl fl; /* MUST follow iq */ 471} __aligned(CACHE_LINE_SIZE); 472 473static inline struct sge_ofld_rxq * 474iq_to_ofld_rxq(struct sge_iq *iq) 475{ 476 477 return (__containerof(iq, struct sge_ofld_rxq, iq)); 478} 479#endif 480 481struct wrqe { 482 STAILQ_ENTRY(wrqe) link; 483 struct sge_wrq *wrq; 484 int wr_len; 485 uint64_t wr[] __aligned(16); 486}; 487 488/* 489 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 490 * and offload tx queues are of this type. 491 */ 492struct sge_wrq { 493 struct sge_eq eq; /* MUST be first */ 494 495 struct adapter *adapter; 496 497 /* List of WRs held up due to lack of tx descriptors */ 498 STAILQ_HEAD(, wrqe) wr_list; 499 500 /* stats for common events first */ 501 502 uint64_t tx_wrs; /* # of tx work requests */ 503 504 /* stats for not-that-common events */ 505 506 uint32_t no_desc; /* out of hardware descriptors */ 507} __aligned(CACHE_LINE_SIZE); 508 509struct sge { 510 int timer_val[SGE_NTIMERS]; 511 int counter_val[SGE_NCOUNTERS]; 512 int fl_starve_threshold; 513 int s_qpp; 514 515 int nrxq; /* total # of Ethernet rx queues */ 516 int ntxq; /* total # of Ethernet tx tx queues */ 517#ifdef TCP_OFFLOAD 518 int nofldrxq; /* total # of TOE rx queues */ 519 int nofldtxq; /* total # of TOE tx queues */ 520#endif 521 int niq; /* total # of ingress queues */ 522 int neq; /* total # of egress queues */ 523 524 struct sge_iq fwq; /* Firmware event queue */ 525 struct sge_wrq mgmtq; /* Management queue (control queue) */ 526 struct sge_wrq *ctrlq; /* Control queues */ 527 struct sge_txq *txq; /* NIC tx queues */ 528 struct sge_rxq *rxq; /* NIC rx queues */ 529#ifdef TCP_OFFLOAD 530 struct sge_wrq *ofld_txq; /* TOE tx queues */ 531 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 532#endif 533 534 uint16_t iq_start; 535 int eq_start; 536 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 537 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 538 539 u_int fl_buf_sizes __aligned(CACHE_LINE_SIZE); 540 struct fl_buf_info fl_buf_info[FL_BUF_SIZES_MAX]; 541}; 542 543struct rss_header; 544typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 545 struct mbuf *); 546typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 547typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 548 549struct adapter { 550 SLIST_ENTRY(adapter) link; 551 device_t dev; 552 struct cdev *cdev; 553 554 /* PCIe register resources */ 555 int regs_rid; 556 struct resource *regs_res; 557 int msix_rid; 558 struct resource *msix_res; 559 bus_space_handle_t bh; 560 bus_space_tag_t bt; 561 bus_size_t mmio_len; 562 int udbs_rid; 563 struct resource *udbs_res; 564 volatile uint8_t *udbs_base; 565 566 unsigned int pf; 567 unsigned int mbox; 568 569 /* Interrupt information */ 570 int intr_type; 571 int intr_count; 572 struct irq { 573 struct resource *res; 574 int rid; 575 void *tag; 576 } *irq; 577 578 bus_dma_tag_t dmat; /* Parent DMA tag */ 579 580 struct sge sge; 581 int lro_timeout; 582 583 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */ 584 struct port_info *port[MAX_NPORTS]; 585 uint8_t chan_map[NCHAN]; 586 587#ifdef TCP_OFFLOAD 588 void *tom_softc; /* (struct tom_data *) */ 589 struct tom_tunables tt; 590 void *iwarp_softc; /* (struct c4iw_dev *) */ 591#endif 592 struct l2t_data *l2t; /* L2 table */ 593 struct tid_info tids; 594 595 int doorbells; 596 int open_device_map; 597#ifdef TCP_OFFLOAD 598 int offload_map; 599#endif 600 int flags; 601 602 char ifp_lockname[16]; 603 struct mtx ifp_lock; 604 struct ifnet *ifp; /* tracer ifp */ 605 struct ifmedia media; 606 int traceq; /* iq used by all tracers, -1 if none */ 607 int tracer_valid; /* bitmap of valid tracers */ 608 int tracer_enabled; /* bitmap of enabled tracers */ 609 610 char fw_version[32]; 611 char cfg_file[32]; 612 u_int cfcsum; 613 struct adapter_params params; 614 struct t4_virt_res vres; 615 616 uint16_t linkcaps; 617 uint16_t niccaps; 618 uint16_t toecaps; 619 uint16_t rdmacaps; 620 uint16_t iscsicaps; 621 uint16_t fcoecaps; 622 623 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 624 625 struct mtx sc_lock; 626 char lockname[16]; 627 628 /* Starving free lists */ 629 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 630 TAILQ_HEAD(, sge_fl) sfl; 631 struct callout sfl_callout; 632 633 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 634 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 635 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 636 637#ifdef INVARIANTS 638 const char *last_op; 639 const void *last_op_thr; 640#endif 641}; 642 643#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 644#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 645#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 646#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 647 648/* XXX: not bulletproof, but much better than nothing */ 649#define ASSERT_SYNCHRONIZED_OP(sc) \ 650 KASSERT(IS_BUSY(sc) && \ 651 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 652 ("%s: operation not synchronized.", __func__)) 653 654#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 655#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 656#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 657#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 658 659#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 660#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 661#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 662#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 663#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 664 665#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 666#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 667#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 668#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 669 670#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 671#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 672#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 673#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 674#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 675 676#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 677#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 678#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 679#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 680#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 681 682#define for_each_txq(pi, iter, q) \ 683 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \ 684 iter < pi->ntxq; ++iter, ++q) 685#define for_each_rxq(pi, iter, q) \ 686 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \ 687 iter < pi->nrxq; ++iter, ++q) 688#define for_each_ofld_txq(pi, iter, q) \ 689 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \ 690 iter < pi->nofldtxq; ++iter, ++q) 691#define for_each_ofld_rxq(pi, iter, q) \ 692 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \ 693 iter < pi->nofldrxq; ++iter, ++q) 694 695/* One for errors, one for firmware events */ 696#define T4_EXTRA_INTR 2 697 698static inline uint32_t 699t4_read_reg(struct adapter *sc, uint32_t reg) 700{ 701 702 return bus_space_read_4(sc->bt, sc->bh, reg); 703} 704 705static inline void 706t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 707{ 708 709 bus_space_write_4(sc->bt, sc->bh, reg, val); 710} 711 712static inline uint64_t 713t4_read_reg64(struct adapter *sc, uint32_t reg) 714{ 715 716 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 717} 718 719static inline void 720t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 721{ 722 723 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 724} 725 726static inline void 727t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 728{ 729 730 *val = pci_read_config(sc->dev, reg, 1); 731} 732 733static inline void 734t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 735{ 736 737 pci_write_config(sc->dev, reg, val, 1); 738} 739 740static inline void 741t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 742{ 743 744 *val = pci_read_config(sc->dev, reg, 2); 745} 746 747static inline void 748t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 749{ 750 751 pci_write_config(sc->dev, reg, val, 2); 752} 753 754static inline void 755t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 756{ 757 758 *val = pci_read_config(sc->dev, reg, 4); 759} 760 761static inline void 762t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 763{ 764 765 pci_write_config(sc->dev, reg, val, 4); 766} 767 768static inline struct port_info * 769adap2pinfo(struct adapter *sc, int idx) 770{ 771 772 return (sc->port[idx]); 773} 774 775static inline void 776t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 777{ 778 779 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 780} 781 782static inline bool 783is_10G_port(const struct port_info *pi) 784{ 785 786 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 787} 788 789static inline bool 790is_40G_port(const struct port_info *pi) 791{ 792 793 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 794} 795 796static inline int 797tx_resume_threshold(struct sge_eq *eq) 798{ 799 800 return (eq->qsize / 4); 801} 802 803/* t4_main.c */ 804void t4_tx_task(void *, int); 805void t4_tx_callout(void *); 806int t4_os_find_pci_capability(struct adapter *, int); 807int t4_os_pci_save_state(struct adapter *); 808int t4_os_pci_restore_state(struct adapter *); 809void t4_os_portmod_changed(const struct adapter *, int); 810void t4_os_link_changed(struct adapter *, int, int, int); 811void t4_iterate(void (*)(struct adapter *, void *), void *); 812int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 813int t4_register_an_handler(struct adapter *, an_handler_t); 814int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 815int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 816int begin_synchronized_op(struct adapter *, struct port_info *, int, char *); 817void end_synchronized_op(struct adapter *, int); 818 819/* t4_sge.c */ 820void t4_sge_modload(void); 821void t4_init_sge_cpl_handlers(struct adapter *); 822void t4_tweak_chip_settings(struct adapter *); 823int t4_read_chip_settings(struct adapter *); 824int t4_create_dma_tag(struct adapter *); 825void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 826 struct sysctl_oid_list *); 827int t4_destroy_dma_tag(struct adapter *); 828int t4_setup_adapter_queues(struct adapter *); 829int t4_teardown_adapter_queues(struct adapter *); 830int t4_setup_port_queues(struct port_info *); 831int t4_teardown_port_queues(struct port_info *); 832int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int); 833void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t); 834void t4_intr_all(void *); 835void t4_intr(void *); 836void t4_intr_err(void *); 837void t4_intr_evt(void *); 838void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 839int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *); 840void t4_update_fl_bufsize(struct ifnet *); 841int can_resume_tx(struct sge_eq *); 842 843/* t4_tracer.c */ 844struct t4_tracer; 845void t4_tracer_modload(void); 846void t4_tracer_modunload(void); 847void t4_tracer_port_detach(struct adapter *); 848int t4_get_tracer(struct adapter *, struct t4_tracer *); 849int t4_set_tracer(struct adapter *, struct t4_tracer *); 850int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 851int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 852 853static inline struct wrqe * 854alloc_wrqe(int wr_len, struct sge_wrq *wrq) 855{ 856 int len = offsetof(struct wrqe, wr) + wr_len; 857 struct wrqe *wr; 858 859 wr = malloc(len, M_CXGBE, M_NOWAIT); 860 if (__predict_false(wr == NULL)) 861 return (NULL); 862 wr->wr_len = wr_len; 863 wr->wrq = wrq; 864 return (wr); 865} 866 867static inline void * 868wrtod(struct wrqe *wr) 869{ 870 return (&wr->wr[0]); 871} 872 873static inline void 874free_wrqe(struct wrqe *wr) 875{ 876 free(wr, M_CXGBE); 877} 878 879static inline void 880t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 881{ 882 struct sge_wrq *wrq = wr->wrq; 883 884 TXQ_LOCK(wrq); 885 t4_wrq_tx_locked(sc, wrq, wr); 886 TXQ_UNLOCK(wrq); 887} 888 889#endif 890